FAIRCHILD semiconductor 74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs handbook
Contents
1. 40 C to 85 C Symbol Parameter see IRON i aide aac Units C 50 pF C1 50 pF Min Typ Max Min Max fax Maximum Clock Frequency 150 150 MHz tPLH Propagation Delay 1 8 6 2 18 6 2 feui CP to On 18 59 18 59 5 tPzH Output Enable Time 1 2 5 6 1 2 5 6 tek 16 53 16 53 tpyz Output Disable Time 2 2 7 1 2 2 7 1 tpLz 2 2 6 6 2 2 6 6 ue AC Operating Requirements Ty 25 C Ty 40 C to 85 C Symbol Parameter ee Meg hare Units C 50 pF C 50 pF Min Max Min Max ts H Setup Time HIGH Aa TA te L or LOW D to CP 14 11 ti ty H Hold Time HIGH 1 3 1 3 tH L or LOW D to CP 1 3 1 3 R tw H Pulse Width CP 3 0 3 0 AR tw L HIGH or LOW 3 0 3 0 Capacitance gt Conditions Symbol Parameter Typ Units Ta 25 C Cin Input Capacitance 5 0 pF Voc OV Cour Note 5 Output Capacitance 11 0 pF Voc 5 0V Note 5 Cour is measured at frequency f 1 MHz per MIL STD 883 Method 3012 www fairchildsemi com 4 Physical Dimensions inches millimeters unless otherwise noted 0 398 0 417 10 10 10 60 oO Jo 010 0 25 c 3 AQ LEAD 1 IDENT 0 291 0 299 7 40 7 59 meal 0 005 0 009 0 13 0 22 1 TI 24 4 zall Ees Ti iye GAUGE PLANE 0 02040 003 0 635 0 010 0 51 0 08 0 25 a 0 020 0 040 TYP 2 z 2 008 0 012 1 0 51 1 01 0 21 0 30 e ponio DETAIL E TYP 0 015 0 025 45 x 0 39 0 63 tae 0e 108 SEATING PLANE l l piez SEE DETAIL E ATN P2. Dg Dg Dio Diy 12 www fairchildsemi com Absolute Maximum Ratings note 1 Storage Temperature Ambient Temperature under Bias 65 C to 150 C 55 C to 125 C Junction Temperature under Bias 55 C to 150 C Vec Pin Potential to Ground Pin 0 5V to 7 0V Input Voltage Note 2 0 5V to 7 0V Input Current Note 2 Voltage Applied to Any Output in the Disabled or Power Off State in the HIGH State Current Applied to Output in LOW State Max DC Latchup Source Current 30 mA to 5 0 mA 0 5V to 5 5V 0 5V to Voc twice the rated Io mA OE Pin 350 mA Across Comm Operating Range Other Pins 500 mA Recommended Operating Conditions Free Air Ambient Temperature 40 C to 85 C Supply Voltage 4 5V to 5 5V Minimum Input Edge Rate AV At Data Input 50 mV ns Enable Input 20 mV ns Clock Input 100mV ns Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Over Voltage Latchup I O 10V Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol Parameter Min Typ Max Units Vec Conditions Vin Input HIGH Voltage 2 0 Vv Recognized HIGH Signal Vit Input LOW Voltage 0 8 Vv Recognized LOW Signal Vep Input Clamp Diode Voltage 1 2
3. Vv Min lin 18 mA Vou Output HIGH Voltage 2 5 Vv Min lop 3 mA 2 0 V Min lop 32 mA VoL Output LOW Voltage 0 55 Vv Min lo 64 mA lH Input HIGH Current 1 A Max Vin 2 7V Note 3 Vin Voc IBvi Input HIGH Current Breakdown Test 7 A Max Vin 7 0V lit Input LOW Current 1 x ke Vin 0 5V Note 3 4 Vin 0 0V Vip Input Leakage Test 4 75 V 0 0 lp 1 9 uA All Other Pins Grounded ozH Output Leakage Current 10 A 0 5 5V_ Vout 2 7V OE 2 0V OZL Output Leakage Current 10 A 0 5 5V_ Vout 0 5V OE 2 0V os Output Short Circuit Current 100 275 mA Max Voyt 0 0V CEX Output HIGH Leakage Current 50 A Max Vout Vcc zz Bus Drainage Test 100 A 0 0 Vout 5 5V All Others Voc or GND CCH Power Supply Current 2 0 mA Max All Outputs HIGH CCL Power Supply Current 62 mA Max All Outputs LOW cez Power Supply Current 20 mA Max OE Vcc All Others at Vec or GND CCT Additional I Input Outputs Enabled 2 5 mA Vi Vec 2 1V Outputs 3 STATE 2 5 mA Max Enable Input Vj Vcc 2 1V Outputs 3 STATE 2 5 mA Data Input Vi Voc 2 1V All Others at Vecor GND locp Dynamic Icc No Load mA Max Outputs Open Note 3 0 30 MHz OE GND Note 4 One Bit Toggling 50 Duty Cycle Note 3 Guaranteed but not tested Note 4 For 8 bit toggling Iccp lt 0 8 mA MHz 3 www fairchildsemi com pLE9LLEVPL 74ABT16374 AC Electrical Characteristics SSOP Package Ta 25 C T4
4. 2578 74A BT 163744 hy A e a l FAIRCHILD e SEMICONDUCTOR 74ABT16374 March 1994 Revised May 2005 16 Bit D Type Flip Flop with 3 STATE Outputs General Description The ABT16374 contains sixteen non inverting D type flip flops with 3 STATE outputs and is intended for bus oriented applications The device is byte controlled A buffered clock CP and Output Enable OE are common to each byte and can be shorted together for full 16 bit operation Features E Separate control logic for each byte E 16 bit version of the ABT374 E Edge triggered D type inputs E Buffered Positive edge triggered clock E High impedance glitch free bus loading during entire power up and power down cycle E Non destructive hot insertion capability E Guaranteed latch up protection Ordering Code Order Number Package Number Package Description 74ABT16374CSSC MS48A 48 Lead Small Shrink Outline Package SSOP JEDEC MO 118 0 300 Wide 74ABT16374CMTD MTD48 48 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 6 1mm Wide Devices also available in Tape and Reel Specify by appending suffix letter X to the ordering code Logic Symbol og lg l5 by Ib Ig to h1 hz h3 h4 h5 0E CP Og 02 03 04 O5 Os 07 Os Og Oio 011 012 3 4 O5 Pin Descriptions Pin Name Description OE 3 STATE Output Enable Input Active LOW CP Clock Pulse Input Active Rising Edge Do Di
5. 5 Data Inputs Oo O 5 3 STATE Outputs Connection Diagram 2005 Fairchild Semiconductor Corporation DS011668 www fairchildsemi com sindino 3LVLS YUM doj4 dij4 edAL q 49 94 PLZEILLEVPZ 74ABT16374 Functional Description The ABT16374 consists of sixteen edge triggered flip flops Truth Tables with individual D type inputs and 3 STATE true outputs Inputs Outputs The device is byte controlled with each byte functioning ae a 2 identically but independent of the other The control pins CP OE Do D7 Oo 07 can be shorted together to obtain full 16 bit operation Each al L H H byte has a buffered clock and buffered Output Enable com mon to all flip flops within that byte The description which am L L L follows applies to each byte Each flip flop will store the L L xX Previous state of their individual D inputs that meet the setup and hold time requirements on the LOW to HIGH Clock CP x H x Z transition With the Output Enable OE LOW the con sui Sabi tents of the flip flops are available at the outputs When pe APES OE is HIGH the outputs go to the high impedance state CP OE De D15 Og O45 Operation of the OE input does not affect the state of the Pa L H H flip flops a L L L L L X Previous X H xX Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Logic Diagrams Byte 1 0 7 Do D Dy Ds Dy D5 Dg D7 Byte 2 8 15 D
6. SSOP JEDEC MO 153 6 1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the user 2 A critical component in any component of a life support device or system whose failure to perform can be rea sonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com www fairchildsemi com
7. v QT E aes AZ A 0 004 0 10 Do 2 9 025 yp 0 10 vin w 0 635 0 25 0 8 TYP 48 Lead Small Shrink Outline Package SSOP JEDEC MO 118 0 300 Wide Package Number MS48A MS48A REV E www fairchildsemi com pLEILLEVPL 74ABT16374 16 Bit D Type Flip Flop with 3 STATE Outputs Physical Dimensions inches millimeters un less otherwise noted Continued 12 50 0 10 p A 0 40 TYF lig 48 3 30 23 48 43 30 25 TUNA E S T i w g 8 m i a lt 8 24 Q o 2 c BIA 7 5 g D PIN 1 IDENT ALL LEAD TIPS il Poze 0 50 LAND PATTERN RECOMMENDATION SIo i J 1 2 MAX ALL LEAD TIPS o g0t0 13 SEE DETAL A SPREE ame N E H bk L es 0 50 H 0 17 0 27 0 10 0 05 0 13 A 8 c DIMENSIONS ARE IN MILLIMETERS NOTES A CONFORMS TO JEDEC REGISTRATION MO 153 VARIATION ED DATE 4 97 B DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS D DIMENSIONS AND TOLERANCES PER ANSI Y14 5M 1982 MTD48REVC 12 00 TOP amp BOTTOM RO 16 GAGE PLANE RO S1 0 25 ie A p az area 0 6040 10 SEATING PLANE 1 00 DETAIL A 48 Lead Thin Shrink Small Outline Package T
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FAIRCHILD semiconductor 74ABT16374 16 Bit D Type Flip Flop with 3 STATE Outputs handbook