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TEXAS INSTRUMENTS THS3201 handbook

1. 0 1 dB GAIN FLATNESS NONINVERTING SMALL SIGNAL FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE 24 24 6 4 22 2 Gain 2 22 G 10 RF 464 0 20 G ORES DI a 6 3 H Rp 7150 Bon 18 rm Ree 1 18 TTT m 62 Vo 0 2 Vpp S 16 G 5 RF 576 m d G 5 RF 549 Q T Ve c5 V 14 1 14 S 64 2 RL 1009 S 42 RL 100Q i 12 D o 10 Vo 0 2 Vpp 9 49 Vo 0 2 Vpp 2 a E Vg 5V B a Vs s5V Zz 8 G 2 RF 715Q9 S lt B 59 2 6 H z 4 4 G 2 RF 5762 S ng 2 LLL zZz o 2 G 1 RF 1 2 kQ 0 H 57 2 2 G 1 Rp 576 0 H 4 5 6 7 100 M ou 100M G 0G 100 M 10M 00M 1G 0G 100k 1M OM 100M G 0G f Frequency Hz f Frequency Hz f Frequency Hz Figure 35 Figure 36 Figure 37 2nd HARMONIC DISTORTION 3rd HARMONIC D
2. INSTRUMENTS www ti com THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 POWER SUPPLY S cas M 5 RL 1000 The performance of the THS3201 is dependent upon the ont VO 2Vpp power supply Slew rate bandwidth and distortion are 65 graphed against the power supply to highlight this 7 dependence As the power supply is increased from 5 V 2 e to 7 5 V the slew rate increases the bandwidth 2 m o increases and the distortion improves E 3 8 11000 MEI E 90 Vs 7 5V Rise S Kee Vg 7 5V S 95 R 7680 9000 RF 768 Q 100 n 9000 1 0 100 7o00 Rise f Frequency MHz gt Vg 5V N b 6000 RF 7150 Zo E ioo Fal Figure 59 3rd Harmonic Distortion vs Frequency Vs 7 5 z RF 7689 Z 4000 E 3000 Fall SS Vg 5V Gain 2 1000 REp 7152 Rp 1000 0 0 1 2 3 4 5 6 7 8 9 10 Vo Output Voltage Step Vpp Vg 7 5V Figure 57 Slew Rate vs Output Voltage Step 6 Rp 7680 D 45 75 ai E 50 amp 4 d 55 2 Vor tov al vg 5v 5 60 RF 715Q H RE 7150 5 765 5 2 eo A 70 Vs 7 5V Gain 2 o RF 768 Q Ir RL 1000 E 75 Vo 2 Vpp S 80 r 10 100 1k 10k S 85 Ga
3. FREQUENCY RESPONSE 24 22 G 10 RF 487 Q 20 D e rr c 16 G 5 Rp 619 0 S 14 Z cl RL 1009 t 1 Vo 0 2 Vpp S H Vs 27 5V E 8 G 2 RE 768 Q o 6 Z 4 2 G 1 RF 1 2 kQ 0 2 4 100 k M 0M 00 M G 0G f Frequency Hz Figure 2 INVERTING LARGE SIGNAL FREQUENCY RESPONSE D D I E D Q 2 5 E 100 k M 0M 00M 1G f Frequency Hz Figure 5 RECOMMENDED Rjso vs CAPACTIVE LOAD C Capacitive Load pF Figure 8 Noninverting Gain dB 2nd Harmonic Distortion dBc d TEXAS INSTRUMENTS www ti com INVERTING SMALL SIGNAL FREQUENCY RESPONSE 24 22 G 10 RF 499 Q 20 m 18 TT T UB G 5 RF 549 S IE En 9 127 vo 0 2Vpp S 10 vg 27 5V 5 8 S 6 B 4 G 2 Rf 576 Q z 2 0 2 Gz 1 Rpg 619 Q 4 100k 1M 10M 00M 1G 10G f Frequency Hz Figure 3 0 1 dB GAIN FLATNESS FREQUENCY RESPONSE
4. S PARAMETER S PARAMETER SLEW RATE vs vs vs FREQUENCY FREQUENCY OUTPUT VOLTAGE Vs 45V Vs 15V Gain 10 3 Gain 10 ont C 0PF 20 C 3 3 pF E unt 22 5 40 s22 d E 12 S12 S en 60 7 S11 Be Reo d S11 Be Re 80 i is 80 L 500 500 p a Ze Q 50 af wo E Q 50 af 100 ource 100 1M 10M 100 M 1G 10G 1M 10M 100 M 1G 10G 0 1 2 3 4 5 f Frequency Hz f Frequency Hz Vo Output Voltage Vpp Figure 44 Figure 45 Figure 46 NONINVERTING SMALL SIGNAL INVERTING LARGE SIGNAL TRANSIENT RESPONSE TRANSIENT RESPONSE OVERDRIVE RECOVERY TIME Output Voltage V Vo Output Voltage V V Input Voltage V Vo Output Voltage V 3 0 0 1 0 2 0 3 0 4 0 5 0 6 07 08 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 0 2 0 4 0 6 0 8 1 t Time us t Time us t Time us Figure 47 Figure 48 Figure 49 13 THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 da TEXAS INSTRUMENTS www ti com APPLICATION INFORMATION WIDEBAND NONINVERTING OPERATION The THS3201 is a unity gain stable 1 8 GHz current feedback operational amplifiers designed to operate from a 3 3 V to 7 5 V power su
5. 100k 1M 10M 100M G 0G f Frequency Hz Figure 6 2nd HARMONIC DISTORTION vs FREQUENCY 40 Vo Vpp RL 100 Q SH Vs 7 5V 60 G 1 RFs 12ko 70 G 5 RF 6199 80 G 2 Rp 7680 90 100 1 10 100 f Frequency MHz Figure 9 d TEXAS INSTRUMENTS www ti com 3rd Harmonic Distortion dBc Third Order Intermodulation Distortion dBc THI THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 3rd HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION vs vs vs FREQUENCY OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING 60 50 Gain 5 55 HD2 RL 499 Q 65 S W 90 HD2 5 8 MHz E o 60L RL 1000 8 at vg szsv HD2 RL 4990 1 HD2 RL 100 0 Z R S 75 S 70 T z HD3 S op _75 RL 499 Q S E 80 2 85 o o 85 E E HD3
6. 50 Q Source R to G V 2870 576 0 RM e e BLU 0 1 uE 6 8uF 100 pF 7 5v VS Figure 51 Wideband Inverting Gain Configuration d TEXAS INSTRUMENTS www ti com SINGLE SUPPLY OPERATION The THS3201 has the capability to operate from a single supply voltage ranging from 6 6V to 15V When operating from a single power supply care must be taken to ensure the input signal and amplifier is biased appropriately to allow for the maximum output voltage swing The circuits shown in Figure 52 demonstrate methods to configure an amplifier in a manner conducive for single supply operation Vs 50 Q Source 4 S Re 768 Q 500 Figure 52 DC Coupled Single Supply Operation VIDEO AND HDTV DRIVERS The exceptional bandwidth and slew rate of the THS3201 matches the demands for professional video and HDTV Most commercial HDTV standards requires a video passband of 30 MHz To ensure high signal quality with minimal degradation of performance a 0 1 dB gain flatness should be at least 7x the passband frequency to minimize group delay variations requiring 210 MHz 0 1 dB frequency flatness from the amplifier High slew rates ensures there is minimal distortion of the video signal Component video and RGB video signals require fast transition times and fast settling times to keep a high signal quality The THS8135 for example is a 240 MSPS video DAC and has a transiti
7. Thermal Pad See Note D Gage Plane 1 07 MAX A 10 10 H 4073271 C 08 03 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMAOO2 for information regarding recommended board layout This document is available at www ti com http www ti com gt E Falls within JEDEC MO 187 PowerPAD is a trademark of Texas Instruments da TEXAS INSTRUMENTS www ti com MECHANICAL DATA D R PDSO G8 PLASTIC SMALL OUTLINE PACKAGE Pin 1 Index Area 0 020 0 51 0 012 0 31 0 010 0 25 0 050 1 27 e EE Y be 0 25 0 069 1 75 Max 0 004 0 10 7 0 004 0 10 Gauge Plane Seating Plane 0 010 0 25 4040047 2 F 07 2004 NOTES All linear dimensions are in inches millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 006 0 15 Falls within JED
8. f Frequency Hz Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet Copyright 2003 2004 Texas Instruments Incorporated THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 d TEXAS INSTRUMENTS www ti com ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted 1 C O Continuous power dissipation See Dissipation Rating Table 150 C Maximum junction temperature T 9 Maximum junction temperature continuous operation long term reliability Tj 4 Operating free air temperature range TA 40 C to 85 C Storage temperature range Ts 65 C to 150 C Lead temperature 300 C 1 6 mm 1 16 inch from case for 10 seconds 1 Stresses above these ratings may cause permanent damage Exposure to absolute maximum conditions for extended periods may degrade device reliability These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified is not implied The THS3201 may incorporate a PowerPAD on the underside of the chip This acts as a heat sink and must be connected to a thermally dissipative plane for proper power dissipation Failure to do so may result in exceeding the maximum junction temperature which could permanently damage t
9. 3 3 3 V Min Maximum operating voltage Absolute maximum t8 25 t8 25 8 25 V Max Maximum quiescent current 14 18 21 21 mA Max Power supply rejection PSRR VS 27Vto8V 69 63 60 60 dB Min Power supply rejection PSRR Vg 7Vto 8V 65 58 55 55 d TEXAS INSTRUMENTS THS3201 www ti com SLOS416A JUNE 2003 REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS Vs 2 5 V Rf 715 Q RL 100 Q and G 2 unless otherwise noted THS3201 OVER TEMPERATURE g sn O C to 40 C MIN TYP eanna E 1 oe Small signal bandwith A T fe Vo 200 mVpp ese H H 710 Te 464 Q 42 Vo 200 mVpp Bandwidth for 0 1 dB flatness e 7150 170 Large signal bandwidth 2 VO 2 2 Vgg Rp 715 Q G 1 V9 5 V step Slew rate 25 to 75 level Ge Vo 5V step G 2 Vo 4 V step Rise and fall time RE 7150 Settling time to 0 1 G 2 VO 2 V step 0 01 G 2 Vo 2 V step Harmonic distortion G 5 f 10 MHz VO 2 Vpp 2nd harmonic 500 Q 1009 sae LES EE RL 500 kQ Third order intermodulation distortion IMD3 G 10 fc 100 MHz Af 200 kHz VO envelope 2 Vpp PARAMETER TEST CONDITIONS AC PERFORMANCE alo D SIE 9 ISIS oa o N 5le Third order output intercept point OIP3 wo Go n Noise figure G 10 fg 100 MHz S RF 255 Q RG 28 input voltage noise Input current noise noninverting Input current noise inverting G 2 RL 150 Q PaL 0 004 _ Rr 7
10. 3ATHS3201 hy gs d TEXAS INSTRUMENTS www ti com D 8 DBV 5 E g DGN 8 DGK 8 THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 1 8 GHz LOW DISTORTION CURRENT FEEDBACK AMPLIFIER FEATURES Unity Gain Bandwidth 1 8 GHz High Slew Rate 10500 V us Distortion at 100 MHz G 10 V V D 100 Oo 2 Vpp envelope IMD3 80 dBc OIP3 41 dBm Noise Figure 11 dB G 10 V V Rg 28 Q Rp 255 Q Input Referred Noise f gt 10 MHz Voltage Noise 1 65 nV VHz u Noninverting Current Noise 13 4 pA VHz Inverting Current Noise 20 pA VHz Output Current 115 100 mA Power Supply Voltage Range 3 3 V to 7 5 V APPLICATIONS Arbitrary Waveform Driver High Resolution High Sampling Rate ADC Drivers High Resolution High Sampling Rate DAC Output Buffers f Amplification for Wireless Communications Applciations Broadcast Video and HDTV Line Drivers Low Noise Low Distortion Wideband Application Circuit 7 5 V 50 Source 768 Q 768 Q NOTE Power supply decoupling capacitors not shown A PowerPAD is a trademark of Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters 50 Q DESCRIPTION The THS3201 is a wide band high speed c
11. Quiescent Current mA d TEXAS INSTRUMENTS www ti com INPUT OFFSET VOLTAGE vs CASE TEMPERATURE Vg 47 5V 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Tc Case Temperature C Figure 20 SLEW RATE VS OUTPUT VOLTAGE KO Kl ITT BH IST poe e ETA _ 0 1 2 3 4 5 6 7 8 9 10 Vo Output Voltage Vpp Figure 23 QUIESCENT CURRENT vs SUPPLY VOLTAGE TA 85 C Ta 25 C Ta 40 C 225 335 445 555 6 65 7 75 Vs Supply Voltage V Figure 26 10 x TEXAS NSTRUMENTS THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 OUTPUT VOLTAGE REJECTION RATIO vs vs NONINVERTING SMALL SIGNAL LOAD RESISTANCE FREQUENCY TRANSIENT RESPONSE 7 80 6 Vg 47 5V i TN a a HE 5 70 Output 60 gt e 3 m 1 9 2 1 CMRR g 1 Vg 2375 V
12. any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interf
13. the required isolation Together the R and C form a real pole in the s plane located at the frequency fp t SE 2nRC 16 d TEXAS INSTRUMENTS www ti com Placing this pole at about 10x the highest frequency of interest insures it has no impact on the signal Since the resistor is typically a small value it is very bad practice to place the pole at or very near frequencies of interest At the pole frequency the amplifiers sees a load with a magnitude of 2 xR If Ris only 10 Q the amplifier is very heavily loaded above the pole frequency and generates excessive distortion DAC DRIVER APPLICATION The THS3201 can be used as a high performance DAC output driver in applications like radio transmitter stages and arbitrary waveform generators All high performance DAOs have differential current outputs Two THS3201s can be used as a differential drive amplifier in these applications as shown in Figure 56 Rpy on the DAC output is used to convert the output current to voltage The 24 9 O resistor and 47 pF capacitor between each DAC output and the op amp input is used to reduce the images generated at multiples of the sampling rate The values shown form a pole a 136 MHz Rour sets the output impedance of each amplifier r e RF ANN ROUT VOUTI ROUT TT Vour2 Re NAN AVDD __J Figure 56 Differential DAC Driver Circuit d TEXAS
14. the thermal coefficient from the silicon junctions to the case C W 0cA is the thermal coefficient from the case to ambient air C W d TEXAS INSTRUMENTS www ti com For systems where heat dissipation is more critical the THS3201 is offered in an 8 pin MSOP with PowerPAD and the THS3201 is available in the SOIC 8 PowerPAD package offering even better thermal performance The thermal coefficient for the PowerPAD packages are substantially improved over the traditional SOIC Maximum power dissipation levels are depicted in the graph for the available packages The data for the PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application note number SLMAO02 The following graph also illustrates the effect of not soldering the PowerPAD to a PCB The thermal impedance increases substantially which may cause serious heat and performance issues Be sure to always solder the PowerPAD to the PCB for optimum performance Ty 125 C 9JA 58 4 C W 8JA 98 C W 0 5 Pp Maximum Power Dissipation W ie eo 9JA 158 C W 40 20 0 20 40 60 80 100 TA Free Air Temperature C Results are With No Air Flow and PCB Size 3 x3 DA 58 4 C W for 8 Pin MSOP w PowerPad DGN DA 98 C W for 8 Pin SOIC High Test PCB D JA 158 C W for 8 Pin MSOP w PowerPad w o Solder Figure 63 Maximum
15. 01 is available through either the Texas Instruments web site www ti com or as one model on a disk from the Texas Instruments Product Information Center 1 800 548 6132 The PIC is also available for design assistance and detailed product information at this number These models do a good job of predicting small signal ac and transient performance under a wide variety of operating conditions They are not intended to model the distortion characteristics of the amplifier nor do they attempt to distinguish between the package types in their small signal ac performance Detailed information about what is and is not modeled is contained in the model file itself Connector edge SMAPCBjack Jt J2 J4 Johnson 142 0701 801 17 4 Keystone 1804 19 U1 1 20 Board printedoireut 1 TI THS3201DGN TI Edge 6447972 Rev A ADDITIONAL REFERENCE MATERIAL PowerPAD Made Easy application brief SLMA004 PowerPAD Thermally Enhanced Package technical brief SLMA002 Voltage Feedback vs Current Feedback amplifiers SLVA051 Current Feedback Analysis SLOA021 and Compensation Current Feedback Amplifiers Review Stability and Application SBOA081 Effect of parasitic capacitance in op amp circuits SLOA013 23 K Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 11 Feb 2005 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco
16. 68 2 Ntsc 009 PAL o0 DC PERFORMANCE D Ver E ee E se ala eio ALG E o Nu yp EE w x lt x TEXAS THS3201 NSTR MENTS SLOS416A JUNE 2003 REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS continued Vs 2 5 V Rf 715 Q RL 100 Q and G 2 unless otherwise noted THS3201 PARAMETER TEST CONDITIONS INPUT Common mode rejection ratio Vom 2 5 V 71 780 Input resistance 2 SENT NN n Input capacitance 1 OUTPUT Voltage output swing Current output sourcing Current output sinking Closed loop output impedance POWER SUPPLY Minimum operating voltage Absolute minimum 3 3 3 3 3 3 V Min Maximum operating voltage Absolute maximum 8 25 t8 25 8 25 V Max Maximum quiescent current 14 16 8 19 20 mA Max Power supply rejection PSRR VS 4 5 V to 5 5 V 69 63 60 60 dB Min Vs 45 V t0 55V 65 s 55 55 dB j x TEXAS NSTRUMENTS THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 TYPICAL CHARACTERISTICS Table of Graphs Vc 47 5 V owwewgsmasyaememyemows O avering smal signal requency sone S S Noninvering large signal fequency response averngerge signal tequency esponse S oe gin faness requeney eaponse wmetetaiemenymaone aan HS EE eet leese Jl EE Table of Graphs Vs 5 V Noninvertin
17. BL 1000 S 90 E 90 95 HDS RES 1000 ES Gain 5 Rp 6190 HD3 RL 4990 f 32 MHz Vg 47 5 V 100 100 1 10 100 005 115 2 25 335 445 5 005 115225 3 35 4 45 5 f Frequency MHz Vo Output Voltage Swing V Vo Output Voltage Swing V Figure 10 Figure 11 Figure 12 RD ORDER INTERMODULATION THIRD ORDER OUTPUT DISTORTION INTERCEPT POINT S PARAMETER vs vs vs FREQUENCY FREQUENCY FREQUENCY RL 1009 e Vo 2 Vpp Envelope Vg 47 5 V Vo 2Vpp Envelope m Ri 1009 Gain 10 _ Vg 47 5 V C 0pF cw ied l 200 kHz Tone Spacin 20 S11 200 kHz Tone Spacing E pne pe ng I I jp tiv cip tl o o ao G 2 Rp 7680 S s sof S22 o D S12 g E S 5 amp om d Re Re o 5 E S 500 j 502 2500 502 G 10 RF 487 Q E G 2 RF 7689 Source 100 10 100 200 0 20 40 60 80 100 1M 10M 100 M 1G 10G f Frequency MHz f Frequency MHz f Frequency Hz Figure 13 Figure 14 Figure 15 INPUT VOLTAGE S PARAMETER UT VOLTAG vs AND CURRENT NOISE vs FREQUENCY N d FREQUENCY Vg 47 5V N E St et Vs 47 5 Vand 5 V Gain 10 Z 45 T 25C 35 2 C 3 3 pF A 25 5 5 20 i a S Bom dE 1 2 Vn H gs 40 S22 35 25 2 a o 9 12 e 2 E 30 15 8 amp 60f au Invert 2 inverting U n Re RF n S 5 oise Current 0 5 a d EI E 80 SL o MES E t 509 2 Noninverting 500 d N aaa S 15 Current Noise U 100 Source k 1 10 1M 10M 100M 1G 10G 100 k 1M 10M 100 M f Frequency Hz f Frequency Hz Figure 16 Fi
18. EC MS 012 variation AA 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TTS terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to
19. EVM Circuit Configuration 21 THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 J5 9 L El D hd FB2 PD REF PD J8 IN Jo BR 885 vou TEXAS INSTRUMENTS THS3201DGN EVM EDGE 6450764 Figure 65 THS3201 EVM Board Layout Top Layer Figure 66 THS3201 EVM Board Layout Second Layer Ground 22 d TEXAS INSTRUMENTS www ti com Figure 67 THS3201 EVM Board Layout Third Layer Power Figure 68 THS3201 EVM Gm Layout Bottom d TEXAS INSTRUMENTS www ti com THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 Table 2 Bill of Materials THS3201DGN EVM Steward HI1206N800R 00 AVX TAJD226K025R AVX AQ12EM101JAJME AVX 4 Cap 0 1 uF ceramic X7R 50V 0805 C3 C6 2 AVX 08055C104KAT2A 7 Resistor 49 9 O 1 8W 196 0805 R6 1 Phycomp 9C08052A49R9FKHFT s Resistor 766 0 ew oos as 2 PheompyecososeAreenrkHE 3 Ow Oase co 2 38 ___Testpoin back H e CES on 9 2 Standoff 4 40 hex 0 625 length IC THS3201 NOTE The components shown in the BOM were used in test by TI Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems This is particularly true for video and Re amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance A SPICE model for the THS32
20. ISTORTION HARMONIC DISTORTION vs vs vs FREQUENCY FREQUENCY OUTPUT VOLTAGE SWING 40 50 Vo 2 Vpp HD2 RL 499 2 ge RL 100 9 55 RL a Vg 5V a a S 45 d g HD2 RL 1000 1 1 9 e S 60 G 1 RF 1 2kQ 5 1 E E 2 o 7 o A 70 L i 2 75 d G 5 Rp 5760 m a HD3 RL 499 Q 5 9 80 B 80 5 ie HD3 BL 1000 SS as 2 S ia E T T T 2 G 2 RF 715Q s sn Gain 5 e B E Hr 576 Q a 90 o _95 f 8 MHz Vg 5V 100 100 1 10 100 0 05 1 15 2 25 335 445 5 f Frequency MHz f Frequency MHz Vo Output Voltage Swing V Figure 38 Figure 39 Figure 40 THIRD ORDER INTERMODULATION THIRD ORDER OUTPUT HARMONIC DISTORTION DISTORTION v INTERCEPT POINT vs vs OUTPUT VOLTAGE SWING FREQUENCY FREQUENCY o 45 HD2 RL 4992 Rie 1000 Vo 2 Vpp Envelope op io oq L 1 Vo 2Vpp Envelope amp R Hen P 8 HD2 RL 1000 S Vg 5V Vs 45V m 55 s 200 kHz Tone Spacing z 200 kHz Tone Spacing 2 60 E 3 o a n 65 c 2 7 HD3 RL 1002 Z 8 a E gm HD3 RL 499 Q 8 E 80 ER E 3 E 85 Gain 5 E 6 90 Rp 576Q S G 5 RF 576 9 S 95 f232 MHz 6 i an ndo bn 6 2 Vg 45V G 10 Rp 464 Q 3 100 0 05 1 15 2 253 35 4 45 5 E 10 100 200 20 m m 80 Vo Output Voltage Swing V 0 H P f Frequency MHz f Frequency MHz Figure 41 Figure 42 Figure 43 12 x TEXAS NSTRUMENTS THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004
21. Plan Lead Ball Finish MSL Peak Temp DI Type Drawing Qty THS3201D ACTIVE SOIC D 8 75 Pb Free CU NIPDAU Level 2 260C 1YEAR RoHS Level 1 220C UNLIM THS3201DBVR ACTIVE SOT 23 DBV 5 3000 Green RoHS amp CU NIPDAU Level 1 260C UNLIM no Sb Br THS3201DBVT ACTIVE SOT 23 DBV 5 250 Green RoHS amp CU NIPDAU Level 1 260C UNLIM no Sb Br THS3201DGK ACTIVE MSOP DGK 8 100 Green RoHS amp CUNIPDAU Level 1 260C UNLIM no Sb Br THS3201DGKR ACTIVE MSOP DGK 8 2500 Green RoHS amp CU NIPDAU Level 1 260C UNLIM no Sb Br THS3201DGN ACTIVE MSOP DGN 8 80 Green RoHS amp CU NIPDAU Level 1 260C UNLIM Power no Sb Br PAD THS3201DGNR ACTIVE MSOP DGN 8 2500 Green RoHS amp CU NIPDAU Level 1 260C UNLIM Power no Sb Br PAD THS3201DR ACTIVE SOIC D 8 2500 Pb Free CU NIPDAU Level 2 260C 1YEAR RoHS Level 1 220C UNLIM The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan May not be currently available please check http www ti com productcontent for the latest ava
22. Power Dissipation vs Ambient Temperature When determining whether or not the device satisfies the maximum power dissipation requirement it is important to not only consider quiescent power dissipation but also dynamic power dissipation Often times this is difficult to THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 quantify because the signal pattern is inconsistent but an estimate of the RMS power dissipation can provide visibility into a possible problem DESIGN TOOLS Evaluation Fixture Spice Models and Applications Support Texas Instruments is committed to providing its customers with the highest quality of applications support To support this goal an evaluation board has been developed for the THS3201 operational amplifier The board is easy to use allowing for straightforward evaluation of the device The evaluation board can be ordered through the Texas Instruments web site www ti com or through your local Texas Instruments sales representative The schematic diagram board layers and bill of materials of the evaluation boards are provided below R5 Vs 768 Q dh R6 Vin 0 J4 49 9 Q R7 Vout Not Populated Ver s Ae PD Ref J2 Vin l cr 49 90 S R4 7 Does Not Apply to the THS3201 J6 GND TP1 J7 J5 VS VS vS FB1 FB2 _e Y c1 c6 c5 c4 6i c bi 22uF 0 1 uE 100 pF 100 pF_ _0 1 uF 22 uF Figure 64 THS3201
23. a and Figure 61 b This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package see Figure 61 c Because this thermal pad has direct thermal contact with the die excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad The PowerPAD package allows for both assembly and thermal management in one manufacturing operation During the surface mount solder operation when the leads are being soldered the thermal pad can also be soldered to a copper area underneath the package Through the use of thermal paths within this copper area heat can be conducted away from the package into either a ground plane or other heat dissipating device The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the heretofore awkward mechanical methods of heatsinking Side View a f DIE Ne End View b Bottom View c Figure 61 Views of Thermally Enhanced Package THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 Although there are many ways to properly heatsink the PowerPAD package the following steps illustrate the recommended approach 0 017 Top View Figure 62 DGN PowerPAD PCB Etch and Via Pattern 19 THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 PowerPAD PCB LAYOUT CONSIDERATIONS 1 Prepare the PCB
24. ace interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2005 Texas Instruments Incorporated Copyright Each Manufacturing Company All Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 100 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
25. g o B 7 o 0 TA 40 to 85 C 40 B a S PSRR 3 8 9 6 1 3 ZS 1 2 A 20 Ks E 10 6 E 0 19 109 1009 TER di Kei aia 0 0 1 02 03 0405 06 07 08 RL Load Resistance Q f Frequency Hz l 1 Time us MEM Figure 27 Figure 28 Figure 29 DIFFERENTIAL GAIN vs INVERTING LARGE SIGNAL OVERDRIVE RECOVERY TIME NUMBER OF LOADS TRANSIENT RESPONSE 10 5 0 030 gt oe 8 G 2 4 Gain 2 Rr 768 9 0025 RF 7689 6 Vg 2375V 3 l Vg 7 5V 5 T gt gt lt 40 IRE NTSC and Pal 1 g U 1 0 020 Worst Case 100 IRE Ramp amp 2 1 B i S 838 PAL s Z 0 0 g 0015 2 2 12 5 6 pP a 1 0010 NTSC 1 2 a o e x S 0 005 8 4 10 5 0 0 0 2 0 4 0 6 0 8 1 0 1 2 3 4 5 6 7 8 0 0 1 0 2 0 3 0 4 0 5 06 0 7 0 8 t Time jis Ger or Loads 150 t t Time us Figure 30 Figure 31 Figure 32 DIFFERENTIAL PHASE CLOSED LOOP OUTPUT IMPEDANCE vs vs NUMBER OF LOADS FREQUENCY 0 040 1000 Gain 2 a 0 035 F RE 768ko 400 Vg 7 5V 8 9 0 030 F 40 IRE NTSC and Pal s 8 0 025 Worst Case 100 IRE Ramp E 10 amp S 0 020 PAL 2 1 5 6 5 0 015 S od i NTSC E 0 010 8 om 0 005 o 0 0 001 0 1 2 3 4 5 6 7 8 100 k M 0M M 1G Number of Loads 150 Q f Frequency Hz Figure 33 Figure 34 11 x TEXAS THS3201 NSTR MENTS SLOS416A JUNE 2003 REVISED JANUARY 2004 Vs 5 V Graphs INVERTING SMALL SIGNAL
26. g small signal frequency response Pe Inverting small signal frequency response e 2nd harmonic distortion vs Frequency Harmonic distortion vs Output voltage swing wwewgsmaspwimsen manne S Hmesgmgespaanenemowe owwwmeeywe THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 NONINVERTING SMALL SIGNAL FREQUENCY RESPONSE 8 REp 6190 7 Rr 768 Q m 6 Kl 1 MI 5 5 RF 1kQ o P 4 S lt LL Gain 2 z RL 100 9 H Vo 0 2 Vpp Vg 7 5V 0 100 M 0M 00M G 0G f Frequency Hz Figure 1 INVERTING LARGE SIGNAL FREQUENCY RESPONSE 16 G 2 5 RF 576 Q 14 T 12 m Kl U 10 5 8 5 G 2 Rp 7150 E 6 E BL 100 2 VO 2 Vpp Vg 47 5 V 0 100 k M OM 00M G f Frequency Hz Figure 4 CAPACITIVE LOAD FREQUENCY RESPONSE R iso 30 9 CL 522 pF m Kl U D o 100 pF R ISO 20 9 CL 47 pF f Frequency MHz Figure 7 Q Recommended R ISO Vs 47 5 V Graphs NONINVERTING SMALL SIGNAL
27. gure 17 THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 NOISE FIGURE VS FREQUENCY Noise Figure dB Gain 10 Rg 28 0 RF 255 Q Vg 47 5V amp 45V 0 50 f Frequency MHz Figure 18 INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE 17 lt 16 1 15 E g 4 o S m 13 5 a i 12 m tw 10 0 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Tc Case Temperature C Figure 21 SETTLING TIME Rising Edge gt 1 2 Gain 2 8 RL 1009 9 RF 576 5 f 1 MHz 2 Vg 47 5V o L J 2 Falling Edge 0 2 4 6 8 10 t Time ns Figure 24 100 150 200 250 300 350 400 los Input Offset Currents u A Transimpedance Gain dBQ SR Slew Rate V us TRANSIMPEDANCE VS FREQUENCY 1M 10M f Frequency Hz Figure 19 SLEW RATE VS OUTPUT VOLTAGE 0 0 05 1 15 2 25 3 35 4 45 5 Vo Output Voltage Vpp Figure 22 SETTLING TIME Rising Edge Gain 2 RL 1000 Rp 576 f 1 MHz Vg 47 5V Falling Edge 0 2 5 5 7 5 10 t Time ns Figure 25 100M G 12 5 Vos Input Offset Voltage mV SR Slew Rate V S
28. he device See TI technical briefs SLMA002 and SLMAO004 for more information about utilizing the PowerPAD thermally enhanced package The absolute maximum temperature under any condition is limited by the constraints of the silicon process 4 The maximum junction temperature for continuous operation is limited by package constraints Operation above this temperature may result in reduced reliability and or lifetime of the device PACKAGE ORDERING INFORMATION P 9 TEMPERATURE A This integrated circuit can be damaged by ESD Texas dy A Instruments recommends that all integrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures can cause damage ESD damage can range from subtle performance degradation to complete device failure Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications PACKAGE DISSIPATION RATINGS a POWER RATING 2 PACKAGE penn Fo Ty 125 C 1 This data was taken using the JEDEC standard High K test PCB 2 Power rating is determined with a junction temperature of 125 C This is the point where distortion starts to substantially increase Thermal management of the final PCB should strive to keep the junction temperature at or below 125 C for best performance and long term reliability RECOMMENDED OPERATING CONDITIONS S
29. ietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 MECHANICAL DATA DBV R PDSO G5 PLASTIC SMALL OUTLINE PACKAGE Seating Plane Q 0 10 b 4073253 4 H 10 2003 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion D Falls within JEDEC MO 178 Variation AA da TEXAS INSTRUMENTS www ti com MECHANICAL DATA DGK S PDSO G8 PLASTIC SMALL OUTLINE PACKAGE EN A 1 4 3 10 2 90 Y EEE SE L 110 MAX T Bi ES 4073329 D 12 03 NOTES All linear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion Falls within JEDEC MO 187 variation AA da TEXAS INSTRUMENTS www ti com MECHANICAL DATA DGN S PDSO G8 PowerPAD PLASTIC SMALL OUTLINE PACKAGE
30. ilability information and additional product content details None Not yet available Lead Pb Free Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Green RoHS amp no Sb Br TI defines Green to mean Pb Free and in addition uses package materials that do not contain halogens including bromine Br or antimony Sb above 0 1 of total product weight 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be propr
31. in 42 f Frequency Hz Lu M RL 1000 p Vo ever D n D D E T m Figure 60 Noninverting Small Signal f Frequency MHz Frequency Response Figure 58 2nd Harmonic Distortion vs Frequency 17 THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 PRINTED CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE Achieving optimum performance with high frequency amplifier like devices in the THS3201 requires careful attention to board layout parasitic and external component types Recommendations that optimize performance include 18 Minimize parasitic capacitance to any ac ground for all of the signal VO pins Parasitic capacitance on the output and input pins can cause instability To reduce unwanted capacitance a window around the signal VO pins should be opened in all of the ground and power planes around those pins Otherwise ground and power planes should be unbroken elsewhere on the board Minimize the distance 0 25 from the power supply pins to high frequency 0 1 uF and 100 pF decoupling capacitors At the device pins the ground and power plane layout should not be in close proximity to the signal I O pins Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors The power supply connections should always be decoupled with these capacitors Larger 6 8uF or more tantalum decoupling capacitors effective at lower frequency should also be used on the main supp
32. ly pins These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board The primary goal is to minimize the impedance seen in the differential current return paths For driving differential loads with the THS3201 adding a capacitor between the power supply pins improves 2nd order harmonic distortion performance This also minimizes the current loop formed by the differential drive Careful selection and placement of external components preserve the high frequency performance of the THS3201 Resistors should be a very low reactance type Surface mount resistors work best and allow a tighter overall layout Again keep their leads and PC board trace length as short as possible Never use wirebound type resistors in a high frequency application Since the output pin and inverting input pins are the most sensitive to parasitic capacitance always position the feedback and series output resistors if any as close as possible to the inverting input pins and output pins Other network components such as input termination resistors should be placed close to the gain setting resistors Even with a low parasitic capacitance shunting the external resistors excessively high resistor values can create significant time constants that can degrade performance Good axial metal film or surface mount d TEXAS INSTRUMENTS www ti com resistors have approximately 0 2 pF in shunt with the
33. on time approaching 4 ns The THS3201 is a perfect candidate for interfacing the output of such high performance video components THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 768 Q 768 Q 75 Q Transmission Line Vo 1 THS3201 1 759 7 H 7 759 Figure 53 Video Distribution Amplifier Application ADC DRIVER APPLICATION The THS3201 can be used as a high performance ADC driver in applications like radio receiver IF stages and test and measurement devices All high performance ADCs have differential inputs The THS3201 can be used in conjunction with a transformer as a drive amplifier in these applications Figure 54 and Figure 55 show two different approaches In Figure 54 a transformer is used after the amplifier to convert the signal to differential The advantage of this approach is fewer components are required Bour and Ry are required for impedance matching the transformer VS E 0 1 uF C RG RF CM AAA ROUT 1 n 2490 AAA ka VIN RT 47pF_L 2490 lI Vs E 47pF 0 1 uP 2 4 eo zi E d UM Figure 54 Differential ADC Driver Circuit 1 In Figure 55 a transformer is used before two amplifiers to convert the signal to differential The two amplifiers then amplify the differential signal The advantage to this approach is each amplifier is required to drive half the voltage as before Ry is used to impedance match the transfo
34. p 7860 06 rs mw Setting time to 0 1 G 2Vo 2Vsp 2 S 0 01 G 2Vo 2Vsp E Harmonic dstoton 6 s5 amp t T0M zVo 2Vg LL D elek 7 Mm Si Third order intermodulation distortion IMD3 G 10 fe 100 MHz Third ord tout int t Af 200 kHz ird order output intercep V sr point OIP3 O envelope pp RF 255 0 Rg 28 2 0 008 G 42 RL 1500 0 004 Re 768 Q T007 PAL Tom A 11 SR HEN CS roan Los Da Los DC PERFORMANCE Open loop transimpedance gain Vo 1 V RL 1 kQ 300 Input offset voltage Vom 0V 0 Average offset voltage drift Vom 0V Input bias current inverting Vom 0V noni nA C Average bias current drift Vom 0V Input bias current noninverting Vom 0V Average bias current drift Vom 0V uut AR Co x TEXAS THS3201 NSTR MENTS SLOS416A JUNE 2003 REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS Vs 7 5 V Re 768 9 RL 100 Q and G 2 unless otherwise noted THS3201 PARAMETER TEST CONDITIONS INPUT Common mode rejection ratio Vom 3 75 V Inverting input impedance Zin Open loop Input resistance Input capacitance OUTPUT Voltage output swing Current output sourcing Current output sinking Closed loop output impedance POWER SUPPLY Minimum operating voltage Absolute minimum 13 3 13
35. pply Figure 50 shows the THS3201 in a noninverting gain of 2V V configuration typically used to generate the performance curves Most of the curves were characterized using signal sources with 50 O source impedance and with measurement equipment presenting a 50 Q load impedance The 49 9 O shunt resistor at the Viterminal in Figure 50 matches the source impedance of the test generator Figure 50 Wideband Noninverting Gain Configuration Unlike voltage feedback amplifiers current feedback amplifiers are highly dependent on the feedback resistor Hr for maximum performance and stability Table 1 shows the optimal gain setting resistors Rr and Rg at different gains to give maximum bandwidth with minimal peaking in the frequency response Higher bandwidths can be achieved at the expense of added peaking in the frequency response by using even lower values for Rr Conversely increasing Rr decreases the bandwidth but stability is improved 14 Table 1 Recommended Resistor Values for Optimum Frequency Response THS3201 Rf for AC When Rigad 100 2 Gain Su c Paus 6 154 9 er ME fae 7 5 and WIDEBAND INVERTING GAIN OPERATION Figure 51 shows the THS3201 is a typical inverting gain configuration where the input and output impedances and signal gain from Figure 50 are retained in an inverting circuit configuration 75V Vs
36. race dimensions a matching series resistor into the trace from the output of the THS3201 is used as well as a terminating shunt resistor at the input of the destination device Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device this total effective impedance should be set to match the trace impedance If the 6 dB attenuation of a doubly terminated transmission line is unacceptable a long trace can be series terminated at the source end only Treat the trace as a capacitive load in this case This does not preserve signal integrity as well as a doubly terminated line If the input impedance of the destination device is low there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance Socketing a high speed part like the THS3201 is not recommended The additional lead length and pin to pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth stable frequency response Best results are obtained by soldering the THS3201 parts directly onto the board d TEXAS INSTRUMENTS www ti com PowerPAD DESIGN CONSIDERATIONS The THS3201 is available in a thermally enhanced PowerPAD family of packages These packages are constructed using a downset leadframe upon which the die is mounted see Figure 61
37. resistor For resistor values gt 2 0 kQ this parasitic capacitance can add a pole and or a zero that can effect circuit operation Keep resistor values as low as possible consistent with load driving considerations Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines For short connections consider the trace and the input to the next device as a lumped capacitive load Relatively wide traces 50 mils to 100 mils should be used preferably with ground and power planes opened up around them Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary Low parasitic capacitive loads lt 4 pF may not need an Rs since the THS3201 is nominally compensated to operate with a 2 pF parasitic load Higher parasitic Capacitive loads without an Rs are allowed as the signal gain increases increasing the unloaded phase margin If a long trace is required and the 6 dB signal loss intrinsic to a doubly terminated transmission line is acceptable implement a matched impedance transmission line using microstrip or stripline techniques consult an ECL design handbook for microstrip and stripline layout techniques A 50 Q environment is not necessary onboard and in fact a higher impedance environment improves distortion as shown in the distortion versus load plots With a characteristic board trace impedance based on board material and t
38. rmer 15 THS3201 SLOS416A JUNE 2003 REVISED JANUARY 2004 ANN Vgs 0 1 uF Figure 55 Differential ADC Driver Circuit 2 It is almost universally recommended to use a resistor and capacitor between the op amp s output and the ADC s input as shown in both Figures This resistor capacitor RC combination has multiple functions The capacitor is a local charge reservoir for ADC The resistor isolates the amplifier from the ADC n conjunction they form a low pass noise filter During the sampling phase current is required to charge the ADC s input sampling capacitors By placing external capacitors directly at the input pins most of the current is drawn from them They are seen as a very low impedance Source They can be thought of as serving much the same purpose as a power supply bypass capacitor to supply transient current with the amplifier then providing the bulk charge Typically a low value capacitor in the range of 10 pF to 100 pF provides the required transient charge reservoir The capacitance and the switching action of the ADC is one of the worst loading scenarios that a high speed amplifier encounters The resistor provides a simple means of isolating the associated phase shift from the feedback network and maintaining the phase margin of the amplifier Typically a low value resistor in the range of 10 Q to 100 Q provides
39. s exposed The bottom side solder mask should cover the five holes of the thermal pad area This 20 d TEXAS INSTRUMENTS www ti com prevents solder from being pulled away from the thermal pad area during the reflow process 7 Apply solder paste to the exposed thermal pad area and all of the IC terminals 8 With these preparatory steps in place the IC is simply placed in position and run through the solder reflow operation as any standard surface mount component This results in a part that is properly installed POWER DISSIPATION AND THERMAL CONSIDERATIONS To maintain maximum output capabilities the THS3201 does not incorporate automatic thermal shutoff protection The designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device Failure may result if the absolute maximum junction temperature of 150 C is exceeded For best performance design for a maximum junction temperature of 125 C Between 125 C and 150 C damage does not occur but the performance of the amplifier begins to degrade The thermal characteristics of the device are dictated by the package and the PC board Maximum power dissipation for a given package can be calculated using the following formula where Ppmax is the maximum power dissipation in the amplifier W Tmax is the absolute maximum junction temperature C Ta is the ambient temperature C Dia jc OCA D is
40. upply voltage Dual supply 13 3 47 5 6 6 15 Single supply Operating free air temperature TA 40 85 PACKAGED DEVICES PLASTIC SMALL pal PLASTIC MSOP 1 1 OI eu sw peu sw S mw THS3201D THS3201DBVT d THS3201DR THS3201DBVR THS3201DGN THS3201DGK BEN BGP THS3201DGNR THS3201DGKR 1 Available in tape and reel The R suffix standard quantity is 2500 e g THS3201DGNR 2 Available in tape and reel The R suffix standard quantity is 3000 The T suffix standard quantity is 250 e g THS3201DBVT PIN ASSIGNMENTS TOP VIEW VOUT Vs TOP VIEW D DGN DGK NC No Internal Connection NOTE If a PowerPAD is used it is electrically isolated from the active circuitry 2 x TEXAS NSTRUMENTS THS3201 www ti com SLOS416A JUNE 2003 REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS Vs 7 5 V Rf 768 9 RL 100 Q and G 2 unless otherwise noted THS3201 OVER TEMPERATURE TYP PARAMETER TEST CONDITIONS SINE vow anc INVE 5 0 0 PS CO AC PERFORMANCE G 1 RF 1 2kQ o8 T To Small signal bandwidth 3dB G s2Rp 7680 80 T o Vo 200 mVpp G amp Rp 6190 505 Ts we N G d0Rp 470 se TI G 2 VO 200 mVpp Bandwidth for 0 1 dB flatness Rr 768 Q 380 MHz Typ Lage aana bandwidth G 2Vo 2VggRr 7i5o0 amp o m ww G Vos5Vsep lew SENTIT N a NEE Joa T Lp 4 Rise and alime G s 2Vo 4VseeR
41. urrent feedback amplifier designed to operate over a wide supply range of 3 3 V to 7 5 V for todays high performance applications The wide supply range combined with distortion as low as 74 dBc at 10 MHz plus an extremely high slew rate of 10500 V us makes the THS3201 ideally suited for arbitrary waveform driver applications The distortion performance also enables driving high resolution and high sampling rate ADCs Moreover the gain of 2 bandwidth of 850 MHz combined with a 0 1 dB flatness of 380 MHz makes the THS3201 ideal for broadcast video and HDTV applications The THS3201 also offers excellent performance for IF amplification in wireless communications systems by having IMD3 performance of 80 dBc OIP3 of 41 dBm and a noise figure of 11 dB all at 100 MHz with a gain 10 V V while driving a 2 Vpp envelope into a 100 Q load The THS3201 is offered in a 5 pin SOT 23 8 pin SOIC and an 8 pin MSOP with PowerPAD packages THS3202 7 5 V 2 GHz Dual Low Distortion CFB Amplifier THS3122 15 V Dual CFB Amplifier With 350 mA Drive THS4271 7 5 V 1 4 GHz Low Distortion VFB Amplifier NONINVERTING SMALL SIGNAL FREQUENCY RESPONSE 8 7 Rr 768 0 m 6 oO I S 5 D 6 g 4 f o 5 lt LL Gain 2 RL 100 Q IA Vo 0 2 Vpp Vg 7 5V 100k 1M 10M 00 M G 10G
42. with a top side etch pattern as shown in Figure 62 There should be etch for the leads as well as etch for the thermal pad 2 Place five holes in the area of the thermal pad These holes should be 10 mils in diameter Keep them small so that solder wicking through the holes is not a problem during reflow 3 Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area This helps dissipate the heat generated by the THS3201 IC These additional vias may be larger than the 10 mil diameter vias directly under the thermal pad They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem 4 Connect all holes to the internal ground plane 5 When connecting these holes to the ground plane do not use the typical web or spoke via connection methodology Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations This makes the soldering of vias that have plane connections easier In this application however low thermal resistance is desired for the most efficient heat transfer Therefore the holes under the THS3201 PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated through hole 6 Thetop side solder mask should leave the terminals of the package and the thermal pad area with its five hole

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