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TEXAS INSTRUMENTS THS1401 THS1403 THS1408 handbook

1. 4 84 4 00 Top View NOTE All linear dimensions are in millimeters Exposed Thermal Pad Dimensions 4206329 4 F 09 07 LAND PATTERN PHP R PDSO G48 PowerPAD Example Board Layout 0 127mm Thick Stencil Design Example Via pattern and copper pad size Reference table below for other may vary depending on layout constraints solder a Note 44x0 5 48 0 25 44x0 5 r 48x1 55 Non Solder Mask Defined Pad Example Solder Mask Opening Note F Pad Geometry 0 05 Note C All Around 4207626 4 B 03 06 NOTES All linear dimensions are in millimeters B This drawing is subject to change without notice C Publication IPC 7351 is recommended for alternate designs D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMAO02 SLMAO004 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents are available at www ti com http www ti com E Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Refer to IPC 7525 for stencil design cons
2. th Cs WE 5 tsu WE CS LE tsu DA gt gt m A X ADDRESS X Figure 3 Write Timing THS1401 THS1403 Texas THS1408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS POWER SUPPLY CURRENT vs vs FREQUENCY TIME 284 90 282 80 280 a 79 60 50 6 276 5 00 274 3 xag 272 9 20 270 10 268 0 0 1 1 10 0 50 100 150 200 250 300 f Frequency MHz t Time ns Figure 4 Figure 5 FAST FOURIER TRANSFORM fs 1 MSPS fj 100 kHz Output dB 1 ETT A EE UTR Figure 6 10 4 6 INSTRUMENTS www ti com Output dB Output dB INL Integral Nonlinearity LSB THS1401 THS1403 THS1408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM fs 3 MSPS fi 1 MHz f Frequency MHz Figure 7 FAST FOURIER TRANSFORM 15 8 MSPS 20 7 MHz 0 4 2 8 3 1 3 f 2 Figure 8 INTEGRAL NONLINEARITY EU d uL n e 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 9 THS1401 THS1403 TEXAS THS1408 INSTRUMENTS www ti com SLAS248D DECEMBER 1999 RE
3. 0 3 V to AVpp 0 3 V Analog input voltage range 0 3 V to AVpp 0 3 V Digital input voltage range 0 3 V to DVpp 0 3 V Operating free air temperature range Ta 0 C to 70 C SUNIX ete teenie dene EIERE KEEA 40 to 85 C enl ge 40 C to 125 C MESUDE 26 ite 55 C to 125 C Storage temperature range eee THER HIR 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability Terminal Functions TERMINAL NAME yo DESCRIPTION A 1 0 40 41 AGND 7 8 44 45 46 Analog ground AVDD 2 43 47 Analog power supply CLK 32 Clock input CML 4 Reference midpoint This pin requires a 0 1 uF capacitor to AGND cs 37 Chip select input Acti
4. The output code is given by 2s complement Straight binary 8192 at AIN AREF 0 at AREF 0 at 0 8192 atAIN 0 8191 AIN AREF 1 LSB 16383 at AREF 1 LSB 2AREF posse 16384 Table 2 PGA Gain Register Address 1 Read Write o 9 9 9 The PGA gain is determined by writing to 62 0 Gain dB 1dB x G2 0 7dB The range of G2 0 is 0 to 7 Table 3 Offset Register Address 2 Read Write Dean o 9 The offset correction range is from 128 to 127 LSB This value is added to the conversion results from the ADC 15 THS1401 THS1403 Texas THS1408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 PRINCIPLES OF OPERATION Table 4 Control Register Address 3 Read BIT D13 Di2 REF BIT D13 D12 D11 9 1 PWD Power down 0 normal operation 1 power down REF Reference select 0 internal reference 1 external reference FOR Output format 0 straight binary 1 2s complement TM2 0 Test mode 000 normal operation 001 both inputs REF 010 IN at Voltage at CML pin at REF 011 IN at REF IN at REF 100 normal operation 101 both inputs REF 110 IN at REF IN at Voltage CML pin 111 IN at
5. 2 3 LSB 51408 3 5 THS1408Q M 3 5 227 5 Offset error IN IN PGA 0 dB 0 3 FSR C and suffix 1 FSR Gan orf r Q and M suffix 1 75 FSR AC Characteristics Effective number of bits 11 2 11 5 Bits THS1401 3 8 fj 100 kHz 81 Total harmonic distortion THS1403 8 fj 1 MHz 78 51408 fi 4 MHz 77 THS1401 3 8 fi 100 kHz 72 SNR Signal to noise ratio THS1403 8 fj 1 MHz 70 72 dB THS1408 fi 4 MHz 71 THS1401 3 8 fj 100 kHz 70 SINAD _ Signal to noise ratio distortion THS1403 8 fj 1 MHz 69 70 dB THS1408 fi 4 MHz 70 THS1401 3 8 fj 100 kHz 80 51403 THS1408C I 73 80 SFDR Spurious free dynamic range THS1403Q THS1408Q M fi 1 MHz 71 80 51408 fi 4 MHz 80 Analog input bandwidth 140 MHz THS1401 THS1403 X9 Texas THS1408 mE con SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS Cont Over operating free air temperature range AVDD DVDD 3 3V unless otherwise noted PARAMETER TEST CONDITIONS MIN UNIT Reference Voltage Bandgap voltage internal mode 1 425 1 5 1 575 V Input impedance 40 kQ Positive reference voltage REF 2 5 V Negative reference voltage REF 0 5 V Reference difference AREF REF REF 2 V Accuracy internal reference 596 Temperature coefficient 40 ppm C Voltage coefficient 20
6. driving the OE input low Besides the sample results it is also possible to read back the values of the control register the PGA register and the offset register Which register is read is determined by the address inputs A 1 0 The ADC results are available at address 0 The timing of the control signals is described in the following sections THS1401 THS1403 THS1408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION read timing 15 pF load 4 6 INSTRUMENTS www ti com PARAMETER TYP UNIT tsu OE ACS Address and chip select setup time 4 ns ten Output enable 15 ns tdis Output disable 10 ns th A Address hold time 1 ns th CS Chip select hold time 0 ns NOTE All timing parameters refer to a 50 level s PE tsu OE ACS 4 b gt ten gt D 13 0 DATA 4 A 1 0 X ADDRESS Figure 2 Read Timing THS1401 Texas THS1403 INSTRUMENTS THS1408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION write timing 15 pF load PARAMETER MIN TYP UNIT tsu WE CS Chip select setup time 4 ns tsu DA Data and address setup time 29 ns th DA Data and address hold time 0 ns th CS Chip select hold time 0 ns twH WE Write pulse duration high 15 ns NOTE All timing parameters refer to a 50 level
7. 0 ppm V Analog Inputs Positive analog input IN 0 AVDD V Negative analog input IN 0 AVDD V Analog input voltage difference AA N IN IN VREF REF REF VREF V Input impedance 25 kQ PGA range 0 7 dB PGA step size 1 dB PGA gain error 0 25 dB Digital Inputs VIH High level digital input 2 V VIL Low level digital input 0 8 V Input capacitance 5 pF Input current 1 uA Digital Outputs VOH High level digital output 50 uA 2 6 V VOL Low level digital output 50 uA 0 4 V loz Output current high impedance 10 Clock Timing CS low THS1401 0 11 1 1 MHz CLK Clock frequency THS1403 0 11 3 3 MHz THS1408 0 11 8 8 MHz td Output delay time 25 ns Latency 9 5 Cycles t This parameter is not production tested for Q and M suffix devices 351 THS1401 INSTRUMENTS THS1403 www ti com THS1 408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION sample timing The THS1401 3 8 core is based on a pipeline architecture with a latency of 9 5 samples The conversion results appear on the digital output 9 5 clock cycles after the input signal was sampled 11 12 59 Analog 510 Input tw CLK tw CLK JJ NL NL N tg Out Figure 1 Sample Timing The parallel interface of the THS1401 3 8 ADC features 3 state buffers making it possible to directly connect it to a data bus The output buffers are enabled by
8. 19 6 Thermal resistance junction to case O JC PHP package 0 79 C W 1 Thermal resistance is modeled data is not production tested and is given for informational purposes only RECOMMENDED OPERATING CONDITIONS MIN NOM UNIT Supply voltage AVpp DVpp 3 3 3 3 6 V High level digital input 2 3 3 V Low level digital input Vii 0 0 8 V Load capacitance CL 5 15 pF THS1401 0 1 1 1 MHz Clock frequency THS1403 0 1 3 3 MHz THS1408 0 1 8 8 MHz C and I suffix 40 50 60 de de Q and N suffix 5 5 5 C suffix 0 25 70 I suffix 40 25 85 Operating free air temperature C Q suffix 40 25 125 M suffix 55 25 125 4 6 INSTRUMENTS www ti com ELECTRICAL CHARACTERISTICS Over operating free air temperature range AVDD DVDD 3 3V unless otherwise noted THS1401 THS1403 THS1408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 PARAMETER TEST CONDITIONS MIN UNIT Power Supply IDDA Analog supply current AVpp 3 6 V 81 90 mA IDDD Digital supply current DVpp 3 6 V 5 10 Power AVpp DVpp 3 6 V 270 360 mW Power down current 20 uA DC Characteristics Resolution 14 Bits DNL Differential nonlinearity 0 6 ti LSB THS1401 1 5 25 51403 2 5 INL Integral nonlinearity THS1403Q Best fit
9. 257TH S1408Q PH 3 TEXAS INSTRUMENTS www ti com THS1401 THS1403 THS1408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 14 Bit 1 3 8 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA FEATURES 14 Bit Resolution 1 3 and 8 MSPS Speed Grades Available Differential Nonlinearity DNL 0 6 LSB Typ Integral Nonlinearity INL 1 5 LSB Typ Internal Reference Differential Inputs Programmable Gain Amplifier uP Compatible Parallel Interface Timing Compatible With TMS320C6000 DSP 3 3 V Single Supply Power Down Mode Monolithic CMOS Design APPLICATIONS xDSL Front Ends Communication Industrial Control Instrumentation Automotive DESCRIPTION The THS1401 THS1403 and THS1408 are 14 bit 1 3 8 MSPS single supply analog to digital converters ADCs with internal reference differential inputs programmable input gain and on chip sample and hold amplifier Implemented with a CMOS process the device has outstanding price performance and power speed ratios The THS1401 THS1403 and THS1408 are designed for use with 3 3 V systems and with a high speed uP compatible parallel interface making them the first choice for solutions based on high performance DSPs such as the TI TMS320C6000 series The THS1401 THS1403 and THS1408 are available in a TQFP 48 package in standard commercial and industrial temperature ranges The THS1401 THS1403 and THS1408 are also av
10. BG4 ACTIVE TQFP PFB 48 250 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br THS1403QPHP ACTIVE 48 250 TBD CU NIPDAU Level 2 220C 1 YEAR THS1408CPFB OBSOLETE TQFP PFB 48 TBD Call TI Call TI THS1408IPFB ACTIVE TQFP PFB 48 250 Green RoHS amp NIPDAU Level 2 260C 1 YEAR no Sb Br THS1408IPFBG4 ACTIVE TQFP PFB 48 250 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br THS1408QPHP ACTIVE 48 TBD Call TI Call TI The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free ROHS Exempt or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances
11. R Signal to Noise Ratio dB 14 TOTAL HARMONIC DISTORTION VS FREQUENCY fs 3 MSPS at 1 dB 10 100 f Frequency Hz Figure 15 1000 1500 SIGNAL TO NOISE RATIO VS FREQUENCY fs 3 MSPS fj at 1 dB 10 100 f Frequency Hz 1000 1500 Figure 17 THD Total Harmonic Distortion dB SNR Signal to Noise Ratio dB TOTAL HARMONIC DISTORTION VS FREQUENCY fs 8 MSPS fj at 1 dB 10 100 1000 4000 f Frequency Hz Figure 16 SIGNAL TO NOISE RATIO VS FREQUENCY fs 8 MSPS fj at 1 dB 10 100 1000 4000 f Frequency Hz Figure 18 THS1401 4 TEXAS THS1403 THS1408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 PRINCIPLES OF OPERATION registers The device contains several registers The A register is selected by the values of bits 1 and 0 1 0 Register 0 0 Conversion result 0 1 PGA 1 0 Offset 1 1 Control Tables 1 and 2 describe how to read the conversion results and how to configure the data converter The default values were applicable show the state after a power on reset Table 1 Conversion Result Register Address 0 Read MSB dom do se The output can be configured for 2s complement or straight binary format see D11 control register
12. REF IN at REF OF Offset correction 0 enable 1 disable RES Reserved Must be set to 0 APPLICATION INFORMATION driving the analog input The THS1401 3 8 ADCs have a fully differential input A differential input is advantageous with respect to SNR SFDR and THD performance because the signal peak to peak level is 5096 of a comparable single ended input There are three basic input configurations Fully differential Transformer coupled single ended to differential Single ended fully differential configuration In this configuration the ADC converts the difference AIN of the two input signals on IN and IN 220 100 pF IN B THS1401 3 8 220 J IN 100 pF Figure 19 Differential Input 16 THS1401 35 5 INSTRUMENTS THS1403 www ti com THS1 408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 The resistors and capacitors on the inputs decouple the driving source output from the ADC input and also serve as first order low pass filters to attenuate out of band noise The input range on both inputs is 0 V to AVpp The full scale value is determined by the voltage reference The positive full scale output is reached if AIN equals AREF the negative full scale output is reached if AIN equals AREF AIN V OUTPUT full scale 0 0 AREF full scale APPLICATION INFORMATION transformer coupled single ended to differen
13. VISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY o d L fs 3 MSPS 5 5 as ae 2 o 1 z 2 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 10 INTEGRAL NONLINEARITY a o 2 S o 4 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 11 DIFFERENTIAL NONLINEARITY o 1 0 8 gt 06 6 2 O4 tan 5 0 2 0 8 0 2 PTT TRIER _0 4 1 08 1 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 12 4 6 INSTRUMENTS www ti com DNL Differential Nonlinearity LSB DNL Differential Nonlinearity LSB THS1401 THS1403 THS1408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY 6144 8192 10240 12288 14336 16384 Samples Figure 13 DIFFERENTIAL NONLINEARITY dr te 0 4 m PARIT die ab ch fetal 0 6 4096 6144 8192 10240 12288 14336 16384 Samples Figure 14 13 THS1401 THS1403 35 TEXAS THS1408 INSTRUMENTS SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS THD Total Harmonic Distortion dB SN
14. ailable in a PQFP 48 package in automotive temperature range and the THS1408 is available in a PQFP 48 package in military temperature range CLK CONTROL LOGIC D 13 0 OV bit A 1 0 CS WB OE Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments A semiconductor products and disclaimers thereto appears at the end of this data sheet All trademarks are the property of their respective owners PRODUCTION DATA information is current as of publication date Products j Copyright 1999 2005 Texas Instruments Incorporated conform to specifications per the terms of Texas Instruments standard warranty TEXAS On products compliant to MIL PRF 38535 all parameters are tested unless Production processing does not necessarily include testing of all parameters I otherwise noted On all other products production processing does not NSTRUMENTS necessarily include testing of all parameters www ti com THS1401 THS1403 Texas THS1408 OUS SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 ABSOLUTE MAXIMUM RATINGS Over operating free air temperature range unless otherwise noted 1 Supply voltage AVpp to AGND 4V Supply voltage DVpp DGND 2 2 2 4V Reference input voltage range VBG
15. cale Note that the resistors of the op amp and the op amp all introduce gain and offset errors Those errors can be trimmed by varying the values of the resistors Because of the added offset the op amp does not necessarily operate in the best region of its transfer curve best linearity around zero and therefore may introduce unacceptable distortion For ac signals an alternative is described in the following section APPLICATION INFORMATION AC coupled single ended configuration If the application does not require the signal bandwidth to include the level shift shown in Figure 21 is not necessary 10 WN 10 REF 10 10 100 pF Ny THS1401 3 8 Figure 22 Single Ended With Level Shift Because the signal swing on the op amp is centered around ground it is more likely that the signal stays within the linear region of the op amp transfer function thus increasing the overall ac performance IN VPEAK OUTPUT PEAK full scale 0 0 AREF full scale Compared to the transformer coupled configuration the swing on is twice as big which can decrease the ac performance SNR SFD and THD 18 4 6 INSTRUMENTS www ti com APPLICATION INFORMATION internal external reference operation The THS1401 3 8 ADC can either be operated using the built in band gap reference or u
16. formation is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with standard warranty Testing and other quality control techniques are used to the extent deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other in
17. he offset compensation register the ADC result when the input signal is 0 must be read by the host processor and written to the offset register address 2 test modes The ADC core operation can be tested by selecting one of the available test modes see control register description The test modes apply various voltages to the differential input depending on the setting in the control register digital 1 0 The digital inputs and outputs of the THS1401 3 8 ADC are 3 V CMOS compatible In order to avoid current feed back errors the capacitive load on the digital outputs should be as low as possible 50 pF max Series resistors 100 Q on the digital outputs can improve the performance by limiting the current during output transitions The parallel interface of the THS1401 3 8 ADC features 3 state buffers making it possible to directly connect it to a data bus The output buffers are enabled by driving the OE input low Refer to the read and write timing diagrams in the parameter measurement information section for information on read and write access 19 THS1401 THS1403 Texas THS1408 S SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 Revision History SECTION DESCRIPTION Updated page 1 format and layout Moved funtional block diagram from page 2 Moved Terminal Function table from page 3 Moved Absolute Maximum table from page 4 Moved package pinout from page 1 Moved Ordering Options table f
18. iderations F Customers should contact their board fabrication site for recommended solder mask tolerances and via tenting options for vias placed in the thermal pad 35 TEXAS INSTRUMENTS www ti com MECHANICAL DATA MTQF019A JANUARY 1995 REVISED JANUARY 1998 PFB S PQFP G48 PLASTIC QUAD FLATPACK 0 13 NOM 1 12 5 50 TYP 5 7 20 680 Planet i 9 20 8 0 50 1 0 05 Seating Plane t lt 0 08 1 20 4073176 10 96 NOTES A All linear dimensions in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such in
19. including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals and suppliers c
20. m digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Telephony www ti com telephony Low Power www ti com lpw Video amp Imaging www ti com video Wireless Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2007 Texas Instruments Incorporated
21. onsider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by to Customer on an annual basis Addendum Page 1 MECHANICAL DATA PHP S PQFP G48 PowerPAD PLASTIC QUAD FLATPACK Thermal Pad See Note D X Gage Plane T jeg Seating Plane ba 0 08 4146927 08 03 NOTES All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature SLMA002 for information regarding recommended board layout This document is available at www ti com lt http www ti com gt E Falls within JEDEC 5 026 PowerPAD is a trademark of Texas Instruments 435 TEXAS INSTRUMENTS ww
22. rom page 2 Table 1 In section 2s complement 8191 AIN AREF 1 LSB changed to Principles of Operation 8191 AIN AREF 1 LSB In section Straight Binary 16383 at AIN AREF 1 LSB should be changed to 16383 AIN AREF 1 LSB Table 5 In section TM2 0 Test Mode 010 IN at VREF 2 IN at REF changed to 010 IN at Voltage at CML pin IN at REF Same section 110 IN at REF IN at VREF 2 changed to 110 IN at REF IN at VCM Voltage at CML pin Principles of Operation NOTE Page numbers for previous revisions may differ from page numbers in the current version 20 Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 14 Aug 2007 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp 9 Type Drawing Qty 5962 0051101NXD ACTIVE HTQFP PHP 48 250 Green RoHS amp CU NIPDAU 3 260 168 HR no Sb Br THS1401CPFB OBSOLETE TQFP PFB 48 TBD Call TI Call TI 51401 48 250 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br THS1401IPFBG4 ACTIVE TQFP PFB 48 250 Green RoHS amp CU NIPDAU 2 260 1 YEAR no Sb Br THS1401QPHP ACTIVE HTQFP PHP 48 TBD Call TI Call TI THS1403CPFB OBSOLETE TQFP PFB 48 TBD Call TI Call TI THS1403IPFB ACTIVE TQFP PFB 48 250 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br THS1403IPF
23. sing an external precision reference in case very high dc accuracy is needed The REF and REF outputs are given by REF 2 and REF If the built in reference is used VBG equals 1 5 V which results in REF 2 5 V REF 0 5 V and AREF 2 V The internal reference can be disabled by writing 1 to D12 REF in the control register address 3 The band gap reference is then disconnected and can be substituted by a voltage on the VBG pin programmable gain amplifier The on chip programmable gain amplifier PGA has eight gain settings The gain can be changed by writing to the PGA gain register address 1 The range is 0 to 7dB in steps of one dB out of range indication The OV output of the ADC indicates an out of range condition Every time the difference on the analog inputs exceeds the differential reference this signal is asserted This signal is updated the same way as the digital data outputs and therefore subject to the same pipeline delay offset compensation With the offset register it is possible to automatically compensate system offset errors including errors caused by additional signal THS1401 THS1403 THS1408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 conditioning circuitry If the offset compensation is enabled D7 OFF in the control register the value in the offset register address 2 is automatically added to the output of the ADC In order to set the correct value of t
24. tellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that ma
25. tial configuration If the application requires the best SNR SFDR and THD performance the input should be transformer coupled The signal amplitude on both inputs of the ADC is one half as high as in a single ended configuration thus increasing the ADC ac performance 220 IN THS1401 3 8 uF Figure 20 Transformer Coupled The following table shows the input voltages for negative full scale output zero output and positive full scale output IN OUTPUT PEAK full scaleT 0 0 AREF full scalet Tn 1 winding ratio The resistor R of the transformer coupled input configuration must be set to match the signal source impedance R n Rs where Rs is the source impedance and n is the transformer winding ratio APPLICATION INFORMATION single ended configuration In this configuration the input signal is level shifted by AREF 2 17 THS1401 497 THS1403 INSTRUMENTS THS1 408 www ti com SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 10 10 REF 10 0 10kQ2 100 pF t 10 10 gt Figure 21 Single Ended With Level Shift THS1401 3 8 IN REF 100 pF The following table shows the input voltages for negative full scale output zero output and positive full scale output AIN V OUTPUT AREF full scale 0 0 AREF full s
26. ve low DGND 9 15 25 33 34 Digital ground DVpp 14 20 26 30 31 42 Digital power supply D 13 0 11 12 13 16 17 18 Data inputs outputs 19 21 22 23 24 27 28 29 NC 38 39 No connection do not use Reserved IN 48 Positive differential analog input IN 1 Negative differential analog input OE 35 Output enable Active low OV 10 Out of range output REF 5 Positive reference output This pin requires a 0 1 uF capacitor to AGND REF Negative reference output This pin requires 0 1 uF capacitor to AGND VBG 3 Reference input This pin requires 1 uF capacitor to AGND WR 36 Write signal Active low 351 THS1401 INSTRUMENTS THS1403 www ti com THS1 408 SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 PFB AND PHP PACKAGE TOP VIEW NC No internal connection AVAILABLE OPTIONS PACKAGED DEVICE TQFP PQFP Power Pad PFB PHP THS1401CPFB 0 C to 70 C THS1403CPFB THS1408CPFB THS1401IPFB 40 to 85 C 14031 THS1408IPFB THS1401QPHP 40 C to 125 C THS1403QPHP THS1408QPHP 55 C to 125 C THS1408MPHP THS1401 THS1403 Texas INSTRUMENTS THS1 408 www ti com SLAS248D DECEMBER 1999 REVISED SEPTEMBER 2005 THERMAL CHARACTERISTICS 1 TYP UNIT mE 859 Thermal resistance junction to ambient O JA PHP package 288 C W PFB package
27. w ti com 49 6 THERMAL PAD MECHANICAL DATA INSTRUMENTS 5 648 Zu ERMAL INFORMA TION This PowerPAD package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink The thermal pad must be soldered directly to the printed circuit board PCB After soldering the PCB can be used as a heatsink In addition through the use of thermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities refer to Technical Brief PowerPAD Thermally Enhanced Package Texas Instruments Literature No SLMAO02 and Application Brief PowerPAD Made Easy Texas Instruments Literature No SLMAOO4 Both documents are available at www ti com The exposed thermal pad dimensions for this package are shown in the following illustration 36 25 37 24 Exposed Thermal 4 84 4 00 48 13
28. y be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is Solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti co

TEXAS INSTRUMENTS THS1401 THS1403 THS1408 handbook

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