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TEXAS INSTRUMENTS THS1209 handbook(1)

1. Po 0 Po po ps o o 2777 3 9 fo p Papo fo 0 reeves E Pa fs Po fo 5 reeves S 3 E E EO EO a fo 5 pese Pap BEDS OM E EE test mode The test mode of the ADC is selected via bit 8 and bit 9 of control register 0 The different selections are shown in Table 11 Table 10 Test Mode BIT 9 BIT8 TEST1 TESTO OUTPUT RESULT Lo 0 1 1 0 VnEEMMVREEP2 Three different options be selected This feature allows support testing of hardware connections between the ADC and the processor d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 15 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 analog input channel selection continued conirol register 1 see Table 8 sre ere en7 ens ors e
2. 1 5 V and 3 5 V are provided An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application The THS1209C is characterized for operation from 0 C to 70 C and the THS12091l is characterized for operation from 40 C to 85 C AVAILABLE OPTIONS PACKAGED DEVICE TA TSSOP DA 0 C to 70 THS1209CDA 40 C to 85 C THS1209IDA Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright 2000 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments L standard warranty Production processing does not necessarily include testing of all parameters EXAS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 functional block diagram REFP REFM RERIN Single Ended and or AINP ise AINM D CONV CLK D10 RAO 50 D11 RA1 Zn Register __ RD Control g WR R W Sou 5 d TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVE
3. AVpp 5 V DVpp BVpp 3 V fin 500 kHz Al fin 500 kHz AIN 1 dBFS o 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 fs Sampling Frequency MHz fs Sampling Frequency MHz Figure 17 Figure 18 d TEXAS INSTRUMENTS 24 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION VS INPUT FREQUENCY SINGLE ENDED THD Total Harmonic Distortion dB AVpp 5 V DVpp BVpp 3 V fs 8 MSPS AIN 1 dBFS 0 05 1 015 20 25 30 35 40 fj Input Frequency MHz Figure 19 SPURIOUS FREE DYNAMIC RANGE VS INPUT FREQUENCY SINGLE ENDED AVpp 5 V DVpp BVpp 3 V fs 8 MSPS 1 dBFS SFDR Spurious Free Dynamic Range dB 0 05 10 15 20 25 3 0 35 40 f Input Frequency MHz Figure 21 SINAD Signal to Noise and Distortion dB SNR Signal to Noise dB SIGNAL TO NOISE AND DISTORTION VS INPUT FREQUENCY SINGLE ENDED AVpp 5 V DVpp BVpp 3 V fs 8 MSPS AIN 1 dB 0 05 10 15 20 25 30 35 40 fj Input Frequency MHz Figure 20 SIGNAL TO NOISE VS INPUT FREQUENCY SINGLE ENDED AVpp 5 V DVpp BVpp 3 V fs 8 MSPS AIN 1 dBFS 0 05 10 15 20 25 30 3 5 4 0 fj Input Frequency MHz Figure 22 d TEXAS INSTRUM
4. active while the write input WR is inactive The first of those external signals going to its inactive state will then deactivate again Writing to the THS1209 takes place by an internal WRint signal which is generated from the logical combination of the external signals CSO CS1 and WR This signal is then used to strobe the control words into the control registers 0 and 1 The last external signal either CS0 CS1 or WR to become valid will make WRint active while the read input RD is inactive The first of those external signals going to its inactive state will then deactivate WRint again gt cs1 e RD WRint WR lt Control Data Registers Data Bits Figure 4 Logical Combination of CS0 CS1 RD and WR d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 17 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 timing and signal description of the THS1209 continued read timing using R W CSO controlled Figure 5 shows the read timing behavior when the WR R W input is programmed as a combined read write input R W The RD input has to be tied to high level in this configuration This timing is called CSO controlled because CS0 is the last external signal of CSO CS1 and RW which becomes valid The reading of the data should be done with a certain timing re
5. converter The THS1209 uses a 12 bit pipelined multistaged architecture which achieves a high sample rate with low power consumption The THS1209 distributes the conversion over several smaller ADC sub blocks refining the conversion with progressively higher accuracy as the device passes the results from stage to stage This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC A sample and hold amplifier SHA within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples conversion An external clock signal with a duty cycle of 50 has to be applied to the clock input CONV A new conversion is started with every falling edge of the applied clock signal The conversion values are available at the output with a latency of 5 clock cycles sampling rate The maximum possible conversion rate per channel is dependent on the selected analog input channels Table 1 shows the maximum conversion rate for different combinations Table 1 Maximum Conversion Rate The maximum conversion rate in the continuous conversion mode per channel fc is given by 8 MSPS channels d TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 convers
6. first code transition The full scale point is defined as level 1 2 LSB beyond the last code transition The deviation is measured from the center of each particular code to the true straight line between these two points differential nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart DNL is the deviation from this ideal value A differential nonlinearity error of less than 1 LSB ensures no missing codes zero offset The major carry transition should occur when the analog input is at zero volts Zero error is defined as the deviation of the actual transition from that point gain error The first code transition should occur at an analog value 1 2 LSB above negative full scale The last transition should occur at an analog value 1 1 2 LSB below the nominal full scale Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions signal to noise ratio distortion SINAD SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc The value for SINAD is expressed in decibels effective number of bits ENOB For a sine wave SINAD can be expressed in terms of the number of bits Using the following formula SINAD 1 76 6 02 it is possible to get a measure of performance expressed as N
7. not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Te publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated
8. 0 Q in differential configuration Sinewave cS UB o 9 qve Small signal bandwidth with a source impedance of E 150 Q in single ended configuration DEER timing specifications AVpp DVpp 5 V BVpp 3 3 V Vr_er Internal lt 30 pF PARAMETER TEST CONDITIONS MAX UNIT CONV td pipe Latency 5 CLK su READH CONV_CLKL Setup ime OSinvalidto fr 5 Delay ime CONV td CONV CLKL SYNCH Delay time low SYNC high d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 detailed description reference voltage The THS1209 has a built in reference which provides the reference voltages forthe ADC VREFP is setto 3 5 V and VREFM is set to 1 5 V An external reference can also be used through two reference input pins REFP and REFM if the reference source is programmed as external The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full scale and zero scale reading respectively analog inputs The THS1209 consists of two analog inputs which are sampled simultaneously These inputs can be selected individually and configured as single ended or differential inputs The desired analog input channel can be programmed
9. 000 ADC Code Figure 31 INTEGRAL NONLINEARITY vs ADC CODE PON Y 2 d AVpp 5 DVpp BVpp 3 fs 8 MSPS 0 500 1000 1500 2000 2500 3000 3500 4000 ADC Code Figure 32 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 Magnitude dB Magnitude dB THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM 4096 POINTS SINGLE ENDED vs FREQUENCY AVpp 5 V DVpp BVpp 3 V fs 8 MSPS AIN 1 dBFS fin 1 25 MHz 0 1000000 2000000 3000000 4000000 f Frequency Hz Figure 33 FAST FOURIER TRANSFORM 4096 POINTS DIFFERENTIAL VS FREQUENCY AVpp 5 V DVpp BVpp 3 V fs 8 MSPS AIN 1 dBFS fin 1 25 MHz 0 1000000 2000000 3000000 4000000 f Frequency Hz Figure 34 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 29 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 definitions of specifications and terminology integral nonlinearity Integral nonlinearity refers to the deviation of each individual code from aline drawn from zero through full scale The point used as zero occurs 1 2 LSB before the
10. Data N 4 Data N 3 Data 2 Data N 1 Data N Data 1 Data 2 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 T READ is the logical combination from CSO CS1 and RD Figure 1 Conversion Timing in 1 Channel Operation d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 Figure 3 shows the conversion timing when two analog input channels are selected The maximum throughput rate per channel is 4 MSPS in this mode The data flow in the bottom of the figure shows the order the converted data is available to the data bus The SYNC signal is always active low if data of channel 1 is available to the data bus There is a certain timing relationship required for the read signal with respect to the conversion clock This can be seen in Figure 2 and Table 2 A more detailed description of the timing is given in the section timing and signal description of the THS1209 Sample N Sample N 1 Sample N 2 Sample N 3 Sample N 4 Channel 1 2 Channel 1 2 Channel 1 2 Channel 1 2 Channel 1 2 AIN gt Ie b 4 tw CONV CLKH K l tw CONV_CLKL CONV CLK K te 4 dk es tsu READH CONV CLKL tsu CONV CLKL READL td CONV CLKL SYNCL e td CONV CLKL SYNCH SYNC Channel 1 Channel 2 Channel 1 Channel 2 Channel 1 Channel 2 Channel 1 t
11. ENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 25 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL TO NOISE AND DISTORTION vs vs INPUT FREQUENCY DIFFERENTIAL INPUT FREQUENCY DIFFERENTIAL AVpp 5 V DVpp BVpp 3 V fs 8 MSPS AIN 1 dBFS THD Total Harmonic Distortion dB AVpp 5 V DVpp BVpp 3 V fs 8 MSPS AIN 1 dBFS SINAD Signal to Noise and Distortion dB 0 05 10 15 20 25 30 35 40 0 05 10 15 20 25 30 35 40 f Input Frequency MHz fj Input Frequency MHz Figure 23 Figure 24 SPURIOUS FREE DYNAMIC RANGE SIGNAL TO NOISE vs vs INPUT FREQUENCY DIFFERENTIAL INPUT FREQUENCY DIFFERENTIAL m AVpp 5 V DVpp BVpp MSPS AIN 1 dBFS 5 5 c S 8 8 2 o g o m ei tc m AVpp 5 V fs 8 MSPS AIN 1 dBFS 0 05 10 15 20 25 30 35 40 fj Input Frequency MHz fj Input Frequency MHz Figure 25 Figure 26 d TEXAS INSTRUMENTS 26 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 ENOB Effective Number of Bits Bits ENOB Effective Number of Bits Bits THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BI
12. READ is the logical combination from CSO CS1 and RD Figure 2 Conversion Timing in 2 Channel Operation d TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 digital output data format The digital output data format of the THS1209 can be in either binary format or in twos complement format The following tables list the digital outputs for the analog input voltages Table 2 Binary Output Format for Single Ended Configuration SINGLE ENDED BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN VREFP FFFh AIN VREFP VREFM 2 800h AIN VREFM 000h Table 3 Twos Complement Output Format for Single Ended Configuration Table 4 Binary Output Format for Differential Configuration Vin AINP AINM Vin VREF Vin 0 Vin VREF 000h Table 5 Twos Complement Output Format for Differential Configuration DIFFERENTIAL BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE Vin AINP AINM VREF VREFP VREFM Vin VREF 7FFh Vin VREF 800h d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 11 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 ADC control register The THS1209 contains two 10 bit wide control registers CRO CR1 in order to program the device i
13. RTER SLAS288 JULY 2000 Terminal Functions TERMINAL yo DESCRIPTION NAME NO Analog input single ended or positive input of differential channel A Analog input single ended or negative input of differential channel A AINP 3 AINM 2 AVDD 23 2 0 9 Analog supply voltage AGND 24 5 1 Woo 7 CON tK i SYNC 3 paesi m MSN 1 Pista supe votagerorbufer 71 Dstageundforbufer S Tris E 1 E Chip select input active low Chip select input active high Synchronization output This signal indicates in a multi channel operation that data of channel A is brought to the digital output and can therefore be used for synchronization DGND Digital ground Ground reference for digital circuitry DVDD Digital supply voltage DO D9 1 6 9 12 7 Digital input output DO LSB RA0 D10 3 7 Digital input output The data line D10 is also used as an address line RAO for the control register This is required for writing to control register 0 and control register 1 See Table 8 RA1 D11 4 VO Z Digital input output 011 MSB The data line D11 is also used as an address line RA1 for the control register This is required for writing to control register 0 and control register 1 See Table 8 C REFIN 28 Common mode reference input for the analog input channels It is recommended that th
14. TH S1209 Ny 9 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 DA PACKAGE TOP VIEW features Simultaneous Sampling of 2 Single Ended Signals or 1 Differential Signal Signal to Noise Ratio 68 dB at 2 MHz Differential Nonlinearity Error 1 LSB Integral Nonlinearity Error 1 5 LSB Auto Scan Mode for 2 Inputs 3 V or 5 V Digital Interface Compatible Low Power 218 mW Max at 5 V Power Down 1 mW Max 5 V Analog Single Supply Operation Internal Voltage References 50 PPM C and 5 Accuracy Glueless DSP Interface Parallel uC DSP Interface applications Radar Applications Communications Control Applications High Speed DSP Front End Automotive Applications description The THS1209 is a CMOS low power 12 bit 8 MSPS analog to digital converter ADC The speed resolution bandwidth and single supply operation are suited for applications in radar imaging high speed acquisition and communications A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range Internal control registers allow for programming the ADC into the desired mode The THS1209 consists of two analog inputs which are sampled simultaneously These inputs can be selected individually and configured to single ended or differential inputs Internal reference voltages for the ADC
15. TS VS SAMPLING FREQUENCY SINGLE ENDED AVpp 5 V DVpp BVpp 3 V fin 500 kHz AIN 1 dBFS 1 2 3 4 5 6 7 8 fs Sampling Frequency MHz Figure 27 EFFECTIVE NUMBER OF BITS VS INPUT FREQUENCY SINGLE ENDED 0 05 1 0 15 20 25 30 35 fj Input Frequency MHz Figure 29 4 0 ENOB Effective Number of Bits Bits ENOB Effective Number of Bits Bits EFFECTIVE NUMBER OF BITS VS SAMPLING FREQUENCY DIFFERENTIAL 0 1 2 3 4 5 6 7 8 9 fs Sampling Frequency MHz Figure 28 EFFECTIVE NUMBER OF BITS VS INPUT FREQUENCY DIFFERENTIAL AVpp 5 V DVpp BVpp 3 V fs 8 MSPS AIN 1 dBFS 0 05 1 015 20 25 30 3 5 40 fj Input Frequency MHz Figure 30 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 27 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 DNL Differential Nonlinearity LSB INL Integral Nonlinearity LSB 28 TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY vs ADC CODE AVpp 5V DVpp BVpp 3 V fs 8 MSPS ili T 0 500 1000 1500 2000 2500 3000 3500 4
16. URIOUS FREE DYNAMIC RANGE SIGNAL TO NOISE VS VS SAMPLING FREQUENCY SINGLE ENDED SAMPLING FREQUENCY SINGLE ENDED m S m c 9 z g o 2 8 d c 5 H AVpp 5 3 AVpp 5 DVpp BVpp 500 kHz AIN 1 dBFS fin 500 kHz AIN 1 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 fs Sampling Frequency MHz fs Sampling Frequency MHz Figure 13 Figure 14 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 23 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL TO NOISE AND DISTORTION vs vs SAMPLING FREQUENCY DIFFERENTIAL SAMPLING FREQUENCY DIFFERENTIAL THD Total Harmonic Distortion dB AVpp 5 V DVpp BVpp 3 V AVpp 5 V DVpp SINAD Signal to Noise and Distortion dB fin 500 kHz AIN 1 dBFS fin 500 kHz 0 1 2 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 fs Sampling Frequency MHz fs Sampling Frequency MHz Figure 15 Figure 16 SPURIOUS FREE DYNAMIC RANGE SIGNAL TO NOISE vs vs SAMPLING FREQUENCY DIFFERENTIAL SAMPLING FREQUENCY DIFFERENTIAL a 2 8 9 l E 2 E 2 a 5 Se m c 2 9 5 oc 2 o0 77 AVpp 5 V DVpp
17. Write 0x401 to THS1209 Set Reset Bit in CR1 Clear RESET By Clear RESET By Writing 0x400 to Writing 0x400 to CR1 CR1 Write the User Configuration to CRO Write the User Configuration to CR1 Must Exclude RESET Figure 3 51209 Configuration Flow d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 ADC control registers control register 0 see Table 8 C ere f ens any ame ems eva ema emi testi testo SCAN cHsELt cHSELO Po RES VREF Table 8 Control Register 0 Bit Functions RESET VREF Vref select Bit 0 0 The internal reference is selected Bit 0 1 The external reference voltage is selected Pao eee 2 Power down Bit 2 0 The ADC is active Bit 2 1 Power down The reading and writing to and from the digital outputs is possible during power down 3 4 CHSELO Channel select CHSEL1 Bit 3 and bit 4 select the analog input channel of the ADC Refer to Table 8 5 6 1 0 DIFFO DIFF1 Number of differential channels Bit 5 and bit 6 contain information about the number of selected differential channels Refer to Table 8 7 5 Autoscan enable Bit 7 enables or disables the autoscan function of the ADC Refer to Table 8 TESTO Test input enable TEST1 Bit 8 an
18. d bit 9 control the test function of the ADC Three different test voltages can be measured This feedback allows the check of all hardware connections and the ADC operation Refer to Table 8 for selection of the three different test voltages d TEXAS INSTRUMENTS 14 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 analog input channel selection The analog input channels of the THS1209 can be selected via bits 3 to 7 of control register 0 One single channel single ended or differential is selected via bit 3 and bit 4 of control register 0 Bit 5 controls the selection between single ended and differential configuration Bit 6 and bit 7 select the autoscan mode if more than one input channel is selected Table 10 shows the possible selections Table 9 Analog Input Channel Configurations BIT 7 BIT 6 BIT 5 A BIT3 CHS1 CHSO DESCRIPTION OF THE SELECTED INPUTS 0 manane Po fo o fo o _ iereniat rennet ANP ANM Po o 2777 000 OOS 3 9 2 mo singe ended channels ANP ANM ANE Fel jmeee 770000 Pa fe EO 27777 Pap 3 Pa po fs 5 reeves
19. ditions AVpp DVpp 5 V BVpp 3 3 V fs 8 MSPS Vgpgr internal unless otherwise noted dc specifications Gam 958 Analog input LIE Internal voltage reference Tememwecefdeg co Rdeexemke Power supply EE a Paw Power dissipation in power down with con Ji TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 electrical characteristics over recommended operating conditions internal f 8 MSPS fj 2 MHz at 1dBFS unless otherwise noted ac specifications AVpp DVpp 5 V BVpp 3 3 V C lt 30 pF 9 m YP 65 64 69 68 70 67 68 64 SNR Signal to noise ratio THD Total harmonic distortion 64 Differential mode 10 17 10 5 Effective number of bits SNR Single ended mode 10 103 Differential mode 67 71 SFDR Spurious free dynamic range Single ended mode 65 69 dB Analog Input Full power bandwidth with a source impedance of Full scale sinewave 3 dB MHz 150 Q in differential configuration Full power bandwidth with a source impedance of Full scale sinewave 3 dB 54 MHz 150 Q in single ended configuration Small signal bandwidth with a source impedance of 15
20. e Bit 9 1 enable debug mode When bit 9 of control register 1 is set to 1 debug mode is enabled In this mode the contents of control register 0 and control register 1 can be read back The first read after bit 9 is set to 1 contains the value of control register 0 The second read after bit 9 is set to 1 contains the value of control register 1 To bring the device back into normal conversion mode this bit has to be set back to 0 by writing again to control register 1 Ji TEXAS INSTRUMENTS 16 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 timing and signal description of the THS1209 The reading from the THS1209 and writing to the THS1209 is performed by using the chip select inputs 50 CS1 the write input WR and the read input RD The write input is configurable to a combined read write input R W This is desired in cases where the connected processor consists of a combined read write output signal R W The two chip select inputs can be used to interface easily to a processor Reading from the THS1209 takes place by an internal RDj signal which is generated from the logical combination of the external signals CS0 CS1 and RD see Figure 4 This signal is then used to strobe the words outand to enable the output buffers The last external signal either 50 CS1 or RD to become valid will make RDin
21. e use of ratio matched thin film resistor networks minimizes gain and offset errors Ry 35V 25V CL 5V 15V IN R4 ie Rs THS1209 weg AINP 1 25 V T REFIN REFOUT Figure 9 Level Shift for DC Coupled Input differential mode of operation For the differential mode of operation a conversion from single ended to differential is required A conversion to differential signals can be achieved by using an RF transformer which provides a center tap Best performance is achieved in differential mode Mini Circuits T4 1 49 9 0 R THS1209 AINP Q deme R che C 10 uF Figure 10 Transformer Coupled Input d TEXAS INSTRUMENTS 22 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL TO NOISE AND DISTORTION VS VS SAMPLING FREQUENCY SINGLE ENDED SAMPLING FREQUENCY SINGLE ENDED AVpp 5 V DVpp BVpp 3 V AVpp 5 V DVpp 500 kHz AIN 1 dBFS fin 500 kHz AIN THD Total Harmonic Distortion dB SINAD Signal to Noise and Distortion dB 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 fs Sampling Frequency MHz fs Sampling Frequency MHz Figure 11 Figure 12 SP
22. etter signal to noise ratio Figure 8 shows a simplified model for the analog inputs AINM and AINP which are configured for differential operation The differential operation mode provides in terms of performance benefits over the single ended mode and is therefore recommended for best performance The THS1209 offers 1 differential analog input and in the single ended mode 2 analog inputs If the analog input architecture id differential common mode noise and common mode voltages can be rejected Additional details for both modes are given below AINP AINM Figure 8 Differential Input Stage In comparison to the single ended configuration it can be seen that the voltage Vapc which is applied at the input of the ADC is the difference between the input AINP and AINM The voltage Vapc can be calculated as follows Vapc ABS AINP AINM 2 An advantage to single ended operation is that the common mode voltage 20 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 analog input configuration and reference voltage continued V AINM AINP CM 2 3 can be rejected in the differential configuration if the following condition for the analog input voltages is true AGND lt AINM AINP lt AVpp 4 1 lt Vom lt 4V 5 single ended mode of operation The THS1209 can be configu
23. ion mode During conversion the ADC operates with a free running external clock signal applied to the input CONV With every falling edge of the CONV CLK signal a new converted value is available to the databus with the corresponding read signal The THS1209 offers up to two analog inputs to be selected It is important to provide the channel information to the system this means to know which channel is available to the databus To maintain this channel integrity the THS1209 an output signal SYNC which is always active low if data of channel 1 is applied to the databus Figure 3 shows the timing of the conversion when one analog input channel is selected The maximum throughput rate is 8 MSPS in this mode The signal SYNC is disabled for the selection of one analog input since this information is not required for one analog input There is a certain timing relationship required for the read signal with respect to the conversion clock This can be seen in Figure 2 and Table 2 A more detailed description of the timing is given in the section timing and signal description of the THS1209 SampleN Sample N 1 Sample N 2 Sample N 3 Sample N 4 Sample N 5 Sample N 6 Sample N 7 Sample N 8 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 AIN p E Wa a pipe gt tw CONV_CLKH ken tw CONV_CLKL CONV CLK kte l tsu READH_CONV CLKL tsu CONV_CLKL READL READT
24. is pin be connected to the reference output REFOUT REFP 26 Reference input requires a bypass capacitor of 10 uF to AGND in order to bypass the internal reference voltage An external reference voltage at this input can be applied This option can be programmed through control register 0 See Table 9 REFM 25 Reference input requires a bypass capacitor of 10 uF to AGND in order to bypass the internal reference voltage An external reference voltage at this input can be applied This option can be programmed through control register 0 See Table 9 RESET Hardware reset of the THS1209 Sets the control register to default values 27 REFOUT Analog fixed reference output voltage of 2 5 V Sink and source capability of 250 uA The reference output requires a capacitor of 10 uF to AGND for filtering and stability RDf 19 TheRD inputis usedonly ifthe WR inputis configured as a write only input In this case itis a digital input active low as a data read select from the processor See timing section WR R W f 20 This input is programmable It functions as a read write input R W and can also be configured as a write only input WR which is active low and used as data write select from the processor In this case the RD input is used as a read input from the processor See timing section 2 2 1 1 ers e N T The start conditions of RD and WR R W are unknown The first access to the ADC has to be a w
25. lative to the conversion clock CONV CLK as illustrated in Figure 5 tsu CSOH CONV_CLKL lsu CONV CLKL CSOL CONV_CLK 4 tw CS gt SS 10 ml CS1 N 4 tsu R W th R w nk R W 90 90 RS 90 90 D 0 11 Figure 5 Read Timing Diagram Using R W CS0 controlled read timing parameter CSO controlled t ps ta Access time last CS valid to data valid th Hold time first CS invalid to data invalid th R W Hold time first external CS invalid to R W change tw CS Pulse duration CS active tcs CSO d TEXAS INSTRUMENTS 18 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 timing and signal description of the THS1209 continued write timing using R W CSO controlled Figure 12 shows the write timing behavior when the WR R W input is programmed as a combined read write input R W The RD input has to be tied to high level in this configuration This timing is called CSO controlled because CS0 is the last external signal of CSO CS1 and R W which becomes valid The writing to the THS1209 can be performed irrespective of the conversion clock signal CONV CLK 4 tw CS gt 90 50 10 10 CS1 e tsu R W th R W R W 40 10 RD 4 tsu ig gt th 90 90 D 0 11 Figure 6 Write Timing Diagram U
26. n of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability recommended operating conditions power supply Supply voltage analog and reference inputs fa digital inputs BVpp 33 V gt Dow High level input voltage VIH EL 5 25 V 2 8 00 5 BVpp 3 3 V Low level input voltage VIL BV 5 25 V DD gt Input CONV CLK frequency DVpp 4 75 V to 5 25 V MHz CONV pulse duration clock high ty GONV CLKH DVpp 4 75 V to 5 25 V 62 62 5000 pulse duration clock low ty CONV CLKL DVpp 4 75 V to 5 25 V 62 62 5000 THS1209CDA 0 Operating free air temperature TA THSIZ0SIDA 10 d TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 electrical characteristics over recommended operating conditions AVpp DVpp 5 V BVpp 3 3 V unless otherwise noted digital specifications Digital inputs ies Digital outputs REECH I9 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 electrical characteristics over recommended operating con
27. nto the desired mode The bit definitions of both control registers are shown in Table 7 Table 6 Bit Definitions of Control Register CRO and CR1 testo scan orri oiro onse po writing to control register 0 and control register 1 The 10 bit wide control register 0 and control register 1 can be programmed by addressing the desired control register and writing the register value to the ADC The addressing is performed with the upper data bits D10 and 011 which function in this case as address lines RAO and DAT During this write process the data bits DO to D9 contain the desired control register value Table 8 shows the addressing of each control register Table 7 Control Register Addressing DO 09 D10 RAO D11 RA1 Addressed Control Register Desired register value 0 Control register 0 Control register 1 Desired register value o Desired register value 1 Reserved for future i Desired register value Reserved for future d TEXAS INSTRUMENTS 12 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 initialization of the THS1209 The initialization of the THS1209 should be done according to the configuration flow shown in Figure 3 Use Default Values Write 0x401 to THS1209 Set Reset Bit in CR1
28. out notice Body dimensions do not include mold flash or protrusion Falls within JEDEC MO 153 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 31 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the rightto make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does
29. ra ens an s aro RBack orrseT ous mW RES RES RES RES RES RESET Table 11 Control Register 1 Bit Functions RESET RESET Reset Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values To bring the device out of reset a 0 has to be written into this bit gt ms os RW RW RD WR selection Bit 6 of control register 1 controls the function of the inputs RD and WR When bit 6 in control register 1 is set to 1 WR becomes a R W input and RD is disabled From now on a read is signalled with R W high and a write with R W as a low signal If bit 6 in control register 1 is set to 0 the input RD becomes a read input and the input WR becomes a write input 7 BIN 2s Complement select If bit 7 of control register 1 is set to 0 the output value of the ADC is in twos complement If bit 7 of control register 1 is setto 1 the outputvalue ofthe ADC is in binary format Referto Table 20 through Table 23 OFFSET Offset cancellation mode Bit 8 0 normal conversion mode Bit 8 1 offset calibration mode If a 1 is written into bit 8 of control register 1 the device internally sets the inputs to zero and does a con version The conversion result is stored in an offset register and subtracted from all conversions in order to reduce the offset error RBACK Debug mode Bit 9 0 normal conversion mod
30. red for single ended operation using dc or ac coupling In every case the input of the THS1209 should be driven from an operational amplifier that does not degrade the ADC performance Because the THS1209 operates from a 5 V single supply it is necessary to level shift ground based bipolar signals to comply with its input requirements This can be achieved with dc and ac coupling d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 21 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 dc coupling An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the THS1209 The analog input voltage range of the THS1209 goes from 1 5 V to 3 5 V An op amp can be used as shown in Figure 9 Figure 9 shows an example where the analog input signal in the range from 1 V up to 1 V is shifted by an operational amplifier to the analog input range of the THS1209 1 5 V to 3 5 V The operational amplifier is configured as an inverting amplifier with a gain of 1 The required dc voltage of 1 25 V at the noninverting input is derived from the 2 5 V output reference REFOUT of the THS1209 by using a resistor divider Therefore the op amp output voltage is centered at 2 5 V The 10 uF tantalum capacitor is required for bypassing REFOUT REFIN ofthe THS1209 must be connected directly to REFOUT in single ended mode Th
31. rite access to initialize the ADC d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 absolute maximum ratings over operating free air temperature unless otherwise noted t Supply voltage range DGND to DVDD 0 3 V to 8 5 V BOND t BV pp t pb a pue Ri EEN 0 3 V to 8 5 V AGND to AVDD iii bu hee e takes b debida 0 3 V to 8 5 V Analog input voltage range AGND 0 3 V to AVpp 1 5 V heference Input voltage eee emet remet wares 0 3 AGND to AVpp 0 3 V Digital input voltagerange 0 3 V to BVpp DVpp 0 3 V Operating virtual junction temperature range 40 C to 150 C Operating free air temperature range THS1209C 0 C to 70 C WHS 209 uerg e be EE RE AA 40 C to 85 C Storage temperature range KG qu hence dads 85 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operatio
32. sing R W CS0 controlled write timing parameter CSO controlled PARAMETER MIN UNIT tsu R W X Setup time RW stable to last CS valid 201 t Setup time data valid to first CS invalid t Hold time first CS invalid to data invalid th R W Hold time first CS invalid to R W change su h tw CS Pulse duration CS active d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 19 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 analog input configuration and reference voltage The THS1209 features two analog input channels These can be configured for either single ended or differential operation Figure 7 shows a simplified model where a single ended configuration for channel AINP is selected The reference voltages forthe ADC itself are and Vngry either internal or external reference voltage The analog input voltage range goes from to Vngrp This means that defines the minimum voltage and defines the maximum voltage which can be applied to the ADC The internal reference source provides the voltage Vperm of 1 5 V and the voltage of 3 5 V The resulting analog input voltage swing of 2 V can be expressed by V lt AINP V REFM REFP 1 AINP VREFM Figure 7 Single Ended Input Stage A differential operation is desired for many applications due to a b
33. the effective number of bits Thus effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD total harmonic distortion THD THD is the ratio of the rms sum ofthe first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels spurious free dynamic range SFDR SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal d TEXAS INSTRUMENTS 30 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1209 12 BIT 2 ANALOG INPUT 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER SLAS288 JULY 2000 MECHANICAL DATA DA R PDSO G PLASTIC SMALL OUTLINE PACKAGE 38 PINS SHOWN 0 15 NOM l f Gage Plane Y d Y Seating Plane d 20 MAX Z 0 10 PINS 4040066 D 11 98 NOTES A Alllinear dimensions are in millimeters This drawing is subject to change with

TEXAS INSTRUMENTS THS1209 handbook(1)

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