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TEXAS INSTRUMENTS THS1206 handbook

1. 4040066 D 11 98 NOTES A Alllinear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion Falls within MO 153 gom 35 TEXAS INSTRUMENTS 40 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the rightto make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using TI components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by
2. Table 4 Two s Complement Output Format for Single Ended Configuration SINGLE ENDED TWOS COMPLEMENT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN VREFP 7FFh AIN VREFP VREFM 2 000h 800h AIN VREFM Table 5 Binary Output Format for Differential Configuration DIFFERENTIAL BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE Vin AINP AINM VREF VREFP VREFM Vin VREF FFFh Vin 0 800h 000h Vin VREF Table 6 Two s Complement Output Format for Differential Configuration DIFFERENTIAL BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE Vin AINP AINM VREF VREFP VREFM Vin VREF 7FFh Vin 0 000h 800h Vin VREF 5 TEXAS INSTRUMENTS POST OFFICE 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 FIFO description In order to facilitate an efficient connection to today s processors the THS1206 is supplied with a FIFO This integrated FIFO enables a problem free processing of data with today s processors The FIFO is provided as a flexible circular buffer The circular buffer integrated in the THS1206 can store up to 16 conversion values Therefore the amount of interrupts to be served by a processor can be reduced significantly Read Pointer CN Data in FIFO Free Write Pointer Figure 6 Circular
3. REVISED APRIL 2000 Terminal Functions TERMINAL y o DESCRIPTION NAME AINP ET Analog input single ended or positive input of differential channel A AINM Analog input single ended or negative input of differential channel A BINP Analog input single ended or positive input of differential channel B BINM Analog input single ended or negative input of differential channel B AVDD Analog supply voltage AGND 4 Analog ground BVpp 7 Digital supply voltage for buffer BGND Digital ground for buffer CONV_CLK CONVST 15 Digital input This input is used to apply an external conversion clock in continuous conversion mode In single conversion mode this input functions as the conversion start CONVST input A high to low transition on this input holds simultaneously the selected analog input channels and initiates a single conversion of all selected analog inputs DATA AV 16 Data available signal which can be used to generate an interrupt for processors and as a level information of the internal FIFO This signal can be configured to be active low or high and can be configured as a static level or pulse output See Table 14 DGND Digital ground Ground reference for digital circuitry DVDD Digital supply voltage DO D9 1 6 9 12 0 2 Digital input output DO LSB D10 RAO 13 l O Z Digital input output The data line D10 is also used as an address line
4. THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 TYPICAL CHARACTERISTICS GAIN vs INPUT FREQUENCY SINGLE ENDED AVpp 5 V DVpp BVpp 3 V fs 6 MHz AIN 0 5 dB FS 0 10 20 30 40 50 60 70 80 90 100 110 120 fj Input Frequency MHz Figure 41 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 37 38 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM 4096 POINTS SINGLE ENDED vs FREQUENCY AVpp 5 V DVpp BVpp 3 V fs 6 MHz AIN 0 5 dB FS Magnitude dB 0 500000 1000000 1500000 2000000 2500000 3000000 3500000 f Frequency Hz Figure 42 FAST FOURIER TRANSFORM 4096 POINTS DIFFERENTIAL vs FREQUENCY AVpp 5 V DVpp BVpp fs 6 MHz AIN 0 5 dB FS Magnitude dB 0 500000 1000000 1500000 2000000 2500000 3000000 3500000 f Frequency Hz Figure 43 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity Integral nonlin
5. The test mode of the ADC is selected via bit 8 and bit 9 of control register 0 The different selections are shown in Table 11 Table 11 Test Mode BIT9 BIT8 TEST1 TESTO OUTPUT RESULT VREFP 9 VREFM VREFP 2 Three different options be selected This feature allows support testing of hardware connections between the ADC and the processor 35 TEXAS INSTRUMENTS 20 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 analog input channel selection continued control register 1 see Table 8 ens pes p ens ome ems ena smi mo BACK Bizs RW patap DATA T TRIGO OVFL FRST RESET Table 12 Control Register 1 Bit Functions RESET B di i T l Reset Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values In addition the FIFO pointer and offset register is reset After reset it takes 5 clock cycles until the first value is converted and written into the FIFO Overflow flag read only Bit 1 of control register 1 indicates an overflow in the FIFO Bit 1 0 no overflow occurred Bit 1 1 an overflow occurred This bit is reset to 0 after this control register is read from the processor FRST FIFO rese
6. RAO for the control register This is required for writing to the control register 0 and control register 1 See Table 8 D11 RA1 l O Z Digital input output D11 MSB The data line D11 is also used as an address line RA1 for the control register This is required for writing to control register 0 and control register 1 See Table 8 REFIN Common mode reference input for the analog input channels It is recommended that this pin be connected to the reference output REFOUT REFP 26 Reference input requires a bypass capacitor of 10 uF to AGND in order to bypass the internal reference voltage An external reference voltage at this input can be applied This option can be programmed through control register 0 See Table 9 REFM 25 Reference input requires a bypass capacitor of 10 uF to AGND in order to bypass the internal reference voltage An external reference voltage at this input can be applied This option can be programmed through control register 0 See Table 9 REFOUT 27 Analog fixed reference output voltage of 2 5 V Sink and source capability of 250 uA The reference output requires a capacitor of 10 uF to AGND for filtering and stability Rpt 19 The RD input is used only if the WR input is configured as a write only input In this case itis a digital input active low as a data read select from the processor See timing section WR R W T This input is programmable It functions as a read write input R W and can also be configured
7. level condition TRIGO 0 TRIG1 1 Delay time DATA_AV becomes active for the trigger Id DATA AV level condition TRIGO 1 TRIG1 1 t Timing parameters are ensured by design but are not tested p em s C mj 1 analog input TL 1 TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 detailed description reference voltage The THS1206 has a built in reference which provides the reference voltages for the ADC VREFP is setto 3 5 V and VREFM is setto 1 5 V An external reference can also be used through two reference input pins REFP and REFM if the reference source is programmed as external The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full scale and zero scale reading respectively analog inputs The THS1206 consists of 4 analog inputs which are sampled simultaneously These inputs can be selected individually and configured as single ended or differential inputs The desired analog input channel can be programmed converter The THS1206 uses a 12 bit pipelined multistaged architecture with 4 1 bit stages followed by 4 2 bit stages which achieves a high sample rate with low power consumption The THS1206 distributes the conversion over several smaller ADC sub blocks refining the conversion with progress
8. ADC itself are Vngrpand Vnggrw eitherinternalor exteral reference voltage The analoginputvoltage range goes from VREFM to Vngrp This means that Vpaggy defines the minimum voltage which can be applied to the ADC Vngrep defines the maximum voltage which can be applied to the ADC The internal reference source provides the voltage VngrM Of 1 5 V andthe voltage Vngrp of 3 5 V The resulting analog input voltage swing of 2 V can be expressed by V lt AINP lt V REFM REFP 1 VREFM Figure 17 Single Ended Input Stage 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 29 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 analog input configuration and reference voltage continued A differential operation is desired for many applications Figure 18 shows a simplified model for the analog inputs AINM and AINP which are configured for differential operation This configuration has a few advantages which are discussed in the following paragraphs AINP AINM Figure 18 Differential Input Stage In comparison to the single ended configuration it can be seen that the voltage Vapc which is applied at the input of the ADC is the difference between the input AINP and AINM This means that VREFM defines the minimum voltage VApc which can be applied to the ADC Vggrp defines the maximum voltage VADC which can be applied to
9. SS 4 iw RD RD 10 10 90 90 D 0 11 lt td CSDAV p 90 DATA AV Figure 15 Read Timing Diagram Using RD RD controlled read timing parameter RD controlled PARAMETER MIN TYP MAX UNIT tsu CS Setup time RD low to last CS valid ooo n ta Access time last CS valid to data valid td CSDAV Delay time last CS valid to DATA AV inactive th Hold time first CS invalid to data invalid thics Hold time RD change to first CS invalid 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 27 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 timing and signal description of the THS1206 continued write timing using WR WR controlled Figure 16 shows the write timing behavior when the WR R W input is programmed as a write input WR only The input RD acts as the read input in this configuration This timing is called WR controlled because WR is the last external signal of CSO CS1 and WR which becomes valid p E tsu CS th CS a 4 w WR N 10 oe D 0 11 ASSI SS Se SIS SP SP SOS 0000000000 SRR III MIKI DATA_AV 0 0 0 0 0 0 0 t 0 X LXXX XXX XXX X UK OX OX XX XXX OX XXX 2X OX OX XXX XXX XXX OX XX OX OX OX UK OX XX OX XXX X XXX OX OX OX OX XXX OX X Ox CL 0 0 0 LXXX LXXX XXX OX X X OX XX XXX X
10. UNIT tsu R W Setup time RAN high to last CS valid ooo jnm ta Access time last CS valid to data valid td CSDAV Delay time last CS valid to DATA AV inactive th Hold time first CS invalid to data invalid th R W Hold time first external CS invalid to R W change 35 TEXAS INSTRUMENTS 24 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 timing and signal description of the THS1206 continued write timing using R W CSO controlled Figure 14 shows the write timing behavior when the WR R W input is programmed as a combined read write input R W The RD input has to be tied to high level in this configuration This timing is called CSO controlled because CSO is the last external signal of CSO CS1 and R W which becomes valid iw CS 3 RN 90 cso 10 10 csi N amsa tsu R W WR 2 RD lt tsu p 4 tn 90 90 D 0 11 DATA_AV 5 0222222222 22222 Figure 14 Write Timing Diagram Using R W CS0 controlled write timing parameter RD controlled PARAMETER MIN TYP MAX UNIT tsu R W Setup time RAN stable to last CS valid ooo nmn 5 tsu Setup time data valid to first CS invalid th Hold time first CS invalid to data invalid 5 th R W Hold time first CS invalid to R W change os Pulse duration OS acive 5 TEXAS INSTRUMENTS PO
11. as a write only input WR which is active low and used as data write select from the processor In this case the RD input is used as a read input from the processor See timing section T The start conditions of RD and WR RAN are unknown The first access to the ADC has to be a write access to initialize the ADC i TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 absolute maximum ratings over operating free air temperature unless otherwise noted t Supply voltage range DGND to erris areiincsi duenic oii asidi III 0 3 V to 6 5 V BGND t BV pp t Cabe a a Ri eu 0 3 V to 6 5 V AGND to AVDD ercsi iussis uida bug ween takes b debida 0 3 V to 6 5 V Analog input voltage range AGND 0 3 V to AVpp 1 5 V heference Input voltage eee emet remet wares 0 3 AGND to AVpp 0 3 V Digital input voltage range sess 0 3 V to BVpp DVpp 0 3 V Operating virtual junction temperature range Ty 55 C to 150 C Operating free air temperature range Ta THS1206C 0 C to 70 C THS1206l 2 2 40 to 85 TEHS1206Q macaaqp 40 C to 125 C THS1206M eiue
12. can be selected to be sampled simultaneously see Table 2 CONVST 9 t gt k ta A AIN OU TM MER CR dE NP y AV gt DATA AV Trigger Level 1 Figure 1 Timing of Single Conversion Mode The time to between consecutive starts of single conversions is dependent on the number of selected analog input channels The time Ay until DATA AV becomes active is given by tpATA Ay n X Lc This equation is valid for a trigger level which is equivalent to the number of selected analog input channels For all other trigger level conditions refer to the timing specifications of single conversion mode 35 TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 continuous conversion mode The internal clock oscillator used in the single conversion mode is switched off in continuous conversion mode In continuous conversion mode bit 1 of control register 0 set to 0 the ADC operates with a free running external clock signal With every rising edge of the CONV signal a new converted value is written into the FIFO Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected The maximum throughput rate is 6 MSPS in this mode The timing of the DATA AV
13. ere etc e depo 55 C to 125 C Storage temperature range Tstg nnn 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability DISSIPATION RATING TABLE TA lt 25 C DERATING FACTOR Ta 70 C TA 85 C TA 125 C POWER RATING ABOVE TA 25 POWER RATING POWER RATING POWER RATING 1453 mW 11 62 mW C t This is the inverse of the traditional junction to ambient thermal resistance RgJA Thermal resistances are not production tested and are for informational purposes only PACKAGE recommended operating conditions power supply LLL LN N War ww 4 75 5 525 Supply voltage 3 33 5 25 3 33 5 25 analog and reference inputs Analog input voltage in single ended configuration VREFM VREFP Common mode input voltage VCM in differential configuration 1 2 5 4 External reference voltage VRErp optional 3 5 AVpp 1 2 External reference voltage VREFM optional 1 4 1 5 Input voltage difference REFM 35 TEXAS INSTRUMENTS 4 POST OFFIC
14. fs 6 MHz AIN 0 5 dB FS 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 fi Input Frequency MHz Fiqure 36 vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 35 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITS vs vs SAMPLING FREQUENCY SINGLE ENDED SAMPLING FREQUENCY DIFFERENTIAL AVpp 5 V DVpp BVpp 3 V fs 6 MHz AIN 0 5 dB FS AVpp 5 V DVpp BVpp 3 V fs 6 MHz AIN 0 5 dB FS H ENOB Effective Number of Bits Bits ENOB Effective Number of Bits Bits 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 fs Sampling Frequency MHz fs Sampling Frequency MHz Figure 37 Figure 38 EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITS vs vs INPUT FREQUENCY SINGLE ENDED INPUT FREQUENCY DIFFERENTIAL AVpp 5 V DVpp BVpp 3 V fs 6 MHz AIN 0 5 dB FS lt ENOB Effective Number of Bits Bits ENOB Effective Number of Bits Bits 0 0 5 1 0 15 20 25 30 35 0 0 5 1 0 15 20 25 30 35 fj Input Frequency MHz fj Input Frequency MHz Figure 39 Figure 40 35 TEXAS INSTRUMENTS 36 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 G Gain dB
15. generated from the logical combination of the external signals CSO CS1 and WR This signal is then used to strobe the control words into the control registers 0 and 1 The last external signal either CSO CS1 or WR to become valid will make WR active while the read input RD is inactive The first of those external signals going to its inactive state will then deactivate WRint again cso D Read Enable CS1 e RD Write Enable WR Control Data Registers Data Bits Figure 12 Logical Combination of CS0 CS1 RD and WR 22 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 DATA AV type Bit 4 and bit 5 DATA T DATA P of control register 1 are used to program the signal DATA AV Bit 4 of control register 1 determines whether the DATA AV signal is static or a pulse Bit 5 of the control register determines the polarity of DATA AV This is shown in Table 14 Table 14 DATA AV Type BIT 5 4 DATA_P DATA_T DATASAV TYPE 0 i Active low pulse O Active high level The signal DATA AV is set to active when the trigger condition is satisified It is set back inactive independent of the DATA T selection pulse or level If level mode is chosen DATA AV is set inactive after the first of the TL T
16. multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range Internal control registers are used to program the ADC into the desired mode The THS1206 consists of four analog inputs which are sampled simultaneously These inputs can be selected individually and configured to single ended or differential inputs An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor connected to the ADC Internal reference voltages for the ADC 1 5 V and 3 5 V are provided An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application Two different conversion modes can be selected In single conversion mode a single and simultaneous conversion of up to four inputs can be initiated by using the single conversion start signal CONVST The conversion clock in single conversion mode is generated internally using a clock oscillator circuit In continuous conversion mode an external clock signal is applied to the CONV CLK input of the THS1206 The internal clock oscillator is switched off in continuous conversion mode The THS1206C is characterized for operation from 0 C to 70 C the THS1206l is characterized for operation from 40 C to 85 C the THS1206Q is characterized to meet the rigorous requirements of the automotive environment from 40 C to 125 C and the THS1206M is charac
17. 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 9 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 sampling rate continued Table 2 Maximum Conversion Rate in Single Conversion Mode NUMBER OF MAXIMUM CONVERSION CHANNEL CONFIGUHATION CHANNELS RATE PER CHANNEL 1 single ended channel 3 MSPS 2 single ended channels 2 2 MSPS 3 single ended channels 1 5 MSPS single ended and aferentalchames 3 L 12 5 8 single conversion mode In single conversion mode a single conversion of the selected analog input channels is performed The single conversion mode is selected by setting bit 1 of control register 0 to 1 A single conversion is initiated by pulsing the CONVST input On the falling edge of CONVST the sample and hold stages of the selected analog inputs are placed into hold simultaneously and the conversion sequence for the selected channels is started The conversion clock in single conversion mode is generated internally using a clock oscillator circuit The signal DATA AV data available becomes active when the trigger level is reached and indicates that the converted sample s is are written into the FIFO and can be read out The trigger level in the single conversion mode can be selected according to Table 13 Figure 1 shows the timing of the single conversion mode In this mode up to four analog input channels
18. AIN VREFM to VREFP Internal voltage reference V C and suffix 3 33 3 5 ccuracy and M suffix 3 3 3 5 3 67 V 3 7 C and suffix 1 42 1 5 1 58 Accuracy VREFM V Q and M suffix 1 3 1 5 1 7 C and suffix 2 475 2 5 2 525 Q and M suffix 2 8 2 5 2 7 Power dissipation in power down AVpp 5 V DVpp BVpp 3 3 V T Not production tested for M and Q suffix devices 35 TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 electrical characteristics over recommended operating conditions internal fs 6 MHz fj 2 MHz at 1dBFS unless otherwise noted continued ac specifications AVpp 5 V BVpp DVpp 3 3 V Cj 30 pF PARAMETER TEST CONDITIONS MAX Differential mode SINAD Signal to noise ratio distortion Single ended mode see Note 1 Differential mode SNR Signal to noise ratio Single ended mode see Note 1 C and suffix Q and M suffix C and suffix Q and M suffix o R o Differential mode o ER Allo O I o c THD Total harmonic distortion Single ended mode N I D N N o N _ ENOB Differential mode Effective number of bits SNR Single ended mode see Note 1 Differential mode SFDR Spurious free dynamic r
19. Buffer The converted data of the THS1206 is automatically written into the FIFO To control the writing and reading process a write pointer a read pointer and a trigger pointer are used The read pointer always shows the location which will be read next The write pointer indicates the location which contains the last written sample With a selection of multiple analog input channels the converted values are written in a predefined sequence to the circular buffer Autoscan Mode In this way the channel information for the reading processor is continually maintained The FIFO can be programmed through the control register of the ADC The user has the ability to select a specific trigger level according to Table 13 in order to choose the configuration which best fits the application The FIFO provides the signal DATA AV which signals the processor to read the amount of data equal to the trigger level selected in Table 13 The signal DATA AV becomes active when the trigger condition is satisfied The trigger condition is satisfied when as many values as selected for the trigger level where written into the FIFO The signal DATA AV could be connected to an interrupt input of a processor In every interrupt service routine call the processor must read the amount of data equal to the trigger level from the ADC The first data represents the first channel according to the autoscan mode which is shown in Table 10 The channel information is therefore alw
20. CTERISTICS TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY SINGLE ENDED m I S o 2 a 2 x I I a AVpp 5 V DV 500 kHz AIN 0 5 dB SINAD Signal to Noise and Distortion dB 0 1 2 3 4 5 6 7 fs Sampling Frequency MHz Figure 21 SPURIOUS FREE DYNAMIC RANGE vs SAMPLING FREQUENCY SINGLE ENDED SFDR Spurious Free Dynamic Range dB SNR Signal to Noise dB AVpp 5 V DVpp B flN 500 kHz AIN 0 0 1 2 3 4 5 6 7 fs Sampling Frequency MHz Figure 23 35 TEXAS SIGNAL TO NOISE AND DISTORTION vs SAMPLING FREQUENCY SINGLE ENDED AVpp 5 V DVpp BVpp 3 V flN 500 kHz AIN 0 5 dB FS fs Sampling Frequency MHz Figure 22 SIGNAL TO NOISE vs SAMPLING FREQUENCY SINGLE ENDED AVpp 5 V DVpp BVpp 3 V 500 kHz AIN 0 5 dB FS fs Sampling Frequency MHz Figure 24 INSTRUMENTS 32 POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL TO NOISE AND DISTORTION vs vs SAMPLING FREQUENCY DIFFERENTIAL SAMPLING FREQUENCY DIFFERENTIAL AVpp 5 V DVpp BVpp 3 V 3 fiy 500 kHz AIN 0 5dBFS THD Total Harmoni
21. E BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 recommended operating conditions continued digital inputs High level input voltage Low level input voltage VIL Input CONV CLK DVpp 3 V to 5 25 V 5 GlKpusedualon clock Wah WwCONV_GLKR sof Operating free air temperature TA C electrical characteristics over recommended operating conditions VREF internal unless otherwise noted digital specifications Digital inputs o puspa 5 mj Digital outputs High level output voltage EN BVpp 3 3 V 50 Bypp 5V VoL Low level output voltage High state output current CS1 DGND CS0O DVDD 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 electrical characteristics over recommended operating conditions Vref internal unless otherwise noted continued dc specifications PARAMETER TEST CONDITIONS MIN UNIT meae 000 ej Accuracy Integral nonlinearity INL L After calibration in single ended mode 15f 15t Offset error Ee a After calibration in differential mode 5t 5t Gam Analog input Input leakage current V
22. L trigger level reads with the falling edge of READ The trigger condition is checked again after TL reads If pulse mode is chosen the signal DATA AV is a pulse with a width of one half of a CONV CLK cycle in continuous conversion mode and one half of a clock cycle of the internal oscillator in single conversion mode The next DATA AV pulse when the trigger condition is satisfied is sent out the earliest when the TL values written into the FIFO before were read out by the processor 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 23 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 timing and signal description of the THS1206 read timing using R W CSO controlled Figure 13 shows the read timing behavior when the WR R W input is programmed as a combined read write input R W The RD input has to be tied to high level in this configuration This timing is called CSO controlled because CS0 is the last external signal of CSO CS1 and R W which becomes valid amp 90 cso 10 10 CS1 N M h tsu R W th R W P RV 9096 9096 NN T T RD ta p th 4 P 90 90 D 0 11 ta CSDAV 90 po DATA_AV Figure 13 Read Timing Diagram Using R W CS0 controlled read timing parameter CSO controlled PARAMETER MIN TYP MAX
23. ST OFFICE BOX 655303 DALLAS TEXAS 75265 25 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 interfacing the THS1206 to the TMS320C30 31 33 DSP The following application circuit shows an interface of the THS1206 to the TMS320C30 31 33 DSPs The read and write timings using R W CSO controlled shown before are valid for this specific interface THS1206 TMS320C30 31 33 cso csi RD RW DATA_AV CONV_CLK DATA interfacing the THS1206 to the TMS320C54x using 1 0 strobe The following application circuit shows an interface of the THS1206 to the TMS320C54x The read and write timings using R W CSO controlled shown before are valid for this specific interface THS1206 TMS320C54x cso csi RD R W DATA AV CONV CLK DATA 35 TEXAS INSTRUMENTS 26 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 timing and signal description of the THS1206 continued read timing using RD RD controlled Figure 15 shows the read timing behavior when the WR R W input is programmed as a write input only The input RD acts as the read input in this configuration This timing is called RD controlled because RD is the last external signal of CS0 CS1 and RD which becomes valid H a tsu CS th CS EN Up
24. T essen wo sing ended channels ANP AINM AINE 3 o o T 5 stescan tree single ended channels AINE ANM BINE AINE 3 o o essen four single ended channels AINE ANM BIN BINM AIF 1 1 1 Autoscan one differential channel and one single ended channel AINP BINP BINM AINP BINP BINM 1 1 1 Autoscan one differential channel and two single ended channel AINP AINM AINP 1 1 1 Autoscan two differential channels AINP AINM BINP BINM 1 sea _ _ o o a J i r ee C CCC 3 o o o c ee Pa o o o ea 3 o r eee IT To c s ee Pa Po peeve Pap Po EO r ee C C C C E o c eee IT E c r ee I i 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 19 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 kawra ee Re avr acp P analog input channel selection continued test mode
25. THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 TH S1206 v Fi features applications High Speed 6 MSPS ADC e Radar Applications 4Single Ended or 2 Differential Inputs Communications Simultaneous Sampling of 4 Single Ended Control Applications Signals or 2 Differential Signals or High Speed DSP Front End combination Bom Automotive Applications Differential Nonlinearity Error 1 LSB Integral Nonlinearity Error 1 5 LSB DA PACKAGE Signal to Noise and Distortion Ratio 68 dB TOP VIEW at fj 2 MHz DO 32 AINP Auto Scan Mode for 2 3 or 4 Inputs D1 T AINM 3 V or 5 V Digital Interface Compatible D2 30 BINP Low Power 216 mW Max D3 29 BINM 5 V Analog Single Supply Operation D4 28 REFIN Internal Voltage References 50 PPM C 50 DD 5 BGND 25 REFM Glueless DSP Interface D6 24 AGND Parallel uC DSP Interface D7 23 AVpp Integrated FIFO D8 22 CSO Available in TSSOP Package D9 21H CS1 _ D10 RAO 20 WR RW description D11 RA1 19 RD CONV CLK CONVST 18 DVpp The THS1206 is a CMOS low power 12 bit DATA AV 17 DGND 6 MSPS analog to digital converter ADC The speed resolution bandwidth and single supply operation are suited for applications in radar imaging high speed acquisition and communications A
26. The maximum throughput rate per channel is 1 5 MSPS in this mode The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO The timing of the DATA AV signal shown here is for a trigger level of 4 Sample N Sample N 1 Sample N 2 Channel 1 2 3 4 Channel 1 2 3 4 Channel 1 2 3 4 AIN PC NEP ux MM IE M J M4 td Pipe tw CONV CLKH 4 9 9 tw CONV_CLKL 50 50 CONV_CLK M tc td O gt ha Data Into Data N 2N Data NIN Data N 1 N Data N 1N Data N 1 Data N Data N Data Data N FIFO Channel 4 Channel 1 Channel 2 Channel 3 N Channel 4 Channel 1 Channel 2 N Channel 3 Channel 4 td DATA_AV lt DATA AV N Trigger Level 4 Figure 5 Timing of Continuous Conversion Mode 4 channel operation 35 TEXAS INSTRUMENTS 12 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 digital output data format The digital output data format of the THS1206 can either be in binary format or in twos complement format The following tables list the digital outputs for the analog input voltages Table 3 Binary Output Format for Single Ended Configuration SINGLE ENDED BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN VREFP FFFh AIN VREFP VREFM 2 800h AIN VREFM 000h
27. V to 3 5 V An op amp specified for 5 V single supply can be used as shown in Figure 19 Figure 19 shows an application example where the analog input signal in the range from 1 V upto 1 V is shifted by an op amp to the analog input range of the THS1206 1 5 V to 3 5 V The op amp is configured as an inverting amplifier with a gain of 1 The required dc voltage of 1 25 V at the noninverting input is derived from the 2 5 V output reference REFOUT of the THS1206 by using a resistor divider Therefore the op amp output voltage is centered at 2 5 V The use of ratio matched thin film resistor networks minimizes gain and offset errors R 3 5V 2 5 V f 5V 15V ied AEN Rs THS1206 zd M 1 25 V REFIN ui REFOUT R R Figure 19 Level Shift for DC Coupled Input differential mode of operation For the differential mode of operation a conversion from single ended to differential is required A conversion to differential signals can be achieved by using an RF transformer which provides a center tap Best performance is achieved in differential mode Mini Circuits T4 1 49 90 R THS1206 e AINP defe R e 25 Figure 20 Transformer Coupled Input vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 31 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 TYPICAL CHARA
28. XX OX XX XX XXX XXX CX CX SRK KEK 91020 0010200 90 00 92010 91920191204 00 0 091920 KKK RE REND Figure 16 Write Timing Diagram Using WR WR controlled write timing parameter using WR WR controlled tsu CS Setup time CS stable to last WR valid ooo jm tsu Setup time data valid to first WR invalid th Hold time WR invalid to data invalid th CS Hold time WR invalid to CS change 35 TEXAS INSTRUMENTS 28 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 interfacing the THS1206 to the TMS320C6201 DSP The following application circuit shows an interface of the THS1206 to the TMS320C6201 The read using RD RD controlled and write timings using WR WR controlled shown before are valid for this specific interface THS1206 1 TMS320C6201 e CE1 EA20 RD e ARE WR e AWE DATA AV EXT INT6 DATA CONV TOUT TOUT2 EA21 THS1206 2 EXT_INT7 cso CS1 RD WR DATA AV DATA CONV CLK analog input configuration and reference voltage The THS1206 features four analog input channels These can be configured for either single ended or differential operation Best performance is achieved in differential mode Figure 17 shows a simplified model where a single ended configuration for channel AINP is selected The reference voltages for the
29. ange Single ended mode Analog Input Full power bandwidth with a source impedance of 150 Q in differential configuration Pe sinewave 30B Full power bandwidth with a source impedance of FS sinewave 3 dB 150 Q in single ended configuration Small signal bandwidth with a source impedance of 150 Q in differential configuration 100 mv DR sinewave cS OE Small signal bandwidth with a source impedance of 150 single ended configuration TOOMA pp Sinewave oB NOTE 1 The SNR ENOB and SINAD is degraded typically by 2 dB in single ended mode when the reading of data is asynchronous to the sampling clock 68 75 a R a R 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 timing specifications AVpp 5 V BVpp DVpp 3 3 V Vpgr internal CL lt 30 pF TEST CONDITIONS MIN TYP UNIT 5 PARAMETER ld DATA AV Delay time tdio Delay time toipe Latency PARAMETER Clock cycle of the internal clock oscillator Pulse width CONVST Aperture time Time between consecutive start of single conversion Delay time DATA_AV becomes active for the trigger level condition TRIGO 0 TRIG1 0 Delay time DATA_AV becomes active for the trigger Id DATA AV level condition TRIGO 1 TRIG1 0 Delay time DATA_AV becomes active for the trigger
30. annel 2 Channel 1 Channel 2 Channel 1 Channel Channel 1 Channel 2 Channel 1 Channel 2 6 9 tqpara av DATA AV EIS Trigger Level 2 ta DATA AV gt DATA AV N Trigger Level 4 Figure 3 Timing of Continuous Conversion Mode 2 channel operation 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 11 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 continuous conversion mode continued Figure 4 shows the timing of continuous conversion mode when three analog input channels are selected The maximum throughput rate per channel is 2 MSPS in this mode The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO The timing of the DATA_AV signal shown here is for a trigger level set to 3 Sample N Sample N 1 Sample N 2 Channel 1 2 3 Channel 1 2 3 Channel 1 2 3 t ou Tum t d A Cum d c td Pipe gt tw CONV_CLKH Jera tw CONV_CLKL Kem gt B Data Into Data N 2 Data N 2 Data N 1 Data N 1 N Data N 1 Data N 1 FIFO Channel 2 Channel 3 Channel 2 Channel 2 Channel 3 Channel 1 Channel 2 Channel 3 td DATA AV 7 DATA AV N Trigger Level 2 3 Figure 4 Timing of Continuous Conversion Mode 3 channel operation Figure 5 shows the timing of continuous conversion mode when four analog input channels are selected
31. ays maintained 35 TEXAS INSTRUMENTS 14 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 Reading data from the FIFO The THS1206 informs the connected processor via the digital output DATA AV data available that a block of conversion values are ready to be read The block size to be read is always equal to the setting of the trigger level The selectable trigger levels depend on the number of selected analog input channels For example when choosing one analog input a trigger level of 1 4 8 and 14 can be selected The following figures demonstrate the principle of reading the data In Figure 7 atrigger level of 1 is selected The control signal DATA AV is setto an active low pulse This means that the connected processor has the task to read 1 value from the ADC after every DATA AV low pulse Figure 7 Trigger Level 1 Selected In Figure 8 a trigger level of 4 is selected The control signal DATA AV is set to an active low pulse This means that the connected processor has the task to read 4 values from the ADC after every DATA AV low pulse ewe V VS VENA U NATA NATAT NT NA NT NN DATA AV Figure 8 Trigger Level 4 Selected In Figure 9 a trigger level of 8 is selected The control signal DATA AV is set to an active low pulse This means that the connected processor has the task to read 8
32. c Distortion dB SINAD Signal to Noise and Distortion dB 0 5 dB FS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 fs Sampling Frequency MHz fs Sampling Frequency MHz Figure 25 Figure 26 SPURIOUS FREE DYNAMIC RANGE SIGNAL TO NOISE vs vs SAMPLING FREQUENCY DIFFERENTIAL SAMPLING FREQUENCY DIFFERENTIAL 100 95 AVpp 5 V DVpp BVpp 3 V AVpp 5 V DVpp BVpp 3 V 500 kHz AIN 0 5 dB FS fin 500 kHz AIN 0 5 dB FS 90 2 85 S l o 80 9 S 75 2 a 8 70 o 65 D 8 T 5 60 z m 55 o 50 45 40 fs Sampling Frequency MHz fs Sampling Frequency MHz Figure 27 Figure 28 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 33 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL TO NOISE AND DISTORTION VS VS INPUT FREQUENCY SINGLE ENDED INPUT FREQUENCY SINGLE ENDED AVpp 5 V DVpp BVpp 3 V fs 6 MHz AIN 0 5 dB FS AVpp 5 V DVpp BVpp 3 V fs 6 MHz AIN 0 5 dB FS THD Total Harmonic Distortion dB SINAD Signal to Noise and Distortion dB 9 ee hw 20 23 29 0 05 10 15 20 25 30 fj Input Frequency MHz f Input Frequency MHz F
33. differential or a single ended input is considered as one channel The processor therefore always reads the data from the FIFO in the same order and is able to distinguish between the channels Table 13 FIFO Trigger Level TRIGGER LEVEL TRIGGER LEVEL TRIGGER LEVEL TRIGGER LEVEL FOR 1 CHANNEL FOR 2 CHANNELS FOR 3 CHANNEL FOR 4 CHANNELS ADC values ADC values ADC values ADC values 0 01 02 03 1 08 08 09 x Reserved Timing and Signal Description of the THS1206 The reading from the THS1206 and writing to the THS1206 is perfomed by using the chip select inputs CS0 CS1 the write input WR and the read input RD The write input is configurable to a combined read write input RAN This is desired in cases where the connected processor consists of a combined read write ouput signal R W The two chip select inputs can be used to interface easily to a processor Reading from the THS1206 takes place by an internal RDin signal which is generated from the logical combination of the external signals CSO CS1 and RD see Figure 12 This signal is then used to strobe the words out of the FIFO and to enable the output buffers The last external signal either CS0 CS1 or RD to become valid will make RDint active while the write input WR is inactive The first of those external signals going to its inactive state will then deactivate RDint again Writing to the THS1 206 takes place by an internal WRint signal which is
34. e number of selected differential channels Refer to Table 10 7 SCAN Autoscan enable Bit 7 enables or disables the autoscan function of the ADC Refer to Table 10 TESTO Test input enable TEST1 Bit 8 and bit 9 control the test function of the ADC Three different test voltages can be measured This feedback allows the check of all hardware connections and the ADC operation Refer to Table 11 for selection of the three different test voltages 35 TEXAS INSTRUMENTS 18 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 analog input channel selection The analog input channels of the THS1206 can be selected via bits 3 to 7 of control register 0 One single channel single ended or differential is selected via bit 3 and bit 4 of control register 0 Bit 5 controls the selection between single ended and differential configuration Bit 6 and bit 7 select the autoscan mode if more than one input channel is selected Table 10 shows the possible selections Table 10 Analog Input Channel Configurations o 0 _ Araoginput ANP angleere S P s RR o o o o _ Aratoginput NP single ended Lo o o _1 r inge ende o o o o o Bieri channel oo r o preeniarcramer eps T 3 o o o
35. earity refers to the deviation of each individual code from a line drawn from zero through full scale The point used as zero occurs 1 2 LSB before the first code transition The full scale point is defined as level 1 2 LSB beyond the last code transition The deviation is measured from the center of each particular code to the true straight line between these two points differential nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart DNL is the deviation from this ideal value A differential nonlinearity error of less than 1 LSB ensures no missing codes zero offset The major carry transition should occur when the analog input is at zero volts Zero error is defined as the deviation of the actual transition from that point gain error The first code transition should occur at an analog value 1 2 LSB above negative full scale The last transition should occur at an analog value 1 1 2 LSB below the nominal full scale Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions signal to noise ratio distortion SINAD SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc The value for SINAD is expressed in decibels effective number of bits ENOB For a sine wave SINAD can be expressed
36. fset cancellation mode Bit 8 0 normal conversion mode Bit 8 1 offset calibration mode If a 1 is written into bit 8 of control register 1 the device internally sets the inputs to zero and does a con version The conversion result is stored in an offset register and subtracted from all conversions in order to reduce the offset error Debug mode Bit 9 0 normal conversion mode Bit 9 1 enable debug mode When bit 9 of control register 1 is set to 1 debug mode is enabled In this mode the contents of control register 0 and control register 1 can be read back The first read after bit 9 is set to 1 contains the value of control register 0 The second read after bit 9 is set to 1 contains the value of control register 1 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 21 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 FIFO trigger level Bit 2 and bit 3 TRIG1 TRIGO of control register 1 are used to set the trigger level of the FIFO see Table 13 If the trigger level is reached the DATA AV data available signal becomes active according to the setting of the signal DATA AV to indicate to the processor that the ADC values can be read Table 13 shows four different programmable trigger levels for each configuration The FIFO trigger level which can be selected is dependent on the number of input channels Both a
37. igure 29 Figure 30 SPURIOUS FREE DYNAMIC RANGE SIGNAL TO NOISE vs vs INPUT FREQUENCY SINGLE ENDED INPUT FREQUENCY SINGLE ENDED 100 m z 95 5 90 m 85 jo E 75 70 Is 9 65 2 60 2a tc n 55 E 50 uL 45 40 0 0 5 1 0 1 5 2 0 2 5 3 0 0 0 5 1 0 1 5 2 0 2 5 3 0 fi Input Frequency MHz fj Input Frequency MHz Figure 31 Fiaure 32 35 TEXAS INSTRUMENTS 34 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THD Total Harmonic Distortion dB SFDR Spurious Free Dynamic Range dB THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY DIFFERENTIAL AVpp 5 V DVpp BVpp 3 V fs 6 MHz AIN 0 5 dB FS 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 f Input Frequency MHz Figure 33 SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY DIFFERENTIAL MHz AIN 0 5 dB F 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 fj Input Frequency MHz Figure 35 SINAD Signal to Noise and Distortion dB SNR Signal to Noise dB SIGNAL TO NOISE AND DISTORTION vs INPUT FREQUENCY DIFFERENTIAL AVpp 5 V DVpp fs 6 MHz AIN 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 fi Input Frequency MHz Figure 34 SIGNAL TO NOISE vs INPUT FREQUENCY DIFFERENTIAL AVpp 5 V DVpp BVpp 3 V
38. in terms of the number of bits Using the following formula SINAD 1 76 6 02 itis possible to get a measure of performance expressed as N the effective number of bits Thus effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD total harmonic distortion THD n THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels spurious free dynamic range SFDR SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 39 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 MECHANICAL DATA DA R PDSO G PLASTIC SMALL OUTLINE PACKAGE 38 PINS SHOWN 0 15 NOM T Gage Plane 4 1 Y Seating Plane d 20 MAX 0 10 PINS
39. ively higher accuracy as the device passes the results from stage to stage This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC A sample and hold amplifier SHA within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples conversion modes The conversion can be performed in two different conversion modes In the single conversion mode the conversion is initiated by an external signal CONVST An internal oscillator controls the conversion time In the continuous conversion mode an external clock signal is applied to the clock input CONV A new conversion is started with every falling edge of the applied clock signal sampling rate The maximum possible conversion rate per channel is dependent on the selected analog input channels Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations Table 1 Maximum Conversion Rate in Continuous Conversion Mode NUMBER OF MAXIMUM CONVERSION CHANNEL CONFIGURATION CHANNELS RATE PER CHANNEL 1 single ended channel 6 MSPS 2 single ended channels 3 MSPS 3 single ended channels 2 MSPS The maximum conversion rate in the continuous conversion mode per channel fc is given by 6 MSPS channels fc Table 2 shows the maximum conversion rate in the single conversion mode
40. re pee ere ens ema ens ena emi amo testi testo SCAN Difi Dirro cHsEL cHSELO PO MODE VREF Table 9 Control Register 0 Bit Functions RESET VREF Vref select Bit 0 0 The internal reference is selected Bit 0 1 The external reference voltage is selected 1 MODE Continuous conversion mode single conversion mode Bit 1 0 Continuous conversion mode is selected An external clock signal is applied to the CONV input in this mode With every falling edge of the CONV signal a new converted value is written into the FIFO Bit 1 2 1 Single conversion mode is selected In this mode the CONV CLK input functions as a CONVST input A single conversion is initiated on the THS1206 by pulsing the CONVST input On the falling edge of CONVST the sample and hold stages of the selected analog inputs are placed into hold simultaneously and the conversion sequence for the selected channels is started The signal DATA AV data available becomes active when the trigger condition is satisfied 2 Power down Bit 2 0 2 The ADC is active Bit 2 1 Power down The reading and writing to and from the digital outputs is possible during power down It is also possible to read out the FIFO 3 4 CHSELO Channel select CHSEL1 Bit 3 and bit 4 select the analog input channel of the ADC Refer to Table 10 5 6 1 0 DIFFO DIFF1 Number of differential channels Bit 5 and bit 6 contain information about th
41. ress lines RAO and RA1 During this write process the data bits DO to D9 contain the desired control register value Table 8 shows the addressing of each control register Table 8 Control Register Addressing DO D9 D10 RAO D11 RA1 Addressed Control Register Desired register value 0 0 Control Register 0 1 Desired register value 0 Control Register 1 Desired register value 0 1 Reserved for future E Desired register value Reserved for future 35 TEXAS INSTRUMENTS 16 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 initialization of the THS1206 The initialization of the THS1206 should be done according to the configuration flow shown in Figure 11 Use Default Values Write 0x401 to Write 0x401 to THS1206 THS1206 E Set Reset Bit in CR1 Set pes Bitin Clear RESET By Clear RESET By Writing 0x400 to Writing 0x400 to CR1 CR1 Write The User Configuration to CRO Write The User Configuration to CR1 Can Include FIFO Reset Must Exclude RESET Figure 11 THS1206 Configuration Flow vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 ADC control registers control register 0 see Table 8 a
42. signal is shown here in the case of a trigger level set to 1 or 4 Sample N Sample N 1 Sample N 2 Sample N 3 Sample N 4 Sample Ne5 Sample N 6 Sample N 7 Sample N 8 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 AIN uU M EON d CN M tar gt tw CONV_CLKH es tw CONV_CLKL 50 50 Eo 29 7 KU AS Z SZ M ic gt taco gt e Data Into Data N 5 Data N 4 Data N 3 Data N 2N Data N 1 FIFO Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 c i 1d DATA AV DATA_AV Trigger Level 1 td DATA_AV P Ke DATA AV N Trigger Level 4 Figure 2 Timing of Continuous Conversion Mode 1 channel operation Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected The maximum throughput rate per channel is 3 MSPS in this mode The data flow in the bottom of the figure shows the order the converted data is written into the FIFO The timing ofthe DATA AV signal shown here isfor atrigger level set to 2 or 4 Sample N Sample N 1 Sample N 2 Sample N 3 Sample N 4 Channel 1 2 Channel 1 2 Channel 1 2 Channel 1 2 Channel 1 2 AIN k td A A4 ta Pipe gt tw CONV_CLKH 4 94 tw CONV_CLKL 50 50 CONV_CLK e ieh ta o gt Data Into Data N 3 Data N 2 Data N 2 Data N 1 Data N 1 Data N Data N Data N 1 FIFO Ch
43. t write only By writing a 1 into this bit the FIFO is reset FIFO trigger level Bit 2 and bit of control register 1 are used to set the trigger level for the FIFO If the trigger level is reached the signal DATA AV data available becomes active according to the settings of DATA T and DATA P This indicates to the processor that the ADC values can be read Refer to Table 13 DATA type Bit 4 of control register 1 controls whether the DATA AV signal is a pulse or static e g for edge or level sensitive interrupt inputs If itis set to 0 the DATA AV signal is static If itis set to 1 the DATA AV signalisa pulse Refer to Table 14 DATA AV polarity Bit 5 of control register 1 controls the polarity of DATA AV If itis setto 1 DATA AViis active high If itis setto 0 DATA AW is active low Refer to Table 14 R W RD WR selection Bit 6 of control register 1 controls the function of the inputs RD and WR When bit 6 in control register 1 is set to 1 WR becomes a R W input and RD is disabled From now on a readis signalled with R W high and a write with R W as a low signal If bit 6 in control register 1 is set to 0 the input RD becomes aread input and the input WR becomes a write input Complement select If bit 7 of control register 1 is set to 0 the output value of the ADC is in twos complement If bit 7 of control register 1 is set to 1 the output value of the ADC is in binary format Refer to Table 3 through Table 6 Of
44. terized for operation over the full military temperature range of 55 C to 125 C Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright 2000 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL PRF 38535 all parameters are tested standard warranty Production processing does not necessarily include unless otherwise noted On all other products production testing of all parameters EXAS processing does not necessarily include testing of all parameters INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 AVAILABLE OPTIONS TA TSSOP DA 0 C to 70 C THS1206CDA 40 C to 85 C THS1206IDA 40 C to 125 C THS1206QDA 55 C to 125 C THS1206MDA functional block diagram REFOUT Pipeline ADC D D10 RA0 D11 RA1 BGND Control Register 35 TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999
45. the ADC The voltage VApc can be calculated as follows VADC ABS AINP AINM 2 An advantage to single ended operation is that the common mode voltage V _ AINM AINP CM 2 3 can be rejected in the differential configuration if the following condition for the analog input voltages is true AGND x AINM AINP lt AVpp 4 1Vs Voy S 4 V 5 In addition to the common mode voltage rejection the differential operation allows a dc offset rejection which is common to both analog inputs See also Figure 20 single ended mode of operation The THS1206 can be configured for single ended operation using dc or ac coupling In either case the input of the THS1206 must be driven from an operational amplifier that does not degrade the ADC performance Because the THS1206 operates from a 5 V single supply it is necessary to level shift ground based bipolar signals to comply with its input requirements This can be achieved with dc and ac coupling An application example is shown for dc coupled level shifting in the following section dc coupling TEXAS INSTRUMENTS 30 POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 dc coupling An operational amplifier can be configured to shift the signal level according to the analog input voltage range ofthe THS1206 The analog input voltage range of the THS1206 goes from 1 5
46. the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated
47. values from the ADC after every DATA AV low pulse VA VSS SPS SPS A NPP M DATA_AV Figure 9 Trigger Level 8 Selected 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 15 THS1206 12 BIT 6 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTERS SLAS217D MAY 1999 REVISED APRIL 2000 In Figure 10 a trigger level of 14 is selected The control signal DATA AV is set to an active low pulse This means that the connected processor has the task to read 14 values from the ADC after every DATA AV low pulse ewe I N NV NV NN NA NN NN NNI DATA AV MJ M READ Figure 10 Trigger Level 14 Selected READ is always the logical combination of CS0 CS1 and RD ADC Control Register The THS1206 contains two 10 bit wide control registers CR0 CR1 in order to program the device into the desired mode The bit definitions of both control registers are shown in Table 7 Table 7 Bit Definitions of Control Register CR0 and CR1 cms mesm resto scan prr orro casei cese Po woor vrer RBACK OFFSET BIN 2s R W TRIGO OVFL FRST Writing to control register 0 and control register 1 The 10 bit wide control register 0 and control register 1 can be programmed by addressing the desired control register and writing the register value to the ADC The addressing is performed with the upper data bits D10 and D11 which function in this case as add

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