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TEXAS INSTRUMENTS THS1040 handbook

1. 4 0 020 0 51 0 012 0 31 4 0 010 0 25 Pin 1 0 050 1 27 Index Area A L 0 104 2 65 Max ine 0 30 0 004 0 10 7 0 004 0 10 Gauge Plane x Seating Plane 0 010 0 25 4040000 6 F 06 2004 NOTES A All linear dimensions are in inches milimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion not to exceed 0 006 0 15 D Falls within JEDEC MS 013 variation AE d TEXAS INSTRUMENTS www ti com MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW R PDSO G PLASTIC SMALL OUTLINE PACKAGE 14 PINS SHOWN 0 15 NOM i t engel 4 a U U LI LI LI Seating Plane ME ea 20 MAX 0 15 4 40 10 0 05 PINS DIM A MAX A MIN 4040064 F 01 97 NOTES A All linear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 15 Falls within JEDEC MO 153 DOM xi TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated
2. dB THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS fi 10 MHz 0 5 dB fs 40 MSPS Diff Input 2 V FFT fi 4 5 MHz 0 5 dBFS fs 40 MSPS Diff Inpt 2 V f Frequency MHz Figure 18 FFT f Frequency MHz Figure 19 da TEXAS INSTRUMENTS www ti com 13 THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 PRINCIPLES OF OPERATION functional overview See the functional block diagram A single ended sample rate clock is required at pin CLK for device operation Analog inputs AIN and AIN are sampled on each rising edge of CLK in a switched capacitor sample and hold unit the output of which feeds the ADC core where analog to digital conversion is performed against the ADC reference voltages REFT and REFB Internal or external ADC reference voltage configurations are selected by connecting the MODE pin appropriately When MODE AGND the user must provide external sources at pins REFB and REFT When MODE AVpp or MODE AVpp 2 an internal ADC references generator A2 is enabled which drives the REFT and REFB pins using the voltage at pin VREF as its input The user can choose to drive VREF from the internal bandgap reference or disable A1 and provide their own reference voltage at pin VREF On the fourth rising CLK edge following the edge that sampled AIN and AIN the conversion resul
3. DVpp 2 27 AIN e Medical DO 3 261 VREF Difa asf AIN DESCRIPTION p2 ls o4f REFB The THS1040 is a CMOS low power 10 bit 40 MSPS D3 fe 23 MODE analog to digital converter ADC that operates from a D4 7 221 REFT single 3 V supply The THS1040 has been designed to D5 8 21 BIASREF give circuit developers flexibility The analog input to the D6 9 201 TEST THS1040 can be either single ended or differential The D7 10 19 AGND THS1040 provides a wide selection of voltage D8 11 18 REFSENSE references to match the user s design requirements D9 12 17 STBY For more design flexibility the internal reference can be ovR 13 1e OE DGND 14 151 CLK A Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright 2001 2004 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include i testing of all parameters EXAS INSTRUMENTS www ti com k THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 AVAILABLE OPTIONS PRODUCT PACKAGE PACKAGE More PACKAGE ORDERING TRANSPORT MEDIA LEAD DESGIGNATORt RANGE MARKINGS NUMBER QUANTITV THS10
4. Figure 12 An TExAS INSTRUMENTS 10 www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS POWER DISSIPATION TOTAL CURRENT vs vs SAMPLE RATE CLOCK FREQUENCY lt E E I E E o E e 5 E o a FI s a a 4 8 12 16 20 24 28 32 36 40 44 0 5 10 15 20 25 30 35 40 45 fs Sample Rate MSPS folk Clock Frequency MHz Figure 13 Figure 14 INPUT BANDWIDTH Amplitude dB 10 100 300 500 700 900 1100 fj Input Frequency MHz Figure 15 NOTE No series resistors and no bypass capacitors at AIN and AIN inputs da TEXAS INSTRUMENTS www ti com 11 THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS ADC CODES POWER UP TIME FOR INTERNAL vs REFERENCE VOLTAGE FROM STANDBY WAKE UP SETTLING TIME 125 MODE AGND 120 fs 40 MSPS Ext REF 1 V and 2 V I AVpp 3 V 3 115 S G gt o 8 8 110 o 5 O o ZS q 105 2 c 100 E oO D 95 90 9 e o e oO oO oO e e o oO oe oO o 10 5 20 35 50 65 80 95 110 O Pr oO HO st mm ON r O CO r EON Se MM CU D e Wake Up Settling Time us Power Up Time us Figure 16 Figure 17 d Texas INSTRUMENTS 12 www ti com Amplitude dB Amplitude
5. TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 1 V FS Differential Input Range 15 a 50 20 dBFS N THD Total Harmonic Distortion dB I o eo Pat THD Total Harmonic Distortion dB See Note 0 0 10 20 30 40 50 60 70 80 90 100110 120 fi Input Frequency MHz Figure 5 SIGNAL TO NOISE RATIO Vs INPUT FREQUENCV 61 Diff Input 2 V I l t l 59 N SE Input 2 V 53 51 SNR Signal to Noise Ratio dB 49 SFDR Spurious Free Dynamic Range dB 47 0 10 20 30 40 50 60 70 80 90 100 110 120 fj Input Frequency MHz Figure 7 Input series resistor 25 Q 2 V Input Ext Ref REFT 2 V REFB 1 V 0 5 dBFS 1 V Input Ext Ref REFT 1 75 V REFB 1 25 V 0 5 dBFS TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 2 V FS Differential Input Range IK 0 5 dBFS 20 dBFS N 6 dBFS See Note 40 0 10 20 30 40 50 60 70 80 90 100 110 120 fj Input Frequency MHz Figure 6 SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY Diff I 0 SE Input 2 V 10 20 30 40 50 60 70 80 90 100 110 120 fj Input Frequency MHz Figure 8 NOTE AVpp DVpp 3V fg 40MSPS 20 pF capacitors AIN to AGND and AIN to AGND da TEXAS INSTRUMENTS ww
6. is from the power down state to accurate ADC samples being taken and is specified for MODE AGND with external reference sources applied to the device at the time of release of power down and an applied 40 MHz clock Circuits that need to power up are the bandgap bias generator ADC and SHA NOTE 6 External reference values are listed in the Recommended Operating Conditions Table 35 TEXAS INSTRUMENTS www ti com 5 THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 electrical characteristics over recommended operating conditions AVDD 3 V DVDD 3 V fs 40 MSPS 50 duty cycle MODE AVpp internal reference differential input range 1 Vpp and 2 VPP TA Tmin to Tmax unless otherwise noted continued dynamic performance ADC UNIT f 4 8 MHz 0 5 dBFS THD Total harmonic distortion SFDR Spurious free dynamic range 20 MHz 0 5 dBFS E f 4 8 MHz 0 5 dBFS SNR Signal to noise ratio f 20 MHz 05 dBFS f 4 8 MHz 0 5 dBFS SINAD Signal to noise and distortion BW Ful power bandwidth 3 dB o 90 MZ digital specifications PARAMETER MIN NOM MAX UNIT Digital Inputs T TA Clock input 0 8 x AVpp T E ee All other inputs 0 8 x DVDD Digital Outputs Clock Input timing VO BIASREF Output voltage MODE AVDD AVpp 2 0 1 AVpp 2 0 1 da TEXAS INSTRUMENTS 6 www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 PA
7. powers the internal bandgap reference A1 down saving power when A1 is not required If MODE is connected to AVpp or AVpp 2 then the voltage at VREF determines the ADC reference voltages AM BERT DD 4 VREF 9 2 2 AV 10 DD _ VREF REFB 2 5 REFT REFB VREF 11 ee ee E esa q ADC References Buffer A2 MODE AVDD or Avon VREF 0 5V VBG 0 1uF 1uF V REFSENSE e l NENNEN NE ae AGND Figure 25 0 5 V VREF Using the Internal Bandgap Reference A1 da TEXAS INSTRUMENTS www ti com 19 THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 PRINCIPLES OF OPERATION onboard reference generator configuration continued 20 4 ADC References Buffer A2 MODE AVDD or AVpp 2 VREF 1V as O 10 kQ 0 1 uF V REFSENSE 10 kQ l V AGND 4 Figure 26 1 V VREF Using the Internal Bandgap Reference A1 ADC References Buffer A2 Ra REFSENSE Rb VREF 1 Ra Rp 2 e 0 1 uF Figure 27 External Divider Mode da TEXAS INSTRUMENTS www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 PRINCIPLES OF OPERATION onboard reference generator configuration continued ADC References Buffer A2 VREF External 4 REFSENSE Figure 28 Drive VREF Mode operating configur
8. 1040 ADC references REFT and REFB can be driven from external off chip sources or from the internal on chip reference buffer A2 The voltage at the MODE pin determines the ADC references source Connecting MODE to AGND enables external ADC references mode In this mode the internal buffer A2 is powered down and the user must provide the REFT and REFB voltages by connecting external sources directly to these pins This mode is useful where several THS1040 devices must share common references for best matching of their ADC input ranges or when the application requires better accuracy and temperature stability than the on chip reference source can provide Connecting MODE to AVpp or AVpp 2 enables internal ADC references mode In this mode the buffer A2 is powered up and drives the REFT and REFB pins External reference sources should not be connected in this mode Using internal ADC references mode when possible helps to reduce the component count and hence the system cost When MODE is connected to AVpp a buffered AVpp 2 voltage is available at the BIASREF pin This voltage can be used as a dc bias level for any ac coupling networks connecting the input signal sources to the AIN and AIN pins MODEPIN REFERENCE SELECTION BIASREF PIN FUNCTION external reference mode MODE AGND AIN x1 Sample ADC and Core AIN X 1 Hold VREF Internal O Reference Buffer REFT REFB Figure 21 ADC Reference Ge
9. 1VEAR RoHS Level 1 220C UNLIM THS1040IPW ACTIVE TSSOP PW 28 50 None CU NIPDAU Level 2 220C 1 YEAR THS1040IPWR ACTIVE TSSOP PW 28 2000 None CU NIPDAU Level 2 220C 1 YEAR THS1040IPWRG4 ACTIVE TSSOP PW 28 2000 Green RoHS amp CU NIPDAU Level 1 260C UNLIM no Sb Br The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan May not be currently available please check http www ti com productcontent for the latest availability information and additional product content details None Not yet available Lead Pb Free Pb Free RoHS Tl s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Green RoHS amp no Sb Br TI defines Green to mean Pb Free and in addition use
10. 40C C to 70 C TH104 THS1040CPW Tube 50 j Re i THS1040CPWR Tube and Reel 2000 TSSOP 28 MR THS1040IPW Tube 50 EC SAQ ECS rone J1040 THS1040IPWR Tube and Reel 2000 ES ECS o t For the most current specification and package information refer to the TI web site at www ti com mg 0401 functional block diagram AI Digital Control PIENE BIASREF o o AIN oo 3 State Output D 0 9 O Buffers AIN OVR SE MODE DVDD Mode Reference l Detection Resistor Timing d DGND KT Circuit l CLK VREF gt Pd E O G l AVDD m oo T D ium l J 1c AGND FE Lo mma mm a e a e e GHAD e GHAD GHAD GHAD GHAD GHAD GHAD GHS G eee Jm GHAD a a ew GHS GHID ee em REFB REFT VREF REFSENSE NOTE A1 Internal bandgap reference A2 Internal ADC reference generator dn TEXAS INSTRUMENTS 2 www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 Terminal Functions TERMINAL DESCRIPTION NAME When the MODE pin is at AVDD a buffered AVpp 2 is present at this pin that can be used by external input biasing circuits The output is high impedance when MODE is AGND or AVpp 2 Digital data bit O LSB Digital data bit 1 Digital data bit 2 Digital data bit 3 Digital data bit 4 Digital data bit 5 Digital data bit 6 Digital data bit 7 Digital data bit 8 p data bit 9 Se 20 VREF 26 lO Internal or extern
11. AVpp AV 1 875 V aj DD 1 5 V 7 e 1 125 V Zo 3 20 pF 1 875 V 200 1 5 V e AIN 1 125 V B aL PEPE VREF 0 75 V 5 kQ REFSENSE 0 1 uF 10 uF 7 10 kQ 10 uF 0 1 uF e e e j 0 1 WF d Figure 30 Operating Configuration 1 5 V Differential Input Internal ADC References Figure 31 shows a configuration using the internal ADC references and an external VREF source for digitizing a dc coupled single ended input with span 0 5 V to 2 V A 1 25 V external source provides the bias voltage for the AIN pin and also via a buffered potential divider the 0 75 VREF voltage required to set the input range to 1 5 Vp p MODE is tied to AVpp to set internal ADC references configuration AVDD 0 1 uF T 10 ka 0 1uF 10uF e e 1OuF 0 75 V 0 1 uF ew i REFSENSE AVDD Figure 31 Operating Configuration 1 5 V Single Ended Input External VREF Source da TEXAS INSTRUMENTS 22 www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 PRINCIPLES OF OPERATION power management In power sensitive applications such as battery powered systems where the THS1040 is not required to convert continuously power can be saved between conversion intervals by placing the THS1040 into power down mode This is achieved by pulling the STBY pin high In power down mode the device typically consumes less than 0 1 mW of power If th
12. ENTS 4 www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 electrical characteristics over recommended operating conditions AVDD 3 V DVDD 3 V fs 40 MSPS 50 duty cycle MODE AVpp internal reference differential input range 1 Vpp and 2 VPP TA Tmin to Tmax unless otherwise noted power supply PARAMETER TEST CONDITIONS MAX UNIT po Do Rc En Operating supply current See Note 4 Power dissipation See Note 4 Bem senem Es Power up time for all references from standby t py 10 uF bypass REFT REFB internal ADC reference voltages outputs MODE AVpp or AVpp 2 see Note mom E o 32 kemm Ed ees EET Input resistance between REFT and REFB 14 19 25 ko VREF on chip voltage reference generator PARAMETER MAX Internal 0 5 V reference voltage REFSENSE VREF NV Internal 1 V reference voltage REFSENSE AGND ov Reference input resistance REFSENSE AVpp MODE AVpp 2 or AVpp 21 ko dc accuracy PARAMETER Resolution INL Integral nonlinearity see definitions DNL Differential nonlinearity see definitions Zero error see definitions Full scale error see definitions E FSR No missing code assured NOTE 4 Apply a 1 dBFS 10 KHz triangle wave at AIN and AIN with an internal bandgap reference and ADC reference enabled and BIASREF enabled at AVpp 2 Any additional load at BIASREF or VREF may require additional current NOTE 5 Wake up time
13. ORMATION driving the VREF pin continued Note that the maximum current may be up to 30 higher The user should ensure that VREF is driven from a low noise low drift source well decoupled to analog ground and capable of driving the maximum IREF driving REFT and REFB external ADC references MODE AGND AVDD REFT e gt To ADC Core AGND 2kQ AVDD REFB e To ADC Core AGND Figure 36 Equivalent Circuit of REFT and REFB Inputs reference decoupling VREF pin When the on chip reference generator is enabled the VREF pin should be decoupled to the circuit board s analog ground plane close to the THS1040 AGND pin via a 1 uF capacitor and a 0 1 uF ceramic capacitor REFT and REFB pins In any mode of operation the REFT and REFB pins should be decoupled as shown in Figure 37 Use short board traces between the THS1040 and the capacitors to minimize parasitic inductance REFT THS1040 REFB Figure 37 Recommended Decoupling for the ADC Reference Pins REFT and REFB BIASREF pin When using the on chip BIASREF source the BIASREF pin should be decoupled to the circuit board s analog ground plane close to the THS1040 AGND pin via a 1 uF capacitor and a 0 1 uF ceramic capacitor da TEXAS INSTRUMENTS 26 www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 APPLICATION INFORMATION supply decoupling The analog AVpp AGND and digital DVpp DGND power supplies to the THS1040 mu
14. RAMETER MEASUREMENT INFORMATION Sample 2 Sample 3 Sample 6 Sample 7 ample 1 Sample 5 Analog Sample 4 Input 4 te 4 tw ckL tw CKH WR Input Clock fej NZA NZ NS NK NZ NO Note A td o I O Pad Delay or j Pipeline Latency gt i Propagation Delay XXXIX sme X sees Output 4 5 ta DEN ta DZ OE j 01 w NOTE A All timing measurements are based on 50 of edge transition Figure 1 Digital Output Timing Diagram da TEXAS INSTRUMENTS www ti com L THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY vs INPUT CODE AVpp 3V DVpp 3 V fs 40 MSPS Vref 1 V DNL Differential Nonlinearity LSB 0 128 256 384 512 640 768 896 1024 Input Code Figure 2 INTEGRAL NONLINEARITY vs INPUT CODE a o E S o E t o z T AVpp 3V E DVpp 3 V E fs 40 MSPS Vref 1V ES 0 128 256 384 512 640 768 896 1024 Input Code Figure 3 INTEGRAL NONLINEARITY vs INPUT CODE a a AVpp 3 V l DVpp 3V E I fs 40 MSPS Vref 0 5 V o z T o o E I z 0 128 256 384 512 640 768 896 1024 Input Code Figure 4 dAn TEXAS INSTRUMENTS 8 www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS
15. TH S10401D W ROL AZ FE j THS1040 435 TEXAS INSTRUMENTS SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 3 V 10 Bit 40 MSPS CMOS ANALOG TO DIGITAL CONVERTER FEATURES bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the Analog Supply 3 V application The out of range output indicates any Digital Supply 3 V out of range condition in THS1040 s input signal Configurable Input Functions The speed resolution and single supply operation of 8 PE m the THS1040 are suited to applications in set top box 7 pd ki STB video multimedia imaging high speed Differential Nonlinearity 0 45 LSB acquisition and communications The speed and e Signal to Noise 60 dB Typ fin at 4 8 MHz resolution ideally suit charge couple device CCD input Spurious Free Dynamic Range 72 dB systems such as color scanners digital copiers digital Adiustable Internal Voltage Reference cameras and camcorders A wide input voltage range 1 g allows the THS1040 to be applied in both imaging and e On Chip Voltage Reference Generator communications svstems Unsigned Binary mala Sen The THS1040C is characterized for operation from 0 C Out of Range Indicator to 70 C while the THS10401 is characterized for Power Down Mode operation from 40 C to 85 C APPLICATIONS 28 PIN TSSOP SOIC PACKAGE Video CCD Imaging TOP VIEW Communications Set Top Box oe E 28 AVDD
16. al reference 35 TEXAS INSTRUMENTS www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 absolute maximum ratings over operating free air temperature unless otherwise noted t Supply voltage range AVpp to AGND DVpp to DGND ve 0 3 V to 4 V AGND to DGND eg dues tpe annuaires dates 0 3 V to 0 3 V AVDD O DVDD ici tte dra Rieti ole E a ie tla dle ble cp deb atin 4Vto4V MODE input voltage range MODE to AGND 0 3 V to AVpp 0 3 V Reference voltage input range REFT REFB to AGND 0 3 V to AVpp 0 3 V Analog input voltage range AIN to AGND 0 3 V to AVpp 0 3 V Reference input voltage range VREF to AGND 0 3 V to AVpp 0 3 V Reference output voltage range VREF to AGND 0 3 V to AVpp 0 3 V Clock input voltage range CLK to AGND 0 3 V to AVpp 0 3 V Digital input voltage range digital input to DGND 0 3 V to DVpp 0 3 V Digital output voltage range digital output to DGND 0 3 V to DVpp 0 3 V Operating junction temperature range Ty 2 0 C to 150 C Storage temperature range Tag 44444u 65 C to 150 C Lead temperat
17. and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding t
18. ation examples Figure 29 shows a configuration using the internal ADC references for digitizing a single ended signal with span 0 V to 2 V Tying REFSENSE to ground gives 1 V at pin VREF Tying MODE to AVpp 2 then sets the REFT and REFB voltages via the internal reference generator for a 2 Vp p ADC input range The VREF pin provides the 1 V mid scale bias voltage required at AIN VREF should be well decoupled to AGND to prevent sample and hold switching at AIN from corrupting the VREF voltage AVpp 2 ay 200 1V 0v 10 uF VREF 1V 0 1 uF e 10 uF REFSENSE e e REFB 0 1 uF Figure 29 Operating Configuration 2 V Single Ended Input Internal ADC References 3 TEXAS INSTRUMENTS www ti com 21 THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 PRINCIPLES OF OPERATION operating configuration examples continued Figure 30 shows a configuration using the internal ADC references for digitizing a dc coupled differential input with 1 5 Vp p span and 1 5 V common mode voltage External resistors are used to set the internal bandgap reference output at VREF to 0 75 V Tving MODE to AVpp then sets the REFT and REFB voltages via the internal reference generator for a 1 5 Vp p ADC input range If a transformer is used to generate the differential ADC input from a single ended signal then the BIASREF pin provides a suitable bias voltage for the secondarv windings center tap when MODE
19. c coupling networks connecting the signal sources to the AIN or AIN inputs This removes the need for the user to provide a stabilized external bias reference da TEXAS INSTRUMENTS www ti com 17 THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 PRINCIPLES OF OPERATION internal reference mode MODE AVpp or AVpp 2 continued AVDD AVDD or 2 FS AIN _FS FS Fra aft _FS REFSENSE V TREIE a e VREF 1 V Output V Vmip if MODE AVDD 10uF 0 1 uF 0 1 uF OuF O14 BIASREF AVDD High Impedance if MODE D Figure 23 Internal Reference Mode 1 V Reference Span AVDD FS SC or AVDD Em FS DC SOURCE VM O 0 1 uF o o 0 5 V Output V 1 G 0 1 uF OuF 0 1 uF e e REFB REFSENSE V Figure 24 Internal Reference Mode 0 5 V Reference Span Single Ended Input da TEXAS INSTRUMENTS 18 www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 PRINCIPLES OF OPERATION onboard reference generator configuration The internal bandgap reference A1 can provide a supply voltage independent and temperature independent voltage on pin VREF External connections to REFSENSE control A1 s output to the VREF pin as shown in Table 1 Table 1 Effect of REFSENSE Connection on VREF Value REFSENSE CONNECTION A1 OUTPUT TO VREF SEE External divider junction 1 Ra Rb 2 V Figure 27 AVDD Figure 28 REFSENSE AVpp
20. ce at the time of release of power down and an applied 40 MHz clock Circuits that need to power up are the bandgap bias generator ADC and SHA Power up time Power up time is from the power down state to accurate ADC samples being taken and is specified for MODE AVpp 2 or AVpp and an applied 40 MHz clock Circuits that need to power up include VREF reference generation A1 bias generator ADC the SHA and the on chip ADC reference generator A2 Aperture delay The delay between the 50 point of the rising edge of the clock and the instant at which the analog input is sampled Aperture uncertainty Jitter The sample to sample variation in aperture delay 28 da TEXAS INSTRUMENTS www ti com K Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 4 Mar 2005 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty THS1040CDW ACTIVE SOIC DW 28 20 Pb Free CU NIPDAU Level 2 250C 1VEAR RoHS Level 1 220C UNLIM THS1040CDWR ACTIVE SOIC DW 28 1000 Pb Free CU NIPDAU Level 2 250C 1VEAR RoHS Level 1 220C UNLIM THS1040CPW ACTIVE TSSOP PW 28 50 None CU NIPDAU Level 2 220C 1 YEAR THS1040CPWR ACTIVE TSSOP PW 28 2000 None CU NIPDAU Level 2 220C 1 YEAR THS1040IDW ACTIVE SOIC DW 28 20 Pb Free CU NIPDAU Level 2 250C 1VEAR RoHS Level 1 220C UNLIM THS1040IDWR ACTIVE SOIC DW 28 1000 Pb Free CU NIPDAU Level 2 250C
21. ched Capacitor Input AIN input damping The charging current pulses into AIN and AIN can make the signal sources jump or ring especially if the sources are slightly inductive at high frequencies Inserting a small series resistor of 20 Q or less and a small capacitor to ground of 20 pF or less in the input path can damp source ringing see Figure 34 The resistor and capacitor values can be made larger than 20 Q and 20 pF if reduced input bandwidth and a slight gain error due to potential division between the external resistors and the AIN equivalent resistors are acceptable Note that the capacitors should be soldered to a clean analog ground with a common ground point to prevent any voltage drops in the ground plane appearing as a differential voltage at the ADC inputs V en C lt 20 pF V Figure 34 Damping Source Ringing Using a Small Resistor and Capacitor driving the VREF pin Figure 35 shows the equivalent load on the VREF pin when driving the ADC internal references buffer via this pin MODE AVpp 2 or AVpp and REFSENSE AVpp VREF The nominal input current IREF is given by AV 3V HEF AVpp RIN 10 ko k REFSENSE AVpp MODE AVpp NE AVpp 2 or AVpp AGND Oo AVDD VREF 4 V Figure 35 Equivalent Circuit of VREF DD IREF AXR IN 13 da TEXAS INSTRUMENTS www ti com 25 THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 APPLICATION INF
22. e internal VREF generator A1 is not required it can be powered down by tying pin REFSENSE to AVpp saving approximately 1 2 mA of supply current If the BIASREF function is not required when using internal references then tying MODE to AVpp 2 powers the BIASREF buffer down saving approximately 1 2 mA digital UO While the OE pin is held low ADC conversion results are output at pins DO LSB to D9 MSB The ADC input over range indicator is output at pin OVR OVR is also disabled when OE is held high The only ADC output data format supported is unsigned binary output codes 0 to 1023 Twos complement output output codes 512 to 511 can be obtained by using an external inverter to invert the D9 output da TEXAS INSTRUMENTS www ti com 23 THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 APPLICATION INFORMATION driving the THS1040 analog inputs driving the clock input Obtaining good performance from the THS1040 requires care when driving the clock input Different sections of the sample and hold and ADC operate while the clock is low or high The user should ensure that the clock duty cycle remains near 50 to ensure that all internal circuits have as much time as possible in which to operate The CLK pin should also be driven from a low jitter source for best dynamic performance To maintain low jitter at the CLK input any clock buffers external to the THS1040 should have fast rising edges Use a fast logic fami
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25. ly such as AC or ACT to drive the CLK pin and consider powering any clock buffers separately from any other logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter As the CLK input threshold is nominally around AVpp 2 any clock buffers need to have an appropriate supply voltage to drive above and below this level driving the sample and hold inputs driving the AIN and AIN pins 24 Figure 32 shows an equivalent circuit for the THS1040 AIN and AIN pins The load presented to the system at the AIN pins comprises the switched input sampling capacitor Csample and various stray capacitances C4 and Co AVDD CLK 1 2 pF AIN e ke e e CI C2 CSample vj 8pF d 12pF V AGND o CLK e VCM AIN AIN Common Mode Voltage V Figure 32 Equivalent Circuit for Analog Input Pins AIN and AIN The input current pulses required to charge Csample and C2 can be time averaged and the switched capacitor circuit modelled as an equivalent resistor 1 12 R Cs X ok IN2 where Cs is the sum of Csample and C2 This model can be used to approximate the input loading versus source resistance for high impedance sources da TEXAS INSTRUMENTS www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 APPLICATION INFORMATION AVDD R2 1 Cs fci K AIN AGND VCM AIN AIN Common Mode Voltage Figure 33 Equivalent Circuit for the AIN Swit
26. nalog to digital converter VQ is digitized by the ADC using the voltages at pins REFT and REFB to set the ADC zero scale code 0 and full scale code 1023 input voltages VQ ZS REFT REFB 2 VQ FS REFT REFB 3 Any inputs at AIN and AIN that give VQ voltages less than VQ ZS or greater than VQ FS lie outside the ADC s conversion range and attempts to convert such voltages are signalled by driving pin OVR high when the conversion result is output VQ voltages less than VQ ZS digitize to give ADC output code O and VQ voltages greater than VQ FS give ADC output code 1023 complete svstem and svstem input range Combining the above equations to find the input voltages AIN AIN that correspond to the limits of the ADC s valid input range gives REFB REFT lt AIN AIN lt REFT REFB 4 For both single ended and differential inputs the ADC can thus handle signals with a peak to peak input range AIN AIN of AIN AIN pk pk input range 2 x REFT REFB 5 The REFT and REFB voltage difference and the gain sets the device input range The next sections describe in detail the various methods available for setting voltages REFT and REFB to obtain the desired input span and device performance da TEXAS INSTRUMENTS www ti com 15 THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 PRINCIPLES OF OPERATION ADC reference generation The THS
27. neration MODE AGND Connecting pin MODE to AGND powers down the internal references buffer A2 and disconnects its outputs from the REFT and REFB pins The user must connect REFT and REFB to external sources to provide the ADC reference voltages required to match the THS1040 input range to their application requirements The common mode reference voltage must be AVpp 2 for correct THS1040 operation DEET REFB _ AVpp 6 2 2 da TEXAS INSTRUMENTS www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 PRINCIPLES OF OPERATION internal reference mode MODE AVpp or AVpp 2 AVDD VREF 2 AIN x1 Sample ADC and Core ES AIN X 1 Hold VREF Internal e eg Er Reference 2 AGND Buffer Figure 22 ADC Reference Generation MODE AVpp 2 Connecting MODE to AVpp or AVpp 2 enables the internal ADC references buffer A2 The outputs of A2 are connected to the REFT and REFB pins and its inputs are connected to pins VREF and AGND The resulting voltages at REFT and REFB are REFT App 5 VREF S m AVpD VREF 8 Depending on the connection of the REFSENSE pin the voltage on VREF may be driven by an off chip source or by the internal bandgap reference A1 see onboard reference generator to match the THS1040 input range to their application requirements When MODE AVpp the BIASREF pin provides a buffered stabilized AVpp 2 output voltage that can be used as a bias reference for a
28. not return via the supplies to any sensitive analog circuits The THS1040 should be soldered directly to the PCB for best performance Socketing the device degrades performance by adding parasitic socket inductance and capacitance to all pins user tips for obtaining best performance from the THS1040 Choose differential input mode for best distortion performance Choose a 2 V ADC input span for best noise performance Choose a 1 V ADC input span for best distortion performance e Drive the clock input CLK from a low jitter fast logic stage with a well decoupled power supply and short PCB traces e Use a small RC filter typically 20 Q and 20 pF between the signal source s the AIN and AIN input s when the systems bandwidth requirements allow this da TEXAS INSTRUMENTS www ti com 27 THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 APPLICATION INFORMATION definitions Integral nonlinearity INL Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale The point used as zero occurs 1 2 LSB before the first code transition The full scale point is defined as a level 1 2 LSB beyond the last code transition The deviation is measured from the center of each particular code to the true straight line between these two endpoints Differential nonlinearity DNL An ideal ADC exhibits code transitions that are exactly 1 LSB apart DNL is the deviation f
29. rom this ideal value Therefore this measure indicates how uniform the transfer function step sizes are The ideal step size is defined here as the step size for the device under test i e last transition level first transition level 21 23 Using this definition for DNL separates the effects of gain and offset error A minimum DNL better than 1 LSB ensures no missing codes Zero error Zero error is defined as the difference in analog input voltage between the ideal voltage and the actual voltage that switches the ADC output from code O to code 1 The ideal voltage level is determined by adding the voltage corresponding to 1 2 LSB to the bottom reference level The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels 1024 Full scale error Full scale error is defined as the difference in analog input voltage between the ideal voltage and the actual voltage that switches the ADC output from code 1022 to code 1023 The ideal voltage level is determined by subtracting the voltage corresponding to 1 5 LSB from the top reference level The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels 1024 Wake up time Wake up time is from the power down state to accurate ADC samples being taken and is specified for MODE AGND with external reference sources applied to the devi
30. s package materials that do not contain halogens including bromine Br or antimony Sb above 0 1 of total product weight 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 MECHANICAL DATA DW R PDSO 6G28 PLASTIC SMALL OUTLINE PACKAGE 0 713 18 10 0 697 17 70
31. st be separately decoupled for best performance Each supply needs at least a 10 uF electrolytic or tantalum capacitor as a charge reservoir and a 100 nF ceramic type capacitor placed as close as possible to the respective pins to suppress spikes and supply noise digital output loading and circuit board layout The THS1040 outputs are capable of driving rail to rail with up to 10 pF of load per pin at 40 MHz clock frequency and 3 V digital supply Minimizing the load on the outputs improves THS1040 signal to noise performance by reducing the switching noise coupling from the THS1040 output buffers to the internal analog circuits The output load capacitance can be minimized by buffering the THS1040 digital outputs with a low input capacitance buffer placed as close to the output pins as physically possible and by using the shortest possible tracks between the THS1040 and this buffer Inserting small resistors in the range 100 O to 300 Q between the THS1040 I O outputs and their loads can help minimize the output related noise in noise critical applications Noise levels at the output buffers which may affect the analog circuits within THS1040 increase with the digital supply voltage Where possible consider using the lowest DVpp that the application can tolerate Use good layout practices when designing the application PCB to ensure that any off chip return currents from the THS1040 digital outputs and any other digital circuits on the PCB do
32. t is output via data pins DO to D9 The output buffers can be disabled by pulling pin OE high The following sections explain further How signals flow from AIN and AIN to the ADC core and how the reference voltages at REFT and REFB set the ADC input range and hence the input range at AIN and AIN How to set the ADC references REFT and REFB using external sources or the internal reference buffer A2 to match the device input range to the input signal How to set the output of the internal bandgap reference A1 if required signal processing chain sample and hold ADC Figure 20 shows the signal flow through the sample and hold unit to the ADC core REFT VQ AIN ADC Core a AIN VQ REFB Figure 20 Analog Input Signal Flow da TEXAS INSTRUMENTS www ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 PRINCIPLES OF OPERATION sample and hold Differential input signal sources can be connected directly to the AIN4 and AIN pins using either dc or ac coupling For single ended sources the signal can be dc or ac coupled to one of AIN or AIN and a suitable reference voltage usually the midscale voltage see operating configuration examples must be applied to the other pin Note that connecting the signal to AIN results in it being inverted during sampling The sample and hold differential output voltage VQ VQ VQ is given by VQ AIN AIN 1 a
33. ure 1 6 mm 1 16 in from case for 10 seconds 300 C f Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability recommended operating conditions over operating free air temperature range TA unless otherwise noted PARAMETER CONDITION MIN NOM MAX UNIT Power Supply supp votage Wop vo o Po v Analog and Reference Inputs Np 005 AVDA 00 v Analog input voltage differential see Note 1 Analog input capacitance C Clock input see Note 2 Digital Outputs Maximum digital upurtoag resistance Ju qo CS Maximum digital output load capacitance CL II ole Digital Inputs High level input voltage VIH Low level input Te E ET EE EE eme Kl Operating free air temperature TA THS10401 un amp NOTE 1 VI AIN is AIN AIN range based on VI REFT V REFB 1 V Varies proportional to the VI REFT VI REFB Value Input common mode Une is recommended to be auer NOTE 2 The clock pin is referenced to AVss and powered by AVpp NOTE 3 Clock frequency can be extended to this range without degradation of performance 43 TEXAS INSTRUM
34. w ti com THS1040 SLAS290C OCTOBER 2001 REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS SIGNAL TO NOISE PLUS DISTORTION TOTAL HARMONIC DISTORTION vs Vs INPUT FREQUENCV INPUT FREQUENCV Diff t 2V m as 82 Diff Input 2 V 57 Diff Input 1 V d E 2 d Diff Input 1 V 6 AW c 52 N a e g N E a N a w 47 c 2 N 5 2 VE 42 SE Input 1 V c g D o e e o 37 SE Input 2 V o MK S m SE Input 1 V a See Note See Note SE Input 2 V 32 32 0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120 fj Input Frequency MHz fj Input Frequency MHz Figure 9 Figure 10 NOTE AVpp DVpp 3 V fg 40 MSPS 20 pF capacitors AIN to AGND and AIN to AGND Input series resistor 25 Q 2 V Input Ext Ref REFT 2 V REFB 1 V 0 5 dBFS 1 V Input Ext Ref REFT 1 75 V REFB 1 25 V 0 5 dBFS TOTAL HARMONIC DISTORTION SIGNAL TO NOISE RATIO vs Vs SAMPLE RATE SAMPLE RATE 75 2 70 l T 5 1 65 8 o E a e 60 5 5 55 E o e S Gd P 50 l z Q f l 45 E Diff Input 2 V Diff Input 2 V fi 20 MHz 0 5 dBFS fi 20 MHz 0 5 dBFS 40 0 5 10 15 20 25 30 35 40 45 50 55 0 5 10 15 20 25 30 35 40 45 50 55 Sample Rate MSPS Sample Rate MSPS Figure 11

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