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TEXAS INSTRUMENTS THS0842 EVM user manual

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2. 1 4 Default Jumper Positions eens 1 4 Daughtercard Connector J2 ge 2 3 Daughtercard Connector J5 lt eee teens 2 4 Minimum Maximum Reference Input Levels 2 5 Chapter 1 Overview This chapter gives a general overview of the THS0842 evaluation module EVM and describes some of the factors that must be considered in using the module Topic Page deb MIES 1 2 1 2 EVM Basic Function ee e 1 3 1 3 Power Requirements exce aeree Eae Eins 1 3 1 4 THS0842 EVM Operational 1 4 Purpose 1 1 Purpose The THS0842 evaluation module EVM provides a platform for evaluating the THS0842 analog to digital converter ADC under various signal reference and supply conditions The system block diagram is shown below This illustra tion provides a general indication of the features and functions available It should be read in combination with the circuit schematic supplied Figure 1 1 Block Diagram oye Aine e lle THS5651A NET THS0842 lIN m ics DA7 A IIN S CML X o An Qin 5 OUT
3. 5 m 2100 mm 8 000000 00000 2 10000 02 E 3 E THS0842 N eo gt gt E 5 e a So OBE 2 zm 2 g 0000001 5 mr THS0842 EVM 0301 E a 3v DIGITAL 3V ANALOG TP5 SILKSCREEN TOP 4 2 Board Layer 1 Gem aiii e oi l if S POTU JME EE En WR 2 au E DE E MEE Printed Circuit Board Figure 4 3 Printed Circuit Board Layer 2 LAYER 2 AGND PLANE Figure 4 4 Printed Circuit Board Layer 3 Printed Circuit Board LAYER 3 INTERNAL SIGNAL PC Board and Bill of Materials 4 5 Printed Circuit Board Figure 4 5 Printed Circuit Board Layer 4 LAYER 4 POWER PLANE 4 6 Printed Circuit Board Figure 4 6 Printed Circuit Board Layer 5 LAYER 5 DGND P
4. 2 2 2 2 2 Differential Interface 0 2 cet 2 2 2 9 Digital een 2 2 2 31 Internal Clock en ee he ctc eap kin 2 2 2 9 2 External Glock u desert aah E eg ER Re 2 3 2 4 Analog Output se Eodem edo d d cae eie ete 2 3 2 5 Digital Output iunc dee dae ana a a ae 2 3 2 5 ums MEDIEN EIE 2 4 21 POWT ceea 2 5 Layout Decoupling and Grounding Considerations 3 1 PC Board and Bill of Materials 0c cece eee 4 1 4 1 Printed Circuit Board lt tn tenet eens 4 2 4 2 Bil of Materials mm s 4 10 Schem lics oe ese dece wu asia ooo o 6 en 1 Figures 4 5 4 7 Block Diagram TET D 1 2 Printed Circuit Board 0 0 es 4 2 Printed Circuit Board Layer 1 cee cece eee ene 4 3 Printed Circuit Board Layer 2 nneur nannan 4 4 Printed Circuit Board Layer 3 nennen 4 5 Printed Circuit Board Layer 4 4 6 Printed Circuit Board Layer 5 srai 4 7 Printed Circuit Board Layer 6 nn 4 8 Printed Circuit Board Bottom eee ees 4 9 Tables vi Jumper List Table u m tadini aAA Bind d
5. 8 16 Bours 2NBS Series 4816P 1 330 2K R2 R7 1206 1 4W 1206 Chip Mouser 263 2 00K resistor 10K R31 R32 R33 1 4W 1206 Chip Mouser 263 10 R34 R43 R45 resistor R46 R47 R50 R53 R54 R55 R60 1 0K R44 1206 1 4W 1206 Chip Mouser 263 1K resistor T1 1T KK81 T1 T2 T3 T4 MC KK81 RF transformer MINI circuits T1 1T KK81 TSW 101 07 LS TP1 2 TP3 Turret terminal test Samtec TSW 101 07 LS 4 TP5 TP6 point TP7 TP9 TP10 TP11 TP12 TP14 TP15 TP16 1P17 REF test_point2 Turret terminal test Samtec TSW 101 07 LS REF point 74LVC827A 24 SOP DW 10 Bit bus interface FF TI SN74LVC827ADW 350 SN74LVC08A 14 SOP D Quad NAND gate SN74LVCO8AD TL1431CD 8 SOP D Precision TI TL1431QD programmable reference TLV2772 8 SOP D Dual op amp in 8 pin TI TLV27721D SOP package THS0842 48 TQFP PFB THS0842 TI THS0842IPFB THS56X1 28 SOIC DW 2 7 5 5V 10 bit T THS5651IDW 125 MHz communications DAC 2pos_jump 2 Position jumper _ Samtec TSW 102 07 L S 0 1 spacing 3POS JUMPER W9 W12 W13 TSW 103 07 L S W14 W15 W16 3 Position jumper _ 0 1 spacing 4PIN_XTL_DC Crystal oscillator Digikey SG 8002DC 80 MHz SCC 80 00 MHz 3pos jump XTAL PC Board and Bill of Materials 4 11 4 12 Appendix Schematics This Appendix contains the THS0842 EVM schematics A 1 2
6. THS5651A Optional External Reference EVM Basic Function 1 2 EVM Basic Function Analog inputs to the ADC are provided via six external SMB connectors Two pairs of SMB connectors provide true differential inputs or two individual SMB connectors provide single ended transformer coupled signals to the inputs of the device The EVM provides an external SMB connection for input of the ADC clock A crystal oscillator is provided on the board to perform this function and can be used when required Refer to the section on clocking for correct provisioning Digital output from the EVM is via two 25 pin connectors The digital lines from the ADC are buffered before going to the connectors More information on these connectors can be found in the ADC output section Analog output from the EVM is via two SMB connectors J1 and J3 A pair of THS5651 10 bit DACS are used to recreate the analog signal from the ADC s digital data More information on this can be found in the ADC analog output section Power connections to the EVM are via a pair of screw down connectors Separate input connectors are provided for the analog and digital supplies 1 3 Power Requirements 1 3 1 The EVM is powered directly through independent 3 3 V analog and digital supplies Voltage Limits Exceeding the 3 3 V maximum can damage EVM components Under voltage may cause improper operation of some or all of the EVM components Ove
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8. strapped across pins 1 and 2 2 3 Digital Inputs The THS0842 EVM utilizes jumpers for all digital inputs with the exception of the external clock There are no connectors for setting the digital inputs Refer to the jumper table Table 1 1 for a description of the jumpers and their func tion 2 3 1 Internal Clock The EVM provides flexibility as to the source of the ADC s conversion clock This clock can come from an external signal generator as described in Section 2 3 2 orby enabling onboard 80 MHz oscillator X1 Removing the shorting bar from W will enable oscillator X1 Adding a shorting bar to jumper pins W6 will direct clock oscillations from oscillator X1 to buffer amplifier U10A and to the rest ofthe circuit The EVM is shipped with external clock selected W6 open and W3 shorted Dez gt gt gt Note R49 must be removed to avoid loading the output of X1 I 2 2 Circuit Function 2 3 2 External Clock SMB Connector J4 can be used to input a clock signal to the board from an external source The input source should be a 50 Q LVTTL square wave signal with an amplitude of 3 3 V referenced to digital ground This is the default setup for the EVM 2 4 Analog Output The ADC digital data is buffered and sent to a pair of THS5651A DACs The 5651 DACs latch the THS0842 data on COUT Q DAC or COUT I DAC An analog signal is generated on J1 for the l output and J3 for the Q output The DAC outputs can only be used
9. when the THS0842 EVM is set up for dual bus mode W8 installed SELB low For further information on the THS5651A please refer to the product folder on Tl s website http www ti com sc docs products analog ths565 1a htmil 2 5 Digital Output The digital output codes ofthe ADC are made available on two 26 pin headers along with COUT and COUT J2 provides access to the data from the l input and J5 provides access to the data from the Q input The output is 3 3 V TTL compatible Table 2 1 Daughtercard Connector J2 J2 Pin Name Function J2 Pin Name Function 1 DAO louT0 2 DGND Ground 3 DA1 lout 4 DGND Ground 5 DA2 louT2 6 DGND Ground 7 DA3 louT3 8 DGND Ground 9 DA4 louT4 10 DGND Ground 11 DA5 lout 12 DGND Ground 13 DA6 louT6 14 DGND Ground 15 DA7 louT7 16 DGND Ground 17 RSVD NC 18 DGND Ground 19 RSVD NC 20 DGND Ground 21 COUT COUT clock 22 DGND Ground 23 COUT COUT clock 24 DGND Ground 25 80 MHz 80 MHz clock 26 DGND Ground Circuit Functionality 2 3 Circuit Function Table 2 2 Daughtercard Connector J5 2 6 References 2 4 J2 Pin Name Function J2 Pin Name Function 1 DBO 2 DGND Ground 3 DB1 Qour 4 DGND Ground 5 DB2 QouT2 6 DGND Ground 7 DB3 Qout3 8 DGND Ground 9 DB4 Qout4 10 DGND Ground 11 DB5 Qout5 12 DGND Ground 13 DB6 Qour6 14 DGND Ground 15 DB7 Qout7 16 DGND Ground 17 RSVD NC 18 DGND Ground 19 RSVD NC 20 DGND Ground 21 COUT COUT clock 22 DGND Ground 23 COUT COUT clock 24 DGND Ground 25 80 MHz 80 M
10. 78 C80 C82 C84 C85 C87 C89 C91 C43 C51 3216 Low profile tantalum Digikey PCS1475CT ND capacitor 05 C7 C12 C20 8 Multilayer ceramic Mouser 77 VJ08A100V471J C22 C26 C33 C35 C36 C39 C41 C64 C66 C70 C74 C79 C25 C28 C31 805 Multilayer ceramic Digikey PCC1807CT ND C32 805 C1 C9 C27 Multilayer ceramic Mouser 77 VJO8Y50V103K C30 C55 C56 C57 C58 C81 C83 D1 D2 LED 1206 LED with LENS 67 1357 1 J3 SMA JACK PCB mount SMA jack Johnson 142 0701 206 Components 6 7 2term_screw_con 2 Terminal screw 506 5ULVO2 connector J1 J8 J9 SMA_JACK PCB mount SMA jack Johnson 142 0701 206 J10 J11 J12 J13 J2 J5 13x2x0 1 26 Pin header o Tsw 113 07 L D L1 L3 DO1608C DO1608C Series Coil Craft L2 DO1608C DO1608C Series Coil Craft R4 R5 R6 R8 1206 Mouser 263 20 R9 R11 R12 R13 R14 R15 R17 R18 R19 R20 R21 R24 R25 R26 R27 R28 R48 Mouser 77 VJ08Y50V104K Components R39 R40 R41 1206 1 4W 1210 Chip Mouser 290 49 9 resistor R42 R49 R57 R58 R61 R62 R63 R64 Bill of Materials 750 R36 1206 1 4W 1206 Chip Mouser 290 750 resistor 1 00 R16 R23 R35 1206 1 4W 1206 Chip Mouser 263 0 R37 R51 R52 resistor 2 49K 1 R38 1206 1 4W 1206 Chip Mouser 263 2 49K resistor 1 0K R22 R44 R56 1206 1 4W 1206 Chip Mouser 263 1K R59 resistor 2K POT R29 R30 BOURNS Digikey 3214W 202ECT ND 33 R1 R3 R10 2
11. ATH S0842EV M fj fS TEXAS INSTRUMENTS THS0842 EVM Users Guide September 2000 AAP Data Conversion SLAU043C IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express o
12. Hz clock 26 DGND Ground The EVM can use either the THS0842 internal reference a tunable external reference generated on the EVM board or a customer provided external reference The THS0842 s input range is determined by the voltages on its VREFB and VREFT pins Since the part has an internal voltage reference generator it must be powered down W4 removed before applying an external voltage to the REFT and REFB pins It is advantageous to have a wider analog input range especially at higher sampling rates This can be achieved by using external voltage references For example at AVpp 3 3 V the full scale range can be extended from 1 Vpp internal reference to 1 3 Vpp external reference as shown in Table 3 3 These voltages should not be derived from a power supply source via a voltage divider Use instead a bandgap derived voltage reference to derive both references via an operational amplifier circuit Refer to the schematic of the THS0842 evaluation module for an example circuit The full scale ADC input range and its position can be adjusted when using external references The full scale ADC range is always equal to VREFT VREFB The maximum full scale range is dependent on AVDD as shown in the THS0842 data sheet specifications section Aside from the constraint on their difference there are limitations on the useful range of VREFT and individually depending on the value of AVpp Table 3 3 summarizes these limit
13. LANE PC Board and Bill of Materials Printed Circuit Board Figure 4 7 Printed Circuit Board Layer 6 4 8 LAYER 6 SOLDER SIDE BOTTOM Printed Circuit Board Figure 4 8 Printed Circuit Board Bottom MV3 SA802HT A 2 U 30AM SILKSCREEN BOTTOM PC Board and Bill of Materials 4 9 Bill of Materials 4 2 of Materials Part Type 10 uF 0 1 0 1 4 7 uF 470 pF 1 0 0 01 uF GREEN LED SMA JACK KRMZ2 SMA 26PIN IDC 4 7 uH 1 0 uH 20 49 9 C4 C8 C12 Low profile tantalum Digikey PCS1156CT ND C14 C16 C18 capacitor C21 C23 C29 C44 C48 C49 C52 C54 C59 C60 C61 C62 C86 C88 C90 Mouser 77 VJ12U50V104M 2 5 Multilayer ceramic C10 C11 C17 variable footprint C65 C71 C6 C13 C15 Multilayer ceramic C19 C24 C34 C37 C38 C40 C42 C45 C46 C47 C50 C53 C63 C67 C68 C69 C72 C78 C75 C76 C77 C
14. W12 2 3 W13 2 3 W14 2 3 W15 2 3 W16 1 2 1 Set both dc power supplies to read 3 3 V at the output terminals Connect GND of the first power supply to the AGND J6 2 terminal on the EVM and GND of the other power supply to the DGND J7 2 terminal on the EVM Then connect the first power supply s 3 3 V output to the AVDD pow J6 1 terminal of the EVM and the other power supply s 3 3 V output to the DVDD J7 1 terminal of the EVM 2 Switch power supplies on 3 Setfunction generator number one to output a square wave ata frequency of 80 MHz 0 V offset and an amplitude of 3 3 V on the 50 Q output 4 Use a50 Q coaxial cable with BNC SMB connectors to connect generator number 1 to J4 clock input THS0842 EVM Operational Procedure Set function generator number 2 to output a sine wave at a frequency of 1 MHz 0 V offset and an amplitude of 0 8 Vp p on the 50 Q output Use a 50 Q coaxial cable with BNC SMB connectors to connect generator number 2 to J8 Q input Use a T splitter to connect the test signal to chan nel 1 of the oscilloscope Use a 50 Q coaxial cable with BNC SMB connectors to connect the se cond channel of the oscilloscope to J3 Q output The two sine waves should have the same period their amplitudes may differ Repeat Step 5 with the SMB connected to J11 l input Repeat Step 6 except connect to J1 l output Overview 1 5 1 6 Chapter 2 Circuit Functionality This ch
15. apter describes the digital interface master clock ADC data and power supply Topic Page 2 10 Circuit 3 2 2 72 SECHS 2 2 2 3 DigitallIMPUtsS een as 2 2 24 Analog Output yer eee 2 3 ZAD IFA E EIE 2 3 26 ACU 2 4 ZO 2 5 2 1 Circuit Function 2 1 Circuit Function The following sections describe the function of individual circuits Refer to the relevant data sheet for device operating characteristics 2 2 Analog Inputs The ADC has either transformer coupled single ended or differential analog inputs These are provided on the EVM via SMB connectors J8 and J11 for single ended inputs or J9 J10 and J12 J13 for differential inputs and can configured in two ways as discussed in Sections 2 2 1 and 2 2 2 2 2 1 Single Ended Transformer Coupled Interface Connectors J8 and J11 1 are single ended inputs that use a 1 1 transform er to provide differential analog inputs to the I l and Q Q inputs of U11 THS0842 The signal input is nominally 0 89 Vpp W12 W13 W14 and W15 should be strapped across pins 2 and 3 The inputs have 50 Q terminators 2 2 2 Differential Interface Connectors J9 A J10 Q J12 II and J13 I are used to connect ac coupled differential signals directly to U11 THS0842 The signal inputis nom inally a 0 44 Vpp W12 W13 W14 and W15 should be
16. r implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated About This Manual Preface Read This First This document presents a description of the THS0842 evaluation module How to Use This Manual This document contains the following chapters D D D O Chapter 1 Overview Chapter 2 Circuit Functionality Chapter 3 Layout Decoupling and Grounding Considerations Chapter 4 PC Board and Bill of Materials Appendix A Schematics Contents Overview 1 1 1 4 Purpose RR 1 2 1 2 EVMBasic Function een nennen nenn 1 3 1 3 Power Requirements k 1 3 1 3 1 Voltage LIMIS EUR 1 3 1 4 THS0842 EVM Operational Procedure 1 4 Circuit Functionality 4 44 4444 lt lt lt lt lt mh nn 2 1 2 1 Circuit FUNCION wi cc eee e ee 2 2 2 2 Analog IMPULS e site wet odie ce RE BE Goble ele ool alee sade 2 2 2 21 Single Ended Transformer Coupled Interface
17. rview 1 3 THS0842 EVM Operational Procedure 1 4 THS0842 EVM Operational Procedure The THS0842 EVM provides a flexible means of evaluating the THS0842 in anumber of modes of operation A basic setup procedure that can be used as a board confidence check follows 1 Verify all jumper settings against the schematic jumper list in Table 1 1 Table 1 1 Jumper List Table Jumper Function Installed Removed Default W1 Reserved for future use Required Do not use Installed W2 Reserved for future use Required Do not use Installed W3 Oscillator power down Power down Active Installed WA Reference select Internal External Installed W5 THS0842 standby Active Power down Installed W6 Select clock source Onboard Offboard Removed W7 Digital bus output enable 3 state bus Active Removed W8 Single dual bus mode Dual mode Single mode Installed W9 External REFB source 1 2 onboard 2 3 offboard 1 2 W10 External REFB feed External Internal Removed wii External REFT feed External Internal Removed W12 Q Input select 1 2 differential 2 3 single ended 2 3 W13 Q Input select 1 2 differential 2 3 single ended 2 3 W14 1 Input select 1 2 differential 2 3 single ended 2 3 W15 I Input select 1 2 differential 2 3 single ended 2 3 W16 External REFT source 1 2 onboard 2 3 offboard 1 2 Table 1 2 Default Jumper Positions EVM Jumper Table connection THS0842 W1 W2 W3 W4 W5 W7 W9 1 2
18. s for three cases Circuit Function Table 2 3 Minimum Maximum Reference Input Levels AVpp VREFB min 3 0 V 3 3V 3 6 V 2 7 Power 0 8 V 0 8 V 0 8 V VREFB max VREFT min VREFT max VnErr VREFBlmax 1 2V 1 8V 2 2V 1 0 V 1 2V 2 1V 25V 13V 1 2 V 2 4 V 2 8 V 1 6 V Power is supplied to the EVM via screw down connectors For best perfor mance use a separate low noise analog power supply connected to J6 1 3 3 V and 46 2 GND Use a separate low noise digital power supply connected to J7 1 3 3 V and J7 2 GND The positive side is marked by a on the EVM s silkscreen placed next to the connectors themselves Circuit Functionality 2 5 2 6 Chapter 3 Layout Decoupling and Grounding Considerations Proper grounding and layout of the PCB is essential to achieve the stated performance It is advised to use separate analog and digital ground planes that are spliced underneath the device The THS0842 has digital and analog terminals on opposite sides of the package to make this easier Since there is no internal connection between analog and digital grounds they have to be joined on the PCB This should be done at one point in close proximity to the THS0842 Separate analog and digital power supply terminals are provided on the device AVpp DVpp The supply to the digital output drivers DRVpp is also kept separate Lowering the voltage on this supply to 3 V instead of the nominal 3 3 V improves performance d
19. ue to the lower switching noise caused by the output buffers Because of the high sampling rate and switched capacitor architecture the THS0842 generates transients on the supply and reference lines Proper decoupling of these lines is essential Decoupling as shown in the schematic of the THS0842 EVM is recommended 3 1 3 2 Chapter 4 PC Board and of Materials This chapter presents the PC board design and a listing of the parts required to build this evaluation module Topic Page 41 oer ana 4 2 4 10 42 Bill of Materials 4 1 Printed Circuit Board 4 1 Printed Circuit Board This section presents the printed circuit board for the THS0842 EVM Figure 4 1 Printed Circuit Board Top TPi4 TPIS I 100 v sna 2 0 Ino a sna 000000000000 zi 5 5 i 2 5 5 jse

TEXAS INSTRUMENTS THS0842 EVM user manual

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