PHILIPS 74ABT00 handbook
Contents
1. 14 leads body width 3 9 mm SOT108 1 Hu 2 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions inches Note 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAJ PROJECTION SOT 108 1 07655088 MS 012AB ET 97 05 22 ISSUE DATE 1995 Sep 18 6 Philips Semiconductors Quad 2 input NAND gate SSOP14 plastic shrink small outline package 14 leads body width 5 3 mm pin 1 index DIMENSIONS mm are the original dimensions Product specification 74ABT00 SOT337 1 UNIT A3 max 2 0 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES VERSION JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT337 1 MO 150AB E40 25 02 04 96 01 18 1995 Sep 18 7 Philips Semiconductors Quad 2 input NAND gate TSSOP14 plastic thin shrink small outline package 14 leads body width 4 4 mm Ge sj pin 1 index DIMENSIONS mm are the original dimensions Product specification 74ABT00 SOT402 1 UNIT A A2 Ag D j Ee 0 15 0 95 5 1 4 5 0 05 0 80 4 9 4 3 Notes 1 Plastic or metal protrusions of 0 15 mm maximum per sid2. GENERATOR lt 2 ke tTHL tF AMP V POSITIVE PULSE Test Circuit for Outputs 10 VM 1 5V Input Pulse Definition DEFINITIONS Load resistor see AC CHARACTERISTICS for value INPUT PULSE REQUIREMENTS Load capacitance includes jig and probe capacitance FAMILY see AC CHARACTERISTICS for value Amplitude Rep Rate tw te Termination resistance should be equal to Zour of pulse generators 3 0V 1MHz 2 5ns SH00067 1995 Sep 18 4 Philips Semiconductors Quad 2 input NAND gate DIP14 plastic dual in line package 14 leads 300 mil seating plane in 1 index a 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions Product specification 74ABT00 SOT27 1 A UNIT max Ay min Az max by p EM 4 2 0 51 3 2 19 50 6 48 18 55 6 20 inches 0 17 0 020 0 13 0 77 0 73 0 26 0 24 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT27 1 050G04 MO 001AA EJO 9092 1447 95 03 11 1995 Sep 18 Philips Semiconductors Product specification Quad 2 input NAND gate 74ABT00 014 plastic small outline package
3. e are not included 2 Plastic interlead protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN PROJECTION VERSION JEDEC EIAJ ISSUE DATE SOT402 1 MO 153 E 94 0712 95 04 04 1995 Sep 18 8 Philips Semiconductors Product specification Quad 2 input NAND gate 74ABT00 NOTES 1995 Sep 18 9 Philips Semiconductors Product specification Quad 2 input NAND gate 74ABT00 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development Specifications may change in any manner without notice This data sheet contains preliminary data and supplementary data will be published at a later date Philips Preliminary Specification Preproduction Product Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product This data sheet contains Final Specifications Philips Semiconductors reserves the right to make changes Product Specification Full Production at any time without notice in order to improve design and supply the best possible product Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes without notice in the products including circuits standard cells and or software described or co
4. i INTEGRATED CIRCUITS DATA SAHEET 74ABT00 Quad 2 input NAND gate Product specification 1995 Sep 18 IC23 Data Handbook i sS PHILIPS Semiconductors DH l LI DS Philips Semiconductors Product specification Quad 2 input NAND gate 74ABTOO QUICK REFERENCE DATA LOGIC DIAGRAM CONDITIONS SYMBOL PARAMETER Tamb 25 C TYPICAL UNIT GND 0V Propagation tPLH delay D tPHL An or Bn 0 to Yn 4 3 50 2 2 0 Voc Pin 14 GND Pin 7 SA00360 tosLH Output to tosHL Output skew Input Total supply Outputs disabled cc current Voc 5 5V NUMBER SYMBOL NAME AND FUNCTION PIN CONFIGURATION 5755 5687 Ground OV Positive supply voltage PIN DESCRIPTION SA00333 LOGIC SYMBOL AO BO Ai Bi A2 B2 A3 B3 YO Y1 Y2 Y3 Oo oO 0 SF00004 Voc Pin 14 GND Pin7 SA00334 NOTES H High voltage level L Low voltage level ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 14 Pin Plastic DIP 40 C to 85 C 74ABTOON 74ABTOO N SOT27 1 14 Pin plastic SO 40 C to 85 C 74ABTO0 D 74ABT00 D SOT108 1 14 Pin Plastic SSOP Type II 40 C to 85 C 74ABT00 DB 74ABT00 DB SOT337 1 14 Pin Plastic TSSOP Type 40 C to 85 C 74ABT00 PW 74ABTOOPW DH SOT402 1 1995 Sep 18 2 853 1809 15755 Philips Semiconductors Product specification Quad 2 input NAND gate 74ABT00 ABSOLUTE MAXIMUM RATINGS 2 Veg D suppyvorage P pf OC Cid v
5. i fbcmpuvotegee 4050 fv Tag Storage temperatur amg id oT NOTES 1 Stresses beyond those listed may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 The performance capability of a high performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability The maximum junction temperature of this integrated circuit should not exceed 150 C 3 The input and output voltage ratings may be exceeded if the input and output current ratings are observed RECOMMENDED OPERATING CONDITIONS NT a SYMBOL PARAMETER UNIT a SGV dFH yt HH 5 5 vi freuvoiae 0 vo Tv Ve Hohlevstinputvorage 20 fv Vi ftoievelinpuvetege 0 fv on fmistievetouputeumen pp m tor Lowreveloutpatourent 2 m aay finputanstionnseorfaliae 0 ps fn DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb 25 C Ed C unit ee Vic fiputdampvotage Voc asvinestem I Si te et Vou High level output voege Veo 45Vilon temai Vuorvn 25 20 as fv Vor Lowreveloutputvotage Voo 45Vilo 20mAVi Vuorvn I oases os v i inpatteakagecurent V
6. nics North America Corporation 811 East Arques Avenue register eligible circuits under the Semiconductor Chip Protection Act P O Box 3409 Copyright Philips Electronics North America Corporation 1995 Sunnyvale California 94088 3409 All rights reserved Printed in U S A Telephone 800 234 7381 print code Date of release July 1994 Document order number 9397 750 04854
7. ntained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances devices or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale Philips Semiconductors Philips Semiconductors and Philips Electro
8. oos venos O fonja of Torr Poweroffeakage curent Voo 00W Voon eas feofeo jeo pA C oe Output High eakage curent Voc 55V Vo SV Vi nDoro 50 50 50 a io ommo Vecs fe fs eo a Too JOviescent supply curent Voo 55V VIND arvos e fo sf soc huge PY oren Per pes at vegorang no fom soo soo fu NOTES 1 Not more than one output should be tested at a time and the duration of the test should not exceed one second 2 This is the increase in supply current for each input at 3 4V 1995 Sep 18 3 Philips Semiconductors Product specification Quad 2 input NAND gate 74ABT00 AC CHARACTERISTICS GND OV tp te 2 5ns Ci 50pF Ry 5000 UMTS Tamb AN Tamb 40 C to 85 C SYMBOL PARAMETER WAVEFORM Ve 5 ov Veg 5 0V 20 5V UNIT tpLy Propagation delay 1 0 2 5 3 6 tPHL An or Bn to Yn 1 0 2 0 2 8 fosHL Output to Output skew 0 4 0 5 tosLH An or Bn to Yn 0 4 0 5 NOTE 1 Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device The specification applies to any outputs switching in the the same direction either HIGH to LOW tosH_ or LOW to HIGH tosLH parameter guaranteed by design AC WAVEFORMS Vu 1 5V Vin GND to 3 0V SA00336 Waveform 1 Propagation delay for inverting outputs TEST CIRCUIT AND WAVEFORMS 90 NEGATIVE PULSE J ov PULSE Van tTLH tR
Download Pdf Manuals
Related Search
PHILIPS 74ABT00 handbook