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MOTOROLA MC68331 user manual

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1. VDD VDD NC BGACK CS2 ADDR1 51 ADDR2 BRICSO ADDR3 CSBOOT ADDR4 DATAO ADDR5 DATA ADDR6 DATA2 ADDR7 DATA3 ADDR8 Vgs Vss DATA4 ADDR9 DATA5 ADDR10 DATAG ADDR11 ADDR12 Vss Vss MC68331 DATA8 ADDR13 DATA9 ADDR14 DATA10 ADDR15 DATA11 ADDR16 VDD Vss Vss DATA12 ADDR17 DATA13 ADDR18 DATA14 PQSO MISO DATA15 PQS1 MOSI ADDRO PQS2 SCK PEO DSACKO PQS3 PCSO SS PE1 DSACK1 PQS4 PCS1 PE2 AVEC 55 52 PES RMC PQS6 PCS3 PE5 DS VpD o a QO arc I A IO oN ro x OW o 952285952525 ERE S ERSS 9 Qu d e Pe Pe ee Oo Jit 9 gt Q Eg n ica a 331 132 PIN Figure 1 132 Plastic Surface Mount Package Pin Assignments MOTOROLA MECHANICAL DATA AND ORDERING INFORMATION MC68331 B 2 USER S MANUAL NC Vss BGACK CS2 PEO DSACKO PE1 DSACK1 PE2 AVEC PES DS Vpp 0 53 FC1 CS4 FC2 CS5 ADDR19 CS6 ADDR20 CS7 ADDR21 CS8 ADDR22 CS9 ADDR23 CS10 PAI 3P7 ICA OC5 OC1 PGP6 OC4 PGP
2. 3 7 2 MCU Module Pin Function During Reset SECTION 4 SYSTEM INTEGRATION MODULE 4 1 Genel alc a siu e UNE UEM E 4 2 System Configuration and Protection 4 2 1 Module edo 4 2 2 Interrupt Arbitration neenon sono tae or bebe 4 2 3 Show Internal Cycles 4 2 4 Faclory Test Mode citri 4 2 5 Register ACCOSS cios ia E 4 2 6 Reset Salis iei E e e lad Un ue iE 4 2 7 Bis Momtor etia duo bono pcd ui 4 2 8 dee T 4 2 9 Spurious Interrupt Monitor 4 2 10 Software Watchdog MC68331 USER S MANUAL Page MOTOROLA iii TABLE OF CONTENTS Continued Paragraph Title Page 4 2 11 Periodic Interrupt TITIO 4 7 4 2 12 Low Power STOP Operation D E oad Guta 4 8 4 2 13 Freeze Operation m 4 9 4 3 DV SIGINT ot a E E E e E 4 9 4 3 1 Clock SOUICOS re LL LL a 4 10 4 3 2 Clock Synthesizer Operation 4 10 4 3 3 External Bus Clock 4 4 15 4 3 4 bow Power ODOFallOH diode eic re 4 15 4 3 5 Loss of Reference Signal
3. A 16 A 8 Bus Arbitration Timing Diagram Active Bus Case A 17 A 9 Bus Arbitration Timing Diagram Idle Bus Case A 18 A 10 Show Cycle Timing Diagram A 18 A 11 Chip Select Timing A 19 A 12 Reset and Mode Select Timing A 19 A 13 Background Debugging Mode Timing Diagram Serial Communication 21 A 14 Background Debugging Mode Timing Diagram Freeze Assertion A 21 A 15 Timing e DEDISSE PAPA 23 A 16 QSPI Timing Master 0 A 25 A 17 QSPI Timing Master 1 0004400 00 A 25 A 18 QSPI Timing Slave 0 A 26 19 QSPI Timing Slave 1 A 26 B 1 132 Pin Plastic Surface Mount Package Pin Assignments B 2 B 2 144 Pin Plastic Surface Mount Package Pin Assignments B 3 D 1 User Programming Model ar DEED x veris D 2 D 2 Supervisor Programming Model D 2 MOTOROLA MC68331 xii USER S MANUAL LIST OF TABLES Table Title 3 1 MGU Driver TYPOS 3 2 MCU P
4. ADDRESS 80 BYTE REGISTER QSPI RAM CONTROL LOGIC STATUS REGISTER CONTROL REGISTERS CHIP SELECT COMMAND DELAY COUNTER MSB LSB 8 16 BIT SHIFT REGISTER MOSI PROGRAMMABLE LOGIC ARRAY Rx Tx DATA REGISTER 5 gt MISO lt gt 50 55 E 3 PCS 3 1 BAUD RATE GENERATOR SUR QSPI BLOCK Figure 6 2 QSPI Block Diagram 6 3 1 QSPI Registers The programmer s model for the QSPI consists of the QSM global and pin control reg isters four QSPI control registers SPCR 0 3 a status register SPCR and the 80 byte QSPI RAM Registers and RAM can be read and written by the CPU Refer to APPENDIX D REG ISTER SUMMARY for register bit and field definitions MOTOROLA QUEUED SERIAL MODULE MC68331 6 6 USER S MANUAL 6 3 1 1 Control Registers Control registers contain parameters for configuring the QSPI and enabling various modes of operation The CPU has read and write access to all control registers but the QSM has read only access to all bits except the SPE bit in SPCR1 Control regis ters must be initialized before the QSPI is enabled to ensure defined operation SPCR1 must be written last because it contains the QSPI enable bit SPE Writing a new value to any control register except SPCR2 while the QSPI is enabled disrupts operation SPCR2 is buffered New SPCR
5. Temperature Frequency Package Order Number MHz Order Quantity 40 to 85 C 16 MHz 2 pc tray SPAKMC331CFC16 36 pc tray MC68331CFC16 20 MHz 2 pc tray SPAKMC331CFC20 36 pc tray MC68331CFC20 40 to 105 16 MHz 2 pc tray SPAKMC331VFC16 36 pc tray MC68331VFC16 20 MHz 2 pc tray SPAKMC331VFC20 36 pc tray MC68331VFC20 40 to 125 16 MHz 2 pc tray SPAKMC331MFC16 36 pc tray 68331 6 20 MHz 2 pc tray SPAKMC331MFC20 36 pc tray MC68331MFC20 40 to 85 16 MHz 2 pc tray SPAKMC331CFV16 44 pc tray MC68331 CFV16 20 MHz 2 pc tray SPAKMC331CFV20 44 pc tray MC68331CFV20 40 to 105 16 MHz 2 pc tray SPAKMC331VFV16 44 pc tray MC68331VFV16 20 MHz 2 pc tray SPAKMC331 VFV20 44 pc tray MC68331VFV20 40 to 125 C 16 MHz 2 pc tray SPAKMC331MFV16 44 pc tray MC68331MFV16 20 MHz 2 pc tray SPAKMC331MFV20 44 pc tray MC68331MFV20 40 to 85 16 MHz 2 pc tray SPAKMC331CPV16 60 pc tray MC68331CPV16 20 MHz 2 pc tray SPAKMC331CPV20 60 pc tray MC68331CPV20 40 to 105 16 MHz 2 pc tray SPAKMC331VPV16 60 pc tray MC68331VPV16 20 MHz 2 pc tray SPAKMC331VPV20 60 pc tray MC68331VPV20 40 to 125 16 MHz 2 pc tray SPAKMC331MPV16 60 pc tray MC68331MPV16 20 MHz 2 pc tray SPAKMC331MPV20 60 pc tray MC68331MPV20 Quantity orders are available as shown in Table 2 Contact your Motorola representative for ordering numbers MOTOROLA B 4 Table B 2 Quantity Orde
6. D 12 D 2 16 PWMONT PWM Count Register D 12 D 2 17 PWMBUFA PWM Buffer Register A D 12 D 2 18 PRESCL QGPT Prescale ie pe a aee dose D 12 D 3 System Integration Module D 13 0 3 1 SIMCR Module Configuration Register D 14 D 3 2 SIMTR System Integration Test Register D 15 D 3 3 SYNCR Clock Synthesizer Control Register D 15 D 3 4 RSR Reset Status Register D 16 9 3 5 SIMTRE System Integration Test Register ECLK D 17 D 3 6 PORTEO PORTE1 Port E Data D 17 D 3 7 DDRE Port E Data Direction Register D 17 D 3 8 PEPAR Port E Pin Assignment D 17 D 3 9 PORTFO PORTF1 Port F Data Register D 18 D 3 10 DDRF Port F Data Direction D 18 D 3 11 PFPAR Port Pin Assignment D 18 D 3 12 SYPCR System Protection Control Register D 19 D 3 13 PICR Periodic Interrupt Control Register D 20 D 3 14 PITR Perio
7. 2 111 4 17 MOL e reor eti 4 18 Chip Select Circuit Block Diagram 4 19 CPU Space Encoding for Interrupt Acknowledge 5 1 CPUS2 Block E 5 2 User Programming Model 5 3 Supervisor Programming Model Supplement 5 4 Data Organization in Data 5 5 Address Organization in Address Registers 5 6 Memory Operand Addressing 5 7 Common In Circuit Emulator Diagram 5 8 Bus State Analyzer Configuration 5 9 Debug Serial I O Block Diagram 5 10 BBM Serial Data iu er 5 11 BDM Connector 5 12 Loop Mode Instruction 6 1 QSM Block Diagram sse 6 2 OSP Block Diagram MC68331 USER S MANUAL MOTOROLA xi LIST OF ILLUSTRATIONS Continued Figure Title Page 6 3 QSP RAM tons bp 6 7 6 4 Flowchart of QSPI Initialization 6 11 6 5 Flowchart of QSPI Master Operation Part 1
8. COMMAND CONTROL PERIPHERAL CHIP SELECT PCSO bit represents the dual function PCSO SS Command is used by the QSPI when in master mode The CPU32 writes one byte of control information to this segment for each QSPI command to be executed The QSPI cannot modify information in command RAM Command RAM consists of 16 bytes Each byte is divided into two fields The periph eral chip select field enables peripherals for transfer The command control field pro vides transfer options A maximum of 16 commands can be in the queue Queue execution proceeds from the address in NEWQP through the address in ENDQP both of these fields are in SPCR2 CONT Continue 0 Control of chip selects returned to PORTQS after transfer is complete 1 Peripheral chip selects remain asserted after transfer is complete BITSE Bits per Transfer Enable 0 Eight bits 1 Number of bits set in BITS field of SPCRO DT Delay after Transfer The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that have a latency requirement The delay between transfers is de termined by the SPCR1 DTL field DSCK PCS to SCK Delay 0 PCS valid to SCK transition is one half SCK 1 SPCR1 DSCKL field specifies delay from PCS valid to SCK PCS 3 0 Peripheral Chip Select Peripheral chip select bits are used to select an external device for serial data transfer More th
9. 0 3 MOTOROLA MC68331 viii USER S MANUAL TABLE OF CONTENTS Continued Paragraph Title Page D 2 Gaerieral Purpose TIMET occu o Eb ot ode o Rudd D 4 D 2 1 GPTMCR GPT Module Configuration Register D 4 D 2 2 GPTMTR GPT Module Test Register Reserved D 5 D 2 3 ICR GPT Interrupt Configuration Register D 5 D 2 4 DDRGP Port GP Data Direction Register D 6 D 2 5 1 Action Mask D 6 D 2 6 Timer Counter Register 1 1 D 6 D 2 7 Pulse Accumulator Control Register D 7 D 2 8 TIC 1 3 Input Capture Registers 1 3 D 8 D 2 9 TOC 1 4 Output Compare Registers 1 4 D 8 D 2 10 TI4 O5 Input Capture 4 Output Compare 5 Register D 8 D 2 11 TCTL1 TCTL2 Timer Control Registers 1 and 2 D 8 D 2 12 TMSK1 TMSK2 Timer Interrupt Mask Registers 1 and 2 D 9 D 2 13 TFLG1 TFLG2 Timer Interrupt Flag Registers 1 and 2 D 10 D 2 14 CFORC Compare Force D 10 D 2 15 PWMA PWMB PWM Registers
10. PQSPAR Field PQSPAR Bit Pin Function 0 PQSO 1 MISO PQSPA1 0 PQS1 1 MOSI PQSPA2 0 Pas 1 SCK PQSPA3 0 PQS3 1 50 55 4 0 PQS4 1 PCS1 PQSPA5 0 PQS5 1 PCS2 PQSPA6 0 PQS6 1 PCS3 PQSPA7 0 572 1 TXD 1 PQS2 is a digital I O pin unless the SPI is enabled SPE in SPCR1 set in which case it becomes SPI serial clock SCK 2 PQS7 is a digital I O pin unless the SCI transmitter is enabled TE in SCCR1 1 which case it becomes SCI serial output TXD DDRQS determines whether pins are inputs or outputs Clearing a bit makes the cor responding an input setting a bit makes the pin an output DDRQS affects both QSPI function and function Table 0 15 Effect of DDRQS on PORTQS Pins Pin DDRGS Bit Pin Function 50 0 Digital Input 1 Digital Output PQS1 0 Digital Input 1 Digital Output PQS2 0 Digital Input 1 Digital Output PQS2 0 Digital Input 1 Digital Output PQS3 0 Digital Input 1 Digital Output PQS4 0 Digital Input 1 Digital Output PQS5 0 Digital Input 1 Digital Output PQS6 0 Digital Input 1 Digital Output PQS7 0 Digital Input 1 Digital Output MC68331 REGISTER SUMMARY MOTOROLA USER S MANUAL D 31 Table 0 16 Effect of DDRQS QSM Pin Function Pin Function Serial Data Input to QSPI Disables Data Input Slave Disables Data Output Nod Serial Data Output from
11. 6 12 6 5 Flowchart of QSPI Master Operation Part 2 6 13 6 5 Flowchart of QSPI Master Operation Part 3 6 14 6 6 Flowchart of QSPI Slave Operation Part 1 6 15 6 6 Flowchart of QSPI Slave Operation Part 2 6 16 6 7 SCI Transmitter Block BIagEalTis rv in c bee tete 6 23 6 8 SCI Receiver Block 6 24 7 1 GPT Block Dia ea 7 2 7 2 Prescaler Block Diagram om pov ecu maid 7 9 7 3 Capture Compare Unit Block Diagram 7 10 7 4 Input Capture Timing Example pennas 7 12 7 5 Pulse Accumulator Block 7 15 7 6 PWM 7 16 1 CLKOUT Output Timing 12 2 External Clock Input Timing Diagram A 12 A 3 Output Timing Diagram ocio cero e Pene A 12 4 Read Cycle Timing Diagram A 13 A 5 Write Cycle Timing arms acie EE bt A 14 A 6 Fast Termination Read Cycle Timing Diagram A 15 A 7 Fast Termination Write Cycle Timing
12. Figure 3 3 Pin Assignments for 144 Pin Package 3 3 Pin Descriptions ADDR18 PQSO MISO PQS1 MOSI PQS2 SCK 53 50 55 PQS4 PCS1 PQS5 PCS2 PQS6 PCS3 VDD IPIPE DSO RXD PQS7 TXD VSS NC 331 144 PIN QFP The following tables are a summary of the functional characteristics of MCU pins Ta ble 3 1 shows types of output drivers Table 3 2 shows all inputs and outputs Digital inputs and outputs use CMOS logic levels An entry in the Discrete I O column indi cates that pin can also be used for general purpose input output or both The I O port designation is given when it applies Table 3 3 shows characteristics of power pins Refer to Figure 3 1 for port organization MC68331 USER S MANUAL OVERVIEW MOTOROLA 3 5 Table 3 1 MCU Driver Types Type yo Description A O Output only signals that are always driven no external pull up required Aw O Type A output with weak P channel pull up during reset B O Three state output that includes circuitry to pull up output before high impedance is established to ensure rapid rise time An external holding resistor is required to maintain logic level while the pin is in the high impedance state Bo O Type B output that can be operated in an open drain mode Table 3 2 MCU Pin Characteristics Pin Output Input Input Discrete
13. rennene 4 16 4 4 External Bus Interface eene 4 17 4 4 1 B s SignalS deca ox qo dp Drury DU Mq pidum Rr 4 18 4 4 1 1 rd aou Sota uU T aene tex 4 18 4 4 1 2 Address Up HERUM esie ates 4 18 4 4 1 3 Data dE 4 18 4 4 1 4 Ri ad Ales 4 18 4 4 1 5 Read Write 2 044 4 44600 4 18 4 4 1 6 Size Signals 4 18 4 4 1 7 PUNE HOM GOOG cece E EN 4 19 4 4 1 8 Data and Size Acknowledge Signals 4 19 4 4 1 9 BUS EIMOR Signal 4 19 4 4 1 10 4 20 4 4 1 11 Signal 4 20 4 4 2 Dynamic BUS SIZING 4 20 4 4 3 4 21 4 4 4 Misaligrned Operands ues cul 4 21 4 4 5 Operand Transfer Cases 4 22 4 5 BUS edle dd 4 22 4 5 1 synchronization to CLKOUT orent eee 4 23 4 5 2 Regular Bus CyGles 4 23 4 5 2 1 Head Cycle ien ioo RED UR ER REL M er eres ME 4 24 4 5 2 2 Write Cycle PEE 4 25 4 5 3 Fast Termination Cycles 4 05 4 5 4 CPU Space Cycles 2 0042 4 26 4 5 4 1 Breakpoin
14. 4 20 Assignment Field Encoding 4 21 Block Size Encoding 4 22 Option Register Function Summary 4 23 Chip Select Base and Option Register Reset Values 4 24 CSBOOT Base and Option Register Reset Values 5 1 Instruction Set SUMMAN aoo eoo reete tee tet 5 2 Exception Vector Assignments 5 3 Source Summary essen 5 4 Polling the Entry Source 5 5 Background Mode Command Summary 5 6 CPU Generated Message Encoding 6 1 QSM Pin Function eau e mud 6 2 SP IP itt FUNCION eoe tate diti basi ta ott bte dote 6 3 BITS Encoding 6 4 SGI PIM FUNCION MC68331 USER S MANUAL MOTOROLA xiii LIST OF TABLES Continued Table Title Page 6 5 Seral Frame FOImalS 25 ute ca S e 6 26 6 6 Effect of Parity Checking on Data Size 6 27 7 1 GPT Status Fla 7 4 7 2 Interrupt Sources BOE Seeds 7 5 7 3 PWM Frequency Ranges Using 16 78 MHz 20 97 MHz System Clocks 7 17 A 1 Maxim m a
15. 15 14 11 10 8 7 6 5 4 3 2 1 0 14 05F OCF ICF TOF 0 PAOVF PAIF 0 0 0 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 These registers show condition flags that correspond to GPT events If the corre sponding interrupt enable bit in TMSK1 TMSK2 is set an interrupt occurs 14 05F Input Capture 4 Output Compare 5 Flag When 14 05 is zero this flag is set each time TCNT matches the TOC5 val TI4 O5 When 14 05 is one the flag is set each time a selected edge is detected at the 14 O5 pin OCF 4 1 Output Compare Flags An output compare flag is set each time TCNT matches the corresponding TOC reg ister OCF 4 1 correspond to OC 4 1 ICF 3 1 Input Capture Flags A flag is set each time a selected edge is detected at the corresponding input capture pin ICF 3 1 correspond to IC 3 1 TOF Timer Overflow Flag This flag is set each time TCNT advances from a value of FFFF to 0000 PAOVF Pulse Accumulator Overflow Flag This flag is set each time the pulse accumulator counter advances from a value of FF to 00 PAIF Pulse Accumulator Flag In event counting mode this flag is set when an active edge is detected on the PAI pin In gated time accumulation mode it is set at the end of the timed period D 2 14 CFORC Compare Force Register YFF924 PWMC PWM Control Register C YFF925 15 11 10 9 8 7 6 4 3 2 1 0 0 FPWMA FPWMB
16. FREEZE Output 1 HALT Input Output 0 IC 4 1 Input Output IPIPE Output IRQ 7 1 Input MISO Input Output M ODCLK Input MOSI OC b 1 Input Output Output PAI Input 6 0 Output P 3 0 Input Output PE 7 0 Input Output PF 7 0 PGP 7 0 Input Output Input Output PQS 7 0 Input Output PCLK Input PWMA PWMB Output QUOT Output Input Output Output Output Input Input Output Output Input Table 3 5 Signal Function Signal Name Mnemonic Function Address Bus ADDR 23 0 24 bit address bus Address Strobe AS Indicates that a valid address is on the address bus Autovector AVEC Requests an automatic vector during interrupt acknowledge Bus Error BERR Indicates that a bus error has occurred Bus Grant BG Indicates that the MCU has relinquished the bus Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus mastership Breakpoint BKPT Signals a hardware breakpoint to the CPU Bus Request BR Indicates that an external device requires bus mastership System Clockout CLKOUT System clock output Chip Selects CS 10 0 Select external devices at programmed addresses Boot Chip Select CSBOOT Chip select for external boot start up ROM Data Bus DATA 15 0 16 bit data bus MOTOROLA OVERVIEW MC68331 3 8 USER S
17. ICI TOI 0 PAOVI CPROUT CPR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMSK1 enables OC and IC interrupts TMSK2 controls pulse accumulator interrupts and TCNT functions 14 051 Input Capture 4 Output Compare 5 Interrupt Enable 0 IC4 OC5 interrupt disabled 1 1C4 OC5 interrupt requested when 14 flag in TFLG1 is set OCI 4 1 Output Compare Interrupt Enable 0 OC interrupt disabled 1 OC interrupt requested when OC flag set OCI 4 1 correspond to OC 4 1 ICI 3 1 Input Capture Interrupt Enable 0 IC interrupt disabled 1 IC interrupt requested when flag set ICI 3 1 correspond to IC 3 1 TOI Timer Overflow Interrupt Enable 0 Timer overflow interrupt disabled 1 Interrupt requested when TOF flag is set PAOVI Pulse Accumulator Overflow Interrupt Enable 0 Pulse accumulator overflow interrupt disabled 1 Interrupt requested when PAOVF flag is set PAII Pulse Accumulator Input Interrupt Enable 0 Pulse accumulator interrupt disabled 1 Interrupt requested when PAIF flag is set CPROUT Capture Compare Unit Clock Output Enable 0 Normal operation for OC1 pin 1 TONT clock driven out OC1 pin CPR 2 0 Timer Prescaler PCLK Select Field This field selects one of seven prescaler taps or PCLK to be TCNT input MC68331 REGISTER SUMMARY MOTOROLA USER S MANUAL D 9 0 2 13 TFLG1 TFLG2 Timer Interrupt Flag Registers 1 and 2 YFF922
18. 3 4 Internal Register Memory 3 5 Overall Memory 3 6 Separate Supervisor and User Space 3 7 Supervisor Space Separate Program Data Space Map 3 8 User Space Separate Program Data Space Map 4 1 System Integration Module Block Diagram 4 2 System Configuration and 4 3 Periodic Interrupt Timer and Software Watchdog Timer 4 4 System Clock Block Diagram 4 5 System Glock Oscillator 4 6 System Clock Filter Networks lt 4 7 MCU Basic System 4 8 Operand Byte Order 4 9 Word Read Cycle 4 10 Write Cycle Flowchart x ose e casei rt ba i xt perat 4 11 CPU Space Address Encoding 4 12 Breakpoint Operation 4 13 LPSTOP Interrupt Mask 4 14 Bus Arbitration Flowchart for Single Request 4 15 Data Bus Mode Select 4 16 Power On
19. J M 68M EV B1632 hy f MC68331 User s Manual Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or deat
20. The chip select block provides 12 chip select signals Each chip select signal has an associated base register and option register that contain the programmable character istics of that chip select Chip select pins can also be configured for use as general purpose output port C The system test block incorporates hardware necessary for testing the MCU It is used to perform factory tests and its use in normal applications is not supported MC68331 SYSTEM INTEGRATION MODULE MOTOROLA USER S MANUAL 4 1 SYSTEM CONFIGURATION AND PROTECTION CLKOUT CLOCK SYNTHESIZER EXTAL MODCLK CHIP SELECTS CHIP SELECTS EXTERNAL BUS EXTERNAL BUS INTERFACE lt gt RESET TSC FACTORY TEST FREEZE QUOT S C IM BLOCK Figure 4 1 System Integration Module Block Diagram 4 2 System Configuration and Protection The system configuration and protection functional block controls module configura tion preserves reset status monitors internal activity and provides periodic interrupt generation Figure 4 2 is a block diagram of the submodule MOTOROLA SYSTEM INTEGRATION MODULE MC68331 4 2 USER S MANUAL MODULE CONFIGURATION AND TEST RESET STATUS HALT MONITOR RESET REQUEST CLOCK RESET REQUEST 29 PRESCALER PERIODIC INTERRUPT TIMER IRQ 7 1 SYS PROTECT BLOCK Figure 4 2 System Configuration and Protection 4 2 1 Module Mapping Control registers for all the modules in the microcontroller are mapped into
21. to insure a particular configuration out of reset use an active device to put DATAO in a known state during reset The base address field in chip select base address register boot CSBARBT has a reset value of all zeros so that when the initial access to address 000000 is made an address match occurs and the CSBOOT signal is asserted The block size field in CSBARBT has a reset value of 1 Mbyte Table 4 24 shows CSBOOT reset values MOTOROLA SYSTEM INTEGRATION MODULE MC68331 4 56 USER S MANUAL Table 4 24 CSBOOT Base and Option Register Reset Values Fields Reset Values Base Address 000000 Block Size 1 Mbyte Async Sync Mode Asynchronous Mode Upper Lower Byte Both Bytes Read Write Read Write AS DS AS DSACK 13 Wait States Address Space Supervisor User Space IPL Any Level Autovector Interrupt Vector Externally 4 9 Parallel Input Output Ports Fifteen SIM pins can be configured for general purpose discrete input and output Al though these pins are organized into two ports port E and port F function assignment is by individual pin Pin assignment registers data direction registers and data regis ters are used to implement discrete I O 4 9 1 Pin Assignment Registers Bits in the port E and port F pin assignment registers PEPAR and PFPAR control the functions of the pins in each port Any bit set to one defines the corresponding pin as a bus control signal Any bit cleared to zero d
22. 3 Vpp Supply Current Ipp RUN 113 mA LPSTOP VCO off 125 LPSTOP External clock maxi fsys 3 75 Clock Synthesizer Operating Voltage 5 0 V 5 VppsvN Supply Current IDDSYN VCO on maximum fsys 1 0 mA External Clock maximum fs 5 0 mA LPSTOP VCO off 100 Vpp powered down 50 uA 6 Dissipation Pp 570 mW MOTOROLA ELECTRICAL CHARACTERISTICS MC68331 A 2 USER S MANUAL Table A 3 Thermal Characteristics Num Rating Symbol Value Unit 1 Thermal Resistance Ova C W Plastic 132 Pin Surface Mount 38 Plastic 144 Pin Surface Mount 46 Thin Plastic 144 Pin Surface Mount 49 NOTES The average chip junction temperature can be obtained from TA Pp x Oya 1 where Ambient Temperature Package Thermal Resistance Junction to Ambient C W Pp Pint Pro Pint Watts Chip Internal Power Power Dissipation on Input and Output Pins User Determined For most applications lt and can be neglected An approximate relationship between Pp and Ty if Pio is neglected is Pp K Ty 273 C 2 Solving equations 1 and 2 for K gives Pp Ta 273 C Oga x Pp 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by mea suring Pp at equilibrium for a known Using this value of the values of Pp and Ty can be ob tained by solving equations 1 and 2 it
23. Contains five 2 bit fields CSPA1 4 0 that determine the functions of corresponding chip select pins CSPAR1 15 10 are not used These bits always read zero write has no effect The CSPAR1 pin assignments table shows alternate functions that can be enabled by data bus mode selection during reset Table 0 10 CSPARO and CSPAR1 Pin Assignment Field Encoding Bit Field Description 00 Discrete Output 01 Alternate Function 10 Chip Select 8 Bit Port 11 Chip Select 16 Bit Port Does not apply to the CSBOOT field MOTOROLA D 22 REGISTER SUMMARY MC68331 USER S MANUAL 0 3 25 CSBARBT Chip Select Base Address Register Boot ROM YFFA48 CSBAR 0 10 Chip Select Base Address Registers YFFA4C YFFA74 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR BLKSZ 23 22 21 20 19 18 17 16 15 14 13 12 11 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Each chip select pin has an associated base address register A base address is the lowest address in the block of addresses enabled by a chip select CSBARBT contains the base address for selection of a bootstrap peripheral memory device Bit and field definition for CSBARBT and CSBAR 0 10 are the same but reset block sizes differ ADDR 23 11 Base Address This field sets the starting address of a particular address space BLKSZ Block
24. IRQ7 is transition sensitive as well as level sensitive level 7 interrupt is not detected unless a falling edge transition is detected on the IRQ line This prevents redundant servicing and stack overflow A nonmaskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask changes from 96111 to a lower number while IRQ7 is asserted Interrupt requests are sampled on consecutive falling edges of the system clock In terrupt request input circuitry has hysteresis to be valid a request signal must be as serted for at least two consecutive clock periods Valid requests do not cause immediate exception processing but are left pending Pending requests are pro cessed at instruction boundaries or when exception processing of higher priority ex ceptions is complete The 2 does not latch the priority of a pending interrupt request If an interrupt source of higher priority makes a service request while a lower priority request is pend ing the higher priority request is serviced If an interrupt request with a priority equal to or lower than the current IP mask value is made the CPU32 does not recognize the occurrence of the request If simultaneous interrupt requests of different priorities are made and both have a priority greater than the mask value the CPU32 recognizes the higher level request 4 7 3 Interrupt Acknowledge and Arbitration When the CPU32 detects one or more interrupt re
25. bit of destination BGND none none If background mode enabled then enter background mode else format vector offset SSP gt SSP SR gt SSP vector BKPT lt data gt none If breakpoint cycle acknowledged then execute returned operation word else trap as illegal instruction BRA lt label gt 8 16 32 PC d PC BSET Dn lt ea gt 8 32 bit number gt of destination Z lt data gt lt ea gt 8 32 1 bit of destination BSR lt label gt 8 16 32 SP 4 gt SP PC d BTST Dn ea 8 32 bit number of destination gt Z lt data gt ea 8 32 CHK ea Dn 16 32 If Dn 0 or Dn lt ea then CHK exception CHK2 ea Hn 8 16 32 If Rn lower bound or Rn upper bound then CHK exception CLR ea 8 16 32 0 Destination CMP ea Dn 8 16 32 Destination Source CCR shows results CMPA ea An 16 32 Destination Source CCR shows results CMPI lt data gt ea 8 16 32 Destination Data CCR shows results CMPM An 8 16 32 Destination Source CCR shows results CMP2 lt ea gt Rn 8 16 32 Lower bound Rn Upper bound CCR shows result DBcc Dn lt label gt 16 If condition false then Dn 1 PC if Dn z 1 then PC d DIVS DIVU ea Dn 32 16 16 16 Destination Source Destination signed or unsigned MC68331 CENTRAL PROCESSING UNIT MOTOROLA 5 11 Table 5 1 Instruction Set Summary
26. B10 FREEZE Asserted to IFETCH Valid tERZIF TBD Notes 1 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted MOTOROLA A 20 ELECTRICAL CHARACTERISTICS MC68331 USER S MANUAL FREEZE BKPT DSCLK lt IFETCH DSI X X gt lt 68300 BKGD DBM SER COM TIM Figure A 13 Background Debugging Mode Timing Diagram Serial Communication B6 FREEZE IFETCH DSI 68300 BKGD DBM FRZ TIM Figure A 14 Background Debugging Mode Timing Diagram Freeze Assertion MC68331 ELECTRICAL CHARACTERISTICS MOTOROLA USER S MANUAL A 21 Table A 8 16 78 MHz ECLK Bus Timing Vpp 5 0 10 Vss 0 T to Ty Characteristic Symbol Min Max Unit E1 ECLK Low to Address Valid tEAD 60 ns E2 Low to Address Hold 15 ns ECLK Low to CS Valid CS delay tecsp 150 E4 Low to CS Hold 15 ns E5 CS Negated Width tecsn 30 Read Data Setup Time tEDSR 30 ns E7 Read Data Hold Time tEDHR 5 E ns E8 Low to Data High Impedance tepHz 60 ns E9 CS Negated to Data Hold Read tECDH 0 ns E10 CS Negated to Data High Impedance tecpz 1 E11 ECLK Low to Data Valid Write teppw 2 E12 ECLK Low to Data Hold Write tepHw 15 ns E13 Address Access Time Re
27. Idle Bus Case 0 41 42 43 0 1 52 A0 A23 DS un D0 D15 START OF gt SHOW CYCLE 9 EXTERNAL CYCLE 68300 SHW CYC TIM NOTE Show cycles can stretch during S42 when bus accesses take longer than two cycles due to wait state insertion by IMB modules Figure A 10 Show Cycle Timing Diagram MOTOROLA ELECTRICAL CHARACTERISTICS MC68331 A 18 USER S MANUAL 0 51 52 53 54 55 50 51 52 3 54 5 5 00 015 68300 CHIP SEL TIM NOTE AS and DS timing shown for reference only Figure A 11 Chip Select Timing Diagram 00 015 68300 RST MODE SEL TIM Figure A 12 Reset and Mode Select Timing Diagram MC68331 ELECTRICAL CHARACTERISTICS MOTOROLA USER S MANUAL A 19 Table 7 Background Debugging Mode Timing Vpp 5 0 10 Vgs 0 Ta T to Ty Num Characteristic Symbol Min Max Unit BO DSI Input Setup Time tpsisU 15 ns B1 Input Hold Time 10 ns B2 DSCLK Setup Time tpscsu 15 ns B3 DSCLK Hold Time tpscH 10 ns B4 DSO Delay Time tpsop 25 ns B5 DSCLK Cycle Time tpsccvc 2 B6 CLKOUT High to FREEZE Asserted Negated tFRZAN 50 ns B7 CLKOUT High to IFETCH High Impedance 50 8 CLKOUT High to IFETCH Valid tir 50 ns 9 DSCLK Low Time tpscLo 1
28. SCI transmitter is busy 1 SCI transmitter is idle RDRF Receive Data Register Full 0 Register RDR is empty or contains previously read data 1 Register contains new data RAF Receiver Active 0 SCI receiver is idle 1 SCI receiver is busy IDLE Idle Line Detected 0 SCI receiver did not detect an idle line condition 1 SCI receiver detected an idle line condition OR Overrun Error 0 is cleared before new data arrives 1 RDRF is not cleared before new data arrives NF Noise Error Flag 0 No noise detected on the received data 1 Noise occurred on the received data MC68331 REGISTER SUMMARY MOTOROLA USER S MANUAL D 29 FE Framing Error 0 No framing error on the received data 1 Framing error or break occurred on the received data PF Parity Error 0 No parity error on the received data 1 Parity error occurred on the received data 0 4 7 SCDR SCI Data Register YFFCOE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R8 T8 R7 T7 R6 T6 5 5 R2 T2 RO TO RESET 0 0 0 0 0 0 0 U U U U U U U U U SCDR consists of two data registers located at the same address RDR is a read only register that contains data received by the SCI serial interface Data comes into the receive serial shifter and is transferred to RDR TDR is a write only register that con tains d
29. SUPERVISOR SPACE YFFOO0 YFF900 57 000 YFF93F 7 0004 00 INTERNAL REGISTERS INTERNAL REGISTERS SIM RESERVED AE YFFCOO QSM YFFDFF 5000 YFFFFF 00004 FFFFFF x SFFFFFF NOTES 1 Location of the exception vector table is determined by the vector base register The vector address is the sum of the vector base register and the vector offset 2 Location of the module control registers is determined by the state of the module mapping MM bit in the SIM configuration register Y M111 where M is the state of the MM bit 3 Unused addresses within the internal register block are mapped externally RESERVED blocks are not mapped externally 4 Some internal registers are not available in user space 331 S U SEP MAP Figure 3 6 Separate Supervisor and User Space Map MC68331 OVERVIEW MOTOROLA USER S MANUAL 3 13 VECTOR VECTOR EXCEPTION VECTORS LOCATED OFFSET NUMBER IN SUPERVISOR PROGRAM SPACE 0000 0 RESET INITIAL STACK POINTER XX0000 0004 1 RESET INITIAL PC XX0004 000000 000000 VECTOR VECTOR EXCEPTION VECTORS LOCATED OFFSET NUMBER IN SUPERVISOR DATA SPACE INITIAL STACK POINTER XX0000 RESET INITIAL PC BUS ERROR ADDRESS ERROR LLEGAL INSTRUCTION ZERO DIVISION CHK CHK2 INSTRUCTIONS INSTRUCTIONS PRIVILEG
30. VDD MOTOROLA 3 4 MC68331 VDD BGACK CS2 BG CS1 BR CSO CSBOOT DATAO DATA1 DATA2 DATAS VDD VSS DATA4 DATA5 DATA6 DATA7 VSS DATA8 DATA9 DATA10 DATA11 VDD VSS DATA12 DATA13 DATA14 DATA15 ADDRO PEO DSACKO PE1 DSACK1 PE2 AVEC PE3 RMC 5 05 VDD VSS mE CD polit 29295595 5 ERPASOFSFEMOES XS gt m 2 gt x LL TL gn oO x ere o dcc S ud N 2 a o W S u NS m a Figure 3 2 Pin Assignments for 132 Pin Package OVERVIEW RW PE7 SIZ1 PEA AS VSS PE6 SIZO 331 132
31. Vpp 0 2 V 710 0 Group 1 2 4 input output and all output pins 7 CMOS Output Low Voltage VoL 0 2 V lo 10 0 uA Group 1 2 4 input output and all output pins 8 Output High Voltage 3 VoH Vpp 0 8 V 0 8 mA Group 1 2 4 input output and all output pins 9 Output Low Voltage VoL V lo 1 6 mA Group 1 Pins CLKOUT FREEZE QUOT IPIPE 0 4 lol 5 3 mA Group 2 and Group 4 I O Pins CSBOOT BG CS 0 4 lg 12 mA Group 3 0 4 10 State Control Input High Voltage 1 6 9 1 V 11 Data Bus Mode Select Pull up Current Vin Vi DATA 15 0 120 Vin Vin DATA 15 0 15 12 Vpp Supply Current RUN 4 140 mA LPSTOP 32 768 kHz crystal Off STSIM 0 Sipp 350 LPSTOP External clock input frequency maximum Sipp 5 mA 13 Synthesizer Operating Voltage VppsvN 4 75 5 25 V 14 Supply Current 32 768 kHz crystal VCO on maximum fsys IDDSYN 2 mA External Clock maximum fsys IDDSYN 6 mA LPSTOP 32 768 kHz crystal VCO off STSIM 0 SIDDSYN 150 32 768 kHz crystal powered down IDDSYN 100 15 Dissipation Pp 766 mW 16 Capacitance 8 All input only pins Cin 10 pF All input output pins m 20 17 Load Capacitance Group 1 Pins and CLKOUT FREEZE QUOT IPIPE CL 90 pF Group 2 I O Pins and CSBOOT BG CS 100 Group 3 pins 130 G
32. propriate low order byte or word in byte or word operations respectively is used or changed the remaining high order portion is unaffected The least significant bit LSB of a long word integer is addressed as bit zero and the most significant bit MSB is addressed as bit 31 Figure 5 4 shows the o