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MOTOROLA MC68331 user manual

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1. NC VSS FCO CS3 FC1 CS4 FC2 CS5 ADDR19 CS6 ADDR20 CS7 ADDR21 CS8 ADDR22 CS9 ADDR23 CS10 3P7 ICA4 OC5 OC1 PGP6 OC4 VDD VSS NC 5 1 PGP4 OC2 OC1 PGP3 OC1 PGP2 IC3 PGP1 IC2 PGPO IC1 NC VSS NC MC68331 NC VSS PE4 AS PE6 SIZO PE7 SIZ1 R W PFO MODCLK PF1 IRQ1 PF2 IRQ2 PF3 IRQ3 PF4 IRQ4 PF5 IRQ5 PF6 IRQ6 PF7 IRQ7 BERR FREEZE QUOT TSC BKPT DSCLK IFETCH DSI Figure 3 3 Pin Assignments for 144 Pin Package 3 3 Pin Descriptions ADDR18 PQSO MISO PQS1 MOSI PQS2 SCK 53 50 55 PQS4 PCS1 PQS5 PCS2 PQS6 PCS3 VDD IPIPE DSO RXD P
2. USER S MANUAL Instruction Syntax Operand Size Operation ABCD Dn Dn 8 1 Destinationj9 X Destination An An 8 ADD Dn lt ea gt 8 16 32 Source Destination Destination lt ea gt Dn 8 16 32 ADDA lt ea gt An 16 32 Source Destination Destination ADDI lt data gt lt ea gt 8 16 32 Immediate data Destination Destination ADDQ lt data gt lt ea gt 8 16 32 Immediate data Destination Destination ADDX Dn 8 16 32 Source Destination X Destination An An 8 16 32 AND lt ea gt Dn 8 16 32 Source Destination Destination Dn lt ea gt 8 16 32 ANDI lt data gt lt ea gt 8 16 32 Data Destination Destination ANDI to CCR lt data gt CCR 8 Source CCR ANDI to SR1 lt data gt SR 16 Source SR SR ASL Dn Dn 8 16 32 lt data gt Dn 8 16 32 lt ea gt 16 ASR Dn Dn 8 16 32 lt data gt Dn 8 16 32 lt ea gt 16 Bcc label 8 16 32 If condition true then PC d PC BCHG Dn ea 8 32 bit number of destination Z lt data gt ea 8 32 bit of destination BCLR Dn ea 8 32 bit number of destination Z lt data gt ea 8 32 0 bit of destination BGND none none If background mode enabled then enter background mode else format vector offset SSP gt SSP SR gt SSP vector BKPT lt data gt n
3. MODE BYTE R W STRB DSACK SPACE IPL AVEC 0 ASYNC 00 Disable 00 Rsvd 0 5 0000 0 WAIT 00 CPU SP 000 All 0 Off 1 SYNC 01 Lower 01 Read 1 05 0001 1 WAIT 01 User SP 001 Priority 1 1 On 10 102 Write 0010 2 WAIT 10 Supv 5 010 Priority 2 11 Both 11 Both 0011 3 WAIT 11 S U SP 011 Priority 0100 4 WAIT 100 Priority 4 0101 2 5 WAIT 101 Priority 5 0110 2 6 WAIT 110 Priority 6 0111 2 7 WAIT 111 Priority 7 1000 8 WAIT 1001 2 9 WAIT 1010 2 10 WAIT 1011 2 11 WAIT 1100 2 12 WAIT 1101 2 13 WAIT 1110 F term 1111 External MOTOROLA REGISTER SUMMARY MC68331 D 24 USER S MANUAL D 4 Queued Serial Module Table D 13 displays the QSM address map The column labeled Access indicates the privilege level at which the CPU must be operating to access the register A des ignation of S indicates that supervisor access is required a designation of S U in dicates that the register can be programmed to the desired privilege level Table D 13 QSM Address Map Access Address 15 87 0 5 YFFCOO QSM MODULE CONFIGURATION QSMCR S 2 QSM TEST 5 S YFFCO4 QSM INTERRUPT LEVEL QILR QSM INTERRUPT VECTOR QIVR S U YFFCO6 NOT USED S U YFFCO8 SCI CONTROL 0 SCCRO S U YFFCOA SCI CONTROL 1 SCCR1 S U YFFCOC SCI STATUS
4. GPT Access Address 15 817 0 5 FFF900 GPT MODULE CONFIGURATION GPTMCR S FFF902 RESERVED FOR TEST S FFF904 INTERRUPT CONFIGURATION ICR S U FFF906 PGP DATA DIRECTION DDRGP PGP DATA PORTGP S U FFF908 OC1 ACTION MASK 1 OC1 ACTION DATA OC1D S U FFF90A TIMER COUNTER TCNT S U FFF90C PA CONTROL PACTL PA COUNTER S U FFF90E INPUT CAPTURE 1 TIC1 S U FFF910 INPUT CAPTURE 2 TIC2 S U FFF912 INPUT CAPTURE 3 S U FFF914 OUTPUT COMPARE 1 TOC1 S U FFF916 OUTPUT COMPARE 2 TOC2 S U FFF918 OUTPUT COMPARE 3 TOC3 S U FFF91A OUTPUT COMPARE 4 4 S U FFF91C INPUT CAPTURE 4 OUTPUT COMPARE 5 TI4 O5 S U FFF91E TIMER CONTROL 1 TCTL1 TIMER CONTROL 2 TCTL2 S U FFF920 TIMER MASK 1 TMSK1 TIMER MASK 2 TMSK2 S U FFF922 TIMER FLAG 1 TFLG1 TIMER FLAG 2 TFLG2 S U FFF924 FORCE COMPARE CFORC PWM CONTROL C PWMC S U FFF926 PWM CONTROL A PWMA PWM CONTROL B PWMB S U FFF928 PWM COUNT PWMCNT S U FFF92A PWMA BUFFER PWMBUFA PWMB BUFFER PWMBUFB S U FFF92C GPT PRESCALER PRESCL FFF92E NOT USED Access Address 15 87 0 5 MODULE CONFIGURATION SIMCR S FFFA02 FACTORY TEST SIMTR 5 FFFA04 CLOCK SYNTHESIZER CONTROL SYNCR 5 6 NOT USED RESET STATUS RSR S FFFAO08 MODULE TEST E SIMTRE S FFFAOA NOT USED NOT USED S FFFAOC NOT USED NOT USED S FFFAOE NO
5. CSPAQ 3 52 5 2 CST BG CSPAQ 1 50 CSBOOT CSBOOT E Contains seven 2 bit fields CSPAO 6 1 and CSBOOT that determine the functions of corresponding chip select pins CSPARO 15 14 not used These bits always read zero write has no effect CSPARO bit 1 always reads one writes to CSPARO bit 1 have no effect The alternate functions can be enabled by data bus mode selection during reset D 3 24 CSPAR1 Chip Select Pin Assignment Register 1 YFFA46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ololololo CSPA1 4 CSPA1 8 CSPA1 2 CSPA1 1 CSPA1 0 RESET 0 0 0 0 0 0 DATA7 1 DATA6 1 DATAS 1 DATA4 1 DATA3 1 Table 0 9 CSPAR1 Pin Assignments 1 Field CSPAR1 Signal Alternate Signal Discrete Output CSPA1 4 510 ADDR23 ECLK CSPA1 3 CS9 ADDR22 PC6 CSPA1 2 58 ADDR 1 PC5 CSPA1 1 CS7 ADDR20 PC4 CSPA1 0 CS6 ADDR19 PC3 Contains five 2 bit fields CSPA1 4 0 that determine the functions of corresponding chip select pins CSPAR1 15 10 are not used These bits always read zero write has no effect The CSPAR1 pin assignments table shows alternate functions that can be enabled by data bus mode selection during reset Table 0 10 CSPARO and CSPAR1 Pin Assignment Field Encoding Bit Field Description 00 Discrete Output 01 Alternate Function 10 Chip Select 8 Bit Por
6. 4 3 Periodic Interrupt Timer and Software Watchdog Timer 4 4 System Clock Block Diagram 4 5 System Glock Oscillator soeeccscansace 4 6 System Clock Filter Networks lt 4 7 MCU Basic System 4 8 Operand Byte 4 9 Word Read Cycle 4 10 Write Cycle Flowchart x ose e casei rt ba i xt perat 4 11 CPU Space Address Encoding 4 12 Breakpoint Operation 4 13 LPSTOP Interrupt Mask 4 14 Bus Arbitration Flowchart for Single Request 4 15 Data Bus Mode Select 4 16 Power On 2 111 4 17 MOL cyte reor eti 4 18 Chip Select Circuit Block Diagram 4 19 CPU Space Encoding for Interrupt Acknowledge 5 1 CPUS2 Block E 5 2 User Programming Model 5 3 Supervisor Programming Model Supplement
7. NC 107 Vss 106 PE4 AS 105 PE6 SIZO PE7 SIZ1 PFO MODCLK PF1 IRQ1 PF2 IRQ2 PF4 IRO4 PF5 IRQ5 PF6 IRQ6 PF7 IRQ7 BERR FREEZE QUOT TSC BKPT DSCLK IFETCH DSI IPIPE DSO RXD PQS7 TXD Vss NC ADDR18 PQSO MISO PQS1 MOSI PQS2 SCK PQS3 PCSO SS PQS4 PCS1 PQSS PCS2 PQS6 PCS3 331 144 PIN QFP Figure B 2 144 Pin Plastic Surface Mount Package Pin Assignments MC68331 USER S MANUAL MECHANICAL DATA AND ORDERING INFORMATION MOTOROLA B 3 Table B 1 MCU Ordering Information Package Type 132 Pin PQFP 144 QFP 144 TQFP Temperature Frequency Package Order Number MHz Order Quantity 40 to 85 C 16 MHz 2 pc tray SPAKMC331CFC16 36 pc tray MC68331CFC16 20 MHz 2 pc tray SPAKMC331CFC20 36 pc tray MC68331CFC20 40 to 105 C 16 MHz 2 pc tray SPAKMC331VFC16 36 pc tray MC68331VFC16 20 MHz 2 pc tray SPAKMC331
8. 6 1 6 2 QSM Registers and Address 6 2 6 2 1 QSM Global Registers 0 6 2 6 2 1 1 Low Power Stop Operation 2 6 2 MOTOROLA MC68331 USER S MANUAL TABLE OF 5 Continued Paragraph Title Page 6 2 1 2 Freeze A aake 6 3 6 2 1 3 OSM IDIemupls Joi oic eer PEE EG E eed n dt 6 3 6 2 2 QSM Pin Control Registers 44 2112 6 4 6 3 Queued Serial Peripheral Interface 6 5 6 3 1 COS TFIGUISIGIS a 6 6 6 3 1 1 Control Registers p 6 7 6 3 1 2 Status Register s oer baton price ero ei pr gr e IU C eee 6 7 6 3 2 6 7 6 3 2 1 Receive RAM 6 8 6 3 2 2 Transmit RAM oe eb ee Erde tas Sh aad 6 8 6 3 2 3 oa aiu sa aa a 6 8 6 3 3 od ooh quas br aas REMO 6 8 6 3 4 OSPIMOPGRAUON E E nda Eon eR APPS 6 9 6 3 5 QSPI Operating Modes te n tede na adis 6 10 6 3 5 1 M ster Mode EN 6 17 6 3 5 2 Master Wraparound Mode seen 6 19 6 3 5 3 Slave Mode 5 E 6 20
9. D 30 D 4 9 PQSPAR PORT QS Pin Assignment Register D 30 D 4 10 SPCRO QSPI Control Register 0 D 32 D 4 11 SPCR1 QSPI Control Register 1 D 33 D 4 12 SPCR2 QSPI Control Register 2 D 34 D 4 13 SPCR3 QSPI Control Register D 34 D 4 14 RR 0 F Receive Data 44211 D 35 D 4 15 TR O F Transmit Data 22 1 D 35 D 4 16 CR O F Command RAM tenete adus D 36 MOTOROLA MC68331 X USER S MANUAL LIST OF ILLUSTRATIONS Figure Title 3 1 MGU BlackDIagt altis ear cor e t e b oa rest 3 2 Pin Assignments for 132 Pin 3 3 Pin Assignments for 144 Pin 3 4 Internal Register Memory 3 5 Overall Memory 00 004400 3 6 Separate Supervisor and User Space 3 7 Supervisor Space Separate Program Data Space Map 3 8 User Space Separate Program Data Space Map 4 1 System Integration Module Block Diagram 4 2 System Configuration and
10. RSR contains a status bit for each reset source in the MCU RSR is updated when the MCU comes out of reset A set bit indicates what type of reset occurred If multiple sources assert reset signals at the same time more than one bit in RSR may be set This register can be read at any time a write has no effect EXT External Reset Reset caused by an external signal POW Power Up Reset Reset caused by the power up reset circuit SW Software Watchdog Reset Reset caused by the software watchdog circuit HLT Halt Monitor Reset Reset caused by the halt monitor MOTOROLA REGISTER SUMMARY MC68331 D 16 USER S MANUAL LOC Loss of Clock Reset Reset caused by loss of clock frequency reference SYS System Reset Reset caused by a RESET instruction TST Test Submodule Reset Reset caused by the test submodule Used during system test only D 3 5 SIMTRE System Integration Test Register ECLK 08 Register is used for factory test only 0 3 6 PORTEO PORTE1 Port E Data Register YFFA11 YFFA13 15 8 7 6 5 4 3 2 1 0 NOT USED PE7 PE6 5 4 2 0 RESET U U U U U U U U PORTE is an internal data latch that can be accessed at two locations PORTE can be read or written at any time If a pin in I O port E is configured as an output the corre sponding bit value is driven out on the pin When a pin is configured fo
11. 3 7 Module Pin Functions 244 4 1 Show Cycle Enable BIS nn oki t eoe ies 4 2 Bus Monitor 4 3 MODCLK Pin SWP Bit During Reset 4 4 Software Watchdog Ratio 4 5 MODCLK Pin and Bit at Reset 4 6 Periodic 4 7 Clock Control Multipliers 2 00 2 4 8 System Frequencies from 32 768 kHz Reference 4 9 Clock Control M 4 10 Size Signal Encoding 4 11 Address Space Encoding ecd o bei ere contes 4 12 Effect of DSACK Signals 22 22 4 13 Transfer Cases 4 14 DSACK BERR and HALT Assertion Results 4 15 Reset Source Summary eese 4 16 Reset Mode Selection 2 24222 1 4 17 Module Pin 4 18 SIM Pin Reset States iieri oen qr need nenas 4 19 Chip Select Pin Functions 040 4 20 Assignment Field Encoding 4 21 Block Size Encoding 4 22 Option Register Function Summary 4 23 Chip S
12. MC68331 VDD BGACK CS2 BG CS1 BR CSO CSBOOT DATAO DATA1 DATA2 DATAS VDD VSS DATA4 DATA5 DATA6 DATA7 VSS DATA8 DATA9 DATA10 DATA11 VDD VSS DATA12 DATA13 DATA14 DATA15 ADDRO PEO DSACKO PE1 DSACK1 PE2 AVEC PE3 RMC 5 05 VDD 55 mE OF FIR xt 29295595 5 XS OS MSU E E E T TE E Q N m 2 gt x LL TL gn oO eu x oc n c W o dcc S ud N 2 a o W S u mm w m a Figure 3 2 Pin Assignments for 132 Package OVERVIEW RW PE7 SIZ1 PEA AS VSS PE6 SIZO 331 132 PIN QFP MC68331 USER S MANUAL 5 gt 9200 Az QQ AS S E gt PEO DSACKO PE1 DSACK1 PE2 AVEC PE3 RMC PE5 DS VDD
13. 3 7 2 MCU Module Pin Function During Reset SECTION 4 SYSTEM INTEGRATION MODULE 4 1 Genel alc a siu e UNE UEM E 4 2 System Configuration and Protection 4 2 1 Module edo 4 2 2 Interrupt Arbitration neenon sono tae or bebe 4 2 3 Show Internal Cycles 4 2 4 Faclory Test Mode 4 2 5 Register ACCOSS ene eur ESO 4 2 6 Reset Salis iei E e e lad Un ue iE 4 2 7 Bis Momtor etia duo bono pcd ui 4 2 8 dee A T 4 2 9 Spurious Interrupt Monitor 4 2 10 Software Watchdog MC68331 USER S MANUAL Page MOTOROLA iii TABLE 5 Continued Paragraph Title Page 4 2 11 Periodic Interrupt TITIO ooa oe ar o E p o E rot 4 7 4 2 12 Low Power STOP Operation E Eee 4 8 4 2 13 Freeze Operation m 4 9 4 3 DV SIGINT E oou E E E e E 4 9 4 3 1 Clock SOUICOS re LL LL a 4 10 4 3 2 Clock Synthesizer S rv 4 10 4 3 3 External Bus Clock 4 e ieee ae Ds M 4 15 4 3 4 bow Power ODOFallOH diode eic re 4 15 4 3 5 Loss of Referenc
14. 6 16 6 7 SCI Transmitter Block BIagEalTis rv in c bee tete 6 23 6 8 SCI Receiver Block 2 6 24 7 1 GPT Block Dia aims nee citate redeo ea cde 7 2 7 2 Prescaler Block Diagram om pov ecu maid 7 9 7 3 Capture Compare Unit Block 7 10 7 4 Input Capture Timing Example pennas 7 12 7 5 Pulse Accumulator Block 7 15 7 6 PWM Block Diagram es ied aa A Andr 7 16 A 1 CLKOUT Output Timing A 12 A 2 External Clock Input Timing A 12 A 3 Output Timing Diagram ocio cero e Pene A 12 4 13 5 Write Gycle Timirig DIagf arms acie EE bt e ED A 14 A 6 Fast Termination Read Cycle Timing Diagram A 15 A 7 Fast Termination Write Cycle Timing A 16 A 8 Bus Arbitration Timing Diagram Active Bus Case A 17 A 9 Bus Arbitration Timing Diagram Idle Bus Case A 18 A 10 Show Cycle Timing Diagram uice ice
15. YFF900 GPT 57 000 INTERNAL REGISTERS SIM SYFFATF RESERVED DEAE YFFC00 3 05 YFFDFF FF0000 INTERNAL REGISTERS FFFFFF YFFFFF FFFFFF NOTES 1 Location of the module control registers is determined by the state of the module mapping MM bit in the SIM configuration register Y M111 where M is the state of the MM bit 2 Unused addresses within the internal register block are mapped externally RESERVED blocks are not mapped externally 3 Some internal registers are not available in user space 331 USER P D MAP Figure 3 8 User Space Separate Program Data Space Map MC68331 OVERVIEW MOTOROLA USER S MANUAL 3 15 3 7 System Reset The following information is a concise reference only System reset is a complex op eration To understand operation during and after reset refer to SECTION 4 SYSTEM INTEGRATION MODULE paragraph 4 6 Reset for a more complete discussion of the reset function 3 7 1 SIM Reset Mode Selection The logic states of certain data bus pins during reset determine SIM operating config uration In addition the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines what happens during subsequent breakpoint as sertions Table 3 6 is a summary of reset mode selection options Table 3 6 SIM Reset Mode Selection Mode Sel
16. MC68331 ELECTRICAL CHARACTERISTICS MOTOROLA USER S MANUAL A 9 Table A 6a 20 97 MHz Timing Continued Vpp and VppsvN 5 0 5 Vas 0 Vac TA TL to Num Characteristic Symbol Min Max Unit 14 JAS CS Width Asserted tswa 80 ns 14A 5 CS Width Asserted Write tswaw 36 ns 14B 5 CS Width Asserted Fast Write Cycle tswDW 32 ns 15 TAS DS CS Width Negated tsn 32 ns 16 Clock High to AS DS R W High Impedance 47 ns 17 AS DS CS Negated to R W Negated tSNRN 10 ns 18 Clock High to R W High tcHRH 0 23 ns 20 Clock High to R W Low tcHRL 0 23 ns 21 R W Asserted to AS CS Asserted tRAAA 10 ns 22 R W Low to DS CS Asserted Write 54 ns 23 High to Data Out Valid tcHDo 23 ns 24 Data Out Valid to Negating Edge of AS CS 10 ns 25 5 CS Negated to Data Out Invalid Data Out Hold teNDOI 10 ns 26 Out Valid to DS CS Asserted Write tovsa 10 ns 27 Dataln Valid to Clock Low Data Setup tpicL 5 ns 27A Late BERR HALT Asserted to Clock Low Setup Time tBELCL 15 ns 28 AS DS Negated to DSACK 1 0 BERR HALT AVEC Negated tswpN 0 60 ns 29 DS CS Negated to Data In Invalid Data In Hold tsNDI 0 ns 29A DS CS Negated to Data In High Impedance
17. 15 14 13 12 1 8 7 6 5 4 3 0 SPIFIE WREN WRTO 0 ENDQP 0 0 0 0 NEWQP RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCR2 contains QSPI queue pointers wraparound mode control bits and an interrupt enable bit The CPUS2 has read write access to SPCR2 but the QSM has read ac cess only SPCR2 is buffered New SPCR2 values become effective only after com pletion of the current serial transfer Rewriting NEWQP in SPCR2 causes execution to restart at the designated location SPCR2 reads return the value of the register not the buffer SPIFIE SPI Finished Interrupt Enable 0 QSPI interrupts disabled 1 QSPI interrupts enabled WREN Wrap Enable 0 Wraparound mode disabled 1 Wraparound mode enabled WRTO Wrap To 0 Wrap to pointer address 0 1 Wrap to address in NEWQP ENDQP Ending Queue Pointer This field contains the last QSPI queue address NEWQP New Queue Pointer Value This field contains the first QSPI queue address 0 4 13 SPCR3 QSPI Control Register 3 YFFC1E SPSR QSPI Status Register YFFC1F 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 LOOPQ HALT SPIF MODF HALTA 0 CPTQP RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCRS contains the loop mode enable bit halt and mode fault interrupt enables and the halt control bit The CPU has read write access to SPCR3 but the QSM has read access only SPCR3 must be initialized before QSPI opera
18. 5 4 Data Organization in Data 5 5 Address Organization in Address Registers 5 6 Memory Operand Addressing 5 7 Common In Circuit Emulator Diagram 5 8 Bus State Analyzer Configuration 5 9 Debug Serial I O Block Diagram 5 10 BDM Serial Data iu er 5 11 BDM Connector siad 5 12 Loop Mode Instruction 6 1 QSM Block Diagram sse 6 2 OSP Block Diagram MC68331 USER S MANUAL MOTOROLA xi LIST OF ILLUSTRATIONS Continued Figure Title Page 6 3 S d dimid tap ante bp Doe edet obs bad 6 7 6 4 Flowchart of QSPI Initialization 6 11 6 5 Flowchart of QSPI Master Operation Part 1 6 12 6 5 Flowchart of QSPI Master Operation Part 2 6 13 6 5 Flowchart of QSPI Master Operation Part 3 6 14 6 6 Flowchart of QSPI Slave Operation 1 6 15 6 6 Flowchart of QSPI Slave Operation Part 2
19. Test Module Repetition D 21 D 3 20 CREG Test Submodule Control Register D 21 D 3 21 DREG Distributed D 21 MC68331 MOTOROLA USER S MANUAL ix TABLE OF 5 Continued Paragraph Title Page D 3 22 PORTC Port C Data D 21 D 3 23 CSPARO Chip Select Pin Assignment Register O D 21 D 3 24 CSPAR1 Chip Select Pin Assignment Register 1 D 22 D 3 25 CSBARBT Chip Select Base Address Register Boot ROM D 23 D 3 26 CSORBT Chip Select Option Register Boot ROM D 23 D 4 Oueued Serial MOOUle cit oto bt TEC D 25 D 4 1 QSMCR QSM Configuration Register D 25 D 4 2 QTEST QSM Test Register ieri retenta D 26 D 4 3 QSM Interrupt Level D 26 D 4 4 SCCRO SCI Control Register 0 D 27 D 4 5 SCCR1 SCI Control Register 1 D 27 D 4 6 SCSR Status Register 2 2 D 29 D 4 7 SCDR SCI Data roe pido D 30 D 4 8 PORTQS Port QS Data Register
20. D 22 D 9 D 22 D 10 CSPARO and CSPAR1 Pin Assignment Field Encoding D 22 D 11 Block Size Encoding 444044544 D 23 D 12 Option Register Function Summary D 24 9 12 QSM Address MaD a E o ERR re eor US re D 25 D 14 PQSPAR Pin Assignments o ceo err ERE erro SE pube D 31 D 15 Effect of DDROS on PORTOS Pins s iiio oe eph EU REPRE D 31 D 16 Effect of DDRQS on QSM Pin Function D 32 D 17 68331 Module Address Map D 37 D 18 Register Bit and Field Mnemonics D 40 MOTOROLA MC68331 xiv USER S MANUAL SECTION 1INTRODUCTION The 68331 a highly integrated 32 bit microcontroller combines high performance data manipulation capabilities with powerful peripheral subsystems The MCU is built up from standard modules that interface through a common intermodule bus IMB Standardization facilitates rapid development of devices tailored for specific applica tions The MCU incorporates a 32 bit CPU CPU32 a system integration module SIM general purpose timer GPT and a queued serial module QSM The MCU can either synthesize an internal clock signal from an external reference or use an external clock input directly Operation with a 32
21. MEMORY ADDR 23 0 1 Can be decoded to provide additional address space 2 Vari ndin n peripheral memory size aries depending upon perip y 32 EXAMPLE SYS BLOCK Figure 4 17 Basic MCU System Chip select assertion can be synchronized with bus control signals to provide output enable read write strobe or interrupt acknowledge signals Chip select logic can also generate DSACK and AVEC signals internally Each signal can also be synchronized with the ECLK signal available on ADDR23 When a memory access occurs chip select logic compares address space type ad dress type of access transfer size and interrupt priority in the case of interrupt ac knowledge to parameters stored in chip select registers If all parameters match the appropriate chip select signal is asserted Select signals are active low If a chip select function is given the same address as a microcontroller module or an internal memory array an access to that address goes to the module or array and the chip select sig nal is not asserted The external address and data buses do not reflect the internal ac cess All chip select circuits are configured for operation out of reset However all chip se lect signals except CSBOOT are disabled and cannot be asserted until the BYTE field in the corresponding option register is programmed to a nonzero value selecting a MC68331 SYSTEM INTEGRATION MODULE MOTOROLA USER S MANUAL 4 49 4 transfer
22. is zero this flag is set each time TCNT matches the TOC5 val ue in TI4 O5 When 14 O5 in PACTL is one the flag is set each time a selected edge is detected at the 14 O5 pin OCF 4 1 Output Compare Flags An output compare flag is set each time TCNT matches the corresponding TOC reg ister OCF 4 1 correspond to OC 4 1 ICF 3 1 Input Capture Flags A flag is set each time a selected edge is detected at the corresponding input capture pin ICF 3 1 correspond to IC 3 1 TOF Timer Overflow Flag This flag is set each time TCNT advances from a value of FFFF to 0000 PAOVF Pulse Accumulator Overflow Flag This flag is set each time the pulse accumulator counter advances from a value of FF to 00 PAIF Pulse Accumulator Flag In event counting mode this flag is set when an active edge is detected on the PAI pin In gated time accumulation mode it is set at the end of the timed period D 2 14 CFORC Compare Force Register YFF924 PWMC PWM Control Register C YFF925 15 11 10 9 8 7 6 4 3 2 1 0 FOC 0 FPWMA FPWMB PPROUT PPR SFA SFB FIA F1B RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting a bit in CFORC causes a specific output on OC or PWM pins PWMC sets PWM operating conditions FOC 5 1 Force Output Compare 0 Has no meaning 1 Causes pin action programmed for corresponding OC pin but the OC flag is not set FOC 5 1 correspond to OC 5 1 MOTOR
23. NEGATE AS AND DS S5 TERMINATE CYCLE S5 1 REMOVE DATA FROM DATA BUS 2 NEGATE DSACK START NEXT CYCLE 50 RD CYC FLOW Figure 4 9 Word Read Cycle Flowchart MOTOROLA SYSTEM INTEGRATION MODULE MC68331 4 24 USER S MANUAL 4 5 2 2 Write Cycle During a write cycle the MCU transfers data to an external memory or peripheral de vice If the instruction specifies a long word or word operation the MCU attempts to write two bytes at once For a byte operation the MCU writes one byte The portion of the data bus upon which each byte is written depends on operand size peripheral ad dress and peripheral port size Refer to 4 4 2 Dynamic Bus Sizing and 4 4 4 Misaligned Operands for more infor mation Figure 4 10 is a flowchart of a write cycle operation for a word transfer Refer to the S M Reference Manual SIMRM AD for more information MCU PERIPHERAL ADDRESS DEVICE 50 SET R W TO WRITE DRIVE ADDRESS ON ADDR 23 0 DRIVE FUNCTION CODE ON FC 2 0 DRIVE SIZ 1 0 FOR OPERAND SIZE ASSERT AS 51 PLACE DATA ON DATA 15 0 S2 ASSERT DS AND WAIT FOR DSACK S3 ACCEPT DATA S2 S3 1 DECODE ADDRESS 2 LATCH DATA FROM DATA BUS 3 ASSERT DSACK SIGNALS TERMINATE OUTPUT TRANSFER S5 1 NEGATE DS AND AS 2 REMOVE DATA FROM DATA BUS TERMINATE CYCLE START NEXT CYCLE Figure 4 10 Write Cycle Flowchart 1 NEGATE DSACK WR CYC FLOW 4 5 3 Fast Termination Cycles
24. A 3 4 16 78 MHz Clock Control Timing 3 4 20 97 MHz Clock Control Timing s c oct eed tede A 4 A 5 16 79 MHz DG Characteristics 5 2 comer ES A 5 A 5 20 97 MHz DC Characteristics LOU EAE Rei A 6 A 6 16 78 MHZ AG ocu eontra ri e bs gea ir ub owe rat A 8 A 6 ACTIF aos edt eot rb A 9 A 7 Background Debugging Mode A 20 A 8 16 78 MHz EGLK Bus Timing A 22 A 8 20 97 MHz Bus Timing sxe coi oo EPA OR UL CES MAIOR A 22 A 9 OSPITI PERO EO e bestes anu a A 24 B 1 MCU Ordering Inrorimetiot eoi S ibo pec e RE UI bn VE B 4 B 2 Quantity Order Suffix cata demo Se 4 C 1 MC68331 Development Tools C 1 D 1 Module Address Map roo Ui tob OU eu D 1 D 2 GET Address tpi Ue epa ed od ms at albidae D 4 D 3 SIM Address Map dt et Rs bi deno eta cet d Late D 13 D 4 Port E Pin Assignments D 18 D 5 Port F Pin Assignments D 19 D 6 Software Watchdog Ratio nash cb bapie dede D 19 D 7 BUS Monitor Period D 20 D 8 CSPARO Pin ASSIQGMIMGINS ocio o
25. or 144 pin plastic surface mount package This appendix provides package pin assignment drawings and ordering information MC68331 MECHANICAL DATA AND ORDERING INFORMATION MOTOROLA USER S MANUAL B 1 Vss NC PGPO IC1 PGP1 IC2 PGP2 IC3 PGP3 OC1 PGP4 0C2 0C1 PGP5 OC3 OC1 PGP7 IC4 OC5 OC1 PAI NC Sx na na AQOVOOFZ0 HO gt gt gt gt ADDR23 CS10 PC6 ADDR22 CS9 PC5 ADDR21 CS8 PC4 ADDR20 CS7 PC3 ADDR19 CS6 PC2 FC2 CS5 PC1 FC1 CS4 PCO FCO CS3 VDD VDD NC BGACK CS2 ADDR1 51 ADDR2 BRICSO ADDR3 CSBOOT ADDR4 DATAO ADDR5 DATA ADDR6 DATA2 ADDR7 DATA3 ADDR8
26. DDRQS determines whether pins are inputs or outputs Clearing a bit makes the cor responding pin an input setting a bit makes the pin an output DDRQS affects both QSPI function and function Table 0 15 Effect of DDRQS PORTQS Pins Pin DDRGS Bit Pin Function PQSO 0 Digital Input 1 Digital Output PQS1 0 Digital Input 1 Digital Output PQS2 0 Digital Input 1 Digital Output PQS2 0 Digital Input 1 Digital Output PQS3 0 Digital Input 1 Digital Output PQS4 0 Digital Input 1 Digital Output PQS5 0 Digital Input 1 Digital Output PQS6 0 Digital Input 1 Digital Output PQS7 0 Digital Input 1 Digital Output MC68331 REGISTER SUMMARY MOTOROLA USER S MANUAL D 31 Table D 16 Effect of DDRQS QSM Pin Function Pin Function Serial Data Input to QSPI Disables Data Input Slave Disables Data Output Nod Serial Data Output from QSPI Master Disables Data Output Serial Data Output from QSPI Slave Serial Data Input to QSPI Disables Data Input Master Disables Clock Output Clock Output from QSPI Slave Clock Input to QSPI Disables Clock Input 50 55 Master Assertion Causes Mode Fault Chip Select Output Slave QSPI Slave Select Input Disables Select Input PCS 3 1 Master Disables Chip Select Output ES Chip Select Output Slave Inactive Inactive Transmit Serial Data Output from SCI Receive Serial Data Input to SCI 1 PQS2 is a
27. Excel or veo A 18 A 11 Chip Select Timing 19 A 12 Reset and Mode Select Timing A 19 A 13 Background Debugging Mode Timing Diagram Serial Communication 21 A 14 Background Debugging Mode Timing Diagram Freeze Assertion A 21 A 15 Timing DIOE elTc cete A 23 A 16 QSPI Timing Master 0 A 25 A 17 QSPI Timing Master 1 A 25 A 18 QSPI Timing Slave 0 A 26 19 QSPI Timing Slave 1 A 26 B 1 132 Pin Plastic Surface Mount Package Pin Assignments B 2 B 2 144 Pin Plastic Surface Mount Package Pin Assignments B 3 D 1 User Programming Model ar DEED x veris D 2 D 2 Supervisor Programming Model D 2 MOTOROLA MC68331 xii USER S MANUAL LIST TABLES Table Title 3 1 MGU Driver TYPOS ioo et rore e vx t en eda 3 2 MCU Pin Characteristics osi ctor 3 3 MCU Power Connections 3 4 signal Characteristics pe ie stetit euch 3 5 Signal FUNGUO eter dedu batis tectus suede 3 6 SIM Reset Mode Selection
28. J M 68M EV 163 68331 User s Manual Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or
29. Port size determines the way in which bus transfers to an external address are allo cated Port size of eight bits or sixteen bits can be selected when a pin is assigned as a chip select Port size and transfer size affect how the chip select signal is asserted Refer to 4 8 1 3 Chip Select Option Registers for more information Out of reset chip select pin function is determined by the logic level on a correspond ing data bus pin These pins have weak internal pull up drivers but can be held low by external devices Refer to 4 6 3 1 Data Bus Mode Selection for more informa tion Either 16 bit chip select function 9611 or alternate function 9601 can be select ed during reset All pins except the boot ROM select pin CSBOOT are disabled out of reset There are twelve chip select functions and only eight associated data bus pins There is not a one to one correspondence Refer to 4 8 4 Chip Select Reset Operation for more detailed information The CSBOOT signal is normally enabled out of reset The state of the DATAO line dur ing reset determines what port width CSBOOT uses If DATAO is held high either by the weak internal pull up driver or by an external pull up device 16 bit width is select ed If DATAO is held low 8 bit port size is selected MC68331 SYSTEM INTEGRATION MODULE MOTOROLA USER S MANUAL 4 51 A pin programmed as a discrete output drives external signal to the value specified in the data register No d
30. The system test block incorporates hardware necessary for testing the MCU It is used to perform factory tests and its use in normal applications is not supported MC68331 SYSTEM INTEGRATION MODULE MOTOROLA USER S MANUAL 4 1 SYSTEM CONFIGURATION AND PROTECTION CLKOUT CLOCK SYNTHESIZER EXTAL MODCLK CHIP SELECTS CHIP SELECTS EXTERNAL BUS EXTERNAL BUS INTERFACE lt gt RESET TSC FACTORY TEST FREEZE QUOT S C IM BLOCK Figure 4 1 System Integration Module Block Diagram 4 2 System Configuration and Protection The system configuration and protection functional block controls module configura tion preserves reset status monitors internal activity and provides periodic interrupt generation Figure 4 2 is a block diagram of the submodule MOTOROLA SYSTEM INTEGRATION MODULE MC68331 4 2 USER S MANUAL MODULE CONFIGURATION AND TEST RESET STATUS HALT MONITOR RESET REQUEST CLOCK RESET REQUEST 29 PRESCALER PERIODIC INTERRUPT TIMER IRQ 7 1 SYS PROTECT BLOCK Figure 4 2 System Configuration and Protection 4 2 1 Module Mapping Control registers for all the modules in the microcontroller are mapped into a 4 Kbyte block The state of the module mapping bit MM in the SIM module configuration reg ister SIMCR determines where the control register block is located in the system memory map When MM 0 register addresses range from 7 000 to 7FFFFF when 1 register address
31. MC68331 ELECTRICAL CHARACTERISTICS MOTOROLA USER S MANUAL A 23 Table 9 QSPI Timing Vpp 5 0 s 1095 Vss 0 TL to 200 pF load on all QSPI pins Num Function Symbol Min Max Unit Operating Frequency fop Master DC 1 4 System Clock Frequency Slave DC 1 4 System Clock Frequency 1 Time lacyc Master 4 510 Slave 4 2 Enable Lead Time tlead Master 2 128 Slave 2 3 Enable Lag Time Master 1 2 SCK Slave 2 4 SCK High Low Time tow Master 2 toyo 60 255 ns Slave 2 ns 5 Sequential Transfer Delay ttd Master 17 8192 Slave Does Not Require Deselect 13 lcyc 6 Data Setup Time Inputs tsu Master 30 ns Slave 20 ns 7 Data Hold Time Inputs thi Master 0 m ns Slave 20 ns 8 Slave Access Time ta 1 9 Slave MISO Disable Time tdis 2 10 Data Valid after SCK Edge ty Master 50 ns Slave 50 ns 11 Data Hold Time Outputs tho Master 0 ns Slave 0 ns 12 Rise Time Input ti 2 us Output tro 30 ns 13 Time Input 2 us Output lto 30 ns Notes 1 All AC timing is shown with respect to 20 Vpp and 7096 Vpp levels unless otherwise noted 2 In formula n External SCK rise External SCK fall time 3 Data can be recognized properly with longer transition times as long as MOSI MIS
32. All exception vectors are located in supervisor data space except the reset vector which is located in supervisor program space Only the initial reset vector is fixed in the processors memory map Once initialization is complete there are no fixed as signments Since the vector base register VBR provides the base address of the vec tor table the vector table can be located anywhere in memory Refer to SECTION 5 CENTRAL PROCESSING UNIT for more information concerning memory manage ment extended addressing and exception processing Refer to SECTION 4 SYSTEM INTEGRATION MODULE for more information concerning function codes and ad dress space types MOTOROLA OVERVIEW MC68331 3 10 USER S MANUAL YFFOO0 YFF900 YFF93F 00 SIM YFFA7F YFFA80 YFFAFF RESERVED YFFCOO YFFDFF YFFFFF Y M111 where M is the state of the module mapping MM bit in the SIM configuration register 331 ADDRESS MAP Figure 3 4 Internal Register Memory Map MC68331 OVERVIEW MOTOROLA USER S MANUAL 3 11 000000 VECTOR VECTOR TYPE OF OFFSET NUMBER EXCEPTION 0000 RESET INITIAL STACK POINT