AMIC A67L06181/A67L93361 DATA SHEET
Contents
1. 67LO6181 hy f A67L06181 A67L93361 Preliminary 1M X 18 512K X 36 LVTTL Flow through ZeBL SRAM Document Title 1M X 18 512K X 36 LVTTL Flow through ZeBL SRAM Revision History Rev History Issue Date Remark 0 0 Initial issue August 20 2005 Preliminary PRELIMINARY August 2005 Version 0 0 AMIC Technology Corp AMIC Preliminary Features Fast access time 6 5 7 5 8 5 ns 153 133 117 MHz W Zero Bus Latency between READ and WRITE cycles allows 100 bus utilization Signal 3 3V 5 power supply W Individual Byte Write control capability W Clock enable CEN pin to enable clock and suspend operations General Description The AMIC Zero Bus Latency ZeBL SRAM family employs high speed low power CMOS designs using an advanced CMOS process The A67L06181 A67L93361 SRAMs integrate a 1M X 18 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2 bit burst counter These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write Read alternation The positive edge triggered single clock input CLK controls all synchronous inputs passing through the registers The synchronous inputs include all address all data inputs active low chip enable CE two additional chip enables for easy depth expansion CE2 CE2 cycle start input ADV LD synchronous clock enable CEN byte write enables BW1 BW2 BW32. 14 ol Don t Care AMIC Technology Corp i AMIC A67L06181 A67L93361 READ WRITE Timing COMMAND Note WRITE WRITE WERT READ READ ped WRITE READ WRITE 4 D A1 D A2 D A241 Q A3 Q A4 Q A441 5 Q A6 D A7 Don t Care Undefined 1 For this waveform ZZ is tied LOW 2 Burst sequence order is determined by MODE 0 linear 1 interleaved BRST operations are optional 3 CE represents three signals When 0 it represents CE 0 0 CE2 1 4 Data coherency is provided for all possible operations If a READ is initiated the most current data is used The most recent data may be from the input data register PRELIMINARY August 2005 Version 0 0 15 AMIC Technology Corp A67L06181 A67L93361 NOP STALL and Deselect Cycles CLK yo tKHQX gt COMMAND WRITE READ srati READ WRITE STAIL READ CONTINUE D A1 Q A2 Q A3 D A4 Q A5 DESELECT Don t Care Dx Undefined Note 1 The IGNORE CLOCK EDGE or STALL cycle clock 3 illustrates CEN being used to create a pause A WRITE is not performed during this cycle 2 For this waveform ZZ and OE are tied LOW 3 CE represents three signals When CE it represents CE 0 0 CE2 1 4 Data coherency is provided for all possible operations If a READ is initiated the most current data is used The most recent da
3. BW4 and read write R W Asynchronous inputs include the output enable OE clock CLK SLEEP mode ZZ tied LOW if unused and burst mode MODE Burst Mode can provide either interleaved or linear operation burst operation can be initiated by synchronous address Advance Load ADV LD pin in Low state Subsequent burst address can be internally PRELIMINARY August 2005 Version 0 0 A67L06181 A67L93361 1M X 18 512K X 36 LVTTL Flow through ZeBL SRAM Clock controlled and registered address data and control signals Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control address pipelining Internally self timed write cycle Selectable BURST mode Linear or Interleaved SLEEP mode ZZ pin provided Available in 100 pin LQFP package generated by the chip and controlled by the same input pin ADV LD in High state Write cycles are internally self time and synchronous with the rising edge of the clock input and when R W is Low The feature simplified the write interface Individual Byte enables allow individual bytes to be written BW1 controls l Oa pins BW2 controls pins BW3 controls 1 pins and BWA controls l Od pins Cycle types can only be defined when an address is loaded The SRAM operates from a 3 3V power supply and all inputs and outputs are LVTTL compatible The device is ideally suited for high bandwidth utilization systems AM
4. LOW time 2 5 Clock to output valid 6 5 Clock to output invalid 3 0 2 8 2 8 3 0 7 5 10 100 MHz 3 0 5 3 0 5 8 5 3 0 Clock to output in Low Z 2 ns 1 2 3 5 2 5 2 5 DE woouputvaid 35 35 me OE toouputinowz o 0 tee toouputinnignz 35 as Setup Times Clock enable CER Conto signa Hold Times Notes 1 This parameter is sampled 2 Output loading is specified with C1 5pF as in Figure 2 3 Transition is measured 200 from steady state voltage 4 OE can be considered a Don t Care during WRITE however controlling OE can help fine tune a system for turnaround timing 5 This is a synchronous device All addresses must meet the specified setup and hold times for all rising edges of CLK when ADV LD is LOW and chip enabled All other synchronous inputs meet the setup and hold times with stable logic levels for all rising edges of clock CLK when the chip is enabled Chip enable must be valid at each rising edge of CLK when ADV LD is LOW to remain enabled PRELIMINARY August 2005 Version 0 0 12 AMIC Technology Corp A67L06181 A67L93361 AC Test Conditions Input Pulse Levels GND to 3 0V Input Rise and Fall Times 1 0ns Input Timing Reference Levels 1 25V Output Reference Levels 1 25V Figure 1 Figure 2 Output Load Equival
5. X10 X X11 X X00 X X11 X X10 X X01 PRELIMINARY August 2005 Version 0 0 9 AMIC Technology Corp AMIC Absolute Maximum Ratings Power Supply Voltage VCC 0 3V to 4 6V Voltage Relative to GND for any Pin Except VCC Vin Vout 0 3V to VCC 0 3V Operating Temperature Topr Storage Temperature Tbias Storage Temperature Tstg A67L06181 A67L93361 Comments Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device These are stress ratings only Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended Exposure to the absolute maximum rating conditions for extended periods may affect device reliability DC Electrical Characteristics and Operating Conditions 0 C lt Ta lt 70 C VCC VCCQ 3 3V 5 unless otherwise noted Parameter Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current ILo VoH Output High Voltage VoL Output Low Voltage Capacitance Control Input Capacitance Supply Voltage Isolated Output Buffer Supply Input Output Capacitance I O Conditions OV x lt VCC Output s disabled OV x Vins VCC 1 0 lo 1 0mA Conditions 25 C f 1 2 VCC 3 3V Address Capacitance Note 1 All voltages refe
6. depth expansion Synchronous Chip Enable This active high input is used to enable the device and is sampled only when a new external address is loaded ADV LD LOW This input can be used for memory depth expansion Output Enable This active low asynchronous input enables the data I O output drivers ADV LD Synchronous Address Advance Load When HIGH this input is used to advance the internal burst counter controlling burst access after the external address is loaded When HIGH R W is ignored A LOW on this pin permits a new address to be loaded at CLK rising edge CEN Synchronous Clock Enable This active low input permits CLK to propagate throughout the device When HIGH the device ignores the CLK input and effectively internally extends the previous CLK cycle This input must meet setup and hold times around the rising edge of CLK PRELIMINARY August 2005 Version 0 0 6 AMIC Technology Corp Synchronous Chip Enable This active low input is used to enable the device and is sampled only when a new external address is loaded ADV LD LOW This input can be used AMIC Pin Description continued 52 53 56 57 58 59 62 63 51 68 69 72 73 74 75 78 79 80 2 3 6 7 8 9 12 13 1 13 12 9 8 18 19 22 23 24 25 28 29 30 1 2 3 6 7 25 28 38 39 42 43 29 30 38 39 42 43 51 52 53 56 57 75 78 79 95 96 74 73 72 69 68 63 62 59 58 24 23 22 19 18 A6
7. 61 Block Diagram 512K X 36 ZZ 0 18 ADDRESS REGISTERS ADV LD RW BW1 BW2 BW3 BWA BURST LOGIC ADDRESS COUNTER CLR WRITE ADDRESS REGISTER BYTEa WRITE DRIVER BYTEb WRITE 512KX9X4 DRIVER MEMORY BYTEc WRITE ARRAY DRIVER BYTEd WRITE DRIVER OUTPUT BUFFERS DATA IN REGISTERS q CE CHIP P FLOW THROUGH CE2 ENABLE ENABLE CE2 LOGIC LOGIC OUTPUT ENABLE LOGIC OE PRELIMINARY August 2005 Version 0 0 4 AMIC Technology Corp A67L06181 A67L93361 AMIC Block Diagram 1M X 18 Sa 22 MODE MODE gt LOGIC ADVID 4 ay 0 CLK LOGIC L4 BURST LOGIC ADDRESS COUNTER CLR ADDRESS 0 19 REGISTERS LI i BYTEa WRITE 1MX9X2 u DRIVER ADVILD 3 MEMORY SENSE OUTPUT RW AMPS BUFFERS UNIT BYTEb ARRAY BW WRITE BW2 DRIVER DATA IN REGISTERS CE CHIP FLOW ENABLE THROUGH LOGIC ENABLE LOGIC CE2 OUTPUT ENABLE LOGIC PRELIMINARY August 2005 Ve
8. 7L06181 A67L 93361 Description Snooze Enable This active high asynchronous input causes the device to enter a low power standby mode in which all data in the memory array is retained When active all other inputs are ignored Read Write This active input determines the cycle type when ADV LD is LOW This is the only means for determining READs and WRITEs READ cycles may not be converted into WRITEs and vice versa other than by loading a new address A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK Full bus width WRITEs occur if all byte write enables are LOW SRAM Data I O Byte a is pins Byte b is I Ob pins Byte c is l Oc pins Byte d is I Od pins Input data must meet setup and hold times around CLK rising edge Mode This input selects the burst sequence A LOW on this pin selects linear burst NC or HIGH on this pin selects interleaved burst Do not alter input state while device is operating No Connect These pins can be left floating or connected to GND to minimize thermal impedance 15 16 41 65 91 15 16 41 65 91 ve Power Supply 4 11 20 27 4 11 20 27 54 61 70 77 54 61 70 77 VCCQ Isolated Output Buffer Supply 14 17 40 66 90 17 40 66 90 14 17 40 66 90 VSS Goud GND 000000000 Ground GND 5 10 21 26 5 10 21 26 VSSQ Isolated Output Buffer Ground 55 60 71 76 55 60 71 76 PRELIMINAR
9. IC Technology Corp AMIC Pin Configuration A67L06181 A67L93361 512K X 36 es e sis BIEIEIZIEIB S 8 2 2 ming zip he PLETE ess 25 5 gt GB BS BS NC 1 1 A10 l Oba l Oco 2 NC l Obe VCCQ vcCQ 4 VCCQ VSSQ 550 15 550 VSSQ l Oc2 NC 6 NC l Obs l Oca NC LI 7 l Oba Oca Obs 8 l Ocs 19 2 VSSQ 550 110 550 VSSQ VCCQ vccQ 1 VCCQ l Oce Obs L__ 12 Oa l Obi VObs 13 __ Oa4 l Obo vss vss 14 A67L06181E 1 vss vss VCC 115 A67L93361E vss vss VCC vCC L 16 vec VCC VSS vss 17 12 22 l Odo VOba 18 Oas l Oaz Oda Obs 19 VCCQ E 20 VCCQ VSSQ VSSQ 21 550 VSSQ 2 VOb2 22 7 l Oas 23 1 Oas VOaa l Od4 124 NC l Oas l Ods NC 25 1 NC l Oa2 VSSQ VSSQ 126 550 VSSQ VCCQ vCCQ 27 vccQ VCCQ 1 Ode NC C 28 NC l Oa1 NC 29 NC l Oao l Ode NC 7 NC 8 8858858 881595 881588680 PPTL IPP veges essss gt PRELIMINARY August 2005 Version 0 0 3 AMIC Technology Corp AMIC A67L06181 A67L933
10. Y August 2005 Version 0 0 7 AMIC Technology Corp A67L06181 A67L93361 Truth Table Notes 5 7 oe Kl Gd a bd a Gn ida Kd Operation m Used LD mu I II Power down mu a a Power down dG Power down Cycle mm a Begin Burst mx Continue Burst Begin Burst Continue Burst Kd a E Begin Burst Fa Continue Burst Begin Burst Continue Burst Fal a Stall SLEEP Mode None x x x H X x Notes 1 Continue Burst cycles whether READ or WRITE use the same control inputs The type of cycle performed READ or WRITE is chosen in the initial Begin Burst cycle A Continue Deselect cycle can only be entered if a Deselect cycle is executed first 2 Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation A WRITE Abort means a WRITE command is given but no operation is performed 3 may be wired LOW to minimize the number of control signals to the SRAM The device will automatically turn off the output drivers during a WRITE cycle Some users may use OE when the bus turn on and turn off times do not meet their requirements 4 If an Ignore Clock Edge command occurs during a READ operation the I O bus will remain active Low Z If it occurs during a WRITE cycle the bus will remain in High Z No WRITE operations will
11. be performed during the Ignored Clock Edge cycle 5 X means Don t Care means logic HIGH L means logic LOW BWx means all byte write signals BW1 BW2 BW3 BW4 are HIGH BWx means one or more byte write signals are LOW 6 BW1enables WRITEs to Byte a l Oa pins BW2 enables WRITEs to Byte b l Ob pins Bw3 enables WRITEs to Byte c 1 pins BW4 enables WRITEs to Byte d I Od pins 7 The address counter is incremented for all Continue Burst cycles PRELIMINARY August 2005 Version 0 0 8 AMIC Technology Corp A67L06181 A67L93361 Partial Truth Table for READ WRITE Commands X18 WRITE Abort NOP Note Using R W and BYTE WRITE s any one or more bytes may be written Partial Truth Table for READ WRITE Commands X36 w WRITE Byte ____ o n WRITE Byte w ____ o Lon J t ____ t t t p to to y abo o n Note Using R W and BYTE WRITE s any one or more bytes may be written tHE i I t I Linear Burst Address Table MODE LOW X X10 X X11 X X00 X X11 X X00 X X01 Interleaved Burst Address Table MODE HIGH or NC First Address External Second Address Internal Third Address Internal Fourth Address Internal X X00 X X01 X X10 X X11 X
12. ent Output Load Equivalent PRELIMINARY August 2005 Version 0 0 13 AMIC Technology Corp AMIC SLEEP Mode SLEEP Mode is a low current Power down mode in whic h the device is deselected and current is reduced to Isgzz This duration of SLEEP Mode is dictated by the length of time th ZZ is in a HIGH state After entering SLEEP Mode all inputs except ZZ become disabled and all outputs go to High Z The ZZ pin is asynchronous active high input that causes the device to enter SLEEP Mode When the ZZ pin becomes logic HIGH ISB2Z is guaranteed after the time tzzi SLEEP Mode Electrical Characteristics VCC VCCQ 3 3V 5 Parameter Current during SLEEP Mode ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current ZZ gt A67L06181 A67L93361 is met Any operation pending when entering SLEEP Mode is not guaranteed to successfully complete Therefore SLEEP Mode READ or WRITE must not be initiated until valid pending operations are completed Similarly when exiting SLEEP Mode during trzz only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP Mode Conditions To ate a eee Note 1 This parameter is sampled SLEEP Mode Waveform CLK ZZ IsurpLy 1158227 ALL INPUTS except ZZ Output Q PRELIMINARY August 2005 Version 0 0
13. renced to VSS GND 2 Overshoot Undershoot Power up Vin 4 6V for t 2 for x 20mA Vit gt 0 7V for t lt tkuku 2 for lt 20mA Vin 3 465V and VCC lt 3 135V for t x 200ms 3 The load used for Vou Vor testing is shown in Figure 2 AC load current is higher than the shown DC values AC I O curves are available upon request 4 VCC and VCCQ can be externally wired together to the same power supply 5 This parameter is sampled PRELIMINARY August 2005 Version 0 0 10 AMIC Technology Corp AMIC Operating Condition and Maximum Limits Symbol Parameter Power Supply Current Operating M PRELIMINARY August 2005 Version 0 0 11 A67L06181 A67L93361 Conditions Device selected All inputs lt Vit or 2 Vin Cycle time gt tkc MIN VCC MAX Output open Device deselected VCC MAX All inputs lt VSS 0 2 or gt 0 2 Cycle time gt tke MIN Device deselected VCC MAX All inputs lt VSS 0 2 or gt 0 2 All inputs static CLK frequency MAX ZZ gt Vcc 0 2V Device deselected VCC MAX All inputs lt Vit or 2 Vin All inputs static CLK frequency 0 AMIC Technology Corp AMIC AC Characteristics Note 4 0 lt Ta lt 70 VCC 3 3V 5 Parameter A67L06181 A67L93361 Clock Clock cycle time T5 tkF Clock frequency 133 Clock HIGH time 2 5 Clock
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15. rsion 0 0 5 AMIC Technology Corp mmm AMIC CAG 7L06181 AG7L93361 Pin 24 7 Synchronous Address Inputs These inputs are registered and must meet the setup and hold times around the rising 35 34 33 32 35 34 33 32 2 9 edge of CLK Pins 83 and 84 reserved as address bits 100 99 82 81 100 99 82 81 for higher density 9Mb and 18Mb DBA SRAMS respectively 44 45 46 47 45 46 47 48 A11 A18 AO and 1 are the two lest significant bits LSB of the 48 49 50 83 49 50 83 84 address field and set the internal burst counter if burst is 84 19 desired 80 44 A10 93 BW1 93 BW1 BW1 Synchronous Byte Write Enables These active low inputs 94 BW2 94 BW2 BW2 allow individual bytes to be written when a WRITE cycle is 95 BW3 BW3 active and must meet the setup and hold times around the 96 BW4 BWA rising edge of CLK BYTE WRITES need to be asserted on the same cycle as the address BWs are associated with addresses and apply to subsequent data BW1 controls pins BW2 controls pins BW3 controls pins BWA controls I Od pins Clock This signal registers the address data chip enables byte write enables and burst control inputs on its rising edge All synchronous inputs must meet setup and hold times around the clock s rising edge Synchronous Chip Enable This active low input is used to enable the device This input is sampled only when a new external address is loaded ADV LD LOW for memory
16. ta may be from the input data register PRELIMINARY August 2005 Version 0 0 16 AMIC Technology Corp A67L06181 A67L93361 Ordering Information A67L06181E 7 5F 100L Pb Free LQFP A67L06181E 8 5 100L LQFP A67L06181E 8 5F 100L Pb Free LQFP A67L06181E 10 0 100L LQFP A67L06181E 10 0F 10ns 8 5ns 100L Pb Free LQFP A67L93361E 7 5 7 5ns 6 5ns 100L LQFP A67L93361E 7 5F 7 5ns 6 5ns 1001 Pb Free LQFP A67L93361E 8 5 8 5ns 7 5ns 100L LQFP 512K X 36 A67L93361E 8 5F 8 5ns 7 5ns 100L Pb Free LQFP A67L93361E 10 0 10ns 8 5ns 100L LQFP A67L93361E 10 0F 10ns 8 5ns 100L Pb Free LQFP PRELIMINARY August 2005 Version 0 0 17 AMIC Technology Corp i AMIC A67L06181 A67L93361 Package Information LQFP 100L Outline Dimensions unit inches mm Symbol Dimensions in inches Dimensions in mm s om sms oz 020 0 630 BSC 16 00 BSC D 0 551 BSC 14 00 BSC 0 026 BSC 0 65 BSC 71 so ora cas 075 a 0 039 REF 1 00 REF Notes 1 Dimensions D and E do not include mold protrusion 2 Dimensions b does not include dambar protrusion Total in excess of the b dimension at maximum material condition Dambar cannot be located on the lower radius of the foot PRELIMINARY August 2005 Version 0 0 18 AMIC Technology Co
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AMIC A67L06181/A67L93361 DATA SHEET