intel iPLDLV22V10-15 handbook
Contents
1. iPLDLV22V10 macrocell registers can be preset or reset using global preset and reset p terms Register preset is synchronous and must meet the specified setup time to the clock signal Register reset is asyn chronous and has no setup requirement to the clock Preset and reset set or reset the register Out put polarity is selected separately Powered by ICminer com Programmable Output Enable Each macrocell contains an output buffer that can place the respective output in a high impedance state three state The output buffer is controlled by a single p term per macrocell in the logic array and is asynchronous POWER ON CHARACTERISTICS iPLDLV22V10 inputs and outputs begin responding 1 ps max after Voc power up Vcc 3 0V or after a power loss power up sequence All macro cells programmed as registers are set to a logic low 2 139 Electronic Library Service CopyRight 2003 Powered by ICminer com IPLDLV22V 10 15 PROGRAMMING CHARACTERISTICS Prior to programming all EPROM logic array cells are in the connected state The macrocells by de fault are configured for registered output active low operation with registered feedback Intelligent Programming Alogrithm The iPLDLV22V10 supports the Intelligent Program ming Algorithm a fast reliable algorithm for pro gramming many types of Intel programmable devic es PROCESS TECHNOLOGY The iPLDLV22V10 is fabricated on Intel s CHMOS EPROM process Over 202. UP RESET POWER Weg REGISTER OUTPUT T EN M 2 E es tee 290487 10 SOpF 70pF 110pF 150pF J90pF Capacitance lusu POWER UP RESET TC CHARACTERISTICS Voc 475V Parameter Parameter 2 Symbol Description t Pi 7 OWER UP RESET o PR Internal power up reset circuits ensure that all flip VON Turn On 25V fiops will be reset to a logic O after the device has Voltage powered up Because Vcc rise can vary significantly from one application to another Vcc rise must be monotonic Input Output Equivalent Schematics Vcc ESD PROTECTION INPUT PROGRAM VERIF Y CIRCUITS WEAK PULL UP 290487 11 1 0 PIN ESD PROTECTION INPUT PIN FEEDBACK PROGRAM VERIFY CIRCUITS 290487 12 2 145 Powered by ICminer com Electronic Library Service CopyRight 2003
3. million devices including EPROMs and Microcontrollers have been fabricat ed on this process TESTABILITY The iPLDLV22V10 is completely tested at the facto ry Unlike fuse based PLDs which have one time programmable fuse links that limit testing to smail Scale sampling each EPROM cell in the iPLDLV22V10 is tested and erased prior to ship ment SECURITY A single programmable bit called the security bit or verify protect bit controls access to the data pro grammed into the device Once this security bit is set the design cannot be copied Since data in the device is stored in EPROM cells the contents of the device cannot be read even with a intel microscopic examination providing an additional level of design security not available with fuse based devices DEVELOPMENT SOFTWARE Third Party Support The iPLDLV22V10 is supported by choosing the standard 22V10 from third party logic compilers such as ABEL CUPL PLDesigner Log IC etc Programming support is provided by third party pro grammer companies such as Data I O Logical De vices STAG etc Please refer to the Third Party Support lists in the Programmable Logic handbook for complete information and vendor contacts PLDshell Plus Full logic compilation and functional simulation for the iPLDLV22V10 is supported by PLDshel Plus software by choosing the PLD22V10 option on the programming menu PLDshell Plus design software is Intel s new us
4. EST POINTS X1 5v 0 OUTPUT 1 5V X TEST POINTS X 1 5v 290487 6 A C Testing Inputs are Driven at 3 0V for a Logic 1 and OV fora Logic 0 Timing Measurements are made at 1 5V Outputs are measured at 1 5V Device input rise and fall times 3 ns CAPACITANCE Ta 0 C to 70 C Voc 3 3V 10 5 Symbo Parameter Mi Cw put Capactance 5 oo vocaweanme s Cou crk Capectanes Max unite Comes amp s vw ovr Lome e sr Vour F7 romz 2 142 Powered by ICminer com Electronic Library Service CopyRight 2003 IPLDLV22V 10 15 intel COMBINATORIAL MODE A C CHARACTERISTICS TA 0 C to 70 C Voc 3 3V 10 6 me rama ie tpp 7 Input or I O to Output Valid w 10 Outputs Switching 6 tpzx9 Input or I O to Output Enable 6 IPLDLV22V 10 15 ipxz 8 Input or 1 O to Output Disable Input or I O to Asynch Reset NOTES 5 These values are evaluated at initial characterization and whenever design modifications occur that may affect capaci tance 6 Typical values are at TA 7 Ten outputs switching 8 tpzx and tpxz are measured at 0 5V from steady state voltage as driven by spec output load tpxz is measured with CL 5 pF Z H and Z L are measured at 1 5V on output 9 Measured with device configured as a 10 bit counter 28 C Voc 3 3V RE
5. GISTER MODE SYNCHRONOUS CLOCK A C CHARACTERISTICS Ta Symbol fonti 0 C to 70 C Veg 3 3V t 1096 Parameter Max Counter Frequency 1 tgy tco External Feedback fontz peas Max Counter Frequency 1 tcur Internal Feedback Max Frequency Pipelined 1 tcp No Feedback tco2 Input or I O Hold Time from CLK CLK to Output Valid ES dM Input or 1 0 Setup Time to CLK a amet or O Setup Time to Synchronous Preset Hes m ns ns CLK to Output Valid Fed Through Combinatorial Macrocell Register Output Feedback to Register Input Internal Path enr Powered by ICminer com CLK Low Time CLK High Time CLK Period Asynchronous Reset Pulse Duration Asynchronous Reset to CLK T Recovery Time v Electronic Library Service CopyRight 2003 ns 2 143 iPLDLV22V10 15 in COMBINATORIAL MODE 1 INPUT OR 1 0 X teo COMBINATORIAL OUTPUT i HIGH IMPEDANCE COMBINATORIAL OR 3 STATE REGISTERED OUTPUT HIGH IMPEDANCE q ASYNCHRONOUSLY RESET OUTPUT 1 1 VALID INPUT MAY CHANGE A INPUT A INPUT MAY CHANGE tog FROM REGISTER CLOCK 0 TO OUTPUT i VALID OUTPUT T o to FROM REGISTER CLOCK THROUGH J ADDITIONAL COMB OUTPUT VALID OUTPUT 2 144 Powered by ICminer com Electronic Library Service CopyRight 2003 iPLDLV22V 10 15 POWER
6. Voltage V 1 2 0 5V to Voc 0 5V Operating Conditions is not recommended and ex M ig tended exposure beyond the Operating Conditions Storage Temperature Tsig 65 C to 150 C may affect device reliability Ambient Temperature Ta 10 Cto 86 C RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage 30o Input Voltage o Output Voltage Low Level Input Voltage TTL High Output Voltage amos rign ouput vonage vos oa os Voc 3 0V lon 0 4 mA esl eles MEAE ing i pe cc E Voc Max Vout 0 5V Power Supply Current Voc 3 6V NOTES 1 Voltages with respect to GND 2 Minimum D C input is 0 5V During transitions the inputs may undershoot to 2 0V or overshoot to 7 0V for periods of less than 20 ns under no load conditions 3 Absolute values with respect to device GND all over and undershoots due to system or tester noise are included 4 Not more than 1 output should be tested at a time Duration of that test should not exceed 1 second 2 141 Powered by ICminer com Electronic Library Service CopyRight 2003 IPLDLV22V 10 15 i ntel e A C TESTING LOAD CIRCUIT Test Point tpzx Z gt H Open 50 pF 2400 1 5V Z L Closed ipxz H Z Open 5pF H Z Voy 0 5V L Z Closed L Z VoL 0 5V A C TESTING INPUT OUTPUT WAVEFORM 3 0 INPUT 1 5V T
7. er friendly design tool for PLD design PLDshell Plus allows users to incorporate their preferred text edi tor programming software and additional design tools into a easy to use menued design environ ment that includes Intel s PLDasm logic compiler and simulation software along with disassembly conversion and translation utilities The PLDasm compiler and simulator software accepts industry standard PDS source files that express designs as Boolean equations truth tables or state machines On line help datasheet briefs technical notes and error message information along with waveform viewing printing capability make the design task as easy as possible PLDshell Plus software is available from Intel Literature channels or from your local Intel sales representative order 611942 ABEL is a trademark of Data I O Corp CUPL is a trademark of Logical Devices Inc PLDesigner is a trademark of MINC Inc Log IC is a trademark of ISDATA Corporation 2 140 Electronic Library Service CopyRight 2003 i ntel e iPLDLV22V10 15 ABSOLUTE MAXIMUM RATINGS NOTICE This is a production data sheet The specifi cations are subject to change without notice 1 P Supply Voltage Voo scr sta 20Vto 7 0V WARNING Stressing the device beyond the Absolute Programming Supply Maximum Ratings may cause permanent damage Voltage VppY sous 2 0V to 13 5V These are stress ratings only Operation beyond the D C Input
8. get application Figure 3 shows the architec ture of each macrocell Output Polarity The output polarity for each iPLDLV22V 10 macrocell is programmable Each combinatorial or registered output can be active high or active iow Feedback Options iPLDLV22V10 macrocells programmed as combina torial outputs support pin feedback to the logic array i e feedback from the I O pin iPLDLV22V10 mac rocells programmed as registers allow internal regis ter feedback to the logic array Operating Range 2 137 Electronic Library Service CopyRight 2003 IPLDLV22V 10 15 i ntel e PROGRAMMABLE AND ARRAY 44 x 132 MS O EC 1 0 9 CLK INPO 2 Hee E 31 0 8 z or I 72 ro BENE i 0 Hs O K 0 7 A ik sae yf 21 0 6 in o mes B F wis Te Hoo revo re E ab HL 172 LI ee sr pu Heeres peque pese lll p pre Figure 2 iPLDLV22V 10 Global Architecture 2 138 Powered by ICminer com Electronic Library Service CopyRight 2003 iPLDLV22V 10 15 8 16 PRODUCT e TERMS e 1 0 PIN FEEDBACK FEEDBACK SELECT Figure 3 iPLDLV22V10 Macrocell Architecture Table 1 lists the macrocell configurations Table 1 iPLDLV22V 10 Macrocell Configurations Een ao eee Registered Active Low Registered Registered Active High Registered Combinatorial Active Low Pin Combinatorial Active High Pin Register Preset Reset
9. umber 290487 001 Powered by ICminer com Electronic Library Service CopyRight 2003 intel INTRODUCTION The iPLDLV22V10 is a low voltage high perform ance high integration general purpose CMOS PLD and operates at 3 3V core logic and I O The iPLDLV22V10 accommodates logic functions with up to 22 inputs and 10 1 O macrocells 1 0 macro cells include an average of 12 p terms for input with a separate p term for output enable Figure 2 shows the global architecture of the device JEDEC AND PIN COMPATIBILITY The iPLDLV22V10 is 100 JEDEC pin and func tion compatible with the industry standard 22V10 PLD JEDEC files developed for 22V10 devices can be used to program the iPLDLV22V10 When the N PLDLV22V10 28 pin PLCC is used to replace a conventional 22V10 in an existing design socket pins 8 15 22 and 1 are left as No Connects NC New designs can take advantage of the additional device Vcc and grounds these pins offer ORDERING INFORMATION fonts MHz fmax MH2 Powered by ICminer com tpp ns Order Code iPLDLV22V 10 15 PROGRAMMABLE MACROCELLS in addition to the 12 dedicated input pins the iPLDLV22V10 contains 10 programmable macro cells Each of the macrocells can be programmed to function as an input or as a combinatorial or regis tered output Programmable output polarity and programmable feedback options alow the iPLDLV22V 10 to be tailored to the precise needs of the tar
10. zi PPLD22V 10 10 hv f iPLDLV22V 10 15 LOW VOLTAGE HIGH PERFORMANCE 10 MACROCELL CMOS PLD m Supply Voltage Range 3 0V to 3 6V m Global Asynchronous Clear and m tpp 15 ns 50 MHz with Feedback Synchronous Preset P terms 83 3 MHz with No Feedback m 1 Micron CHMOS IIIE EPROM m Max icc 35 mA Technology m 12 Dedicated Inputs and 10 1 O Pins m Programmable Security Bit Allows Total Protection of Proprietary Designs m 10 Macrocells with Programmable 1 0 100 Generically Tested Logic Array Architecture Register Combinatorial Available in 300 mil 24 Pin PDIP and m Variable P terms Up to 16 per a Macrocell Selectable Output Polarity 28 Pin PLCC Packages Separate Output Enable P term See Packaging Spec Order Number 240800 Package Type N and P ez zx a gt Sym aa 88999 CLK INPO Et 24 3 Vcc zz o9 INP1 92 23 11 0 9 LLILLLELILALI 4 32 1 INP2 E43 22 1 0 8 INPS E 5 25 11 0 7 INP3 E 4 21E11 0 7 iNP4 16 24 11 0 6 INP4 C15 2011 0 6 E inP5 7 23 11 0 5 iin ia pee GND or NC OJ 8 PLDLV22V10 22 0 GN or NC or or INP6 E 7 S 18 D3i7o 4 l N INPe 19 21 11 0 4 INP7 E 8 17 3170 5 INP7 C 10 20 31 0 3 INP8 CJ 9 16 i 0 2 d NPB C 19 3170 2 iNPS E 10 15 1170 1 Cn eto 14 14 0 1 0 0 LI LJ LJ LJ LI LJ Li GND E 13E NP 1 2 2O29 2 28 22 ESS 290487 1 e 290487 2 Figure 1 Pinout Diagrams Log IC is a trademark of ISDATA Inc October 1993 2 136 Order N
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