ELPIDA EBD51RC4AKFA 512MB Registered DDR SDRAM DIMM handbook
Contents
1. 6B 7A 7B Parameter Symbol min max min max min max Unit Notes e ae uma tCK 75 12 7 5 12 10 12 ns 10 CL 2 5 tCK 6 12 7 5 12 7 5 12 ns CK high level width tCH 0 45 0 55 0 45 0 55 0 45 0 55 tCK CK low level width tCL 0 45 0 55 0 45 0 55 0 45 0 55 tCK CK half period tHP WA ane teu en K k ean tCK Ra basa dee css Ung Mom tAC 07 0 7 0 75 0 75 0 75 075 ns 211 DQS output access time from CK CK tDQSCK 0 6 0 6 0 75 0 75 0 75 0 75 ns 2 11 DQS to DQ skew tDQSQ 0 45 0 5 0 5 ns 3 DQ DQS output hold time from DQS tQH tHP tQHS tHP tQHS tHP tQHS ns Data hold skew factor tQHS 0 55 0 75 0 75 ns Ace ngkampedang ETE ANA 0 7 0 75 075 0 75 075 ns 5 11 mais low impedance time from CK tLZ 07 0 7 0 75 0 75 0 75 0 75 na 6 11 Read preamble tRPRE 0 9 1 1 0 9 1 1 0 9 1 1 tCK Read postamble tRPST 0 4 0 6 0 4 0 6 0 4 0 6 tCK DQ and DM input setup time tDS 0 45 0 5 0 5 ns 8 DQ and DM input hold time tDH 0 45 0 5 0 5 ns DQ and DM input pulse width tDIPW 1 75 1 75 1 75 ns 7 Write preamble setup time tWPRES 0 0 0 ns Write preamble tWPRE 0 25 0 25 0 25 tCK Write postamble tWPST 0 4 0 6 0 4 0 6 0 4 0 6 tCK 9 ASAP ATO AHAS an 1 25 0 75 1 25 075 1 25 tCK DQS falling edge to CK setup time tDSS 0 2 0 2 0 2 tCK DQS falling edge hold time from CK tDSH 0 2 0 2 0 2 tCK DQS input high pu2. CKO PLL Note Wire per Clock loading table Wiring diagrams Data Sheet E0377E20 Ver 2 0 SAO SA1 SA2 Notes N The SDA pull up resistor is required due to the open drain open collector output The SCL pull up resistor is recommended because of the normal SCL line inacitve high state ELPIDA EBD51RC4AKFA Differential Clock Net Wiring CKO CKO Ons nominal 120Q CKO sgt N CKO a 1200 2400 H Register1 SDRAM Typically two registers per DIMM Feedback 2400 Register2 Notes 1 The clock delay from the input of the PLL clock to the input of any SDRAM or register willl be set to 0 ns nominal 2 Input output and feedback clock lines are terminated from line to line as shown and not from line to ground 3 Only one PLL output is shown per output type Any additional PLL outputs will be wired in a similar manner 4 Termination resistors for feedback path clocks are located after the pins of the PLL Data Sheet E0377E20 Ver 2 0 ELPIDA Electrical Specifications e All voltages are referenced to VSS GND Absolute Maximum Ratings EBD51RC4AKFA Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT 1 0 to 43 6 V Supply voltage relative to VSS VDD 1 0 to 3 6 V Short circuit output current IOS 50 mA Power dissipation PD 18 W Operating ambient temperature TA Oto 70 C 1 Storage temperature Tstg 55 t
3. DQS8 93 VSS 139 VSS 2 DQO 48 AO 94 DQ4 140 DM8 DQS17 3 VSS 49 CB2 95 DQ5 141 A10 4 DQ1 50 VSS 96 VDD 142 CB6 5 DQSO 51 CB3 97 DMO DQS9 143 VDD 6 DQ2 52 BA1 98 DQ6 144 CB7 7 VDD 53 DQ32 99 DQ7 145 VSS 8 DQ3 54 VDD 100 VSS 146 DQ36 9 NC 55 DQ33 101 NC 147 DQ37 10 RESET 56 DQS4 102 NC 148 VDD 11 VSS 57 DQ34 103 NC 149 DM4 DQS13 12 DQ8 58 VSS 104 VDD 150 DQ38 13 DQ9 59 BAO 105 DQ12 151 DQ39 14 DQS1 60 DQ35 106 DQ13 152 VSS 15 VDD 61 DQ40 107 DM1 DQS10 153 DQ44 16 NC 62 VDD 108 VDD 154 RAS 17 NC 63 WE 109 DQ14 155 DQ45 18 VSS 64 DQ41 110 DQ15 156 VDD 19 DQ10 65 ICAS 111 NC 157 CSO 20 DQ11 66 VSS 112 VDD 158 NC 21 CKEO 67 DQS5 113 NC 159 DM5 DQS14 22 VDD 68 DQ42 114 DQ20 160 VSS 23 DQ16 69 DQ43 115 A12 161 DQ46 24 DQ17 70 VDD 116 VSS 162 DQ47 25 DQS2 71 NC 117 DQ21 163 NC 26 VSS 72 DQ48 118 A11 164 VDD 27 A9 73 DQ49 119 DM2 DQS11 165 DQ52 ELPIDA Data Sheet E0377E20 Ver 2 0 EBD51RC4AKFA Pin No Pin name Pin No Pin name Pin No Pin name Pin No Pin name 28 DQ18 74 VSS 120 VDD 166 DQ53 29 A7 75 NC 121 DQ22 167 NC 30 VDD 76 NC 122 A8 168 VDD 31 DQ19 77 VDD 123 DQ23 169 DM6 DQS15 32 A5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 A6 171 DQ55 34 VSS 80 DQ51 126 DQ28 172 VDD 35 DQ25 81 VSS 127 DQ29 173 NC 36 DQS3 82 VDDID 128 VDD 174 DQ60 37 A4 83 DQ56 129 DM3 IDQS12 175 DQ61 38 VDD 84 DQ57 130 A3 176 VSS 39 DQ26 85 VDD 131 DQ30 177 DM7 DQS16 40 DQ27 86 DQS7 132 VSS 1
4. PW boards with semiconductor MOS devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin The unused pins must be handled in accordance with the related specifications STATUS BEFORE INITIALIZATION OF MOS DEVICES Power on does not necessarily define initial status of MOS devices Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the MOS devices with reset function have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers MOS devices are not initialized until the reset signal is received Reset operation must be executed immediately after power on for MOS devices having reset function CME0107 Data Sheet E0377E20 Ver 2 0 ELPIDA 18 EBD51RC4AKFA The information in this document is subject to change without notice Before using this document confirm that this is t
5. 36 to 40 Superset information 0 0 0 0 0 0 0 0 OOH Future use 41 EI command period tRC 0 0o 1 A A 1 0 0 3CH 60ns 7A 7B 0 1 0 0 0 0 0 1 41H 65ns Auto refresh to active 42 Auto refresh command cycle tRFC 0 1 0 0 1 0 0 0 48H 72ns 6B 7A 7B 0 1 0 0 1 0 1 1 4BH 75ns 43 SDRAM tCK cycle max tCK max 0 0 1 1 0 0 0 0 30H 12ns 44 Baa 0 0 1 0 4 4 0 4 20H 0 45ns 7A 7B 0 0 1 1 0 0 1 0 32H 0 5ns 45 W aaa a 0 1 0 4 0 4 0 1 55H 0 55ns 7A 7B 0 1 1 1 0 1 0 1 75H 0 75ns 46 to 61 Superset information 0 0 0 0 0 0 0 0 OOH Future use 62 SPD revision 0 0 0 0 0 0 0 0 00H Initial 63 ea for bytes O to 62 0 1 0 1 0 0 0 1 51H 81 TA 0 0 0 0 1 0 0 0 08H 8 7B 0 0 1 1 0 0 1 1 33H 51 64 to 65 Manufacturer s JEDEC ID code 04 4 A 4 A A 1 7H A 66 Manufacturer s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory ELPIDA Data Sheet E0377E20 Ver 2 0 EBD51RC4AKFA Byte No Function described Bit Bit Bits Bit4 Bits Bit2 Bit1 BitO Hexvalue Comments 67 to71 Manufacturer s JEDEC ID code 0 0 0 0 0 0 0 0 00H 72 Manufacturing location x x x x x x x x xx ee 73 Module part number 0 1 0 0 0 1 0 1 45H E 74 Module part number 0 1 0 0 0 0 1 0 42H B 75 Module part number 0 1 0 0 0 1 0 0 44H D 76 Module part number 0 0 1 1 0 1 0 1 35H 5 TI Module part number 0 0 1 1 0 0 0 1 31H 1 78 Module part number 0 1 0 1 0 0 1 0 52H R 79 Module part number 0 1 0 0 0 0 1 1 43H C 80 Modul
6. 78 DQ62 41 A2 87 DQ58 133 DQ31 179 DQ63 42 VSS 88 DQ59 134 CB4 180 VDD 43 A1 89 VSS 135 CB5 181 SAO 44 CBO 90 NC 136 VDD 182 SA1 45 CB1 91 SDA 137 CKO 183 SA2 46 VDD 92 SCL 138 CKO 184 VDDSPD Data Sheet E0377E20 Ver 2 0 ELPIDA Pin Description EBD51RC4AKFA Pin name Function Address input A0 to A12 Row address AO to A12 Column address AO to AQ A11 BAO BA1 Bank select address DQO to DQ63 Data input output CBO to CB7 Check bit Data input output RAS Row address strobe command ICAS Column address strobe command IWE Write enable CSO Chip select CKEO Clock enable CKO Clock input CKO Differential clock input DQSO to DQS8 Input and output data strobe DMO to DM8 DQS9 to DQS17 Input and output data strobe SCL Clock input for serial PD SDA Data input output for serial PD SAO to SA2 Serial address input VDD Power for internal circuit VDDSPD Power for serial EEPROM VREF Input reference voltage VSS Ground VDDID VDD identification flag RESET Reset pin forces register inputs low NC No connection Data Sheet E0377E20 Ver 2 0 ELPIDA EBD51RC4AKFA Serial PD Matrix Byte No Function described Bit7 Bit6 Bits Bit4 Bits Bit2 Biti1 BitO Hexvalue Comments 0 Number of bytes utilized by module 1 0 0 0 0 0 0 0 80H 128 manufacturer 1 Total number of bytes in serial PD 0 0 0 0 1 0 0 0 08H 256 by
7. B 1 0 1 0 0 0 0 0 AOH Maximum data access time tAC from 24 clock at CLX 0 5 0 1 1 1 0 0 0 0 70H 0 70ns 6B 7A 7B 0 1 1 1 0 1 0 1 75H 0 75ns 25 Minimum clock cycle time at CLX 1 0 0 0 0 0 0 0 0 00H Maximum data access time tAC from clock at CLX 1 o 0 0 0 0 0 O 0 00H 27 W a row precharge time tRP 0 1 0 o i A 6 F ai PANG 7A 7B 0 1 0 1 0 0 0 0 50H 20ns ELPIDA Data Sheet E0377E20 Ver 2 0 EBD51RC4AKFA Byte No Function described Bit7 Bit Bits Bit4 Bits Bit2 Bit1 Bito Hexvalue Comments Minimum row active to row active 28 delay tRRD 0 0 1 1 0 0 0 0 30H 12ns 6B 7A 7B 0 0 1 1 1 1 0 0 3CH 15ns 29 ee RAS to CAS delay tRCD 0 1 0 0 1 0 0 0 48H 18ns 7A 7B 0 1 0 1 0 0 0 0 50H 20ns Minimum active to precharge time 30 tRAS 0 0 1 0 1 0 1 0 2AH 42ns 6B 7A 7B 0 0 1 0 1 1 0 1 2DH 45ns 3 1 rank 31 Module rank density 1 0 0 0 0 0 0 0 80H 512MB Address and command setup time 32 before clock tIS 0 1 1 1 0 1 0 1 75H 0 75ns 6B 7A 7B 1 0 0 1 0 0 0 0 90H 0 9ns Address and command hold time after 33 clock tIH 0 1 1 1 0 1 0 1 75H 0 75ns 6B 7A 7B 1 0 0 1 0 0 0 0 90H 0 9ns Data input setup time before clock 34 tDS 0 1 0 0 0 1 0 1 45H 0 45ns 6B 7A 7B 0 1 0 1 0 0 0 0 50H 0 5ns 35 S hold time after clock tDH 0 1 0 0 0 1 0 1 45H 0 45ns 7A 7B 0 1 0 1 0 0 0 0 50H 0 5ns
8. ELPIDA 2574 EBD 51RC4A KFA V S DATA SHEET 512MB Registered DDR SDRAM DIMM EBD51RC4AKFA 64M words x 72 bits 1 Rank Description The EBD51RC4AKFA is a 64M words x 72 bits 1 rank Double Data Rate DDR SDRAM Module mounting 18 pieces of DDR SDRAM sealed in TSOP package Read and write operations are performed at the cross points of the CK and the CK This high speed data transfer is realized by the 2 bit prefetch pipelined architecture Data strobe DQS both for read and write are available for high speed and reliable data bus design By setting extended mode register the on chip Delay Locked Loop DLL can be set enable or disable This module provides high density mounting without utilizing surface mount technology Decoupling capacitors are mounted beside each TSOP on the module board Document No E0377E20 Ver 2 0 Date Published January 2004 K Japan URL http www elpida com Features e 184 pin socket type dual in line memory module DIMM PCB height 30 48mm Lead pitch 1 27mm e 2 5V power supply e Data rate 333Mbps 266Mbps max e 2 5 V SSTL_2 compatible I O e Double Data Rate architecture two data transfers per clock cycle e Bi directional data strobe DQS is transmitted received with data to be used in capturing data at the receiver e Data inputs and outputs are synchronized with DQS e 4 internal banks for concurrent operation Component e DQS is edge aligned with data
9. ON FOR HANDLING MEMORY MODULES When handling or inserting memory modules be sure not to touch any components on the modules such as the memory ICs chip capacitors and chip resistors It is necessary to avoid undue mechanical stress on these components to prevent damaging them In particular do not push module cover or drop the modules in order to protect from mechanical defects which would be electrical defects When re packing memory modules be sure the modules are not touching each other Modules in contact with other modules may cause excessive mechanical stress which may damage the modules MDE0202 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when once it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity MOS devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap MOS devices must not be touched with bare hands Similar precautions need to be taken for
10. S export control regulations or another country s export control laws or regulations you must follow the necessary procedures in accordance with such laws or regulations If these products technology are sold leased or transferred to a third party or a third party is granted license to use these products that third party must be made aware that they are responsible for compliance with the relevant laws and regulations MO1E0107 ELPIDA Data Sheet E0377E20 Ver 2 0 19
11. ameters are measured Otherwise absolute minimum values of these values are 10 of tCK 12 VDD is assumed to be 2 5V 0 2V VDD power supply variation per cycle expected to be less than 0 4V 400 cycle 13 tDAL tWR tCK tRP tCk For each of the terms above if not already an integer round to the next highest integer Example For 7A Speed at CL 2 5 tCK 7 5ns tWR 15ns and tRP 20ns tDAL 15ns 7 5ns 20ns 7 5ns 2 3 tDAL 5 clocks ELPIDA Data Sheet E0377E20 Ver 2 0 13 EBD51RC4AKFA Timing Parameter Measured in Clock Cycle for Registered DIMM Number of clock cycle tCK 6ns 7 5ns Parameter Symbol min max min max Unit Write to pre charge command delay WPD 4 BL 2 3 BL 2 pa tek same bank Read to pre charge command delay tRPD BL 2 Ko BL 2 tek same bank Write to read command delay to input WRD 2 4BL 2 2 4 BL 2 CK all data Burst stop command to write command delay tBSTW 2 tCK CL 3 CL 3 5 tBSTW 3 3 tCK Burst stop command to DQ High Z IBSTZ pa 3 3 CK CL 3 CL 3 5 tBSTZ 3 5 3 5 3 5 3 5 tCK Read command to write command delay to output all data tRWD 2 BL 2 tCK CL 3 CL 3 5 tRWD 3 BL 2 3 BL 2 tCK Pre charge command to High Z CL 3 tHZP 3 3 tCK CL 3 5 tHZP 3 5 3 5 3 5 3 5 tCK Write command to data in latency tWCD 2 2 2 2 tCK Write reco
12. d for switching VIH CK min assumed over VREF 0 18V VIL CK max assumed under VREF 0 18V ELPIDA DC Characteristics 1 TA 0 to 70 C VDD 2 5V 0 2V VSS OV EBD51RC4AKFA Parameter Symbol Grade max Unit Test condition Notes i 6B 2190 CKE 2 VIH Operating current ACTV PRE IDDO 7A 7B 2010 mA tRC tRC min 1 2 9 Operating current IDD1 6B 2640 mA CKE 2 VIH BL 4 125 ACTV READ PRE 7A 7B 2370 CL 3 5 tRC tRC min Idle power down standby current DD2P 444 mA CKE lt VIL 4 ae 6B 840 CKE 2 VIH CS 2 VIH Floating idle standby current IDD2F 7A 7B 750 mA DQ DQS DM VREF 4 5 Ha 6B 750 CKE 2 VIH CS 2 VIH Quiet idle standby current IDD2Q 7A 7B 714 mA DQ DOS DM VREF 4 10 Active power down standby 6B 750 irent IDD3P 7A 7B 714 mA CKE lt VIL 3 3 6B 1380 CKE 2 VIH CS 2 VIH Active standby current IDD3N 7A 7B 1290 mA IRAS tRAS max 3 5 6 Operating current 6B 3450 CKE 2 VIH BL 2 Burst read operation DDIR 7A 7B 3090 mA CL 3 5 Won Operating current 6B 3630 CKE 2 VIH BL 2 Burst write operation IDDAW 7A 7B 3270 mA CL 3 5 T2928 6B 3450 tRFC tRFC min Auto refresh current IDD5 TA 7B 3360 mA Input lt VIL or VIH Input 2 VDD 0 2 V Self refresh current IDD6 444 mA Input lt 0 2 V Operating current 6B 6150 a 4 banks interleaving IDDIA 7A 7B 5250 ma BEEd ki Notes 1 These IDD data are measured under conditio
13. e V pa D10 Rs Rs DQAS2 e ANN DM2 DOS11e AAA 1 4 Rs DOS CS DM 4 Rs DQS CS DM DQ16 to DA19e 7 MMN Ipa D2 DQ20 to DA23e Y AMN Ipo D11 Rs Rs DQS3e DM3 DQS12 e ANN 4 Rs DQS CS DM 4 Rs DQS CS DM DQ24 to DQ27e f AW ipa D3 DQ28 to DQ31e AW ADa D12 Rs Rs DOAS4e AM DM4 DOS13e ANA 1 4 Rs DQS CS DM 4 Rs DQS CS DM DQ32 to DQ35e VW pq D4 DQ36 to DQ39e Wg D13 Rs Rs DQS5e _ DM5 DQS14 e ANA 4 Rs DQS CS DM 4 Rs DQS CS DM DQ40 to DA43e WV pq D5 DQ44 toDM47e W pq D14 Rs Rs DOS6e AAA DM6 DQS158 ANA 1 4 Rs DQS CS DM 4 Rs DQS CS DM DQ48 to DAS1e V W pq D6 DQ52 to DA55eZ AMA pa D15 Rs Rs DQS7 e ANA DM7 DQS16e ANN 4 Rs DQS CS DM 4 Rs DQS CS DM DQ56 to DASSe AVWA pa D7 DQ60 to DOE3e AMA poa D16 Rs Rs DQS8 e ANA DM8 DQS17e _ 4 Rs DQS CS DM 4 Rs DQS CS DM CBO to CB3e pq D8 CB4 to CB7e AM Ipo D17 Rs CSO F RCSO gt CS SDRAMs DO to D17 z Rs R DO to D17 256M bits DDR SDRAM BAO to BAT V E RBA0 to RBA1 gt BAO to BAI SDRAMs DO to D17 U0 2k bits EEPROM A0 to A12 AVWA G RAOtoRA12 s A0 to A12 SDRAMs DO to D17 Rs 220 Rs l i PLL CDCV857 et ARAS gt IRAS SDRAMS DO to D17 Register SSTV16857 CAS 4 T E RCAS gt CAS SDRAMs DO to D17 CKEO W z It RCKEOA gt CKE SDRAMs DO to D17 Serial PD ME AW H RWE gt WE SDRAMs DO to D17 SDA PCK RESET PCK VDD e D0 to D17 VREF DO to D17 VSS DO to D17 VDDID o open CKO
14. e part number 0 0 1 1 0 1 0 0 34H 4 81 Module part number 0 1 0 0 0 0 0 1 41H A 82 Module part number 0 1 0 0 1 0 1 1 4BH K 83 Module part number 0 1 0 0 0 1 1 0 46H F 84 Module part number 0 1 0 0 0 0 0 1 41H A 85 Module part number 0 0 1 0 1 A 0 1 2DH 86 ko partnumber O oOo 4 4 0 A 4 0 36H 6 7A 7B 0 0 1 1 0 1 1 1 37H 7 a ayo part number 0 1 o 0 0 0 0 1 41H A 6B 7B 0 1 0 0 0 1 0 42H B 88 to 90 Module part number 0 0 1 0 0 0 0 0 20H Space 91 Revision code 0 0 1 1 0 0 0 0 30H Initial 92 Revision code 0 0 1 0 0 0 0 0 20H Space 93 Manufacturing date x x x x x x x x xx e ii 94 Manufacturing date x x x x x x x x xx pwan code 95 to 98 Module serial number 2 99to127 Manufacturer specific data Notes 1 All serial PD data are not protected 0 Serial data driven Low 1 Serial data driven High 2 Bytes 95 through 98 are assembly serial number 3 These specifications are defined based on component specification not module ELPIDA Data Sheet E0377E20 Ver 2 0 Block Diagram EBD51RC4AKFA VSS e hd RCSO Rs Rs DQS0e ANA DMO DQS9 e AA NA 4 Rs DQS CS DM 4 Rs DQS CS DM DQO to DABB epa DO DQ4 to DA7e 3 NM Ipna D9 Rs Rs DQS1e ANN DM1 DQS10 e AAA 4 Rs DQS CS DM 4 Rs DQS CS DM DQ8 to DQ11 AVA opa D1 DQ12 to DQ15
15. ent for life support or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury Product usage Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory Inc including the maximum ratings operating supply voltage range heat radiation characteristics installation conditions and other related characteristics Elpida Memory Inc bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions Even within the guaranteed ranges and conditions consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail safes so that the equipment incorporating Elpida Memory Inc products does not cause bodily injury fire or other consequential damage due to the operation of the Elpida Memory Inc product Usage environment This product is not designed to be resistant to electromagnetic waves or radiation This product must be used in a non condensing environment If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan Also if you export products technology controlled by U
16. for READs center aligned with data for WRITEs e Differential clock inputs CK and CK e DLL aligns DQ and DQS transitions with CK transitions e Commands entered on each positive CK edge data referenced to both edges of DQS e Auto precharge option for each burst access e Programmable burst length 2 4 8 e Programmable CAS latency CL 2 2 5 e Refresh cycles 8192 refresh cycles 64ms 7 8us maximum average periodic refresh interval e 2 variations of refresh Auto refresh Self refresh e 1 piece of PLL clock driver 2 pieces of register drivers and 1 piece of serial EEPROM 2k bits EEPROM for Presence Detect PD Elpida Memory Inc 2003 2004 EBD51RC4AKFA Ordering Information Component Data rate JEDEC speed bin Contact Part number Mbps max CL tRCD tRP Package pad Mounted devices EBD51RC4AKFA 6B 333 DDR333B 2 5 3 3 184 pin DIMM Gold EDD2504AKTA 6B EBD51RC4AKFA 7A 266 DDR266A 2 3 3 EDD2504AKTA 6B 7A EBD51RC4AKFA 7B DDR266B 2 5 3 3 EDD2504AKTA 6B 7A 7B Notes 1 Module CAS latency component CL 1 Pin Configurations 5 Front side d 1 pin 52 pin53 pin 92 pin fo ts eee eee pee Lo o a RAN AAA soo o 93 pin 144 pin 145 pin 184 pin l Back side o Pin No Pin name Pin No Pin name Pin No Pin name Pin No Pin name 1 VREF 47
17. he CK rising edge and the VREF level in a read or a write command cycle This column address becomes the starting address of a burst operation A10 AP input pin A10 defines the precharge mode when a precharge command a read command or a write command is issued If A10 high when a precharge command is issued all banks are precharged If A10 low when a precharge command is issued only the bank that is selected by BA1 BAO is precharged If A10 high when read or write command auto precharge function is enabled While A10 low auto precharge function is disabled BAO BA1 input pin BAO BAT are bank select signals BA The memory array is divided into bank 0 bank 1 bank 2 and bank 3 See Bank Select Signal Table Bank Select Signal Table BAO BA1 Bank 0 L L Bank 1 H L Bank 2 L H Bank 3 H H Remark H VIH L VIL CKE input pin CKE controls power down and self refresh The power down and the self refresh commands are entered when the CKE is driven low and exited when it resumes to high The CKE level must be kept for 1 CK cycle at least that is if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS at the next CK rising edge CKE level must be kept with proper hold time tIH DQ CB input and output pins Data are input to and output from these pins DQS input and output pin DQS provide the read data strobes as output and the write data strobes as in
18. he latest version No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory Inc Elpida Memory Inc does not assume any liability for infringement of any intellectual property rights including but not limited to patents copyrights and circuit layout licenses of Elpida Memory Inc or third parties by or arising from the use of the products or information listed in this document No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of Elpida Memory Inc or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of the customer s equipment shall be done under the full responsibility of the customer Elpida Memory Inc assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information Product applications Elpida Memory Inc makes every attempt to ensure that its products are of high quality and reliability However users are instructed to contact Elpida Memory s sales office before using the product in aerospace aeronautics nuclear power combustion control transportation traffic safety equipment medical equipm
19. lse width tDQSH 0 35 0 35 0 35 tCK DQS input low pulse width tDQSL 0 35 0 35 0 35 tCK Address and control input setup time tIS 0 75 0 9 0 9 ns 8 Address and control input hold time tlH 0 75 0 9 0 9 ns 8 ELPIDA Data Sheet E0377E20 Ver 2 0 12 EBD51RC4AKFA 6B TA 7B Parameter Symbol min max min max min max Unit Notes Address and control input pulse width tIPW 2 2 22 2 2 ns 7 Mode register set command cycle time tMRD 2 2 2 tCK Active to Precharge command period tRAS 42 120000 45 120000 45 120000 ns Active to Active Auto refresh command tRC 60 65 NG 65 os mel period Auto refresh to Active Auto refresh REC 72 75 75 ma pag command period Active to Read Write delay tRCD 18 20 20 ns Precharge to active command period tRP 18 20 20 ns Active to auto precharge delay tRAP tRCD min tRCD min tRCD min ns Active to active command period tRRD 12 15 15 ns Write recovery time tWR 15 15 15 ns Auto precharge write recovery and DAL tWRI tCK IWRACK tWR tCK tCk 13 precharge time IRPACK tRP tCK tRP tCK Internal write to Read command delay tWTR 1 1 1 tCK Average periodic refresh interval tREF 7 8 7 8 7 8 us Notes 1 All the AC parameters listed in this data sheet is component specifications For AC testing conditions refer to the corresp
20. n that DQ pins are not connected 2 One bank operation 3 One bank active 4 All banks idle 5 Command Address transition once per one cycle 6 DQ DM and DOS transition twice per one cycle 7 4 banks active Only one bank is running at tRC tRC min 8 The IDD data on this table are measured with regard to tCK tCK min in general 9 Command Address transition once every two clock cycles 10 Command Address stable at 2 VIH or s VIL DC Characteristics 2 TA 0 to 70 C VDD VDDQ 2 5V 0 2V VSS OV DDR SDRAM component Specification Parameter Symbol min max Unit Test condition Notes Input leakage current ILI 2 2 yA VDD 2 VIN2 VSS Output leakage current ILO 5 5 KA VDDQ 2 VOUT 2 VSS Output high current IOH 15 2 mA VOUT 1 95V Output low current IOL 15 2 mA VOUT 0 35V Data Sheet E0377E20 Ver 2 0 11 ELPIDA EBD51RC4AKFA Pin Capacitance TA 25 C VDD 2 5V 0 2V Parameter Symbol Pins max Unit Notes Address RAS CAS WE Input capacitance CI1 ICS CKE 15 pF 1 3 Input capacitance CI2 CK CK 20 pF 1 3 Data and DQS input output co DQ DOS CB 15 pF 1 2 3 capacitance Notes 1 These parameters are measured on conditions f 100MHz VOUT VDDQ 2 AVOUT 0 2V 2 Dout circuits are disabled 3 This parameter is sampled and not 100 tested AC Characteristics TA 0 to 70 C VDD VDDQ 2 5V 0 2V VSS OV DDR SDRAM component Specification
21. o 125 C Note 1 Caution DDR SDRAM component specification Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability DC Operating Conditions TA 0 to 70 C DDR SDRAM Component Specification Parameter Symbol min typ max Unit Notes Supply voltage VDD VDDQ 2 3 2 5 2 7 v 1 VSS 0 0 0 V Input reference voltage VREF 0 49 x VDDQ 0 50 x VDDQ 0 51 x VDDQ vV Termination voltage VTT VREF 0 04 VREF VREF 0 04 V Input high voltage VIH DC VREF 0 15 VDDQ 0 3 V 2 Input low voltage VIL DC 0 3 VREF 0 15 V 3 ee antec ia VIN DC 0 3 VDDQ 0 3 Vv 4 sie bi one VIX DC 0 5xVDDQ 0 2V 05xVDDQ 0 5xVDDQ 0 2V V Input differential voltage VID DC 0 36 VDDQ 0 6 v 5 6 CK and CK inputs Notes 1 VDDQ must be lower than or equal to VDD 2 VIH is allowed to exceed VDD up to 3 6V for the period shorter than or equal to 5ns DQ A it ifmeasurement Data Sheet E0377E20 Ver 2 0 10 VIL is allowed to outreach below VSS down to 1 0V for the period shorter than or equal to 5ns VIN DC specifies the allowable DC execution of each differential input VID DC specifies the input differential voltage require
22. onding component data sheet 2 This parameter defines the signal transition delay from the cross point of CK and CK The signal transition is defined to occur when the signal level crossing VTT 3 The timing reference level is VTT 4 Output valid window is defined to be the period between two successive transition of data out or DQS read signals The signal transition is defined to occur when the signal level crossing VTT 5 tHZ is defined as DOUT transition delay from Low Z to High Z at the end of read burst operation The timing reference is cross point of CK and CK This parameter is not referred to a specific DOUT voltage level but specify when the device output stops driving 6 tLZ is defined as DOUT transition delay from High Z to Low Z at the beginning of read operation This parameter is not referred to a specific DOUT voltage level but specify when the device output begins driving 7 Input valid windows is defined to be the period between two successive transition of data input or DQS write signals The signal transition is defined to occur when the signal level crossing VREF 8 The timing reference level is VREF 9 The transition from Low Z to High Z is defined to occur when the device output stops driving A specific reference voltage to judge this transition is not given 10 tCK max is determined by the lock range of the DLL Beyond this lock range the DLL operation is not assured 11 tCK tCK min when these par
23. put ELPIDA Data Sheet E0377E20 Ver 2 0 15 EBD51RC4AKFA VDD power supply pins 2 5V is applied VDD is for the internal circuit VDDSPD power supply pin 2 5V is applied For serial EEPROM VSS power supply pin Ground is connected RESET input pin LVCMOS reset input When RESET is low all registers are reset and all outputs are low Detailed Operation Part and Timing Waveforms Refer to the EDD2504AKTA datasheet E0457E DM pins of component device fixed to VSS level on the module board DIMM CAS latency component CL 1 for registered type ELPIDA Data Sheet E0377E20 Ver 2 0 16 EBD51RC4AKFA Physical Outline Unit mm 128 95 kag 4 00 max 64 48 DATUM A a gt V L Component area Front d NG N ll i 1 EMAN nyon 92 P B A 64 77 E 49 53 1 27 0 10 z ti 133 35 0 15 rat 2 6 2 50 0 10 sa KE U ooo oo oo om 84 O si AS po la 30 48 0 15 e o H o o R 2 00 Detail A Detail B DATUM A X NON A 27 typ a m LI o KO 2 175 L i ai SS po R090 gs S een DODOD 1 Li 6 35 A 2 gt rag 1 00 0 05 o Lu 1 80 0 10 T Note Tolerance on all dimensions 0 13 unless otherwise specified ECA TS2 0050 01 ELPIDA Data Sheet E0377E20 Ver 2 0 17 EBD51RC4AKFA CAUTI
24. te device 2 Memory type 0 0 0 0 0 1 1 1 07H SDRAM DDR 3 Number of row address 0 0 0 0 1 1 0 1 ODH 13 4 Number of column address 0 0 0 0 1 0 1 1 OBH 11 5 Number of DIMM ranks 0 0 0 0 0 0 0 1 01H 1 6 Module data width 0 1 0 0 1 0 0 0 48H 72 bits 7 Module data width continuation 0 0 0 0 0 0 0 OOH 0 8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H SSTL 2 5V 9 ge ai cycle time CL X 0 1 1 0 0 0 0 0 60H CL 2 54 7A 7B 0 1 1 1 0 1 0 1 75H 10 eae access from clock tAC 0 1 1 1 0 0 0 0 70H 0 70ns 7A 7B 0 1 1 1 0 1 0 1 75H 0 75ns 11 DIMM configuration type 0 0 0 0 0 0 1 0 02H ECC 7 8 us 12 Refresh rate type 1 0 0 0 0 0 1 0 82H Self refresh 13 Primary SDRAM width 0 0 0 0 0 1 0 0 04H x4 14 Error checking SDRAM width 0 0 0 0 0 1 0 0 04H x4 SDRAM device attributes 15 Minimum clock delay back to back 0 0 0 0 0 0 0 1 01H 1 CLK column access 16 SDRAM device attributes 0 0 0 0 1 1 1 0 OEH 2 4 8 Burst length supported SDRAM device attributes Number of 1 banks on SDRAM device 0 9 bi o o i g ji ka ai SDRAM device attributes 18 ICAS latency 0 0 0 0 1 1 0 0 OCH 2 2 5 SDRAM device attributes 19 ICS latency 0 0 0 0 0 0 0 1 01H 0 20 SDRAM device attributes 0 0 0 0 0 0 1 0 02H 4 WE latency 21 SDRAM module attributes 0 0 1 0 0 1 1 0 26H Registered 22 SDRAM device attributes General 1 1 0 0 0 0 0 0 COH 0 2V Minimum clock cycle time at CLX 0 5 be 6B 7A 0 1 1 1 0 1 0 1 75H sisi 7
25. very tWR 2 1 tCK Register set command to active or MRD 2 2 tek register set command Self refresh exit to non read command tSNR 12 10 tCK Self refresh exit to read command tSRD 200 200 tCK Power down entry tPDEN 1 1 1 1 tCK Power down exit to command input tPDEX 1 1 tCK ELPIDA Data Sheet E0377E20 Ver 2 0 14 EBD51RC4AKFA Pin Functions CK CK input pin The CK and the CK are the master clock inputs All inputs except DMs DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level When a read operation DQSs and DQs are referred to the cross point of the CK and the CK When a write operation DMs and DQs are referred to the cross point of the DQS and the VREF level DQSs for write operation are referred to the cross point of the CK and the CK CS input pin When CS is low commands and data can be input When CS is high all inputs are ignored However internal operations bank active burst operations etc are held RAS CAS and WE input pins These pins define operating commands read write etc depending on the combinations of their voltage levels See Command operation A0 to A12 input pins Row address AXO to AX12 is determined by the AO to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle Column address AYO to AY9 AY11 is loaded via the AO to the A9 and the A11 at the cross point of t
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ELPIDA EBD51RC4AKFA 512MB Registered DDR SDRAM DIMM handbook