ST L6919E handbook
Contents
1. LAYOUT GUIDELINES Since the device manages control functions and high current drivers layout is one of the most important things 20 33 L6919E to consider when designing such high current applications A good layout solution can generate a benefit in lowering power dissipation on the power paths reducing radi ation and a proper connection between signal and power ground can optimize the performance of the control loops Integrated power drivers reduce components count and interconnections between control functions and drivers reducing the board space Here below are listed the main points to focus on when starting a new layout and rules are suggested for a cor rect implementation m Power Connections These are the connections where switching and continuous current flows from the input supply towards the load The first priority when placing components has to be reserved to this power section minimizing the length of each connection as much as possible To minimize noise and voltage spikes EMI and losses these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces The critical components i e the power transistors must be located as close as possible together and to the controller Considering that the electrical components reported in figure are composed by more than one physical com ponent a ground plane or star grounding connection is suggested to minimize2. 16019 L6919E 5 BIT PROGRAMMABLE DUAL PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENT m 2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL m ULTRA FAST LOAD TRANSIENT RESPONSE m INTEGRATED HIGH CURRENT GATE DRIVERS UP TO 2A GATE CURRENT TTL COMPATIBLE 5 BIT PROGRAMMABLE OUTPUT FROM 0 800V TO 1 550V WITH 25mV STEPS DYNAMIC VID MANAGEMENT 0 6 OUTPUT VOLTAGE ACCURACY 10 ACTIVE CURRENT SHARING ACCURACY DIGITAL 2048 STEP SOFT START OVERVOLTAGE PROTECTION OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET S Rason OR A SENSE RESISTOR m OSCILLATOR EXTERNALLY ADJUSTABLE AND INTERNALLY FIXED AT 200kHz m POWER GOOD OUTPUT AND INHIBIT FUNCTION m REMOTE SENSE BUFFER m PACKAGE SO 28 APPLICATIONS m POWER SUPPLY FOR SERVERS AND WORKSTATIONS m POWER SUPPLY FOR HIGH CURRENT MICROPROCESSORS DISTRIBUTED POWER SUPPLY BLOCK DIAGRAM OSC INH 2 PHASE OSCILLATOR SO 28 ORDERING NUMBERS L6919E L6919ETR DESCRIPTION The device is a power supply controller specifically designed to provide a high performance DC DC conversion for high current microprocessors The device implements a dual phase step down con troller with a 180 phase shift between each phase A precise 5 bit digital to analog converter DAC allows adjusting the output voltage from 0 800V to 1 550V with 25mV binary steps manag ing On The Fly VID code changes The high precision internal reference assures
3. 1 current sense pin The output current may be sensed across a sense resistor or across the low side mosfet Rason This pin has to be connected to the low side mosfet drain or to the sense resistor through a resistor Rg F Remote sense buffer non inverting input It has to be connected to the positive side of the load to perform a remote sense If no remote sense is implemented connect directly to the output voltage in this case connect also the VSEN pin directly to the output regulated voltage E The net connecting the pin to the sense point must be routed as close as possible to the PGNDS net in order to couple in common mode any picked up noise za A noise PGNDS2 Channel 2 Power Ground sense pin The net connecting the pin to the sense point must be routed as close as possible to the ISEN2 net in order to couple in common mode any picked up noise ISEN2 Channel 2 current sense pin The output current may be sensed across a sense resistor or across the low side mosfet Rason This pin has to be connected to the low side mosfet drain or PGNDS1 Channel 1 Power Ground sense pin The net connecting the pin to the sense point must be routed as close as possible to the ISEN1 net in order to couple in common mode any picked up 1 m E to the sense resistor through a resistor Rg The net connecting the pin to the sense point must be routed as close as possible to the PGNDS net in order to couple in common mode any picked up
4. 12V 15 Ty 0 to 70 C unless otherwise specified Vcc SUPPLY CURRENT lcc Vcc supply current HGATEx and LGATEx open 7 5 10 12 5 mA Vccpn VaBoor 12V Boot supply current HGATEx open PHASEx to PGND 0 5 1 1 5 mA Vcc Vagoor 12V POWER ON Turn Off Vcc threshold Vcc Falling Vocpr 5V Turn On Veepr Rising 4 2 4 4 4 6 V Threshold Voc 12V Turn Off Vccpn Veepr Falling 4 0 4 2 4 4 V Threshold Vcc212V OSCILLATOR INHIBIT FAULT OSC OPEN Tj 0 C to 125 C INH Inhibit threshold pem pw Iw 5 we FAULT Voltage at pin OSC OVP or UVP Active REFERENCE AND DAC Output Voltage VIDO VID1 VID2 VID3 VID4 Accuracy see Table1 FBR Vout FBG GND Ipac VID pull up Current VIDx GND VID pull up Voltage VIDx OPEN ERROR AMPLIFIER Bm SR Slew Rate COMP 10pF ss DIFFERENTIAL AMPLIFIER REMOTE BUFFER CMRR Common Mode Rejection Ratio 6 SR Slew Rate VSEN 10pF 3 33 L6919E ELECTRICAL CHARACTERISTICS continued Voc 12V 15 Ty 0 to 70 C unless otherwise specified DIFFERENTIAL CURRENT SENSING 1 Bias Current ILOAD 0 45 50 55 uA IISEN2 1 Bias Current at 85 uA Iisen2 Over Current Threshold IFB Active Droop Current 1 lt 0 0 1 uA ILOAD 100 47 5 50 52 5 uA GATE DRIVERS trise High Side Vgoorx VPHASEx 10V 15 30 ns HGATE Rise Time CHGATEx to PHASEx 3 3nF lugArEx High
5. FB L 2 L L L Ro e g JEE O 2 s Co zts 5 95 00 ESR Considering now that in the application of interest it can be assumed that Ro gt gt R_ ESR lt lt Ro and RpnoopP Ro it results 4 Vin Zp s 1 s Co Rproopt ESR Gi oop S TER 5 AV R R ps P ca ges Co ESR Co 1 The ACM control loop gain is designed to obtain a high DC gain to minimize static error and cross the OdB axes with a constant 20dB dec slope with the desired crossover frequency wt Neglecting the effect of Zr s the transfer function has one zero and two poles Both the poles are fixed once the output filter is designed and the zero is fixed by ESR and the Droop resistance To obtain the desired shape an Rr Cr series network is considered for the Ze s implementation A zero at Oor 1 ReCris then introduced together with an integrator This integrator minimizes the static error while placing the zero in correspondence with the L C resonance a simple 20dB dec shape of the gain is assured See Figure 15 In fact considering the usual value for the output filter the LC resonance results to be at frequency lower than the above reported zero Compensation network can be simply designed placing z e c and imposing the cross over frequency as desired obtaining Ren AV CoL Hic FB osc 5 L pe 2 0 6 ViN 4 T 2 Roroop ESR Figure 15 ACM Control Loop Gain Block Diagram left and Bode Diagram right Z s
6. HS driver supply This pin supplies the relative high side driver Connect through a capacitor 100nF typ to the PHASE1 pin and through a diode to VCC cathode vs boot Device supply voltage The operative supply voltage is 12V 10 Filter with 1uF Typ capacitor vs GND V 7 All the internal references are referred to this pin Connect it to the PCB signal ground COMP This pin is connected to the error amplifier output and is used to compensate the control feedback loop This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop A current proportional to the sum of the current sensed in both channel is sourced from this pin at full load 70pA at the Constant Current threshold Connecting a resistor between this pin and VSEN pin allows programming the droop effect VSEN Manages Over amp Under voltage conditions and the PGOOD signal It is internally connected with the output of the Remote Sense Buffer for Remote Sense of the regulated voltage If no Remote Sense is implemented connect it directly to the regulated voltage in order to manage OVP UVP and PGOOD CC ND FB Connecting 1nF capacitor max vs SGND can help in reducing noise injection BR BG E D F Remote sense buffer inverting input It has to be connected to the negative side of the load to perform a remote sense Pull down to ground if no remote sense is implemented ISEN1 Channel
7. Side VBooTx VPHASEx 10V 2 Source Current RHGaTex High Side VBoorx VPHASEx 12V 1 5 2 Sink Resistance trise Low Side Veepr 10V 30 55 ns LGATE Rise Time CLGATEx to PGNDx 5 6nF ILGATEx Low Side Veepr 10V Source Current RLGATEx Low Side Veepr 12V 0 7 1 1 Sink Resistance PROTECTIONS PGOOD Upper Threshold Vsen Rising 108 Vsen DAC Output PGOOD Lower Threshold Vsen Falling VsEN DAC Output OVP Over Voltage Threshold Vsen Rising VsEN UVP Under Voltage Trip Vsen Falling VsEN DAC Output IPGOODH PGOOD Leakage Vpgoop 5V 4 33 L6919E Table 1 Voltage Identification VID Codes Output Output VIDA VID3 VID2 VID1 VIDO Voltage V VID4 VID3 VID2 VID1 VIDO Voltage V ERR EEE The device automatically regulates 25mV higher than the Hammer specs avoiding the use of any external offset resistor Reference Schematic 5 33 L6919E PIN FUNCTION A EE 1 LGATE1 Channel 1 LS driver output A little series resistor helps in reducing device dissipated power 2 VCCDR LS drivers supply it can be varied from 5V to 12V buses Filter locally with at least 1uF ceramic cap vs PGND 3 PHASE1 Channel 1 HS driver return path It must be connected to the HS1 mosfet source and provides the return path for the HS driver of channel 1 4 UGATE1 Channel 1 HS driver output A little series resistor helps in reducing device dissipated power 5 BOOT1 Channel 1
8. at least 200ns to make proper reading of the delivered current This circuit sources a constant 50uA current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at the same voltage Referring to figure 4 the current that flows in the ISENx pin is then given by the following equation ISENx R l Ap 504A g 10 33 L6919E Figure 4 Current Reading Timing Left and Circuit Right LGATEX ISENX Total current information PGNDSX Track amp Hold Where Rsense is an external sense resistor or the rds on of the low side mosfet and Rg is the transconductance resistor used between ISENx and PGNDSx pins toward the reading points IpHase is the current carried by each phase and in particular the current measured in the middle of the oscillator period The current information reproduced internally is represented by the second term of the previous equation as follow Rsense PpHASE INFOx Since the current is read in differential mode also negative current information is kept this allow the device to check for dangerous returning current between the two phases assuring the complete equalization between the phase s currents From the current information of each phase information about the total current delivered lFB liNFO1 iNFO2 and the average current for each phase lava liNFo1 lINFO2 2 is taken IiNFox is then com pared to lavato give the correction to the PWM outpu
9. compensation network between FB and COMP has always a capacitor in series See fig 8 The voltage regulated is then equal to Vout Vip Res Since Irg depends on the current information about the two phases the output characteristic vs load current is given by R SENSE Vout lout TA 13 33 L6919E Figure 7 Output transient response without a and with b the droop function ESR DROP ESR DROP VpROOP Total Current Info linFo1 linFo2 Ref The feedback current is equal to 50uA at nominal full load IINFO1 linFo2 and 70 at the OC intervention threshold so the maximum output voltage deviation is equal to AVFULL_POSITIVE_LOAD Rfg SOWA AVoc INTERVENTION RrB 70 Droop function is provided only for positive load if negative load is applied and then IinFox lt 0 no current is sunk from the FB pin The device regulates at the voltage programmed by the VID REMOTE VOLTAGE SENSE A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without any additional external components In this way the output voltage programmed is regulated between the re mote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM module The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG FBR is for the regulated voltage sense while FBG is for the g
10. effects due to multiple connec tions Figure 16 Power connections and related connections layout guidelines same for both phases b PCB small signal components placement Fig 16a shows the details of the power connections involved and the current loops The input capacitance Cin TA 21 33 L6919E or at least a portion of the total capacitance needed has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces Low ESR and ESL capacitors are required Power Connections Related Fig 16b shows some small signal components placement and how and where to mix signal and power ground planes The distance from drivers and mosfet gates should be reduced as much as possible Propagation delay times as well as for the voltage spikes generated by the distributed inductance along the copper traces are so minimized In fact the further the mosfet is from the device the longer is the interconnecting gate trace and as a conse quence the higher are the voltage spikes corresponding to the gate PWM rising and falling signals Even if these spikes are clamped by inherent internal diodes propagation delays noise and potential causes of insta bilities are introduced jeopardizing good system behavior One important consequence is that the switching losses for the high side mosfet are significantly increased For this reason it is suggested to have the device oriented with the driv
11. its current from initial to final value Since the inductor has not finished its charging time the output current is supplied by the output capacitors Minimizing the response time can minimize the output capacitance required The response time to a load transient is different for the application or the removal of the load if during the ap plication of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage during the removal it is discharged only by the output voltage The following expressions give approx imate response time for Al load transient in case of enough fast compensation network response L Al _ L AI ee v Vin Your The worst condition depends on the input voltage available and the output voltage selected Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the max imum input voltage available tapplication 17 33 L6919E Figure 12 Inductor ripple current vs Vout L 1 5uH Vin 12V L 3uH Vin 12V 2 a LE 9 o L 3uH Vin 5V O AAD O 1 5 2 5 Output Voltage V MAIN CONTROL LOOP The control loop is composed by the Current Sharing control loop and the Average Current Mode control loop Each loop gives with a proper gain the correction to the PWM in order to minimize the error in its regulation the Current Sharing contr
12. noise 6 33 L6919E PIN FUNCTION continued wm 17 OSC INH Oscillator pin FAULT It allows programming the switching frequency of each channel the equivalent switching frequency at the load side results in being doubled Internally fixed at 1 24V the frequency is varied proportionally to the current sunk forced from into the pin with an internal gain of 6kHz uA See relevant section for details If the pin is not connected the switching frequency is 150kHz for each channel 300kHz on the load The pin is forced high 5V Typ when an Over Under Voltage is detected to recover from this condition cycle VCC Forcing the pin to a voltage lower than 0 6V the device stop operation and enter the inhibit state 18 22 VID4 0 Voltage IDentification pins Internally pulled up connect to GND to program a 0 while leave floating to program a 1 They are used to program the output voltage as specified in Table 1 and to set the PGOOD OVP and UVP thresholds The device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of any external set up resistor specified thresholds and during soft start It cannot be pulled up above 5V If not used may be left floating 24 2 Channel 2 HS driver supply This pin supplies the relative high side driver Connect through a capacitor 100nF typ to the PHASE2 pin and through a diode to VCC cathode vs boot 25 UGATE2 Channel 2 HS
13. starts monitoring VID after the transition has finished PGOOD signal is masked dur ing the transition and it is re activated after the transition has finished while OVP UVP are still active Figure 2 Dynamic VID transition Reference 25mV steps transition 1 Clock Cycle Blanking Time DRIVER SECTION The integrated high current drivers allow using different types of power MOS also multiple MOS to reduce the RasoN maintaining fast switching transition The drivers for the high side mosfets use BOOTx pins for supply and PHASEx pins for return The drivers for the low side mosfets use VCCDRV pin for supply and PGND pin for return A minimum voltage of 4 6V at VC pin is required to start operations of the device The controller embodies a sophisticated anti shoot through system to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes The dead time is reduced to few nanosec onds assuring that high side and low side mosfets are never switched on simultaneously when the high side mosfet turns off the voltage on its source begins to fall when the voltage reaches 2V the low side mosfet gate drive is applied with 30ns delay When the low side mosfet turns off the voltage at LGATEx pin is sensed When it drops below 1V the high side mosfet gate drive is applied with a delay of 30ns If the current flowing in the inductor is negative the source of high side mosfet wil
14. without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2003 STMicroelectronics All rights reserved STMicroelectronics GROUP OF COMPANIES Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www st com 33 33
15. 6 1 5k 196 SMD 0805 R7 1k 196 SMD 0805 H8 1 8k SMD 0805 R9 47k 1 SMD 0805 R10 510 SMD 0805 R11 82 SMD 0805 R12 to R19 0 SMD 0805 C1 Not Mounted SMD 0805 C2 10n SMD 0805 C3 C4 100n SMD 0805 C5 C6 C7 C8 1u Ceramic SMD 1206 C9 C10 10u or 22u 16V TDK Multilayer Ceramic SMD 1206 C11 to C13 1800u 16V Rubycon MBZ Radial 10x23 C14 to C18 2200u 6 3V Rubycon MBZ Radial 10x20 C24 100n SMD 0805 L1 L2 0 81 77121 4Turns U1 L6919E STMicroelectronics 028 Q1 Q1a Q3 Q3a SUB85N03 04P Vishay Siliconix D PACK Q2 Q4 SUB70N03 09BP Vishay Siliconix D PACK D1 D2 STPS340U STMicroelectronics SMB D3 D4 1N4148 STMicroelectronics SOT23 S0 S4 Short 51 52 53 STATIC PERFORMANCES Figure 28 shows the demo board measured efficiency versus load current in steady state conditions without air flow at ambient temperature Figure 28 System Efficiency 30 33 gt S 2 Output Current L6919E Figure 29 shows the mosfets temperature versus output current in steady state condition without any air flow or heat sink It can be observed that the mosfets are under 105 C in any conditions Load regulation is also re ported from 10A to 55A Figure 29 Mosfet Temperature and Load Regulation High side M OS Q2 D High side MOS Q4 X Low side MOS Q1 gt Low side MOS o o 3 z 5 a E o Ee o o z Output Current A Output Current A Figure 30 shows the syst
16. A while the sink current is 2A with VCCDR 12V CURRENT READING AND OVER CURRENT The current flowing trough each phase is read using the voltage drop across the low side mosfets Rason or across a sense resistor RsENsE and internally converted into a current The Tran conductance ratio is issued by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points The full differential current reading rejects noise and allows to place sensing element in different locations with out affecting the measurement s accuracy The current reading circuitry reads the current during the time in which the low side mosfet is on OFF Time During this time the reaction keeps the pin ISENx and PGNDSx atthe same voltage while during the time in which the reading circuitry is off an internal clamp keeps these two pins at the same voltage sinking from the ISENx pin the necessary current Needed if low side mosfet Rason sense is implemented to avoid absolute maximum rating overcome on ISENXx pin The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and negative current This circuit reproduces the current flowing through the sensing element using a high speed Track amp Hold Tran conductance amplifier In particular it reads the current during the second half of the OFF time reducing noise injection into the device due to the mosfet turn on See fig 4 Track time must be
17. cpx e 1 Vour Over current is set anyway when IinFox reaches 35uA Irg 70 The full load value is only a convention to work with convenient values for lFg Since the OCP intervention threshold is fixed to modify the percent age with respect to the load value it can be simply considered that for example to have on OCP threshold of 170 this will correspond to 5 lFB 70 The full load current will then correspond to liNFOx 20 6uA Irp 41 1 UA Torr Integrated Droop Function The device uses a droop function to satisfy the requirements of high performance microprocessors reducing the size and the cost of the output capacitor This method recovers part of the drop due to the output capacitor ESR in the load transient introducing a de pendence of the output voltage on the load current As shown in figure 7 the ESR drop is present in any case but using the droop function the total deviation of the output voltage is minimized In practice the droop function introduces a static error in figure 8 propor tional to the output current Since the device has an average current mode regulation the information about the total current delivered is used to implement the Droop Function This current equal to the sum of both IiNFox is sourced from the FB pin Connecting a resistor between this pin and Vour the total current information flows only in this resistor because the
18. d D 0 75 The power dissipated by the input capacitance is then equal to 2 Prams ESR pms Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle To reach the high RMS value needed by the CPU power supply application and also to minimize components cost the input capacitance is realized by more than one physical capacitor The equivalent RMS current is simply the sum of the single capacitor s RMS current Input bulk capacitor must be equally divided between high side drain mosfets and placed as close as possible 16 33 L6919E to reduce switching noise above all during load transient Ceramic capacitor can also introduce benefits in high frequency noise decoupling noise generated by parasitic components along power path OUTPUT CAPACITOR Since the microprocessors require a current variation beyond 50A doing load transients with a slope in the range of tenth A us the output capacitor is a basic component for the fast response of the power supply Dual phase topology reduces the amount of output capacitance needed because of faster load transient response switching frequency is doubled at the load connections Current ripple cancellation due to the 180 phase shift between the two phases also reduces requirements on the output ESR to sustain a specified voltage ripple When a load transient is applied to the converter s output for first few microseconds the current to the load i
19. d has been set to 45A 22 5A x 2 in the worst case max mosfet temperature Since the device limits the valley of the triangular ripple across the inductors the current ripple must be considered too Considering the inductor core satura tion a current ripple of 10A has to be considered so that the OCP threshold in worst case becomes OCPx 17A 22 5A 5A Considering to sense the output current across the low side mosfet RdsON SUB85N03L 04P has 4 3mQ max at 25 C that becomes 5 6mQ at 100 C considering the temperature variation the resulting transconductance resistor Rg has to be Rason 5 6m Rg locpx 35u 17 7272 R3toR6 Droop function Design Considering a voltage drop of 70mV at full load the feedback resistor Rfg has to be 70mV 1kQ R7 FB 70 R7 Inductor design Transient response performance needs a compromise in the inductor choice value the biggest the in ductor the highest the efficient but the worse the transient response and vice versa Considering then an inductor value of 0 8uH the current ripple becomes Vin Vout d 12 1 2 12 1 LE 65A 11 12 L Fsw O8u 12 200k Output Capacitor Five Rubycon MBZ 2200uF 6 3V 12mQ max ESR has been used implementing a resulting ESR of 2 4mQ resulting in an ESR voltage drop of 45 2 4mQ 108mV after a 45 load transient Compensation Network A voltage loop bandwidth of 20kHz is considered to let the device fast react aft
20. driver output A little series resistor helps in reducing device dissipated power 26 PHASE2 Channel 2 HS driver return path It must be connected to the HS2 mosfet source and provides the return path for the HS driver of channel 2 27 LGATE2 Channel 2 LS driver output A little series resistor helps in reducing device dissipated power 28 PGND LS drivers return path This pin is common to both sections and it must be connected through the closest path to the LS mosfets source pins in order to reduce the noise injection into the device PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above 7 33 L6919E DEVICE DESCRIPTION The device is an integrated circuit realized in BCD technology It provides complete control logic and protections for a high performance dual phase step down DC DC converter optimized for microprocessor power supply It is de signed to drive N Channel MOSFETs in a dual phase synchronous rectified buck topology A 180 deg phase shift is provided between the two phases allowing reduction in the input capacitor current ripple reducing also the size and the losses The output voltage of the converter can be precisely regulated programming the VID pins from 0 825V to 1 575V with 25mV binary steps with a maximum tolerance of 0 6 over temperature and line voltage variations The device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of an
21. e end of the digital soft start the Power Good comparator is enabled and the PGOOD signal is then driven high See fig 10 The Under Voltage comparator is enabled when the reference voltage reaches 0 6V The Soft Start will not take place if both VCC and VCCDR pins are not above their own turn on thresholds During normal operation if any under voltage is detected on one of the two supplies the device shuts down Forcing the OSC INH pin to a voltage lower than 0 6V Typ disables the device all the power mosfets and protections are turned off until the condition is removed TA 15 33 L6919E Figure 10 Soft Start Turn ON threshold 2048 Clock Cydes 004 077 VMTCUms Cha FEV Timing Diagram Acquisition CH1 LGATEx CH2 VCC CH3 VOUT INPUT CAPACITOR The input capacitor is designed considering mainly the input RMS current that depends on the duty cycle as reported in figure 11 Considering the dual phase topology the input RMS current is highly reduced comparing with a single phase operation Figure 11 Input RMS Current vs Duty Cycle D and Driving Relationships t Single Phdse AED BD 1 2D if D 0 5 Dual Phage ME 2D 1 2 2D if D gt 05 Rms Current Normalized lrus lour 0 25 0 50 0 75 Duty Cycle Vout It be observed that the input rms value is one half of the single phase equivalent input current in the worst case condition that happens for D 0 25 an
22. e voltage for the regulation is pro grammed by the voltage identification VID pins These are TTL compatible inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference The VID code drives a multiplexer that selects a voltage on a precise point of the divider The DAC output is delivered to an amplifier obtaining the Vprog voltage reference i e the set point of the error amplifier Internal pull ups are provided realized with a 5uA current generator up to 3 0V Typ in this way to program a logic 1 it is enough to leave the pin floating while to program a logic 0 it is enough to short the pin to GND Programming the 11111 code the device enters the NOCPU mode all mosfets are turned OFF and protections are disabled The condition is latched The voltage identification VID pin configuration also sets the power good thresholds PGOOD and the Over Under Voltage protection OVP UVP thresholds DYNAMIC VID TRANSITION The device is able to manage On The Fly VID Code changes that allow Output Voltage modification during nor mal device operation The device checks every clock cycle synchronously with the PWM ramp for VID code modifications Once the new code is stable for more than one clock cycle the reference steps up or down in 25mV increments every clock cycle until the new VID code is reached During the transition VID code changes are ignored the device re
23. eal current lmax 2 For Rsense 4mO and Imax 40A the current sharing error is equal to 2 5 neglecting errors due to Rg and Rsense mismatches Figure 14 Current Sharing Control Loop CURRENT SHARING DUTY CYCLE CORRECTION DO2IN1393 Average Current Mode ACM Control Loop The average current mode control loop is reported in figure 15 The current information IFg sourced by the FB pin flows into RFB implementing the dependence of the output voltage from the read current The ACM control loop gain results obtained opening the loop after the COMP pin Gi oop S INGENIUM ONE ae F S 1 Zp S 2 S 1 xi Res Where R e Reg is the equivalent output resistance determined by the droop function g Zp s is the impedance resulting by the parallel of the output capacitor and its ESR and the applied load Ro Zr s is the compensation network impedance 21 5 is the parallel of the two inductor impedance A s is the error amplifier gain 4 AVN PWM B AVL is the ACM PWM transfer function where AVosc is the oscillator ramp amplitude OSC and has a typical value of 3V Removing the dependence from the Error Amplifier gain so assuming this gain high enough the control loop gain results TA 19 33 L6919E Vin Zp s Zp S GLoor 9 Am Lorem osc p S Z s Rg Reg With further simplifications it results LOOP 5 Moer Rea 2 Ro R osc
24. egulation The input can be configured in different ways using the jumpers JP1 JP2 and JP6 these jumpers control also the mosfet driver supply voltage Anyway power conversion starts from Vin and the device is supplied from Vcc See Figure 20 Figure 20 Power supply configuration To Vee pin To HS Drains Power Input To BOOTx HS Driver Supply 24 33 TA L6919E Two main configurations can be distinguished Single Supply VCC VIN 12V and Double Supply VCC 12V VIN 5V or different Single Supply In this case JP6 has to be completely shorted The device is supplied with the same rail that is used for the conversion With an additional zener diode DZ1 a lower voltage can be derived to supply the mosfets driver if Logic level mosfet are used In this case JP1 must be left open so that the HS driver is supplied with Viy Vpz1 through BOOTx and JP2 must be shorted to the left to use Vin or to the right to use ViN Vpz1 to supply the LS driver through VCCDR pin Otherwise JP1 must be shorted and JP2 can be freely shorted in one of the two positions Double Supply In this case VCC supply directly the controller 12V while Vin supplies the HS drains for the power conversion This last one can start indifferently from the 5V bus Typ or from other buses allowing maximum flexibility in the power conversion Supply for the mosfet driver can be programmed through the jumpers JP1 JP2 and JP6 as previously illustrated JP6 selects
25. em response to a load transient from 3A to 45A The output voltage is contained in the 50mV range Additional output capacitors can help in reducing the initial voltage spike mainly due to the ESR Figure 30 3A to 45A Load Transient Response Tek Run 2 50MS s Sample 50 0mv v amp M 400gs Chi 7 54mV Figure 31 shows the system response to a VID transient from 1 200V to 0 800V and vice versa at minimum load 3A Figure 31 Dynamic VID Response Run 2 50MS s Sample Tek Run 2 50MS s uide t T T 100 M 400us Chi X TED Toomv M 400gs Chi 7 L 01V 31 33 L6919E OUTLINE AND me EEE MECHANICAL DATA 0 004 0 012 45 typ 0 697 0 713 10 65 0 394 0 419 32 33 L6919E Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems
26. er load transient The Rr Cr network results Reg AVog 5 L 1K 2 5 0 8y Ro 2 20K 211 V 4 T SR ESR 12 4 IN Rproop 2 ZEM 1 2k 2 4m 2 0kQ R8 ees 6 2200p 1 N 2_N 2 _ C2 R 2k Further adjustments be done on the work bench to fit the requirements and to compensate layout parasitic components 27 33 L6919E Part List R2 147k 1 SMD 0805 R1 R20 R21 Not Mounted SMD 0805 R3 R4 R5 R6 2 7k 1 SMD 0805 R7 1k 1 SMD 0805 R8 1 8k SMD 0805 R9 47k 196 SMD 0805 R10 510 SMD 0805 R11 82 SMD 0805 R12 to R19 0 SMD 0805 C1 Not Mounted SMD 0805 C2 22n SMD 0805 C3 C4 100n SMD 0805 C5 C6 C7 C8 1u Ceramic SMD 1206 C9 C10 10u or 22u 16V TDK Multilayer Ceramic SMD 1206 C11 to C13 1800u 16V Rubycon MBZ Radial 10x23 C14 to C18 2200u 6 3V Rubycon MBZ Radial 10x20 C24 100n SMD 0805 L1 L2 0 8u 77121 4Turns U1 L6919E STMicroelectronics SO28 Q1 Q3 SUB85N03 04P Vishay D PACK Q2 Q4 SUB70N03 09BP Vishay D PACK D1 D2 STPS340U STMicroelectronics SMB D3 D4 1N4148 STMicroelectronics SOT23 50 54 Short 51 52 53 STATIC PERFORMANCES Figure 24 shows the demo board measured efficiency versus load current in steady state conditions without air flow at ambient temperature Figure 24 System Efficiency gt amp gt o 2 o 2 15 20 25 30 Output Current 28 33 TA L6919E Figure 25 shows the mosfets temperature versus outpu
27. er side towards the mosfets and the GATEx and PHASEx traces walking together toward the high side mosfet in order to minimize distance see fig 17 In addition since the PHASEx pin is the return path for the high side driver this pin must be connected directly to the High Side mosfet Source pin to have a proper driving for this mosfet For the LS mosfets the return path is the PGND pin it can be connected directly to the power ground plane if implemented or in the same way to the LS mosfets Source pin GATEx and PHASEx connections and also PGND when no power ground plane is implemented must also be designed to handle current peaks in excess of 2A 30 mils wide is suggested Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the system efficiency Figure 17 Device orientation left and sense nets routing right To LS mosfet Towards HS mosfet or sense resistor 30 mils wide Towards LS mosfet 30 mils wide Towards HS mosfet To LS mosfet 30 mils wide or sense resistor To regulated output The placement of other components is also important The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to mini mize the loop that is created Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins Decoupling capacitor from VCCDR and PGND placed as close as possible to those pins This capacitor sustain
28. f the current has to reach the locpx bottom The worst case condition is when the ON time reaches its maximum value When this happens the device works in Constant Current and the output voltage decrease as the load increase Crossing the UVP threshold causes the device to latch FAULT pin is driven high Figure 6 shows this working condition It can be observed that the peak current Ipeak is greater than the locpx but it can be determined as follow Vin Vout Vi Vout IN MIN IN MIN Ipeak p p 0 40 T Where VoutMiN is the minimum output voltage VID 30 as follow The device works in Constant Current and the output voltage decreases as the load increase until the output voltage reaches the Under Voltage threshold Voutmin When this threshold is crossed all mosfets are turned off the FAULT pin is driven high and the device stops working Cycle the power supply to restart operation The maximum average current during the Constant Current behavior results Ipeak 1 OCPx IMAX TOT 2 Imax 2 loce 0025 12 33 L6919E Figure 6 Constant Current operation Droop effect PENNE TonMAX a iux iot Ies 50nA loce 2 locex Ire 70uA a Maximum current for each phase b Output Characteristic In this particular situation the switching frequency results reduced The ON time is the maximum allowed TonMAx while the OFF time depends on the application Ipeak lo
29. l never drop 9 33 L6919E Figure 3 Drivers peak current High Side left and Low Side right Tek 5005 5 43 eqs Tek 500MS s 24 Acqs E M 500ns X 540mA 1 00 1 00 M 500ns Chi X 540m 1 00 A 1 00 A CH3 HGATE1 CH4 HGATE2 CH3 LGATE1 CH4 LGATE2 To allow the turning on of the low side mosfet even in this case a watchdog controller is enabled if the source of the high side mosfet don t drop for more than 240ns the low side mosfet is switched on so allowing the neg ative current of the inductor to recirculate This mechanism allows the system to regulate even if the current is negative The BOOTx and VCCDR pins are separated from IC s power supply VCC pin as well as signal ground SGND pin and power ground PGND pin in order to maximize the switching noise immunity The separated supply for the different drivers gives high flexibility in mosfet choice allowing the use of logic level mosfet Several com bination of supply can be chosen to optimize performance and efficiency of the application Power conversion is also flexible 5V or 12V bus can be chosen freely The peak current is shown for both the upper and the lower driver of the two phases in figure 3 A 10nF capac itive load has been used For the upper drivers the source current is 1 9A while the sink current is 1 5A with VBOOT VPHASE 12V similarly for the lower drivers the source current is 2 4
30. mposed by the previous relationship If the desired output characteristic crosses the Tow limited maximum output voltage the output resulting voltage will start to drop after crossing In this case the device doesn t perform con stant current limitation but only limits the maximum ON time following the previous relationship The output volt age follows the resulting characteristic dotted in Figure 5b until UVP is detected or anyway until 70uA Figure 5 Ton Limited Operation Resulting Output Tow Limited Output characteristic characteristic Desired Output w Characteristic and Tw UVP threshold lour loce72 locex loce72 locex 70 70 a Maximum output Voltage b Ton Limited Output Voltage 2 Constant Current Operation This happens when ON time limitation is reached after the current in each phase reaches locpx gt 35 The device enters in Quasi Constant Current operation the low side mosfets stays ON until the current read becomes lower than liNFox lt 354A skipping clock cycles The high side mosfets can be turned ON with a Ton imposed by the control loop at the next available clock cycle and the device works in the usual way until another OCP event is detected This means that the average current delivered can slightly increase also in Over Current condition since the cur rent ripple increases In fact the ON time increases due to the OFF time rise because o
31. n VIA to GND plane and Source To HS Gate To PHASE and Source connection Wrong left and correct right connections for the current reading sensing nets TA 23 33 L6919E Demo Board Description The L6919E demo board shows the operation of the device in a dual phase application This evaluation board allows output voltage adjustability 0 800V 1 550V through the switches S0 S4 and high output current capa bility The board has been laid out with the possibility to use up to two D PACK mosfets for the low side switch in order to give maximum flexibility in the mosfet choice The four layers demo board s copper thickness is of 70um in order to minimize conduction losses considering the high current that the circuit is able to deliver Demo board schematic circuit is reported in Figure 19 Figure 19 Demo Board Schematic Vee a VoutCORE o PGOOD Several jumpers allow setting different configurations for the device 4 and 5 allow configuring the remote buffer as desired Simply shorting JP4 and JP5 the remote buffer is enabled and it senses the output voltage on board to implement a real remote sense leave these jumpers open and connect the FBG and FBR connectors on the demo board to the remote load To avoid using the remote buffer simply short all the jumpers JP3 JP4 and JP5 Local sense through the R7 is used for the r
32. now Vcc or Vin depending on the requirements Some examples are reported in the following Figures 21 and 22 Figure 21 Jumpers configuration Double Supply Vee 12V HS Drains 5V HS Supply 5V VCCDR LS Supply 5V a Vee 12V VBoorx VCCDR Vin 5V Vee 12V HS Drains 5V HS Supply 12V VCCDR LS Supply 12V b Voc Vaoorx VCCDR 12V Vin 5V Vee 12V HS Drains 12V HS Supply 5 2V L VCCDR LS Supply 12V a Vcc Vin 12V VBoorx 5 2V Vee 12V HS Drains 12V HS Supply 12V il VCCDR LS Supply 12V b Vec VIN VBoor VCCDR 12V 25 33 L6919E PCB AND COMPONENT LAYOUT Figure 23 PCB and Components Layouts Dimensions 10 8mm x 8 2mm Internal PGND Plane Component Side Solder Side c S a 2 o c 2 26 33 L6919E CPU Power Supply 5 to 12Vin 1 2Vour 45Apc Considering the high slope for the load transient a high switching frequency has to be used In addition to fast reaction this helps in reducing output and input capacitor Inductance value is also reduced A switching frequency of 200kHz for each phase is then considered allowing large bandwidth for the compen sation network Considering the high output current power conversion will start from the 12V bus Current Reading Network and Over Current Since the maximum output current is Imax 45 the over current threshol
33. ol loop equalize the currents in the inductors while the Average Current Mode control loop fixes the output voltage equal to the reference programmed by VID Figure 13 reports the block diagram of the main control loop Figure 13 Main Control Loop Diagram CURRENT SHARING DUTY CYCLE CORRECTION REFERENCE PROGRAMMED BY VID DO2IN1392 Current Sharing CS Control Loop Active current sharing is implemented using the information from Tran conductance differential amplifier in an average current mode control scheme A current reference equal to the average of the read current lava is in ternally built the error between the read current and this reference is converted to a voltage with a proper gain and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin See fig 14 The current sharing control is a high bandwidth control loop allowing current sharing even during load transients The current sharing error is affected by the choice of external components choose precise Rg resistor 1 is 18 33 L6919E necessary to sense the current The current sharing error is internally dominated by the voltage offset of Tran conductance differential amplifier considering a voltage offset equal to 2mV across the sense resistor the cur rent reading error is given by the following equation AIREAD _ 2mV IMAX Rsense IMAX Where Alreap is the difference between one phase current and the id
34. ops below the 60 of the ref erence voltage for more than one clock period the device turns off all mosfets and the OSC FAULT is driven high 5V The condition is latched to recover it is required to cycle the power supply Over Voltage protection is also provided when the voltage monitored by VSEN reaches the OVP threshold VOVP the controller permanently switches on both the low side mosfets and switches off both the high side mosfets in order to protect the load The OSC FAULT pin is driven high 5V and power supply Vcc turn off and on is required to restart operations The over voltage percentage is then set by the ratio between the fixed OVP threshold VOVP and the reference programmed by VID Vovyp OVP ReferenceVoltage VID 100 Both Over Voltage and Under Voltage are active also during soft start Under Voltage after than the output volt age reaches 0 6V The reference used in this case to determine the UV thresholds is the increasing voltage driven by the 2048 soft start digital counter while the reference used for the OV threshold is the final reference programmed by the VID pins SOFT START AND INHIBIT At start up a ramp is generated increasing the loop reference from OV to the final value programmed by VID in 2048 clock periods as shown in figure 10 Once the soft start begins the reference is increased upper and lower MOS begin to switch and the output volt age starts to increase with closed loop regulation At th
35. rates the triangular waveform for the PWM charging and discharging with a constant cur rent an internal capacitor The current delivered to the oscillator is typically 25 A Fsw 150kHz and may be varied using an external resistor ROSC connected between OSC pin and GND or Vcc Since the OSC pin is maintained at fixed voltage Typ 1 237V the frequency is varied proportionally to the current sunk forced from into the pin con sidering the internal gain of 6KHz uA In particular connecting it to GND the frequency is increased current is sunk from the pin while connecting ROSC to Vcc 12V the frequency is reduced current is forced into the pin according to the following relationships 6 1 287 kHz 7422 10 R vs GND fe 150kHz 6E 150kHz ux Rosc 7 RoscVS 12V fg 150kHz 12 1 297 gKHz _ pp iz 8 457 10 Rosc uA Rgsc KQ Note that forcing 25uA into this pin the device stops switching because no current is delivered to the oscillator Figure 1 Rosc vs Switching Frequency a a z 7 o 7 gt gt o o CE CE Frequency KHz 8 33 74 L6919E DIGITAL TO ANALOG CONVERTER The built in digital to analog converter allows the adjustment of the output voltage from 0 800V to 1 550V with 25mV as shown in the previous table 1 The internal reference is trimmed to ensure output voltage precision of 0 6 and a zero temperature coefficient around 70 C The internal referenc
36. round sense and reports this voltage internally at VSEN pin with unity gain eliminating the errors Keeping the FBR and FBG traces parallel and guarded by a power plane results in common mode coupling for any picked up noise If remote sense is not required it is enough connecting RFB directly to the regulated voltage VSEN becomes not connected and still senses the output voltage through the remote buffer In this case the FBG and FBR pins must be connected anyway to the regulated voltage See figure 10 The remote buffer is included in the trimming chain in order to achieve 0 5 accuracy on the output voltage when the RB Is used eliminating it from the control loop causes the regulation error to be increased by the RB offset worsening the device performances 14 33 L6919E Figure 9 Remote Buffer Connections Reference REMOTE Reference REMOTE Remote Ground RB used 0 5 Accuracy RB Not Used OUTPUT VOLTAGE MONITOR AND PROTECTIONS The device monitors through pin VSEN the regulated voltage in order to build the PGOOD signal and manage the OVP UVP conditions Power good output is forced low if the voltage sensed by VSEN is not within 12 Typ of the programmed value It is an open drain output and it is enabled only after the soft start is finished 2048 clock cycles after start up During Soft Start this pin is forced low Under voltage protection is provided If the output voltage monitored by VSEN dr
37. s sup plied by the output capacitors The controller recognizes immediately the load transient and increases the duty cycle but the current slope is limited by the inductor value The output voltage has a first drop due to the current variation inside the capacitor neglecting the effect of the ESL AVour Alour ESR A minimum capacitor value is required to sustain the current during the load transient without discharge it The voltage drop due to the output capacitor discharge is given by the following equation 2 Alour L 4 Cour Vin 7 Your Where Dmax is the maximum duty cycle value The lower is the ESR the lower is the output drop during load transient and the lower is the output voltage static ripple AVour INDUCTOR DESIGN The inductance value is defined by a compromise between the transient response time the efficiency the cost and the size The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current AlL between 20 and 30 of the maximum output current The inductance value can be cal culated with this relationship pe Vin Vour Your fsw Al Vin Where fsw is the switching frequency Vin is the input voltage and Vour is the output voltage Increasing the value of the inductance reduces the ripple current but at the same time reduces the converter response time to a load transient The response time is the time required by the inductor to change
38. s the peak currents requested by the low side mosfet drivers Refer to SGND all the sensible components such as frequency set up resistor when present and also the optional resistor from FB to GND used to give the positive droop effect Connect SGND to PGND on the load side output capacitor to avoid undesirable load regulation effect and to ensure the right precision to the regulation when the remote sense buffer is not used 22 33 L6919E An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain This helps in reduc ing noise PHASE pin spikes Since the HS mosfet switches in hard mode heavy voltage spikes can be observed on the PHASE pins If these voltage spikes overcome the max breakdown voltage of the pin the device can absorb energy and it can cause damages The voltage spikes must be limited by proper layout the use of gate resistors Schottky diodes in parallel to the low side mosfets and or snubber network on the low side mosfets to a value lower than 26V for 20nSec at FSW of 600kHz max m Current Sense Connections Remote Buffer The input connections for this components must be routed as parallel nets from the FBG FBR pins to the load in order to compensate losses along the output power traces and also to avoid the pick up of any common mode noise Connecting these pins in points far from the load will cause a non optimum load reg ulation increasing output tolerance Curren
39. t Reading The Rg resistor has to be placed as close as possible to the ISENx and PGNDSx pins in order to limit the noise injection into the device The PCB traces connecting these resistors to the reading point must be routed as parallel traces in order to avoid the pick up of any common mode noise It s also important to avoid any offset in the measurement and to get a better precision to connect the traces as close as possible to the sensing elements dedicated current sense resistor or low side mosfet Rason Moreover when using the low side mosfet Rason as current sense element the ISENx pin is practically con nected to the PHASEx pin DO NOT CONNECT THE PINS TOGETHER AND THEN TO THE HS SOURCE The device won t work properly because of the noise generated by the return of the high side driver In this case route two separate nets connect the PHASEx pin to the HS Source route together with HGATEx with a wide net 30 mils and the ISENx pin to the LS Drain route together with PGNDSx Moreover the PGNDSx pin is always connected through the Rg resistor to the PGND DO NOT CONNECT DIRECTLY TO THE PGND In this case the device won t work properly Route anyway to the LS mosfet source together with ISENx net Right and wrong connections are reported in Figure 18 Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter Figure 18 PCB layout connections for sense nets NOT CORRECT CORRECT ToLS Drai
40. t current in steady state condition without any air flow or heat sink It can be observed that the mosfets are under 100 C in any conditions Load regulation is also re ported from 10A to 45A Figure 25 Mosfet Temperature and Load Regulation 4 High side MOS Q2 te High side MOS Q4 x Low side MOS Q1 o Low side MOS m c A a on ow o o o T 15 20 25 30 35 40 45 10 15 20 25 30 35 40 45 datput Current Output Current DYNAMIC PERFORMANCES Figure 26 shows the system response to a load transient from 3A to 45A The output voltage is contained in the 50mV range Additional output capacitors can help in reducing the initial voltage spike mainly due to the ESR Figure 26 3A to 45A Load Transient Response Tek Run 500kS s Sample EF M so0us Chi 7 s mV Figure 27 shows the system response to a VID transient from 1 200V to 0 800V and vice versa at minimum load 3A Figure 27 Dynamic VID Response ek BEE 1 00MS s 1 Acqs Tek 1 00MS s E F E M 25045 Chi 7 890mV 100mV M 250us Chi 890mV TA 29 33 L6919E DEMO BOARD ENHANCEMENTS 1 200V 52A CPU Power Supply Considering the same application schematic minor changes can be done to achieve the 52A thermal output current required by AMD Hammer processor core Part list has been modified as follow Part List R2 147k 196 SMD 0806 R1 R20 R21 Not Mounted SMD 0805 R3 R4 R5 R
41. t in order to equalize the current carried by the two phases The transconductance resistor Rg can be designed in order to have current information of 254A per phase at full nominal load the over current intervention threshold is set at 140 of the nominal linFox 354A According to the above relationship the over current threshold locpx for each phase which has to be placed at one half of the total delivered maximum current results _ 35uA Rg Rg locpx RSENSE PsENSE 354A Since the device senses the output current across the low side mosfets or across a sense resistors in series with them the device limits the bottom of the inductor current triangular waveform an over current is detected when the current flowing into the sense element is greater than locpx liNFox gt locPx Introducing now the maximum ON time dependence with the delivered current where T is the switching period T 1 fsw 0 40 T lpg 70A R Ton max 0 80 lpg 5 73k T 0 80 SSN lout 5 73k This linear dependence has a value at zero load of 0 80 T and at maximum current of 0 40 T typical and results in two different behaviors of the device 11 33 L6919E 1 Ton Limited Output Voltage This happens when the maximum ON time is reached before the current in each phase reaches liNFox lt 35uA Figure 5a shows the maximum output voltage that the device is able to regulate considering the Tow limitation i
42. the selected output voltage to be within 0 6 The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses The device assures a fast protection against load over current and load over under voltage An inter nal crowbar is provided turning on the low side mosfet if an over voltage is detected In case of over current the system works in Constant Cur rent mode Boori GATE PHASE LOGE PWM ADAPTIVE ANTI CROSS CONDUCTION LGATE1 ISEN1 LOGIC AND PROTECTIONS A PGNDS1 PGND 4 PGNDS2 ERROR AMPLIFIER September 2003 A ISEN2 LGATE2 LOGIC PWM ADAPTIVEANTI CROSS CONDUCTION PHASE2 UGATE2 Boor2 1 33 L6919E ABSOLUTE MAXIMUM RATINGS VUGATE2 V PHASE2 LGATE1 PHASE1 LGATE2 PHASE2 to PGND 0 3 to Vcc 0 3 Ee eel _ _ terns PBN Maximum Withstanding Voltage Range OTHER PINS Test Condition CDF AEC Q100 002 Human Body Model Acceptance Criteria Normal Performance THERMAL DATA PIN CONNECTION LGATE1 VCCDR PHASE1 UGATE1 BOOT1 VCC SGND PGND LGATE2 PHASE2 UGATE2 BOOT2 PGOOD VIDA VID3 VID2 VID1 VIDO OSC INH FAULT ISEN2 PGNDS COMP FB VSEN FBR FBG ISEN1 PGNDS1 ON Oo A A WO PL Se iX Am eel cd a N o 4 2 33 L6919E ELECTRICAL CHARACTERISTICS Voc
43. y external set up resistor The device manages On The Fly VID Code changes stepping to the new configuration following the VID table with no need for external components The device provides an average current mode control with fast transient response It includes a 150kHz free running oscillator The error amplifier features a 15V us slew rate that permits high converter bandwidth for fast transient performances Current information is read across the lower mosfets RdsON or across a sense resistor in fully differential mode The current information corrects the PWM output in order to equalize the av erage current carried by each phase Current sharing between the two phases is then limited at 10 over static and dynamic conditions The device protects against Over Current with an OC threshold for each phase entering in con stant current mode Since the current is read across the low side mosfets the constant current keeps constant the bottom of the inductors current triangular waveform When an under voltage is detected the device latches and the FAULT pin is driven high The device performs also Over Voltage protection that disables immediately the device turn ing ON the lower driver and driving high the FAULT pin OSCILLATOR The switching frequency is internally fixed at 150kHz Each phase works at the frequency fixed by the oscillator so that the resulting switching frequency at the load side results in being doubled The internal oscillator gene
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