FAIRCHILD FQB3N60 FQI3N60 600V N-Channel MOSFET handbook
Contents
1. Maximum lead temperature for soldering purposes 1 8 from case for 5 seconds 300 Thermal Characteristics Symbol Parameter Rejc Thermal Resistance Junction to Case ReJA Thermal Resistance Junction to Ambient ReJA Thermal Resistance Junction to Ambient When mounted on the minimum pad size recommended PCB Mount 2000 Fairchild Semiconductor International Rev A April 2000 Electrical Characteristics Tc 25 C unless otherwise noted 4 Pulse Test Pulse width lt 300us Duty cycle lt 2 5 Essentially independent of operating temperature 1 Repetitive Rating Pulse width limited by maximum junction temperature 2 L 40mH las 3 0A Vpp 50V Ra 25 Q Starting Ty 25 C 3 Isp lt 3 0A di dt lt 200A us Vpp BVpss Starting Ty 25 C Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVpss Drain Source Breakdown Voltage Ves 0 V Ip 250 LA 600 V ABV DSS Breakdown Voltage Temperature Ip 250 HA Referenced to 25 C n 0 6 B VC ATj Coefficient Ipss Vps 600 V Vas 0 V 10 HA Zero Gate Voltage Drain Current Vps 480 V Tc 125 C E 100 uA lassF Gate Body Leakage Current Forward Ves 30 V Vps 0 V 100 nA lass Gate Body Leakage C2. Veg 10V Rostov 2 Drain Source On Resistance X Note T 25 C 0 1 2 3 4 5 6 7 lp Drain Current A Figure 3 On Resistance Variation vs Drain Current and Gate Voltage C C Gy C shorted CaO a C 7C Vg Drain Source Voltage V Figure 5 Capacitance Characteristics 10 v Top 150V 100V EE BOV pit 70V 65V 60V y Bottom 55V gi 5 E Kp e S o 6 X Notes 1 250 us Pulse Test 2 7 2250 10 x R 10 10 10 lp Reverse Drain Current A Vas Gate Source Voltage V Ip Drain Current A a 3 Notes 1 V 50V 2 250 s Pulse Test 2 4 6 8 10 Ves Gate Source Voltage V Figure 2 Transfer Characteristics 02 04 0 6 0 8 10 12 14 1 6 Vp Source Drain Voltage V Figure 4 Body Diode Forward Voltage Variation vs Source Current and Temperature X Note 230A 0 2 4 6 8 10 Qp Total Gate Charge nC Figure 6 Gate Charge Characteristics 2000 Fairchild Semiconductor International Rev A April 2000 Typical Characteristics continued 257 207 Normaiz 5 Rison Normalized Drain Source On Resistance a 8 10r Bos a X Nes a 1 Vs 0V 5 21 2250 4A 05 0 8 00 i i i i i 100 50 0 50 100 150 200 100 50 0 50 100 150 200 T Junction Temperature C T Junction Temperature C Figure 7 Breakdown Voltage V
3. OO FOB3NG0 OO FQB3N60 FQI3N60 Lz FAIRCHILD Ei SEMICONDUCTOR vv FQB3N60 FQI3N60 600V N Channel MOSFET General Description These N Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary planar stripe DMOS technology This advanced technology has been especially tailored to minimize on state resistance provide superior switching performance and withstand high energy pulse in the avalanche and commutation mode These devices are well suited for high efficiency switch mode power supply April 2000 QFET Features 3 0A 600V Rps on 3 62 9 Vas 10 V Low gate charge typical 10 nC Low Crss typical 5 5 pF Fast switching 10096 avalanche tested Improved dv dt capability S D PAK FQB Series GDS 12 PAK FQI Series Absol ute Maxi mum Rati ngs To 25 C unless otherwise noted Symbol Vpss Parameter Drain Source Voltage FQB3N60 FQI3N60 600 Ip Drain Current Continuous Tc 25 C Continuous Tc 100 C 3 0 1 9 lpm Drain Current Pulsed 12 Gate Source Voltage 30 Single Pulsed Avalanche Energy 200 Avalanche Current 3 0 Repetitive Avalanche Energy 7 5 Peak Diode Recovery dv dt 4 5 Power Dissipation Ta 25 C 3 13 Power Dissipation Tc 25 C Derate above 25 C 75 0 6 Operating and Storage Temperature Range 55 to 150
4. Ra Isp controlled by pulse period Gate Pulse Width Ves Gate Pulse Period Driver lem Body Diode Forward Current Isp DUT di dt IRM Body Diode Reverse Current Body Diode Recovery dv dt Body Diode Forward Voltage Drop 2000 Fairchild Semiconductor International Rev A April 2000 O9NEIOS 09N 80H FQB3N60 FQI3N60 Package Dimensions D PAK 4 50 0 20 2 54 0 30 Q 9 90 0 20 e 1 30 20 05 J EN S e e E EX al g S i S S F 0 10 0 15 o e si Y e ai s LO L I 2 40 0 20 S AI i A 5 LO N S 1 27 0 10 _ _ 0 80 0 10 0 10 254TYP 2 54 TYP 11 0 50 0 05 10 00 0 20 8 00 p i B 10 00 0 20 a R F o a lo q F e o po S 9 20 0 20 2000 Fairchild Semiconductor International Rev A April 2000 Package Dimensions continued O9NEIOS 09N 80H p 10 00 0 20 J 9 90 0 20 4 50 0 20 S o 1 80 Qo 1 a 17 i Ex 9 gle al S 3 S 3 oz T g EU sy p sl i S S 8 gt S SARS a 1272010 1 47 0 10 1 E i BH T S 0 80 0 10 o qp S 0 10 2 54 TYP _ _ _ _ 2 54TYP 0 50 0 05 1 2 40 0 20 2000 Fairchild Semiconductor Internati
5. ariation Figure 8 On Resistance Variation vs Temperature vs Temperature E E L Operation in This Area gt L is Limited by R son 10 z z t B oU z 5 E c S kg T 5 a EE eer e X Notes E 1 T 25 C L 2 T 150 C 3 Single Pulse 10 00 i I 10 10 1 10 25 50 75 100 125 150 Va Drain Source Voltage V T Case Temperature C Figure 9 Maximum Safe Operating Area Figure 10 Maximum Drain Current vs Case Temperature o b o c 2 10 i F D 0 5 o r c L 0 2 Notes E 1 Z 0 1 67 C W Max E 2 Duty Factor D t t 8 Ta gt Te Pou Ze yot 10 1 zE S Pou k s El EPI N single pulse Parr 10 10 10 10 10 107 10 10 t Square Wave Pulse Duration sec Figure 11 Transient Thermal Response Curve 2000 Fairchild Semiconductor International Rev A April 2000 O9NEIOS 09N 80H FQB3N60 FQI3N60 Gate Charge Test Circuit amp Waveform Same Type as DUT Charge 90 10 GS der t ton Unclamped Inductive Switching Test Circuit amp Waveforms T BVpss ue 2 BVpss Veo BVpss las Ip t Vop Vps t a ts Time 2000 Fairchild Semiconductor International Rev A April 2000 Peak Diode Recovery dv dt Test Circuit amp Waveforms Same Type as DUT dv dt controlled by
6. life support when properly used in accordance with instructions for use device or system or to affect its safety or effectiveness provided in the labeling can be reasonably expected to PRODUCT STATUS DEFINITIONS Definition of Terms Advance Information Formative or In This datasheet contains the design specifications for Design product development Specifications may change in any manner without notice Preliminary First Production This datasheet contains preliminary data and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design No Identification Needed Full Production This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only 2000 Fairchild Semiconductor International Rev A January 2000
7. onal Rev A April 2000 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks ACEXTM HiSeC TM SuperSOTTM 8 Bottomless TM ISOPLANARTM SyncFET M CoolFET MICROWIRE TinyLogic CROSSVOLT POP UHC E CMOS PowerTrench VCX FACT QFET FACT Quiet Series QSTM FAST Quiet Series FASTr SuperSOT 3 GTO SuperSOT M 6 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL As used herein result in significant injury to the user 1 Life support devices or systems are devices or systems 2 A critical component is any component of a life support which a are intended for surgical implant into the body device or system whose failure to perform can be or b support or sustain life or c whose failure to perform reasonably expected to cause the failure of the
8. urrent Reverse Vas 30 V Vps OV 100 nA On Characteristics Vas th Gate Threshold Voltage Vps Vas lp 250 uA 3 0 m 5 0 Rps on Static Drain Source i Ves 10 V In 1 5 A 3 On Resistance a D ae on a grs Forward Transconductance Vps 250V lp 2 1 5A Note4 2 6 Dynamic Characteristics Ciss Input Capacitance Vps 25 V Ves 0 V 350 450 pF Coss Output Capacitance f21 0MHz 50 65 pF Crss Reverse Transfer Capacitance 5 5 7 5 pF Switching Characteristics ta on Turn On Delay Time Vpp 300 V Ip 3 0 A 10 30 ns t Turn On Rise Time Rg 250 B 30 70 ns la oft Turn Off Delay Time 20 50 ns ty Turn Off Fall Time Do e 30 70 ns A Total Gate Charge Vps 480 V Ip 3 0 A 10 13 nC Qgs Gate Source Charge Vas 10 V 2 7 nc Qga Gate Drain Charge Note 4 5 4 9 nC Drain Source Diode Characteristics and Maximum Ratings ls Maximum Continuous Drain Source Diode Forward Current 3 0 A ISM Maximum Pulsed Drain Source Diode Forward Current 12 A Vsp Drain Source Diode Forward Voltage Ves 0 V Is 3 0 A 3 z 1 4 V trr Reverse Recovery Time Ves 0 V Is 3 0 A 210 ns Qr Reverse Recovery Charge dir dt 100 A us ai aiat 12 uC Notes 2000 Fairchild Semiconductor International Rev A April 2000 O9NEIOS 09NEAOA FQB3N60 FQI3N60 Typical Characteristics Vg Drain Source Voltage V Figure 1 On Region Characteristics 81
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FAIRCHILD FQB3N60 FQI3N60 600V N Channel MOSFET handbook