intersil HUF76105DK8 handbook
Contents
1. DUTY CYCLE DESCENDING ORDER E a E 0 2 Rega 2289C W Q 0 05 2 hn NX 0 02 x x 01 20 01 H Ppm H Ou 9 38 0 01 H N E gt to H NOTES SINGLE PULSE DUTY FACTOR D t to PEAK Ty Ppp X Zoua X RgJA TA 0 001 E 1075 104 103 10 107 100 10 102 103 t RECTANGULAR PULSE DURATION s FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 500 RgJA 2289C W FOR TEMPERATURES ABOVE 25 DERATE PEAK E CURRENT AS FOLLOWS g LI 2 125 x lt n 2 TRANSCONDUCTANCE f MAY LIMIT CURRENT IN THIS REGION 1075 104 103 10 10 100 10 10 10 t PULSE WIDTH s FIGURE 4 PEAK CURRENT CAPABILITY 2 20 Ty RATED 100 n T STARTING Ty 25 C E 10 2 2 z 10 tc 2 I z 9 STARTING Ty 150 C 4 al 1 lt OPERATION IN THIS tav 145 1 3 BVpgs V AREA MAY BE H E 3 R a eee pas oD LIMITED BY rps oN Vpss MAX 30V tav L R In las R 1 3 RATED BVpss Vpp 1 0 1 1 0 01 0 1 1 10 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 5 FORWARD BIAS SAFE OPERATING AREA tay TIME IN AVALANCHE ms NOTE Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 4 intersil HUF76105DK8 Typical Performance Curve2. U 61050 vv ga TM Data Sheet HUF76105DK8 June 2000 File Number 4380 6 5A 30V 0 050 Ohm Dual N Channel Logic Level UltraFET Power MOSFET This N Channel power MOSFET is wie manufactured using the innovative UltraFET process This advanced process technology achieves the lowest possible on resistance per silicon area resulting in outstanding performance This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge It was designed for use in applications where power efficiency is important such as switching regulators switching converters motor drivers relay drivers low voltage bus switches and power management in portable and battery operated products Formerly developmental type TA76105 Features Logic Level Gate Drive 5A 30V Ultra Low On Resistance rps ow 0 0500 Temperature Compensating PSPICE Model Temperature Compensating SABER Model Thermal Impedance SPICE Model Thermal Impedance SABER Model Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature TB334 Guidelines for Soldering Surface Mount Components to PC Boards Ordering Information Symbol PART NUMBER PACKAGE BRAND D1 HUF76105DK8 MS 012AA 76105DK8 b NOTE When ordering use the entire part number Add the suffix T to obtain the variant in tape and reel e g HUF76105DK
3. 9 20 IT 8 17 1 1 9 LDRAIN 2 5 1 9 SESS LSOURCE LGATE 1 9 9 2 10 CIN SOURCE LSOURCE 3 7 3 2e 10 7 o 3 RSOURCE MMED 16 6 8 8 MMEDMOD RLSOURCE MSTRO 16 6 88 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD 12 15 RBREAK Is E N 18 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 9e 3 518 S2B RVTEMP RGATE 9 203 39 13 Gl RLDRAIN 2 5 10 CA 4 RLGATE 199 2 VBAT RLSOURCE 3 7 3 2 RSLC1 5 51 RSLCMOD 1e 6 pus 5 D RSLC2 5 50 1e3 8 RSOURCE 8 7 RSOURCEMOD 22e 3 22 RVTHRES 22 8 RVTHRESMOD 1 RVTHRES RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD 52 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 42 6 MODEL DBODYMOD D IS 3 01 13 IKF 20 RS 1 47 2 TRS1 1 7 3 TRS2 4 5 5 74e 10 TT 2 88e 8 0 43 MODEL DBREAKMOD D RS 3 94 1 51 9 94e 4 TRS2 9 12e 7 MODEL DPLCAPMOD D CJO 2 55e 10 IS 1e 30 N 10M 0 6 MODEL MMEDMOD NMOS VTO 1 92 KP 2 1 IS 1e 30N 10 TOX 1L 1u W 1u RG 3 39 MODEL MSTROMOD NMOS VTO 2 26 KP 19 IS 1 30 N 10 TOX 1L du W 1u MODEL MWEAKMOD NMOS VTO 1 7 KP 0 1 IS 1 30 N 10 TOX 1L 1u W RG 33 9 RS 0 1 MODEL RBREAKMOD RES TC1 9 94e 4 TC2 9 84e 8 MODEL RDRAINMOD RES TC1 8e 3 TC2 5 3e 5 MODEL RSLCMOD RES TC1 1 e 3 TC2
4. 1e 6 MODEL RSOURCEMOD RES TC1 1e 3 TC2 0 MODEL RVTHRESMOD RES TC1 1 87e 3 TC2 1 2e 6 MODEL RVTEMPMOD RES TC1 1 5e 3 TC2 1 7e 6 MODEL S1AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 6 2 VOFF 2 MODEL S1BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 2 VOFF 6 2 MODEL S2AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 5 VOFF 0 5 MODEL S2BMOD VSWITCH RON 1e 5 ROFF 2 0 1 VON 2 0 5 VOFF 0 5 ENDS NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 10 intersil HUF76105DK8 SABER Electrical Model REV June 1998 template huf76105 n2 n1 n3 electrical n2 n1 n3 var i iscl d model dbodymod is 3 01e 13 cjo 5 74e 10 tt 2 88e 8 xti 4 5 m 0 43 d model dbreakmod d model dplcapmod cjo 2 55e 10 is 1e 30 n 10 m 0 6 m model mmedmod type n vto 1 92 kp 2 1 is 1e 30 tox 1 m model mstrongmod n vto 2 26 kp 19 is 1e 30 tox 1 m model mweakmod type n vto 1 7 kp 0 1 is 1 30 tox 1 Sw vcsp model 1 16 5 roff 0 1 von 6 2 voff 2 sw vcsp model sibmod ron 216 5 0 1 von 2 voff 6 2 Sw vcsp model s2amod 16 5 roff 0 1 von 0 5 voff 0 5 Sw vcsp
5. FIGURE 21 SWITCHING TIME TEST CIRCUIT Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature T jy and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation Ppp in an application Therefore the application s ambient temperature C and thermal resistance C W must be reviewed to ensure that T jy is never exceeded Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part EQ 1 In using surface mount devices such as the SOP 8 package the environment in which it is applied will have a significant influence on the part s current and maximum power dissipation ratings Precise determination of Ppy is complex and influenced by many factors 1 Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board Ig REF 0 FIGURE 20 GATE CHARGE WAVEFORMS PULSE WIDTH FIGURE 22 SWITCHING TIME WAVEFORMS The number of copper layers and the thickness of the board The use of external heat sinks The use of thermal vias Air flow and board orientation For non steady state applications the pulse width the duty cycle and the transient thermal response of the part the board and the environment they are in Intersil provides thermal information to assist the des
6. model s2bmod 16 5 roff 0 1 von 0 5 voff 0 5 c ca n12 n8 4 95e 10 c cb n15 n14 5 15e 10 c cin n6 n8 2 9e 10 d dbody n7 n71 model dbodymod d dbreak n72 n11 model dbreakmod d dplcap n10 n5 2 model dplcapmod iit n8 n17 2 1 l Idrain n2 n5 1e 9 I gate n1 n9 9 2e 10 l lsource n3 n7 3 2e 10 m mmed n16 n6 n8 n8 model mmedmod I 1u w 1u m mstrong n16 n6 n8 n8 model mstrongmod I21u w 1u m mweak n16 n21 n8 n8 model mweakmod I 1u w 1u res rbreak n17 n18 1 tc1 9 94e 4 tc2 9 84e 8 res rdbody n71 n5 1 47e 2 tc1 1 7e 3 tc2 4e 5 res rdbreak n72 n5 3 94e 1 tc1 9 94e 4 tc2 9 12e 7 res rdrain n50 n16 9e 3 tc1 8e 3 tc2 5 3e 5 res rgate n9 n20 3 39 res rldrain n2 n5 10 res rlgate n1 n9 9 2 res rlsource n3 n7 3 2 res rsic1 n5 n51 1e 6 tc1 1e 3 tc2 1e 6 res rsic2 n5 n50 1e3 res rsource n8 n7 22e 3 tc1 1e 3 tc2 0 res rvtemp n18 n19 1 tc1 1 5 3 tc2 1 7e 6 res rvthres n22 n8 1 tc1 1 87 3 tc2 1 2e 6 n11 n7 n17 n18 33 87 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 Spe evtemp n20 n6 n18 n22 1 spe evthres n6 n21 n19 n8 1 Sw vcsp s1a n6 n12 n13 n8 model s1amod vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod Sw vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 gt n50 iscl iscl v
7. n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 42 6 All Intersil semiconductor products are manufactured assembled and tested under ISO9000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site www intersil com 11 intersil HUF76105DK8 MS 012AA 8 LEAD JEDEC MS 012AA SMALL OUTLINE PLASTIC PACKAGE A INCHES MILLIMETERS 1 SYMBOL MIN MAX MIN MAX NOTES A 00532 00688 135 175 A1 0 004 0 0098 0 10 0 25 b 0 013 0 020 0 33 0 51 0 0075 0 0098 0 19 0 25 D 0 189 0 1968 4 80 5 00 2 E 0 2284 0 244 5 80 6 20 E4 0 1497 0 1574 3 80 4 00 3 e 0 050 BSC 1 27 BSC H 0 0099 0 0196 0 25 0 50 L 0 016 0 050 0 40 1 27 4 NOTES
8. nC Gate to Source Gate Charge Qgs 5 1 00 nC Gate to Drain Miller Charge 2 40 nC CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Vas OV 325 pF f 1MHz Output Capacitance Coss Figure 13 180 Reverse Transfer Capacitance Crss 5 35 5 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 5A 1 25 V Isp 1 4 1 00 V Reverse Recovery Time trr Isp 1 4A dlsp dt 100A us x 5 39 ns Reverse Recovered Charge Isp 1 4A digp dt 100A us 42 nc Typical Performance Curves 1 2 6 tr a 10 5 Vas 10V RgJA 509C W 5 2 08 24 5 E 06 3 z 9 4 a 04 2 m 02 1 Ves 4 5 Rega 228 C W amp 0 0 0 25 50 75 100 125 150 25 50 75 100 125 150 TA AMBIENT TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE TA AMBIENT TEMPERATURE C AMBIENT TEMPERATURE FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs 3 intersil HUF76105DK8 Typical Performance Curves Continued
9. x 1 All dimensions are within allowable dimensions of Rev C of CONSER 0 004 IN JEDEC MS 012AA outline dated 5 90 0 10 mm 2 Dimension D does not include mold flash protrusions or gate 09 89 burrs Mold flash protrusions or gate burrs shall not exceed 0 006 inches 0 15mm per side 3 Dimension E4 does not include inter lead flash or protrusions Inter lead flash and protrusions shall not exceed 0 010 inches 0 25mm per side 0 050 4 L is the length of terminal for soldering 1 27 5 The chamfer on the body is optional If itis not present a visual index feature must be located within the crosshatched area 6 Controlling dimension Millimeter 7 Revision 8 dated 5 99 4 0mm MINIMUM RECOMMENDED FOOTPRINT FOR 1 5mm SURFACE MOUNTED APPLICATIONS DIA HOLE USER DIRECTION OF FEED 2 0mm 1 75mm TT LEN 58505955999 T E 7 GE gr E 8 0mm 4 40mm MIN ACCESS HOLE gt 18 4 COVER r 13mm 330mm 50mm ii GENERAL INFORMATION gt 12 4mm 1 2500 PIECES PER REEL 2 ORDER IN MULTIPLES OF FULL REELS ONLY 3 MEETS EIA 481 REVISION A SPECIFICATIONS 12 intersil
10. 8T S1 1 G1 2 D2 6 D2 5 2 3 G2 4 Packaging JEDEC MS 012AA BRANDING DASH 5 1 2 3 4 1 CAUTION These devices are sensitive to electrostatic discharge follow proper ESD Handling Procedures UltraFET is a registered trademark of Intersil Corporation PSPICEG is a registered trademark of MicroSim Corporation SABER is a trademark of Analogy Inc 1 888 INTERSIL or 321 724 7143 Intersil and Design is a trademark of Intersil Corporation Copyright Intersil Corporation 2000 HUF76105DK8 Absolute Maximum Ratings 25 C Unless Otherwise Specified Drain to Source Voltage Note 1 Vpss Drain to Gate Voltage Ras 20kQ Note 1 VDGR Gate to Source Voltage tng dette pore rape Bo Sed rents Vas Drain Current Continuous 25 Vas 10V Figure 2 Note 2 Ip Continuous 100 C Vas 5V Note 3 Ip Continuous 100 C Vas 4 5V Note 3 Ip Pulsed Drain G trent mes dx teres en es e TER ite E Bons e RAE Pulsed Avalanche Ratifg mb V ode a d RIDERS EAS Power Dissipation Note 2 Pp Derate Above 2596 ot tek ne ba CU EI EB E e IRA A Operating and Storage Ty Maximum Temp
11. LIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 5 intersil HUF76105DK8 Typical Performance Curves Continued 600 10 Ves OV f 1MHz 5 Ciss Cas iu 500 Cap 1 9 8 Coss Cps Cap 5 ui 400 9 6 5 g 300 5 Q 8 4 a amp 200 w WAVEFORMS IN 2 4 5 DESCENDING ORDER 100 e Ip 5A E D 9 Ip 1 4A 0 0 0 30 0 2 4 6 8 10 Vps DRAIN TO SOURCE VOLTAGE V GATE CHARGE nC NOTE Refer to Intersil Application Notes AN7254 and AN7260 FIGURE 13 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 60 120 Ves 4 5V Vpp 15V Ip 1 3A 11 50 Ves 10V Vpp 15V Ip 5A 3Q ta oFF td OFF 45 90 9 30 S 60 5 15 30 t 0 0 f 0 10 20 30 40 50 0 10 20 30 40 50 Ras GATE TO SOURCE RESISTANCE 0 Ras GATE TO SOURCE RESISTANCE 0 FIGURE 15 SWITCHING TIME vs GATE RESISTANCE FIGURE 16 SWITCHING TIME vs GATE RESISTANCE Test Circuits and Waveforms Vps BVpss VARY tp TO OBTAIN REQUIRED PEAK lAs Vas tp ov tav FIGURE 17 UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18 UNCLAMPED ENERGY WAVEFORM 6 intersil HUF76105DK8 Test Circuits and Waveforms Continued Vps Ig REF FIGURE 19 GATE CHARGE TEST CIRCUIT Vps Vas DUT
12. Vas 5V Figure 9 0 055 0 072 Q Ip 1 3A Vas 4 5V Figure 9 0 060 0 078 Q THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RoJA Pad Area 0 76 in Note 2 50 C W Pad Area 0 027 in See TB377 5 191 C W Pad Area 0 006 in See TB377 228 C W SWITCHING SPECIFICATIONS Vcs 4 5V Turn On Time toN Vpp 15V Ip 1 3A 60 ns Turn On Delay Time im s Vas c 49V 12 ns Rise Time tr Figure 15 28 ns Turn Off Delay Time td OFF 31 ns Fall Time tf 21 ns Turn Off Time tOFF 80 ns 2 intersil HUF76105DK8 Electrical Specifications 25 C Unless Otherwise Specified Continued PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SWITCHING SPECIFICATIONS Vas 10V Turn On Time ton Vpp 15V Ip 5A 5 60 ns 7 Ri 30 Vas 10V Turn On Delay Time td ON Ras 270 17 ns Rise Time t Figure 16 21 ns Turn Off Delay Time td OFF 60 ns Fall Time 20 ns Turn Off Time toFF 120 ns GATE CHARGE SPECIFICATIONS Total Gate Charge QgtoTt Vas 0Vto 10 Vpp 15V Ip 1 4 9 11 nC Ri 10 72 Gate Charge at 5V Qg 5 Vas OV to 5V 1 0mA 5 3 6 4 nC Threshold Gate Charge QgrH Vas 0Vto1V Figure 14 0 35 0 45
13. erature for Soldering Leads at 0 063in 1 6mm from Case for 106 TL Package Body for 10s See Techbrief 334 Tpkg HUF76105DK8 30 30 16 5 14 1 3 Figure 4 Figures 6 17 18 2 5 0 02 55 to 150 300 260 UNITS W C C 96 CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 Ty 25 to 125 C 2 509C W measured using FR 4 board at 1 second 3 2289C W measured using FR 4 board with 0 006 in of copper at 1000 seconds Electrical Specifications 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss 250 Vas OV Figure 12 30 V Zero Gate Voltage Drain Current Ipss Vps 25V Vas 0V 1 uA Vps 25V Vas OV 150 C 250 Gate to Source Leakage Current lass Vas 16 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH Vas Ip 250pA Figure 11 1 3 V Drain to Source On Resistance lp 5A Vas 10V Figures 9 10 0 040 0 050 Ip 1 4A
14. igner s preliminary application evaluation Figure 23 defines the for the device as a function of the top copper component side area This is for a horizontally positioned FR 4 board with 102 copper after 1000 seconds of steady state power with no air flow This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve w Displayed on the curve are Ray values listed in the Electrical Specifications table The points were chosen to depict the compromise between the copper board area the thermal resistance and ultimately the power dissipation 7 intersil HUF76105DK8 Thermal resistances corresponding to other copper areas can be obtained from Figure 23 or by calculation using Equation 2 Rey is defined as the natural log of the area times a coefficient added to a constant The area in square inches is the top copper area including the gate and source pads Roya 103 2 243 In Area EQ 2 Rosa 103 2 24 3 In AREA Rosa CCW 0 001 0 01 0 1 1 AREA TOP COPPER AREA in PER DIE FIGURE 23 THERMAL RESISTANCE vs MOUNTING PAD AREA While Equation 2 describes the thermal resistance of a single die several of the
15. new UltraFETs are offered with two die in the SOP 8 package The dual die SOP 8 package introduces an additional thermal component thermal coupling resistance Equation 3 describes Reg asa function of the top copper mounting pad area Reg 46 4 217 x In Area EQ 3 The thermal coupling resistance vs copper area is also graphically depicted in Figure 23 It is important to note the thermal resistance Raya and thermal coupling resistance are equivalent for both die For example at 0 1 square inches of copper ReJA2 159 C W Rop2 979C W and T jo define the junction temperature of the respective die Similarly P4 and Po define the power dissipated in each die The steady state junction temperature can be calculated using Equation 4 for die 1and Equation 5 for die 2 Example Use Equation 4 to calculate Ty and Equation 5 to calculate T jo with the following conditions Die 2 is dissipating 0 5 Watts die 1 is dissipating 0 Watts the ambient temperature is 709C the package is mounted to a top copper area of 0 1 square inches per die PoRog TA EQ 4 Ty1 0 Watts 159 C W 0 5 Watts 97 C W 70 C 119 C Tyo PoRojatPyRopt Ta EQ 5 0 5 Watts 159 C W 0 Watts 97 C W 70 C 150 C The transient thermal impedance Zega is also effected by varied top copper board area Figure 24 shows the effect of coppe
16. r pad area on single pulse transient thermal impedance Each trace represents a copper pad area in square inches corresponding to the descending list in the graph SPICE and SABER thermal models are provided for each of the listed pad areas Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms For pulse widths less than 100ms the transient thermal impedance is determined by the die and package Therefore CTHERM through CTHERMS5 and RTHERM through RTHERM5 remain constant for each of the thermal models listing of the model component values is available in Table 1 160 COPPER BOARD AREA DESCENDING ORDER 0 020 in 0 140 in 120 0 257 2 0 380 in 80 Zoya THERMAL IMPEDANCE 9C W t RECTANGULAR PULSE DURATION s FIGURE 24 THERMAL RESISTANCE vs MOUNTING PAD AREA 8 intersil HUF76105DK8 SPICE Thermal Model REV June 1998 HUF76105DK8 Copper Area 0 02 in CTHERM1 th 8 8 5e 4 CTHERM 8 7 1 8 3 CTHERNG 7 6 5 0 3 CTHERMA 6 5 1 3e 2 CTHERMS 5 4 4 0e 2 CTHERM6 4 3 9 0e 2 CTHERM7 3 2 4 0e 1 CTHERM8 2 tl 1 4 RTHERM1 th 8 3 5e 2 RTHERM2 8 7 6 0e 1 RTHERMS 7 62 RTHERM4 6 58 RTHERMS 5 4 18 6 4 3 39 3 2 42 RTHERM8 2 tl 48 SABER Thermal Model Copper Area 0 02 in template thermal model th tl thermal c th tl ctherm ctherm1 th 8 8 5e 4 cthe
17. rm ctherm2 8 7 1 8e 3 ctherm ctherm3 7 6 5 0e 3 ctherm ctherm4 6 5 1 3e 2 ctherm ctherm5 5 4 4 0e 2 ctherm ctherm6 4 3 9 0e 2 ctherm ctherm7 3 2 4 0e 1 ctherm ctherm8 2 tl 1 4 rtherm rtherm1 th 8 3 5e 2 rtherm rtherm2 8 7 6 0e 1 rtherm rtherm3 7 6 2 2 rtherm rtherm4 6 5 8 rtherm rtherm5 5 4 18 rtherm rtherm6 4 3 39 rtherm rtherm7 3 2 42 rtherm rtherm8 2 tl 48 RTHERM1 RTHERM2 RTHERM3 RTHERM4 RTHERM5 RTHERM6 RTHERM7 RTHERM8 TABLE 1 THERMAL MODELS JUNCTION CTHERM1 CTHERM2 CTHERM3 CTHERM4 5 CTHERM6 CTHERM7 CTHERM8 COMPONENT CTHERM6 0 02 in 9 0e 2 0 14 in 1 3e 1 0 257 in 1 5e 1 0 493 in 1 5e 1 CTHERM7 4 0e 1 6 0e 1 4 5e 1 7 5e 1 CTHERM8 1 4 2 5 2 2 3 RTHERM6 39 26 20 20 RTHERM7 42 32 31 23 RTHERM8 48 35 38 25 9 intersil HUF76105DK8 PSPICE Electrical Model SSUBCKT HUF76105213 June 1998 CA 12 8 4 95e 10 CB 15 14 5 15e 10 LDRAIN CIN 6 82 9e 10 DPLCAP 5 ip DRAIN o2 10 DBODY 7 5 DBODYMOD RSLC1 HEDRAIN DBREAK 5 11 DBREAKMOD 51 DBREAK DPLCAP 10 5 DPLCAPMOD RSLC2 ESLC 11 EBREAK 11 7 17 18 33 87 50 EDS 14 8 5 81 EGS 138 6 81 RDRAIN DBODY ESG 6 106 8 1 ESG EBREAK EVTHRES 6 21 198 1 P EVTHRES FRUI z EVTEMP 20 6 18 22 1 MWEAK LGATE EVTEMP GATE RGATE 6
18. s Continued 25 PULSE DURATION 8015 DUTY CYCLE 0 5 MAX 25 C Vpp 15V 20 lt x E 1509 15 gt z 10 c a a 5 0 0 1 2 3 4 5 Vas GATE TO SOURCE VOLTAGE V FIGURE 7 TRANSFER CHARACTERISTICS 110 Ip 5A PULSE DURATION 250us DUTY CYCLE 0 5 MAX 90 c 2 E e z i5 Sa oz 5 2 4 6 8 10 Vas GATE TO SOURCE VOLTAGE V FIGURE 9 DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 1 2 T T Ves Vps lp 2504A gt to NORMALIZED GATE THRESHOLD VOLTAGE e 80 40 0 40 80 120 160 Ty JUNCTION TEMPERATURE C FIGURE 11 NORMALIZED THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 25 20 15 Ip DRAIN CURRENT A PULSE DURATION 8015 DUTY CYCLE 0 5 MAX TA 25 C Vps DRAIN TO SOURCE VOLTAGE V FIGURE 8 SATURATION CHARACTERISTICS 18 PULSE DURATION 8015 DUTY CYCLE 0 5 MAX 16 Ves 10V Ip 5A ON RESISTANCE NORMALIZED DRAIN TO SOURCE 80 40 0 40 80 120 160 Ty JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE Ip 250 1 05 e to a NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 80 40 0 40 80 120 160 Ty JUNCTION TEMPERATURE C FIGURE 12 NORMA
Download Pdf Manuals
Related Search