FAIRCHILD HUF75945G3 HUF75945P3 HUF75945S3ST handbook
Contents
1. w SEMICONDUCTOR Data Sheet HUF75945G3 HUF75945P3 HUF75945S3ST December 2001 38A 200V 0 071 Ohm N Channel UltraFET Power MOSFETs Packaging JEDEC TO 247 SOURCE DRAIN GATE DRAIN TAB JEDEC TO 220AB JEDEC TO 263AB SOURCE DRAIN DRAIN FLANGE GATE GATE DRAIN 4 ALL FLANGE Symbol D G S Absolute Maximum Ratings Tc 25 Unless Otherwise Specified Drain to Source Voltage Note 1 Drain to Gate Voltage Ras 20kQ Note 1 Gate lo Source Voltage iis ws x ER RS e ERU dud Drain Current Continuous Tc 25 C Ves 10V Figure 2 Continuous 100 C Vas 10V Figure 2 Pulsed Drain Pulsed Avalanche Rating Power Dissipation 5565 ht x GER WR s Derate Above 259 Operating and Storage Temperature Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case for 106 Package Body for 10s See Techbrief 334 NOTES 1 Ty 25 C to 150 C Features e Ultra Low On Resistance DS ON 0 0710 Vas 10V e Simulation Models Temperature Compensated PSPICE and SABER Electr2. 2 6 5 3 00e 2 CTHERMS 5 4 1 40e 2 CTHERMA 4 3 1 65e 2 5 2 4 85e 2 CTHERM6 2 tl 1 00e 1 RTHERM th 6 3 24e 3 RTHERM2 6 5 8 08e 3 RTHERMS 5 4 2 28e 2 RTHERMA 4 3 1 00e 1 RTHERM5 2 1 10e 1 RTHERM6 2 tl 1 40e 1 SABER Thermal Model SABER thermal model HUF75945T template thermal_model th tl thermal_c th tl ctherm ctherm1 th 6 6 45e 3 ctherm ctherm2 6 5 3 00e 2 ctherm ctherm3 5 4 1 40e 2 ctherm ctherm4 4 3 1 65e 2 ctherm ctherm5 2 4 85e 2 ctherm ctherm6 2 tl 1 00e 1 rtherm rtherm1 th 6 3 24e 3 rtherm rtherm2 6 5 8 08e 3 rtherm rtherm3 5 4 2 28e 2 rtherm rtherm4 4 3 1 00e 1 rtherm rtherm5 2 1 10e 1 rtherm rtherm6 2 tl 1 40e 1 2001 Fairchild Semiconductor Corporation RTHERM1 RTHERM2 RTHERM3 RTHERM4 RTHERM5 RTHERM6 CASE CTHERM1 CTHERM2 CTHERM3 CTHERM4 5 CTHERM6 HUF75945G3 HUF75945P3 HUF75945S3ST Rev B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks ACEx FAST OPTOLOGIC SMART START VCX Bottomless FASTr OPTOPLANAR STAR POWER CoolFET FRFET PACMAN Stealth CROSSVOLT GlobalOptoisolator POP SuperSOT 3 DenseTrench GTO Power247 SuperSOT 6 DOME HiSeC PowerTrench 9 SuperSOT 8 EcoSPARK ISOPLANAR QFET
3. MODEL DBODYMOD D IS 2 8e 12 RS 3 0e 3 XTI 5 5 TRS1 3 5e 3 TRS2 16 5 CJO 2 55e 9 TT 1 52e 7 M 0 42 MODEL DBREAKMOD D RS 1 2e OTRS1 1e 3TRS2 1e 6 MODEL DPLCAPMOD D 4 6e 915 1e 30 N 10 0 9 MODEL MMEDMOD NMOS VTO 3 05 KP 2 5 IS 1e 30 N 10 TOX 1L 1u W 1u RG 0 77 MODEL MSTROMOD NMOS VTO 3 55 KP 100 IS 1 30 N 10 TOX 1L 2 dluW 1u MODEL MWEAKMOD NMOS VTO 2 69 KP 0 05 IS 1e 30 N 10 TOX 1 L 1u W lu RG 7 70 MODEL RBREAKMOD RES TC1 1 27e 2 1 0e 6 MODEL RDRAINMOD RES TC1 9 90e 3 TC2 3 60e 5 MODEL RSLCMOD RES TC1 3 0e 3 TC2 1 0e 6 MODEL RSOURCEMOD RES TC1 1e 3 TC2 1e 6 MODEL RVTHRESMOD RES TC1 2 90e 3 TC2 1 10e 5 MODEL RVTEMPMOD RES TC1 2 80e 3TC2 1 70 7 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH MODEL S2AMOD VSWITCH MODEL S2BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 5 5 VOFF 4 5 RON 1e 5 ROFF 0 1 VON 4 5 VOFF 5 5 RON 1e 5 ROFF 0 1 VON 0 3 0 4 RON 1e 5 ROFF 0 1 VON 0 4 VOFF 0 3 ENDS NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 2001 Fairchild Semiconductor Corporation HUF75945G3 HUF75945P3 HUF75945S3ST Rev B HUF75945G3 HUF7
4. Advance Information Formative or This datasheet contains the design specifications for In Design product development Specifications may change in any manner without notice Preliminary First Production This datasheet contains preliminary data and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design No Identification Needed Full Production This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only Rev H4
5. Drain to Source Breakdown Voltage BVpss Ip 250uA Ves OV Figure 11 200 V Zero Gate Voltage Drain Current Ipss Vps 190V Vas 0V 1 Vps 180V Ves OV Tc 150 C 250 Gate to Source Leakage Current lass Vas 20 100 ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH VGs Vps Ip 250 Figure 10 2 4 V Drain to Source On Resistance DS ON p 38A 10V Figure 9 0 056 0 071 THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RoJC TO 247 TO 220 TO 263 0 48 9C W Thermal Resistance Junction to RoJA TO 247 30 C W TO 220 263 62 C W SWITCHING SPECIFICATIONS Ves 10V Turn On Time ton Vpp 100V Ip 38A 2 33 ns Turn On Delay Time E E 15 ns Rise Time ir Figures 18 19 64 ns Turn Off Delay Time td OFF 65 ns Fall Time tf 80 ns Turn Off Time 217 ns GATE CHARGE SPECIFICATIONS Total Gate Charge Qg rTOT Vas OV to 20V Vpp 100V 215 280 nC Gate Charge at 10V Qgio Ves OV to 10V Ma 118 153 nC Threshold Gate Charge Qg TH Vas OV to 2V Figures 13 16 17 8 10 nC Gate to Source Gate Charge Qgs 15 nC Gate to Drain Miller Charge 42 nC CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Ves 4023 pF Output Capacitance Coss gt 880 pF Reverse Transfer Capacitance Crss 240 Source to Drain Diode Specifications P
6. FIGURE 18 SWITCHING TIME TEST CIRCUIT FIGURE 19 SWITCHING TIME WAVEFORM 2001 Fairchild Semiconductor Corporation HUF75945G3 HUF75945P3 HUF75945S3ST Rev B HUF75945G3 HUF75945P3 HUF75945S3ST PSPICE Electrical Model SUBCKT HUF75945 213 CA 12 8 6 6e 9 CB 15 14 6 5e 9 CIN 6 8 3 80e 9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 221 EDS 14 8 5 81 EGS 138 6 81 ESG 6 106 8 1 EVTHRES 6 21 198 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1 0e 9 LGATE 1 9 8 05e 9 LSOURCE 3 7 5 8e 9 GATE 1 MMED 16 6 8 8 MMEDMOD MSTRO 16688 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 5 0e 2 RGATE 9 20 0 77 RLDRAIN 2 5 10 RLGATE 1 9 80 5 rev 13 October 2000 LDRAIN DPLCAP 5 RLDRAIN DRAIN o 2 51 DBREAK RSLC2 ESLC 11 50 RDRAIN aD EAE MMED I MSTRO o b EVTHRES DBODY EVTEMP MWEAK LGATE 9 20 RLGATE LSOURCE 8 SOURCE 3 CIN RSOURCE RLSOURCE S1A 12 RBREAK 13 14 a 13 17 18 RLSOURCE 3 7 58 RSLC1 5 51 RSLCMOD 1e 6 T RSLC2 5 50 1e3 CA 19 RSOURCE 8 7 RSOURCEMOD 1 8e 3 14 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 RVTEMP 19 9 S2B 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD 52 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD 22 RVTHRES VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 100 2 5
7. 5945P3 HUF75945S3ST SABER Electrical Model REV 13 October 2000 template huf75945 n2 n1 n3 electrical n2 n1 n3 var i iscl dp model dbodymod isl 2 8e 12 rs 3 0e 3 xti 5 5 trs1 3 5e 3 trs2 1 0e 5 cjo 2 55e 9 tt 1 52e 7 m 0 42 dp model dbreakmod rs 1 2 trs1 1 0 3 trs2 1 0 6 dp model dplcapmod cjo 4 9 isl 10e 30 10 m 0 9 m model mmedmod n vto 3 05 kp 2 5 is 1e 30 tox 1 m model mstrongmod type n vto 3 55 kp 100 is 1e 30 tox 1 m model mweakmod type n vto 2 69 kp 0 05 is 1e 30 tox 1 rs 0 1 sw vcsp model s1amod 16 5 roff 0 1 von 5 5 voff 4 5 LDRAIN sw vcsp model s1bmod ron 1 5 roff 0 1 von 4 5 voff 5 5 DPLCAP 5 Yer DRAIN Sw vcsp model s2amod ron 1e 5 0 1 von 0 3 voff 0 4 10 2 sw vcsp model s2bmod 16 5 roff 0 1 von 0 4 voff 0 3 RLDRAIN RSLC1 n12 n8 6 6e 9 51 c cb n15 n14 6 5e 9 RSLC2 c cin n6 n8 3 8e 9 ISCL dp dbody n7 n5 model dbodymod 50 DOSES dp dbreak n5 n11 model dbreakmod RDRAIN dp dplcap n10 n5 model dplcapmod ESG 11 hs EVTHRES DBODY i it n8 n17 2 1 LGATE EVTEMP I MWEAK I drain n2 n5 1 00e 9 e 6 MED l gate n1 n9 8 05 9 9 20 lsource n3 n7 5 80e 9 RLGATE I 4MSTRO 1 LSOURCE m mmed n16 n8 n8 model mmed
8. ARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 38A 1 25 V Isp 19A 1 00 V Reverse Recovery Time trr Isp 38A dlsp dt 100A us 281 ns Reverse Recovered Charge QRR Isp 38A dlsp dt 100A us 2700 nC 2001 Fairchild Semiconductor Corporation HUF75945G3 HUF75945P3 HUF75945S3ST Rev B HUF75945G3 HUF75945P3 HUF75945S3ST Typical Performance Curves tc LJ a E 23 2 LLI Q 2 o Tc CASE TEMPERATURE 9C Tc CASE TEMPERATURE FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE LLL I EHE WE a a ee ttt ttt T a 222 2 NORMALIZED THERMAL IMPEDANCE NOTES SINGLE PULSE A O O DUTY FACTOR D ty to 10 PEAK Tat Pom Zase Rases Te t RECTANGULAR PULSE DURATION s FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 1000 C O EEE EEK 4 j j l FOR TEMPERATURES ABOVE 259 DERATE CURRENT AS FOLLOWS PEAK CURRENT MAY LIMIT CURRENT EHH 103 t PULSE WIDTH s 10 FIGURE 4 PEAK CURRENT CAPABILITY 2001 Fairchild Semiconductor Corporation HUF75945G3 HUF75945P3 HUF75945S3ST Rev B HUF75945G3 HUF75945P3 HUF75945S3ST Typical P
9. E HUF75945G3 HUF75945P3 HUF75945S3ST Rev B HUF75945G3 HUF75945P3 HUF75945S3ST Typical Performance Curves Continued NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 80 40 0 40 80 120 160 200 Tj JUNCTION TEMPERATURE C FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE Ves GATE TO SOURCE VOLTAGE V 10000 sa 2 XD qilia Tr 1000 C CAPACITANCE pF 0 1 1 0 10 100 200 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE WAVEFORMS IN DESCENDING ORDER Ip 38A 10 Qg GATE CHARGE nC NOTE Refer to Fairchild Application Notes AN7254 AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms Vps VARY tp TO OBTAIN REQUIRED las Vas OV FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT 2001 Fairchild Semiconductor Corporation BVpss Vps 2 Vpp gt tav qe FIGURE 15 UNCLAMPED ENERGY WAVEFORMS HUF75945G3 HUF75945P3 HUF75945S3ST Rev B HUF75945G3 HUF75945P3 HUF75945S3ST Test Circuits and Waveforms continued Vps RL Ves 4 Vpp DUT lg REF lg REF 0 FIGURE 16 GATE CHARGE TEST CIRCUIT FIGURE 17 GATE CHARGE WAVEFORMS Vps toN toFF td ON ta OFF RL t Vps 90 Vas Lt Vpp 1096 DUT 90 Res Ves 50 PULSE WIDTH Vas d o 10
10. SyncFET E CMOS LittleFETTM QSTM TinyLogic EnSigna MicroFE TTM Optoelectronics Tru Translation FACT MicroPak Quiet Series UHC FACT Quiet Series MICROWIRE SILENT SWITCHER UltraFET9 STAR POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant into support device or system whose failure to perform can the body or b support or sustain life or whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can be effectiveness reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms
11. erformance Curves Continued 500 H SINGLE PULSE Ty MAX RATED T z oo Lil A sue tr tc gt O 5 10 OPERATION IN THIS 5 AREA MAY LIMITED BY 5 1 1 10 100 500 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 5 FORWARD BIAS SAFE OPERATING AREA PULSE DURATION 8015 DUTY CYCLE 0 5 MAX p Vpp 15V 2 cc cc gt O lt lt cc S Vas GATE TO SOURCE VOLTAGE V FIGURE 7 TRANSFER CHARACTERISTICS 3 5 PULSE DURATION 80us 3 0 F DUTY CYCLE 0 5 MAX L LA NN NN NE NORMALIZED DRAIN TO SOURCE ON RESISTANCE Ves 10V Ip 38A 80 40 0 40 80 120 160 200 Tj JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2001 Fairchild Semiconductor Corporation e z0 tav L lAs 1 3 RATED BVpss Vpp las AVALANCHE CURRENT A Ift RzO tav L R In las R 1 3 RATED BVpss Vpp 1 m 1 0 001 0 01 0 1 1 n tay TIME IN AVALANCHE ms NOTE Refer to Fairchild Application Notes AN9321 and AN9322 FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY Ip DRAIN CURRENT A PULSE DURATION 80us DUTY CYCLE 0 5 MAX Tc 25 C 0 1 2 3 4 5 6 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 8 SATURATION CHARACTERISTICS NORMALIZED GATE THRESHOLD VOLTAGE Ty JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATUR
12. ical Models Spice and SABER Thermal Impedance Models www fairchildsemi com e Peak Current vs Pulse Width Curve UIS Rating Curve Ordering Information PART NUMBER PACKAGE BRAND HUF75945G3 247 759450 HUF75945P3 TO 220AB 75945P HUF75945S3ST TO 263AB 759455 NOTE When ordering use the entire part number HUF75945G3 HUF75945P3 HUF75945S3ST UNITS T Vpss 200 V Tm VDGR 200 V Vas 20 V m ID 38 A rm ID 27 A 481 IDM Figure 4 PET UIS Figures 6 14 15 LU ave ete NE e S ERU Pp 310 W ee eee 2 07 w C PM Ty 55 to 175 C TR TL 300 oC Tpkg 260 9G CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied 2001 Fairchild Semiconductor Corporation HUF75945G3 HUF75945P3 HUF75945S3ST Rev B HUF75945G3 HUF75945P3 HUF75945S3ST Electrical Specifications T 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS
13. mod 1 1 w 1u 8 7 SOURCE m mstrong n16 n6 n8 n8 model mstrongmod l 1u w lu E o 3 m mweak n16 n21 n8 n8 model mweakmod l21u w 1u RSOURCE RLSOURCE res rbreak n17 n18 1 tc1 1 27e 3 tc2 1 00e 6 S1A 9 62 RBREAK res rdrain n50 n16 5 0 2 tcl 9 9e 3 tc2 3 6e 5 12 13 14 15 15 15 res rgate n9 20 0 77 8 13 res rldrain n2 n5 10 RVTEMP res rlgate n1 n9 80 5 218 13 eB res rlsource n3 n7 58 CA CB O 19 res rslc1 n5 n51 1 6 tcl 3e 3 tc2 1 0e 6 14 VEIT res rsic2 n5 n50 1e3 res rsource n8 n7 1 8e 3 tc1 1 0e 3 tc2 1e 6 e 2 t res rvtemp n18 n19 1 tcl 2 8e 3 tc2 1 70e 6 8 res rvthres n22 n8 1 tc1 2 9e 3 tc2 1 1e 5 22 RVTHRES spe ebreak n11 n7 n17 n18 221 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 spe evtemp n20 n6 n18 n22 1 spe evthres n6 n21 n19 n8 1 sw vcsp s1a n6 n12 n13 n8 model s1amod sw vcsp s b n13 n12 n13 n8 model s1bmod sw vcsp s2a n6 n15 n14 n13 model s2amod sw vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i 151 gt 50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 100 2 5 2001 Fairchild Semiconductor Corporation HUF75945G3 HUF75945P3 HUF75945S3ST Rev B HUF75945G3 HUF75945P3 HUF75945S3ST SPICE Thermal Model JUNCTION REV 13 October 2000 th HUF75945T CTHERM th 6 6 45e 3
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