intersil HUF75831SK8 handbook
Contents
1. A INCHES MILLIMETERS 1 SYMBOL MIN MAX MIN MAX NOTES A 00532 00688 135 175 A1 0 004 0 0098 0 10 0 25 b 0 013 0 020 0 33 0 51 0 0075 0 0098 0 19 0 25 D 0 189 0 1968 4 80 5 00 2 0 2284 0 244 5 80 6 20 Ey 0 1497 0 1574 3 80 4 00 3 0 050 BSC 1 27 BSC H 0 0099 0 0196 0 25 0 50 L 0 016 0 050 0 40 1 27 4 NOTES x 1 All dimensions are within allowable dimensions of Rev C of CONSER 0 004 IN JEDEC MS 012AA outline dated 5 90 0 10 mm 2 Dimension D does not include mold flash protrusions or gate 09 89 burrs Mold flash protrusions or gate burrs shall not exceed 0 006 inches 0 15mm per side 3 Dimension E4 does not include inter lead flash or protrusions Inter lead flash and protrusions shall not exceed 0 010 inches 0 25mm per side Ey A 0 050 4 I is the length of terminal for soldering 1 27 5 The chamfer on the body is optional If itis not present a visual index feature must be located within the crosshatched area 6 Controlling dimension Millimeter 7 Revision 8 dated 5 99 4 0mm MINIMUM RECOMMENDED FOOTPRINT FOR 1 5mm SURFACE MOUNTED APPLICATIONS DIA HOLE USER DIRECTION OF FEED 2 0mm 1 75mm TT LEN 58505955999 T E 7 GE gr E 8 0mm 4 40mm MIN ACCESS HOLE gt 18 4 r 13mm 330mm 50 ii GENERAL INFORMATION gt 12 42. UIS Figures 6 14 15 Power DISSIpatlOIn PRAGA dig 2 5 Ww Derate Above 259 C Ludos oi RETRO ERR E bU ees Ex equas 20 mW C Operating and Storage Ty 55 to 150 C Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case for 106 TL 300 oc Package Body for 10s See Tech 70 Tpkg 260 C NOTES 1 Ty 25 C to 125 C 2 50 C W measured using FR 4 board with 0 76 in 490 3 mm copper pad at 10 second 3 1529C W measured using FR 4 board with 0 054 in 34 8 mm copper pad at 1000 seconds 4 1899C W measured using FR 4 board with 0 0115 in 7 42 mm copper pad at 1000 seconds CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied 1 CAUTION These devices are sensitive to electrostatic discharge Follow proper ESD Handling Procedures UltraFET is a trademark of Intersil Corporation PSPICE is a registered trademark of MicroSim Corporation SABER is a Copyright of Analogy Inc 1 888 INTERSIL or 321 724 7143 Intersil and Design is a trademark o
3. 2 0 90 10 80 40 0 40 80 120 160 0 1 1 0 10 150 Ty JUNCTION TEMPERATURE C Vps DRAIN TO SOURCE VOLTAGE V FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE VOLTAGE vs JUNCTION TEMPERATURE 10 8 9 6 2 o o d WAVEFORMS DESCENDING ORDER o 2 Ip 1 Ip 0 5A gt 0 0 10 20 30 40 Qg GATE CHARGE nC NOTE Refer to Intersil Application Notes AN7254 and AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms Vps BVpss VARY tp TO OBTAIN REQUIRED PEAK lAs Vas tp ov gt tav FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15 UNCLAMPED ENERGY WAVEFORMS 5 intersil HUF75831SK8 Test Circuits and Waveforms continued Ig REF FIGURE 16 GATE CHARGE TEST CIRCUIT DUT FIGURE 18 SWITCHING TIME TEST CIRCUIT Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature T and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation in an application Therefore the application s ambient temperature TA C and thermal resistance RA C W must be reviewed to ensure that T jy is never exceeded Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part EQ 1 In using surface mount devices such as the SOP 8
4. OV to 10V unes 1 0mA 35 42 nC Threshold Gate Charge QgrH Vas OV to 2V Figures 13 16 17 24 2 9 nC Gate to Source Gate Charge Qgs 4 3 nC Gate to Drain Miller Charge 11 nC CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Ves OV 5 1175 pF Output Capacitance Coss i 2 275 pF Reverse Transfer Capacitance Crss 72 E pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 1 25 V 1 5A 5 1 00 V Reverse Recovery Time trr Isp digp dt 100A us 5 E 132 ns Reverse Recovered Charge QRR Isp digp dt 100A us 380 nC 2 intersil HUF75831SK8 Typical Performance Curves POWER DISSIPATION MULTIPLIER Zgja NORMALIZED Ibm PEAK CURRENT A 1 2 4 10V Rega 50 C W 1 0 0 8 ul tc ac 0 6 o z E 0 4 81 0 2 0 0 0 25 50 75 100 125 150 25 50 75 100 125 150 AMBIENT TEMPERATURE C Ta AMBIENT TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE FIGURE 2 MAXIMUM C
5. 2 2715 3029 12 intersil
6. Feb 2000 HUF75831SK8 Copper Area 0 04 in CTHERM th 8 2 0e 3 CTHERM 8 7 5 0e 3 th JUNCTION CTHERMB 7 6 1 0e 2 RTHERM1 CTHERM1 CTHERM4 6 5 4 0e 2 5 5 4 9 0e 2 CTHERM6 4 3 1 2e 1 CTHERM7 3 2 0 5 CTHERMB 2 tl 1 3 2 CTHERM2 RTHERM1 th 8 0 1 2 8 7 0 5 RTHEBM E 61 0 RTHERM3 CTHERM3 RTHERM4 6 5 5 0 RTHERMB 5 4 8 0 RTHERMG 4 3 26 RTHERM7 3 2 39 RTHERM8 2 tl 55 RTHERM4 CTHERM4 SABER Thermal Model Copper Area 0 04 in template thermal model th tl 5 5 thermal_c th tl ctherm ctherm1 th 8 2 0e 3 ctherm ctherm2 8 7 5 0e 3 ctherm ctherm3 7 6 1 0e 2 RTHERM6 CTHERM6 ctherm ctherm4 6 5 4 0e 2 ctherm ctherm5 5 4 9 0e 2 ctherm ctherm6 4 3 1 2e 1 ctherm ctherm7 3 2 0 5 THERME ctherm ctherm8 2 tl 1 3 rtherm rtherm1 th 8 0 1 rtherm rtherm2 8 7 0 5 rtherm rtherm3 7 6 1 0 RTHERM8 8 rtherm rtherm4 6 5 5 0 rtherm rtherm5 5 4 8 0 rtherm rtherm6 4 3 26 rtherm rtherm7 3 2 39 rtherm rtherm8 2 tl 55 TABLE 1 THERMAL MODELS COMPONENT 0 04 in 0 28 in 0 52 in 0 76 in 1 0 in CTHERM6 1 2e 1 1 5e 1 2 0e 1 2 0e 1 2 0e 1 CTHERM7 0 5 1 0 1 0 1 0 1 0 CTHERM8 1 3 2 8 3 0 3 0 3 0 RTHERM6 26 20 15 13 12 RTHERM7 39 24 21 19 18 RTHERM8 55 38 7 31 3 29 7 25 10 intersil HUF75831SK8 MS 012AA 8 LEAD JEDEC MS 012AA SMALL OUTLINE PLASTIC PACKAGE
7. 9 10 feqMMeD EBREAK Ligate n1 n9 1 12e 9 9 20 n3 n7 1 29e 10 RLGATE CIN LSOURCE oe m mmed n16 n6 n8 n8 model mmedmod 1 w 1u 8 7 SE 53 m mstrong n16 n6 n8 n8 model mstrongmod I21u w 1u RSOURCE m mweak n16 n21 n8 n8 model mweakmod I 1u w 1u RLSOURCE res rbreak n17 n18 1 tc1 9 97 4 tc2 5 07 7 ls ak RBREAK res rdrain n50 116 5 80 2 tc1 8 52e 3 tc2 2 44e 5 17 18 res rgate 9 20 1 95 n2 n5 10 S1B o 52 res rigate n1 n9 11 2 13 CB 19 res rlsource n3 n7 1 29 CA 14 IT 4 res rsic1 n5 n51 1e 6 tcl 3 28e 3 tc2 0 p VBAT res rsic2 n5 n50 1e3 EGS EDS res rsource n8 n7 2 20e 3 1 00e 3 tc2 0 M res rvtemp n18 n19 1 tc1 3 08e 3 tc2 0 8 dd res rvthres n22 n8 1 tcl 2 08e 3 tc2 8 86e 6 RVTHRES Spe ebreak n11 n7 n17 n18 2 155 4 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 Spe evtemp n20 n6 n18 n22 1 Spe evthres n6 n21 n19 n8 1 Sw vcsp s1a n6 n12 n13 n8 model s1amod vcsp sib n13 n12 n13 n8 model s1bmod vcsp s2a n6 n15 n14 n13 model s2amod Sw vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 40 2 9 intersil HUF75831SK8 SPICE Thermal Model REV 02
8. CER HUF75831SK8 Data Sheet March 2000 File Number 4796 1 3A 150V 0 095 Ohm N Channel UltraFET Power MOSFET Packaging JEDEC MS 012AA Features BRANDING DASH Ultra Low On Resistance TDS ON 0 0950 Vas 10V 5 Simulation Models Temperature Compensated and SABER 2 Electrical Models 3 4 Spice and SABER Thermal Impedance Models www intersil com Peak Current vs Pulse Width Curve Symbol UIS Rating Curve SOURCE 1 DRAIN 8 Ordering Information DRAIN 7 PART NUMBER PACKAGE BRAND DRAIN 6 HUF75831SK8 MS 012AA 75831SK8 DRAIN 5 SOURCE 2 SOURCE 3 GATE 4 NOTE When ordering use the entire part number Add the suffix T to obtain the variant in tape and reel e g HUF75831SK8T Absolute Maximum Ratings 25 C Unless Otherwise Specified HUF75831SK8 UNITS Drain to Source Voltage Note 1 Vpss 150 V Drain to Gate Voltage Ras 20kQ Note 1 VDGR 150 V Gate to Source Voltage ese ere uer een vedi aci et duce Rer esie ean gua Vas 20 V Drain Current Continuous Ta 25 C Vas 10V Figure 2 Ip 3 A Continuous 100 C Vas 10V Figure 2 Ip 2 A Pulsed Drain C rrent ie eee ehh term ex mee Re i end IDM Figure 4 Pulsed Avalanche Rating
9. ERATURE C 40 80 120 160 FIGURE 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 100 HH IfR 0 L Iag 1 3 RATED BVpss Vpp IfRzO L R In las R 1 3 RATED BVpss 1 10 STARTING Ty 25 C las AVALANCHE CURRENT A 0 01 0 1 1 10 100 tay TIME IN AVALANCHE ms NOTE Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 20 15 10 Ip DRAIN CURRENT A PULSE DURATION 80us 71 DUTY CYCLE 0 5 MAX 25 C 0 0 5 1 0 1 5 2 0 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 8 SATURATION CHARACTERISTICS 12 Ves Ip 250A 1 1 1 0 NORMALIZED GATE THRESHOLD VOLTAGE 80 40 0 40 80 120 160 Ty JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 4 intersil HUF75831SK8 Typical Performance Curves continued 1 15 3000 Ves OV f 1MHz z 5 1000 2 1 10 T Ciss Cas Cap 3 lt e5 1 z 9 105 2 a Q A 1 00 amp 100 x 4 lt 5 zm 0 95 A B ru CRss
10. ONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE 3 DUTY CYCLE DESCENDING ORDER 1195 01 Roya 509C W 2 0 05 0 02 0 01 Y 0 1 z al lt d T 0 01 p E NOTES DUTY FACTOR D ty to SINGLE PULSE PEAK Ty X Zoua X Roga TA 0 001 105 104 103 10 2 107 109 101 102 103 t RECTANGULAR PULSE DURATION 5 FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 500 A TA 25 C 50 C W FOR TEMPERATURES t ABOVE 259C DERATE PEAK 100 CURRENT AS FOLLOWS f mum ILL X 150 TA iz Ves 10V 125 10 C TRANSCONDUCTANCE L MAY LIMIT CURRENT L IN THIS REGION 1 105 104 103 10 10 100 101 102 103 t PULSE WIDTH 6 FIGURE 4 PEAK CURRENT CAPABILITY 3 intersil HUF75831SK8 Typical Performance Curves continued Ip DRAIN CURRENT A Ip DRAIN CURRENT A NORMALIZED DRAIN TO SOURCE ON RESISTANCE OPERATION IN THIS AREA MAY BE LIMITED BY rps o Ty TA Vps DRAIN TO SOURCE VOLTAGE V FIGURE 5 FORWARD BIAS SAFE OPERATING AREA PULSE DURATION 80us DUTY CYCLE 0 5 MAX Vpp 15V 2 5 2 0 1 5 1 0 3 5 4 0 4 5 5 0 Vas GATE TO SOURCE VOLTAGE V FIGURE 7 TRANSFER CHARACTERISTICS T T PULSE DURATION 80us DUTY CYCLE 0 5 MAX Ip Ves 10V 80 40 0 Ty JUNCTION TEMP
11. OURCEMOD 2 20e 3 4 14 RVTHRES 22 8 RVTHRESMOD 1 VBAT RVTEMP 18 19 RVTEMPMOD 1 EGS 4 EDS o9 S1A 6 12 13 8 S1AMOD 22 S1B 13 12 13 8 S1BMOD RVTHRES 52 6 15 14 13 S2ZAMOD S2B 13 15 14 13 S2BMOD RLSOURCE VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 40 2 MODEL DBODYMOD D IS 9 95e 13 RS 6 61e 3 TRS1 1 02 4 TRS2 0 1 53e 9 TT 2 12e 7 M 0 62 MODEL DBREAKMOD D RS 9 00e 1 TRS1 9 94e 4 TRS2 1 06e 7 MODEL DPLCAPMOD D 1 35e 9 IS 1 30 M 0 90 MODEL MMEDMOD NMOS VTO 3 18 KP 1 70 IS 1 30 N 10 TOX 1L 1u W 1u RG 1 95 MODEL MSTROMOD NMOS VTO 3 56 KP 30 IS 1e 30 N 10 TOX 1L 1u W 1u MODEL MWEAKMOD NMOS VTO 2 85 KP 0 08 IS 1 30 N 10 TOX 1L 1u W 1 RG 19 5 Rs 0 10 MODEL RBREAKMOD RES TC1 9 97 4 TC2 5 07e 7 MODEL RDRAINMOD RES TC1 8 52e 3 TC2 2 44e 5 MODEL RSLCMOD RES TC1 3 28e 3 TC2 0 MODEL RSOURCEMOD RES TC1 1 00e 3 TC2 0 MODEL RVTHRESMOD RES TC1 2 08e 3 TC2 8 86e 6 MODEL RVTEMPMOD RES TC1 3 08e 3 TC2 0 MODEL S1AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 6 0 VOFF 4 0 MODEL S1BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 4 0 VOFF 6 0 MODEL S2AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 3 0 VOFF 0 0 MODEL S2BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 0 VOFF 3 0 ENDS NOTE For further discussion of the PSPICE model consu
12. e Displayed on the curve are Rea values listed in the Electrical Specifications table The points were chosen to depict the compromise between the copper board area the thermal resistance and ultimately the power dissipation Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2 Roya is defined as the natural log of the area times a coefficient added to a constant The area in square inches is the top copper area including the gate and source pads RgJA 83 2 23 6 x In Area EQ 2 The transient thermal impedance Zaya is also effected by varied top copper board area Figure 21 shows the effect of copper pad area on single pulse transient thermal impedance Each trace represents a copper pad area in square inches corresponding to the descending list in the graph Spice and SABER thermal models are provided for each of the listed pad areas Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms For pulse widths less than 100ms the transient thermal impedance is determined by the die and package Therefore CTHERM through CTHERMS5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models listing of the model component values is available in Table 1 240 Rosa 83 2 23 6 In AREA 200 189 C W 0 0115i in2 160 W 0 054
13. f Intersil Corporation Copyright Intersil Corporation 2000 HUF75831SK8 Electrical Specifications 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip 250A Ves OV Figure 11 150 E V Zero Gate Voltage Drain Current Ipss Vps 140V Vas 0V 1 uA Vps 135V Vas OV Ta 150 C 250 pA Gate to Source Leakage Current lass Vas 20V 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH Vas Ip 250pA Figure 10 2 4 V Drain to Source On Resistance p Vag 10V Figure 9 0 079 0 095 THERMAL SPECIFICATIONS Thermal Resistance Junction to RoJA Pad Area 0 76 in 490 3 mm Note 2 50 C W Ambient Pad Area 0 054 in 34 8 mm Note 3 152 9C W Pad Area 0 0115 in 7 42 mm Note 4 189 9C W SWITCHING SPECIFICATIONS Vcs 10V Turn On Time ton Vpp 75V Ip 5 25 ns Turn On Delay Time ta ON RE x 2 11 ns Rise Time t Figures 18 19 6 ns Turn Off Delay Time td OFF 40 ns Fall Time tf gt 9 ns Turn Off Time tOFF 75 ns GATE CHARGE SPECIFICATIONS Total Gate Charge Qg rOT Vas OV to 20V Vpp 75V 66 80 nC Gate Charge at 10V Qg 10
14. in Rega C W 120 80 0 01 0 1 1 0 AREA TOP COPPER AREA in FIGURE 20 THERMAL RESISTANCE vs MOUNTING PAD AREA 150 COPPER BOARD AREA DESCENDING ORDER 0 04 in 120 0 28 in 0 52 2 ao 0 76 in 2 lt 90 100i ul ul I o aa 60 a 30 0 107 109 10 102 103 t RECTANGULAR PULSE DURATION s FIGURE 21 THERMAL IMPEDANCE vs MOUNTING PAD AREA 7 intersil HUF75831SK8 PSPICE Electrical Model SUBCKT HUF75831SK8 213 rev 4 Feb 2000 CA 12 8 2 00e 9 CB 15 14 2 00e 9 CIN 6 8 1 10e 9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 5 LDRAIN EUR DPLCAP 10 5 DPLCAPMOD os 10 RLDRAIN EBREAK 11 7 17 18 155 4 RSLC1 EDS 1485 81 51 DBREAK EGS 13 8 6 81 RSLC2 ESG6 10681 ESLC i EVTHRES 6 21 198 1 EVTEMP 20 6 18 22 1 50 R DBODY ESG DRAN EBREAK 9 IT 8 17 1 EVTHRES PEU 14 1 MWEAK LDRAIN 2 5 1 0e 9 LGATE EVTEMP LGATE 1 9 1 12 9 GATE RGATE l6 LSOURCE 3 7 1 29e 10 10 ahaa e MMED 16 6 8 8 MMEDMOD RLGATE HC MSTRO MSTRO 16 6 8 8 MSTROMOD LSOURCE MWEAK 16 21 8 8 MWEAKMOD CIN 8 gt il SOURCE MMED RBREAK 17 18 RBREAKMOD 1 RSOURCE RDRAIN 50 16 RDRAINMOD 5 80e 2 i 5 RGATE 9 20 1 95 1A 9 9652 RLDRAIN 2 5 10 12 9 RBREAK T RLGATE 19 11 2 8 B RLSOURCE 3 7 1 29 RSLC1 5 51 RSLCMOD 1 6 SB 828 RVTEMP RSLC2 5 50 1e3 CA 13 CB 19 RSOURCE 8 7 RS
15. lt A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 8 intersil HUF75831SK8 SABER Electrical Model REV 4 feb 2000 template huf75831sk8 n2 n1 n3 electrical n2 n1 n3 var i iscl dp model dbodymod is 9 95e 13 rs 6 61e 3 trs1 1 02e 4 trs2 0 cjo 1 53e 9 tt 2 12e 7 m 0 62 dp model dbreakmod rs 9 00e 1 trs1 9 94e 4 trs2 1 06e 7 dp model dplcapmod cjo 1 35e 9 is 1e 30 m 0 90 m model mmedmod type _n vto 3 18 kp 1 70 is 1e 30 tox m model mstrongmod type _n vto 3 56 kp 30 is 1e 30 tox 1 1 1 m model mweakmod type n vto 2 85 kp 0 08 is 1e 30 tox 1 LDRAIN Sw vcsp model 1 ron 1e 5 roff 0 1 von 6 0 voff 4 0 DPLCAP 5 DRAIN Sw vcsp model s1bmod ron 1 5 0 1 von 4 0 voff 6 0 wee 2 sw_vcsp model s2amod ron 1 5 roff 0 1 von 3 0 voff 0 0 10 sw vcsp model s2bmod ron 1e 5 0 1 von 0 0 voff 3 0 RSLC1 RLDRAIN c ca n12 n8 2 00e 9 RSLC2 c cb n15 n14 2 00e 9 c cin n6 n8 1 10e 9 ISL 50 DBREAK dp dbody n7 n5 model dbodymod dp dbreak n5 n11 model dbreakmod ESG RDRAIN 11 dp dplcap n10 n5 model dplcapmod EVTHRES iit n8 n17 1 z MWEAK LGATE EVTEMP GATE RGATE AN 6 DBODY Lldrain n2 n5 1 00
16. mm 1 2500 PIECES PER REEL 2 ORDER IN MULTIPLES OF FULL REELS ONLY 3 MEETS EIA 481 REVISION A SPECIFICATIONS 11 intersil HUF75831SK8 All Intersil semiconductor products are manufactured assembled and tested under ISO9000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site www intersil com Sales Office Headquarters NORTH AMERICA Intersil Corporation P O Box 883 Mail Stop 53 204 Melbourne FL 32902 TEL 321 724 7000 FAX 321 724 7240 EUROPE Intersil SA Mercure Center 100 Rue de la Fusee 1130 Brussels Belgium TEL 32 2 724 2111 FAX 32 2 724 22 05 ASIA Intersil Taiwan Ltd 7F 6 No 101 Fu Hsing North Road Taipei Taiwan Republic of China TEL 886 2 2716 9310 FAX 886
17. package the environment in which it is applied will have a significant influence on the part s current and maximum power Qgs Ig REF 0 FIGURE 17 GATE CHARGE WAVEFORMS PULSE WIDTH FIGURE 19 SWITCHING TIME WAVEFORM dissipation ratings Precise determination of is complex and influenced by many factors 1 Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board The number of copper layers and the thickness of the board The use of external heat sinks The use of thermal vias Air flow and board orientation For non steady state applications the pulse width the duty cycle and the transient thermal response of the part the board and the environment they are in Intersil provides thermal information to assist the designer s preliminary application evaluation Figure 20 defines the Rega for the device as a function of the top copper 2 In 6 intersil HUF75831SK8 component side area This is for a horizontally positioned FR 4 board with 10z copper after 1000 seconds of steady state power with no air flow This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curv
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