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MOTOROLA MC68LC302 Low Power Integrated Multiprotocol Processor Reference Manual

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1. 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol Min Max Min Min Max Unit 110 Address Valid to AS Low tAVASL 15 12 10 ns 111 AS Low to Clock High tASLCH 30 25 20 ns 112 Clock Low to AS High ASH 45 40 30 ns 113 AS High to Address Hold Time on Write 0 0 0 ns 114 AS Inactive Time tasH 1 1 1 clk 115 UDS LDS Low to Clock High see 2 tsi cu 40 33 27 ns 116 Clock Low to UDS LDS High 45 40 30 ns 117 R W Valid to Clock High see Note 2 tawvcH 30 25 20 ns 118 Clock High to R W High tcHRWH 45 40 30 ns 119 AS Low to IAC High tASLIAH mE 40 mE 35 mE 27 ns 120 AS High to IAC Low tASHIAL 40 35 27 ns 121 AS Low to DTACK Low 0 Wait State tASLDTL 45 40 30 ns 122 Clock Low to DTACK Low 1 Wait State tCLDTL 30 25 20 ns 123 AS High to DTACK High lASHDTH 45 40 30 ns 124 DTACK High to DTACK High Impedance 15 15 10 ns 125 Clock High to Data Out Valid tcHDov 30 25 20 ns 126 AS High to Data High Impedance tASHDZ 45 40 30 ns 127 AS High to Data Out Hold Time tASHDOI 0 0 0 ns 128 AS High to Address Hold Time on Read 0 0 0 ns 129 UDS LDS Inactive Time 1 1 1 ck 130 Data In Valid
2. 4 26 SMC Programming 4 26 SMC Memory Structure and Buffers Descriptors 4 26 SMC1 Receive Buffer 2044 4 4 26 SMC1 Transmit Buffer Descriplot 4 26 SMC2 Receive Buffer Descriptor 444422 4 20 4 27 SMC2 Transmit Buffer Descriptor 444 40 4 0000111 4 27 Section 5 Signal Description Functional 3 LS 5 1 woe M 5 2 ioc dd CHE 5 4 System Control PINS cositas aes 5 5 Address Bus Pins 19 1 00 88 5 7 Data Bus Pins D15 D0 2 uite pra torre 5 8 BUS Control PING ub oat bon oue aet 5 9 B s Arbitration PINS peti Qo petes 5 10 Interrupt COnIF Ol Ps ssi eb e b p REIS 5 11 MC68L C302 Bus Interface Signal 5 12 Physical Layer Serial Interface 5 14 Typical Serial Interface Pin Configurations 5 14 NMSI1 or ISDN Interface 5 14 NMSI2 Porbor sa ta e
3. 4 5 2 2 SMC1 TRANSMIT BUFFER DESCRIPTOR The CP reports information about this transmit byte through the BD 4 26 MC68LC302 REFERENCE MANUAL MOTOROLA Communications Processor 15 14 13 12 10 9 8 7 0 L AR DATA 4 5 2 3 SMC2 RECEIVE BUFFER DESCRIPTOR In the IDL mode this BD is identical to the SMC1 receive BD In the mode SMC2 is used to control channel 15 14 6 5 2 1 0 9 EERS 4 5 2 4 SMC2 TRANSMIT BUFFER DESCRIPTOR In the IDL mode this BD is identical to the SMC1 transmit BD In the GCI mode SMC2 is used to control the C I channel 15 14 6 5 2 1 0 RESERVED 0 MOTOROLA MC68LC302 REFERENCE MANUAL 4 27 Communications Processor CP 4 28 MC68LC302 REFERENCE MANUAL MOTOROLA SECTION 5 SIGNAL DESCRIPTION This section defines the MC68L C302 pinout The input and output signals of the MC68LC302 are organized into functional groups and are described in the following sec tions The MC68L C302 is offered in a 100 lead thin quad flat package TQFP and a 132 pin 13 x 13 pin grid array PGA for emulator applications The MC68LC302 uses a M68000 like bus for communication between both on chip and ex ternal peripherals This bus is a single continuous bus existing both on chip and off chip the MC68LC302 Any access made internal to the device is visible externally Any access made external is visible internally Thus w
4. MC68EC030 T RP SUFFIX PACKAGE CASE 789B 01 lt L K G E v B I 00 NOTES MILLIMETERS INCHES 1 A AND B ARE DATUMS AND TIS A MIN MAX MIN MAX DATUM SURFACE 3404 3505 1340 1 380 2 POSITIONAL TOLERANCE FOR LEADS 132 PL A B 3404 3505 1 340 1 380 9 0 13 0005 2 54 3 81 0 100 0 150 4 CONTROLLING DIMENSION INCH D G K 0 43 0 55 0 017 0 022 2 54 BSC 0 100 BSC 4 32 4 95 0 170 0 195 MOTOROLA MC68LC302 USER S MANUAL SUPPLEMENT 7 3 Mechanical Data and Ordering Information 7 2 2 Surface Mount TQFP NOTES AX 0 20 0 008 H L M N 1 DIMENSIONING AND TOLERANCIN
5. 15 14 13 12 11 10 9 8 2 SYNC SCIT SDIAG1 SDIAGO SDC2 SDC1 B2RB B2RA 7 6 5 4 3 2 1 0 B1RB B1RA DRB DRA MSC3 MSC2 MS1 MSO SETZ Set L1TXD to Zero valid only for the GCI interface 0 Normal operation 1 L1TXD output set to a logic zero used in GCI activation SYNC SCIT SYNC Mode SCIT Select Support valid only in PCM mode 0 One pulse wide prior to the 8 bit data N pulses wide and envelopes the N bit data The SCIT Special Circuit Interface T interface mode is valid only in GCI mode SCIT support disabled SCIT D channel collision enabled Bit 4 of channel 2 used by the IMP for receiv ing indication on the availability of the S interface D channel 4 2 MC68LC302 REFERENCE MANUAL MOTOROLA Communications Processor CP SDIAG1 SDIAGO Serial Interface Diagnostic Mode NMSI1 Pins Only 00 Normal operation 01 Automatic echo Internal loopback Loopback control SDC2 Serial Data Strobe Control 2 0 SDS2 signal is asserted during the B2 channel 1 5051 signal is asserted during the B2 channel 0 1 Data Strobe Control 1 0 5051 signal is asserted during the B1 channel 1 SDS2 signal is asserted during the B1 channel B2RB B2RA B2 Channel Route in IDL GCI Mode or CH 3 Route in PCM Mode 00 Channel not supported 01 Route channel to SCC1 10 Route channel to SCC2 if MSC2 is cleared 11 Ro
6. 2 5 2 4 1 1 Glock Control HeglSIgl axe dte deter veda 2 6 2 4 2 MC68LC302 System Clock Generation 2 6 2 4 2 1 Default System Clock Generation 2 7 2 4 3 IMP System Clock Generation 2 8 2 4 3 1 System Clock a er pee ds 2 8 2 4 3 2 tuts 2 8 2 4 3 3 Phase Locked Loop 2 9 2 4 3 4 Frequency Multiplication rhe dede eto 2 9 2 4 3 4 1 Low Power PLL Clock 2 10 2 4 3 4 2 IMP PLL and Clock Control Register IPLCR 2 10 2 4 3 5 IMP Internal Clock Signals io oie rt er D etta 2 12 2 4 3 5 1 IMP System eels hora ara t aec dete 2 12 2 4 3 5 2 BING DIOC icon mira PESE I MAIS COE UE rene 2 12 2 4 3 5 3 eo a exc vod Mech oe 2 12 2 4 3 6 LZ PIS S eras ette AE Fr cR MEER RUE dE 2 12 2 4 3 6 1 2 12 2 4 3 6 2 e deep eue ge Correa ntes orf wees 2 12 2 4 3 6 3 2 12 2 4 3 6 4 Eb D ed ROME XU 2 12 2 4 4 IMP Power
7. 4 5 4 3 4 SCC Data Synchronization Register 4 6 4 3 5 Buffer Descriptors Table 6 4 6 4 3 6 SCC Parameter RAM Memory 4 7 4 3 7 Interrupt de 4 7 4 3 8 VART eee ere ne 4 7 4 3 8 1 VART Memory o uto en a INE 4 7 4 3 8 2 UART Mode 4 8 4 3 8 3 UART Receive Buffer Descriptor Rx BD 4 8 4 3 8 4 UART Transmit Buffer Descriptor Tx 4 8 4 3 8 5 UART Event Register acie eere 4 9 4 3 8 6 VARFMASK acier eno a e erro rote ace pup 4 9 4 3 9 Autobaud Controller New io fen ae 4 9 4 3 9 1 Autobaud Channel Reception 4 9 4 3 9 2 Autobaud Channel Transmit 4 11 4 3 9 3 Autobaud Parameter RAM cave cate cers Se HERR RU 4 11 4 3 9 4 Autobaud Programming 4 13 4 3 9 4 1 Preparing for the Autobaud 55 4
8. 6 7 AC ELECTRICAL SPECIFICATIONS CLOCK TIMING see Figure 6 1 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol Min Max Min Max Min Max Unit System Frequency fsys dc 16 67 dc 20 00 dc 25 00 MHz Crystal Frequency fXTAL 25 6000 25 6000 25 6000 kHz On Chip VCO System Frequency fsys 10 16 67 10 20 10 25 MHz mem pud eee With external crystal oscillator enabled osc CLKO stability ACLK TBD TBD TBD TBD TBD 1 CLKO Period lcyc 60 50 40 ns 1A EXTAL Duty Cycle ldcyc 40 60 40 60 40 60 96 1 External Clock Input Period 60 50 40 ns 2 3 CLKO Pulse width measured at 1 5v tow TBD TBD TBD ns 4 5 CLKO Rise and fall times full drive 5 4 4 ns 5B EXTAL to CLKO skew PLL disabled 2 11 2 9 2 7 ns Note The minimum VCO frequency and the PLL default values put some restrictions on the minimum system frequency Do lt EXTAL INPUT VOLTAGE MIDPOINT CLKO OUTPUT Figure 6 1 Clock Timing Diagram 6 6 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 6 7 1 AC Electrical Characteristics IMP Phased Lock Loop PLL Characteristics Characteristics Expression Min Max Unit VCO frequency when PLL enabled MF Ef 10 f Note 1 MHz PLL external capacitor XFC pin to VOCSYN
9. ipa Mee enatis remi 4 22 4 3 11 1 BISYNG Memory Map 4 22 4 3 11 2 BISYNC Mode 000 4 22 4 3 11 3 BISYNC Receive Buffer Descriptor Rx 4 22 4 3 11 4 BISYNC Transmit Buffer Descriptor Tx 4 22 4 3 11 5 BISYNC 4 23 4 3 11 6 BISYNC Mask 4 23 4 3 12 Transparent Controller da ote amid c e i 4 23 4 3 12 1 Transparent Memory nnn 4 23 4 3 12 2 Transparent Mode 4 24 viii MC68LC302 REFERENCE MANUAL MOTOROLA Number MOTOROLA Table of Contents Title Page Number Transparent Receive Buffer Descriptor RxBD 4 24 Transparent Transmit Buffer Descriptor Tx 1 4 25 Transparent Event Register 4 25 Transparent Mask 15 4 25 Serial Communication Port 4 25 SCP Programming 4 25 SCP Transmit Receive Buffer 2 2 0 44044 022 4 26 Serial Management Controllers 5
10. 2 13 2 4 4 1 IMP Low Power Modes 2 13 2 4 4 1 1 SOP IMO detti iba 2 13 2 4 4 1 2 DOZE Mode cab 2 13 2 4 4 1 3 STAND BY Mode uo coro rdiet mp 2 13 MOTOROLA MC68LC302 REFERENCE MANUAL Table of Contents Paragraph Title Page Number Number 2 4 4 1 4 SLOW c 2 14 2 4 4 1 5 NORMAL TMIOOB sies OR REEL eo det a 2 14 2 4 4 1 6 IMP Operation Mode Control Register 222 0 2 14 2 4 4 1 7 Low Power Drive Control Register 2 15 2 4 4 1 8 IMP Power Down Register IPWRD 2 15 2 4 4 1 9 Default Operation Modes 1100 2 15 2 4 4 2 LOW POW GR SUpport ete el bo 2 15 2 4 4 2 1 Enter the SLOW da aUe dog 2 15 2 4 4 2 2 Entering the STOP DOZE STAND BY 2 16 2 4 4 2 3 IMP Wake Up from Low Power STOP 2 17 2 4 4 2 4 IMP Wake Up Control Register IWUCR 2 17 2 4 4 3 Fast 1121450 edes ci Pa esu su UMS 2 18 2 4 4 3
11. 30 30 20 ns AS Asserted to RW Low Write see Notes any 2 0 0 7 2 6 21 Address FC Valid to R W Low Write see 15 __ 15 __ 10 __ ns Note 2 22 BW Low to DS Asserted Write see Note taiat 30 30 __ 20 2 h 23 Clock Low to Data Out Valid 30 30 20 ns AS DS Negated to Data Out Invalid Write 25 see Note 2 15 15 10 ns 26 Data Out Valid to DS Asserted Write see tbosL 15 15 10 s Note 2 Data In Valid to Clock Low Setup Time on 7 Read see Note 5 SEP 7 7 T 5 E AS DS Negated to DTACK Negated Asyn 28 chronous Hold see Note 2 CSV teoa 0 110 110 75 ns AS DS Negated to Data In Invalid Hold 29 Time on Head tsHDII 0 0 ns DTACK Asserted to Data In Valid 31 Time see Notes 2 and 5 50 50 Pu 33 32 HALT and RESET Input Transition Time 150 150 150 ns 44 AS DS Negated to AVEC Negated tsuvPH 0 50 0 50 0 33 ns 47 SUPPE Input Setup Time see Note tasi 10 10 gt 7 25 ns 53 Data Out Hold from Clock High 0 0 0 ns 55 to Data Bus Impedance 0 0 0 hs 6 8 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 56 HALT RESET Pulse Width see Note 4 10 10 10 clks 61 Clock High to BCLR High Im
12. Address Width Block Description Base 000 576 Bytes RAM User Data Memory Base 23F Base 240 Reserved Not Implemented Base 3FF The parameter RAM contains the buffer descriptors for each of the two SCC channels the SCP and the two SMC channels The memory structures of the three SCC channels are identical When any SCC SCP or SMC channel buffer descriptors or parameters are not used their parameter RAM area can be used for additional memory For detailed informa tion about the use of the buffer descriptors and protocol parameters in a specific protocol see Section 4 Communications Processor CP CP Base 67E contains the MC68L C302 revision number 2 20 MC68LC302 REFERENCE MANUAL MOTOROLA Configuration Clocking Low Power Modes and Internal Memory Table 2 5 Parameter RAM Address Width Block Description Base 400 4 Word SCC1 Rx BD 0 408 4 Word SCC1 Rx BD 1 Base 410 4 Word 5 1 Rx BD2 Base 418 4 5 1 Rx BD 3 Base 420 4 Word 5 1 Rx BD 4 Base 428 4 Word SCC1 Rx BD 5 Base 430 4 Word 5 1 Rx BD6 Base 438 4 Word SCC1 Rx BD 7 Base 440 4 Word SCC1 Tx BDO Base 448 4 Word 5 1 Tx BD 1 450 4 Word SCC1 Tx BD2 Base 458 4 Word 5 1 Tx BD 3 Base 460 4 Word 5 1 Tx BD 4 Base 468 4 Word 5 1 Tx BD 5 Base 470 4 Word SCC1 Tx BD6 Base 478 4 Word SCC1 Tx BD 7 Base 480 SCC1 Specific Protoc
13. Note 1 MF 5 MF 340 MF 480 pF gt 5 MF 380 MF 970 1 fis the maximum operating frequency Ef is EXTAL frequency CXFC is the value of the PLL capacitor connected between pin and VCCSYN for MF 1 The recommended value for is 400pF for lt 5 and 540pF for MF 5 The maximum VCO frequency is limited to the internal operation frequency as defined above Examples 1 MODCK1 0 01 MF 1 fi 340 lt lt 480 pF 2 MODCK1 0 01 crystal is 32 768 KHz or 4 192 MHz initial MF 401 initial frequency 13 14 MHz later MF is changed to 762 to support a frequency of 25 MHz Minimum is 762 x 380 289 nF maximum is 401 x 970 390 nF The recommended for 25 MHz is 762 x 540 414 289 nF lt lt 390 nF and closer to 414 nF The proper available value for is 390 nF 3 MODCK1 pin 1 crystal is 32 768 KHz or 4 192 MHz initial MF 401 initial frequency 13 14 MHz later MF is changed to 1017 to support a frequency of 33 34 MHz Minimum is 1017 x 380 386 nF Maximum is 401 x 970 390 nF 386 lt lt 390 nF The proper available value for is 390 nF 3A In order to get higher range higher crystal frequency can be used i e 50 KHz in this case Minimum is 667 x 380 253 nF Maximum is 401 x 970 390 nF 2 253 nF lt
14. Disable the SCC by clearing ENR and ENT ssue the Enter Hunt Mode command Initialize the SCC parameter RAM specifically the Rx and Tx internal states and the words containing the Rx and Tx 5 to the state immediately after reset and initialize the protocol specific parameter area for the new protocol Re enable the SCC with the new mode 4 3 10 HDLC Controller The functionality of the HDLC controller has not changed For any additional information on parameters registers and functionality please refer to the MC68302 Users Manual 4 3 10 1 HDLC MEMORY MAP When configured to operate in HDLC mode the IMP over lays the structure shown in Table 4 8 onto the protocol specific area of that SCC parameter RAM Refer to Parameter RAM on page 21 for the placement of the three SCC parameter RAM areas and to Table 4 1 for the other parameter RAM values Table 4 9 HDLC Specific Parameter RAM Address Name Description SCC 9C RCRC L SCC 9E RCRC H Temp Receive CRC Low Temp Receive CRC Hi SCC Base B2 FLR SCC Base B4 MAX cnt h SCC Base AO C MASK L Constant 8 16 Bit CRC DEBB 32 Bit CRC SCC Base A2 C MASK H Constant XXXX 16 Bit CRC 20E3 32 Bit CRC SCC Base A4 CRC Temp Transmit CRC Low SCC Base TCRC H Temp Transmit CRC High SCC Base A8 DISFC Discard Frame Counter SCC Base AA CRCEC CRC Err
15. DOZE Active Not active Not active 2501056 About 500uA SOB narru ORE No STAND_BY Active Notactive About Sma SPB TEP clock 4006 SLOW Active f ARPES Write to DF3 0 Full 2 4 4 1 1 STOP Mode In STOP mode all parts of IMP are inactive and the current con sumption is less than 0 1mA Both the crystal oscillator and the IMP PLL are shut down Because both the oscillator and the PLL must start up the wake up time takes 70000 EXTAL clocks for example 70000 cycles of 32 768 kHz crystal will take about 2 2 seconds The STOP mode is entered by executing the STOP instruction with the LPMO 1 bits in the IOMCR register set to 11 Refer to 2 4 4 2 2 Entering the STOP DOZE STAND BY Mode for an example instruction sequence for use with the STOP instruction 2 4 4 1 2 DOZE Mode In DOZE mode the oscillator is active in the IMP but the IMP PLL is shut down The current consumption depends on the frequency of the external crystal but is on the order of 500 uA In DOZE mode the IMP is shut down The wake up time is 2500 cycles of the external crystal for example 2500 cycles of 32 768 kHz crystal will take about 80 milliseconds Doze mode has faster wake up time than the STOP mode at the price of higher current consumption The DOZE mode is entered by executing the STOP instruction with the 1 0 bits in the IOMCR register set to 10 Refer to 2
16. psc 16 SIB Disable SCC1 Serial Clocks 0000 Base 8F0 Reserved Base FFF 3t Reset only upon total system reset RESET and HALT assert together but not on the execution of an M68000 RESET instruction See the RESET pin description for details The output latches are undefined at total system reset Event register with special properties 2 24 MC68LC302 REFERENCE MANUAL MOTOROLA SECTION 3 SYSTEM INTEGRATION BLOCK SIB The MC68LC302 contains an extensive SIB that simplifies the job of both the hardware and software designer Most of the features are taken from the MC68302 without change fea tures that have been added are highlighted in bold text NOTE This section will only present the register descriptions for each block For more information on the operation of each block please refer to the MC68302 Users Manual Items that are new or have changed will be described in detail The SIB includes the following functions IDMA Controller Interrupt Controller with Two Modes of Operation Parallel Input Output I O Ports Some with Interrupt Capability Parallel Input Output Ports on D15 D8 in 8 bit mode On Chip 1152 Byte Dual Port RAM Four Timers Including a Watchdog Timer and Periodic Interrupt Timer Four Programmable Chip Select Lines with Wait State Generator Logic Glueless Interface to SRAM EPROM Flash EPROM and EEPROM System Control System Status and Control Logic Disable CPU Logic
17. 20 L1CLK 272 L1RQ Valid before Falling Edge of L1SY1 1 1 1 L1CLK 273 L1GR Setup Time to L1SY1 Falling Edge 50 42 34 ns 274 L1GR Hold Time from L1SY1 Falling Edge 50 42 34 ns SDS1 SDS2 Active Delay from L1CLK Ris 275 ing Edge y 10 75 10 65 7 50 ns SDS1 SDS2 Inactive Delay from L1CLK 276 Paling Edge 10 75 10 65 7 50 5 1 The ratio CLKO L1CLK must be greater than 2 5 1 2 High impedance is measured at the 30 and 70 of Vpp points with the line at Vpp 2 through 10K in parallel with 130 pF 3 Where P 1 CLKO Thus for a 16 67 MHz CLKO rate P 60 ns MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics Le gt D se Je JC C Yo C09 oc m Jo C Y se Y oe se 2 gt 2 218 gt LNdLNO 104100 2805 1605 LNdNI 114110 lt LNdNI LASHI Figure 6 19 IDL Timing Diagram 6 31 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 6 20 AC ELECTRICAL SPECIFICATIONS GCI TIMING GCI supports the NORMAL mode and the GCI channel 0 GCNO in MUX mode Normal mode uses 512 kHz clock rate 256K bit rate MUX mode uses 256 x n 3088 kbs clock rate is
18. Min Max Unit 300 1 CLK PCM Clock Frequency see Note __ 6 66 8 0 100 MHz 301 L1CLK Width Low 55 45 37 ns 301A L1CLK Width High see Note 4 10 10 P410 ns 302 Risa Edge Setup Time to L1CLK 0 0 0 303 Faling Edge Hold Time from L1CLK 40 302 33 27 ms 304 115 0 115 1 Width Low 1 1 1 L1CLK 305 Ea Ee Successive Sync Signals 8 __ 8 __ 8 __ LICLK 306 eee Nola after L1 CLK Rising Edge 0 70 0 60 0 47 ns 307 Rising Ege h Impedance from L1CLK 0 50 0 42 0 34 ns 308 Edge to L1CLK Falling 20 17 __ 14 He 309 Educ see Time from L1CLK Falling 50 42 __ 34 __ 5 1 The ratio CLK L1CLK must be greater than 2 5 1 2 L1TxD becomes valid after the L1CLK rising edge or the sync enable whichever is later if long frames are used 3 Specification valid for both sync methods 4 Where P 1 CLKO Thus for a 16 67 MHz CLKO rate P 60 ns MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics L1CLK INPUT 115 0 1 LITXD OUTPUT L1RXD INPUT INPUT 115 0 1 INPUT LITXD OUTPUT LIRXD INPUT NOTE If L1SYn is guaranteed to make a smooth low to high transition no spikes while the clock is high setup time can be defined as shown min 20 ns Figure 6 22 PCM Timing Diagram SYNC P
19. 4 Word CONTROL Character 4 SCC Base B8 5 CONTROL Character 5 SCC BA 6 Word CONTROL Character 6 SCC Base BC CHARACTER7 Word CONTROL Character 7 SCC Base BE CHARACTER8 Word CONTROL Character 8 Initialized by the user M68000 core 4 3 11 2 BISYNC MODE REGISTER Each SCC mode register is a 16 bit memory mapped read write register that controls the SCC operation The term BISYNC mode reg ister refers to the protocol specific bits 15 6 of the SCC mode register when that SCC is configured for BISYNC The read write BISYNC mode register is cleared by reset 15 14 13 12 11 10 9 8 7 6 5 0 EXSYN NTSYN REVD BCS RTR RBCS SYNF ENC COMMON SCC MODE BITS 4 3 11 3 BISYNC RECEIVE BUFFER DESCRIPTOR RX BD The CP reports information about the received data for each buffer using BD The Rx BD is shown in Figure 4 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0 E X B DL PR CR OV CD OFFSET 2 DATA LENGTH OFFSET 4 RX BUFFER POINTER 24 bits used upper 8 bits must be 0 OFFSET 6 Figure 4 6 BISYNC Receive Buffer Descriptor 4 3 11 4 BISYNC TRANSMIT BUFFER DESCRIPTOR TX BD Data is presented to the CP for transmission on an SCC channel by arranging it in buffers referenced by the chan nel s Tx BD table The Tx BD is shown in Figure 4 7 4 22 MC68LC302 REFERENCE MANUAL MOTOROLA Communi
20. PITR count value periodic interrupt timer period 8192 This gives a range from 122 us with value of 0 to 250 ms with value of 7FF assuming 32 768 khz at the EXTAL pin MOTOROLA MC68LC302 REFERENCE MANUAL 3 23 System Integration Block 518 Solving the equation with the prescaler enabled PTP 1 gives the following values PITR count value 32768 512 22 periodic interrupt timer period PITR count value 16 periodic interrupt timer period This gives a range from 62 5 ms with a PITR value of 0 to 128 s with a PITR value of 7FF For a fast calculation of periodic timer period using a 32 768 kHz crystal the following equa tions can be used With prescaler disabled programmable interrupt timer period PITR 122 Us With prescaler enabled programmable interrupt timer period PITR 62 5 ms 3 7 4 3 Using the Periodic Timer As a Real Time Clock The periodic interrupt timer can be used as a real time clock interrupt by setting it up to gen erate an interrupt with a one second period When using a 32 768 kHz crystal the PITR should be loaded with a value of 0F with the prescaler enabled to generate interrupts at a one second rate The interrupt is generated in this case at a precise 1 second rate even if the interrupt is not serviced immediately A true real time clock is obtained if the current in terrupt is serviced completely before the next one occurs 3 7 4 4 Periodic Int
21. WEH WEL OE D15 D0 Read N A 015 00 Write DTACK 25 z BR I O O O BG ES N A BGACK O O N A O HALT I O Open Drain RESET Open Drain 1 Signal Names in parentheses are only available in Disable CPU mode If is generated automatically internally by the chip select logic then it is an output Otherwise it is an input Applies to disable CPU mode only The internal signal IBCLR is used otherwise Applies to disable CPU mode only otherwise N A MOTOROLA MC68LC302 REFERENCE MANUAL 5 13 Signal Description 5 11 PHYSICAL LAYER SERIAL INTERFACE PINS The physical layer serial interface has 18 pins and all of them have multiple functions The pins can be used in a variety of configurations in ISDN or non ISDN environments Table 5 4 shows the functionality of each group of pins and their internal connection to the two SCCs and one SCP controllers The physical layer serial interface can be configured for non mul tiplexed operation NMSI or multiplexed operation that includes IDL GCI and PCM high way modes IDL and GCI are ISDN interfaces When working in one of the multiplexed modes the NMSI1 ISDN physical interface can be connected to both SCC controllers Table 5 5 Serial Interface Pin Functions First Function Connected To Second Function C
22. n etia ct eden ctas 5 17 PAIOP SGP HP IAS tom 5 18 E 5 19 Parallel I O Pins with Interrupt 5 20 SGhipsseleot 5 21 When to Use Pullup 5 21 Section 6 Electrical Characteristics Rats ee oo Er Ee 6 2 Thermal Characteristics ance tec eod agii 6 2 Power DEFECT 6 3 Power 6 4 DC Electrical Characteristics ie corrente 6 5 DC Electrical Characteristics NMSH in IDL 6 6 AC Electrical Specifications Clock 6 6 MC68LC302 REFERENCE MANUAL Table of Contents Paragraph Title Page Number Number 6 7 1 AC Electrical Characteristics IMP Phased Lock Loop PLL CN 6 7 6 8 AC Electrical Specifications IMP Bus Master Cycles 6 8 6 9 AC Electrical 6 13 6 10 AC Electrical Specifications External Master Internal Asynchronous Read Write Cycles 6 16 6 11 AC Electrical Specifications External Master Internal Synchronous Read W
23. By loading the IOMCR register the user can change the power saving divide factor of the IMP PLL MOTOROLA MC68LC302 REFERENCE MANUAL 2 7 Configuration Clocking Low Power Modes and Internal Memory NOTE It is not possible to start the system with PLL disabled and then enable the PLL with software programming 2 4 3 IMP System Clock Generation 2 4 3 1 SYSTEM CLOCK CONFIGURATION The IMP has an on chip oscillator and phased locked loop Figure 2 2 These features provide flexible ways to save power and reduce system cost The operation of the clock generation circuitry is determined by the fol lowing registers The IMP Operation Mode Control Register IOMCR in 2 4 4 1 6 IMP Operation Mode Con trol Register IOMCR The IMP and Clock Control Register IPLCR A 32 768 kHz watch crystal provides an inexpensive reference but the EXTAL reference crystal frequency can be any frequency from 25 kHz to 6 0 MHz Additionally the system clock frequency can be driven directly onto the EXTAL pin In this case the EXTAL frequency should be the exact system frequency desired 0 to Maximum Operating Frequency and the XTAL pin should be left floating Fig ure 2 4 shows all the external connections required for the on chip oscillator as well as the PLL VCC and GND connection PIT CLOCK p IMP SYSTEM CLOCK CLKIN 0 MOF MOF is Maximum Operating Frequency Figure 2 3 IMP System Clocks Schemati
24. LILON LndNI 98 ILON 14110 Oxo Figure 6 5 DMA Timing Diagram IDMA MOTOROLA MC68LC302 REFERENCE MANUAL 6 14 Electrical Characteristics lt au Ajdde jou op pu 2 ANY S IVNSIS 508 303 31949 3LlHWavau 000894 438 WINGS si 1 SJ LON 4100 SV yov99 2 310N 98 2 310N 114100 OXIO Figure 6 6 DMA Timing Diagram SDMA 6 15 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 6 10 AC ELECTRICAL SPECIFICATIONS EXTERNAL MASTER INTERNAL ASYNCHRONOUS READ WRITE CYCLES see Figure 6 7 and Figure 6 8 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol win Max Min Min Unit 100 R W Valid to DS Low trwvps_ 0 0 0 ns 101 DS Low to Data In Valid ipsipiv 30 25 20 ns 102 DTACK Low to Data In Hold Time 0 0 0 ns 103 AS Valid to DS Low 0 0 0 ns 104 DTACK Low to AS DS High tDKLDSH 0 0 0 ns 105 DS to DTACK High 45 40 ns 106 DS Inactive to AS Inactive tosiasi 0 0 0 ns 107 D
25. System Integration Block SIB Bits 15 12 DTACK Field These bits are used to determine whether DTACK is generated internally with a program mable number of wait states or externally by the peripheral Table 3 4 DTACK Field Encoding Bits Description wo 15 No Wait State 1 Wait State 2 Wait States 3 Wait States 4 Wait States 5 Wait States 6 Wait States External DTACK 0 0 0 0 1 1 1 1 oO Oo Bits 12 2 Address Mask These bits are used to set the block size of a particular chip select line The address com pare logic uses only the address bits that are not masked i e mask bit set to one to de tect an address match 0 The address bit in the corresponding BR is masked 1 The address bit in the corresponding BR is not masked MRW Mask Read Write 0 The RW bit in the BR is masked 1 The RW bit in the BR is not masked NOTE For correct operation of the CS logic MRW bit cannot be set in Slave Mode or in systems where an External Master can take ownership of the Bus CFC Compare Function Code 0 The FC bits in the BR are ignored 1 The FC bits on the BR are compared NOTE Compare Function Code may be useful in systems where only Internal Masters CPU or DMA take ownership of the Bus be cause those masters drive the FC2 0 signals internally In Slave Mode or in syst
26. This pin is dedicated to the 1 0302 analog PLL circuits and determines whether the PLL is enabled or not When this pin is connected to Vcc the PLL is enabled and when this pin is connected to ground the PLL is disabled The voltage should be well regulated and the pin should be provided with an extremely low impedance path to the Vcc power rail should be bypassed to GND by a 0 1UF capacitor located as close as possible to the chip package GNDSYN Analog PLL Circuits Ground This pin is dedicated to the IMP analog PLL circuits The pin should be provided with an extremely low impedance path to ground GNDSYN should be bypassed to VCCSYN by a capacitor located as close as possible to the chip package 5 4 SYSTEM CONTROL PINS The system control pins are shown in Figure 5 3 MOTOROLA MC68LC302 REFERENCE MANUAL 5 5 Signal Description RESET HALT BUSW DISCPU FRZ This pin is available in PGA Package only Figure 5 3 System Control Pins RESET This bidirectional open drain signal acting as an input and asserted along with the HALT pin starts an initialization sequence called a total system reset that resets the entire MC68LC302 RESET and HALT should remain asserted for at least 100 ms at power on reset and at least 10 clocks otherwise The on chip system RAM is not initialized during reset except for several locations initialized by the CP NOTE With a 32 768Khz external crystal the m
27. pin is not asserted in this case The timing of IAC is identical to that of the CS3 CSO pins 5 8 BUS ARBITRATION PINS The bus arbitration pins are shown in Figure 5 7 These signals are only available in dis able CPU mode When the core is enabled the bus arbitration signals are the IPL2 0 signals Figure 5 7 Bus Arbitration Pins BR Bus Request This input signal indicates to the on chip bus arbiter that an external device desires to be come the bus master 5 10 MC68LC302 REFERENCE MANUAL MOTOROLA Signal Description BG Bus Grant This signal is an input to the IDMA and SDMA when the internal M68000 core is disabled and indicates that the LC302 has the bus after the current bus cycle completes Grant Acknowledge This bidirectional signal indicates that some device has become the bus master This sig nal is an input when an external device owns the bus This signal is an output when the IDMA or SDMA has become the master of the bus If the SDMA steals a cycle from the IDMA the BGACK pin will remain asserted continuously NOTE BGACK should always be used in the external bus arbitration process 5 9 INTERRUPT CONTROL PINS The interrupt control pins are shown in Figure 5 8 The IPL2 0 signals are only available when the CPU is enabled The FC2 0 and AVEC signals are only available in the PGA package 1 lt a IPL1 IRQG 2 7 l
28. Enable Transmitter 4 6 Exception PB8 3 29 EXTAL 5 2 5 4 External Bus Master 3 28 External Bus Arbitration using HALT 3 28 Master Wait State EMWS 3 5 External Bus Arbitration 3 28 External Master Wait State 3 4 FCR 3 13 Freeze Control 3 5 FRZ 5 7 Function Codes 3 13 5 12 Comparison 2 4 2 2 4 5 12 Register 3 13 MOTOROLA Index G GCI 4 2 5 14 5 15 SCIT 4 2 SIMASK 4 4 SIMODE 4 2 GCI See Signals GIMR 3 14 GNDSYN 2 12 5 5 H HALT 2 4 5 6 HALT See Signals Hardware Watchdog 3 5 BERR 3 5 3 6 HDLC HDLC Event Register 4 21 HDLC Mask Register 4 21 HDLC Memory Map 4 20 HDLC Mode Register 4 20 Rx BD 4 21 SCCE 4 21 SCCM 4 21 Tx BD 4 21 HDLC Controller 4 20 HDLC Event Register 4 21 HDLC Mask Register 4 21 HDLC Memory Map 4 20 HDLC Mode Register 4 20 HDLC Receive Buffer Descriptor 4 21 HDLC Transmit Buffer Descriptor 4 21 5 10 IDL 4 2 5 14 5 15 SIMASK 4 4 SIMODE 4 2 IDL See Signals IDMA Independent DMA Controller DREQ 3 11 IMP Features CP 1 2 IMP Operation Mode Control Register IOMCR 2 14 2 15 IMP PLL and Clock Control Register IPLCR 2 10 IMP PLL Pins 2 12 MOTOROLA MC68LC302 REFERENCE MANUAL GNDSYN 2 12 MODCLK 2 12 VCCSYN 2 12 XFC 2 12 IMP System Clock Generation IOMCR 2 8 2 9 2 10 IPLCR 2 8 2 10 IMP System Clocks Schematic PLL Disabled 2 8 IMP Wake Up from Low Power STOP Modes 2 17 IMR 3 16 Internal Loopback 4 3 Internal Registers 2
29. Figure 2 3 the MC68LC302 system clock schematic shows the IMP clock synthesizer The block includes an on chip oscillator a clock synthesizer and a low power divider which allows a comprehensive set of options for generating the system clock The choices offer many opportunities to save power and system cost without sacrificing flexibility and control In addition to performing frequency multiplication the PLL block can also provide EXTAL to CLKO skew elimination and dynamic low power divides of the output PLL system clock Clock source and default settings are determined during the reset of the IMP The MC68LC302 decodes the MODCLK and VCCSYN pins and the value of these pins deter mines the initial clocking for the part Further changes to the clocking scheme can be made by software After reset the 68000 core can control the IMP clocking through the following registers 1 IMP Operation Mode Control Register IOMCR 2 4 4 1 6 IMP Operation Mode Control Register IOMCR 2 IMP PLL and Clock Control Register IPLCR 2 4 3 4 Frequency Multiplication 3 IMP Interrupt Wake Up Control Register IWUCR 2 4 4 2 4 IMP Wake Up Control Register IWUCR 4 Periodic Interrupt Timer Register PITR See Section 3 System Integration Block SIB 2 6 MC68LC302 REFERENCE MANUAL MOTOROLA Configuration Clocking Low Power Modes and Internal Memory MULTIPLICATION FACTOR DIVIDE FACTOR 11 IM
30. IPA Interrupt Priority Active HWT WPV ADC Hardware Watchdog Timeout Write Protect Violation RME ERRE Address Decode Conflict Ram Microcode Enable VGE External RISC Request Enable Vector Generation Enable WPVE Write Protect Violation Enable RMCST Read Modify Write Cycle Special Treatment EMWS External Master Wait State ADCE Address Decode Conflict Enable BCLM Bus Clear Mask FRZW Freeze Watch Dog Timer Enable FRZ1 Freeze Timer 1 Enable FRZ2 Freeze Timer 2 Enable SAM HWDEN Synchronous Access Mode Hardware Watchdog Enable HWDON Hardware Watchdog Count MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB 3 1 2 System Status Bits Bits 27 24 of the SCR are used to report events recognized by the system control logic On recognition of an event this logic sets the corresponding bit in the SCR These bits may be read at any time A bit is reset by a one and is left unchanged by a zero More than one bit may be reset at a time For more information on these bits please refer to the MC68302 User s Manual After system reset simultaneous assertion of RESET and HALT these bits are cleared IPA Interrupt Priority Active This bit is set when the M68000 core has an unmasked interrupt request NOTE If BCLM is set an interrupt handler will normally clear IPA at the end of the interrupt routine to allow an alternate bus master to regain the bus ho
31. PIT Enable This bit when set enables the IMP to wake up from power down mode and generate an interrupt when the PIT event bit becomes set see 3 7 4 Periodic Interrupt Timer PIT 2 4 4 3 FAST WAKE UP In a system clocked with a 32 kHz oscillator the wake up recovery time from doze and stop modes may be too long for some applications In order to shorten this time an internal ring oscillator called Ringo can clock the chip the term real clock in the following discussion refers to the clock whose source is the external oscillator or crystal the PLL can be either enabled or disabled One reason for using the fast wake up is To allow logic to operate in the time frame between the wake up command and the ac tual real clock recovery from the external crystal or oscillator NOTE If the SCCs use the internal clock or if they use external clock and the Ringo external frequency ratio does not comply with the 1 2 5 maximum ration specification then they cannot be en abled until the real clock has resumed operation 2 18 MC68LC302 REFERENCE MANUAL MOTOROLA Configuration Clocking Low Power Modes and Internal Memory The criteria for enabling Ringo and waking up the CPU by giving it an interrupt is RIN GOEN 1 and an unmasked PITEv PB10Ev PB9Ev event occurs please refer to the IWUCR register The internal ring oscillator is not enabled if the PLL is disabled A system with the PLL dis abled has to ha
32. Ri 0 10 020 0 004 0 008 5 16 00 BSC 0 630 BSC 51 8 00 BSC 0 315 BSC a U 009 0 16 0 004 0 006 2X 02 V 16 00 BSC 0 630 BSC bos E vi 8 00 BSC 0 315 BSC 0 20 0 008 0 08 0 008 T 2 1 00 REF 0 039 REF 9 ol 79 o 79 i AX MAS 01 0 0 A 02 12 12 T K 5 139 5 139 SEATING PAS EE y PLANE FL VIEW AA 0 05 0 002 5 BASE METAL A 2 R1 G U 0 25 0 010 E d Ly D GAGE PLANE A PLATING i 4 m 0 08 0 003 001 NO AB 4 SECTION AB AB 2 ROTATED 90 CLOCKWISE VIEW Y VIEW AA CASE 983 01 ISSUEA DATE 07 14 94 7 4 MC68LC302 USER S MANUAL SUPPLEMENT MOTOROLA Mechanical Data and Ordering Information 7 3 ORDERING INFORMATION Package Type ior Order Number 0 C to 70 MC68LC302RC16 Pin Grid Array 40 C to 85 C MC68LC302CRC16 RC Suffix 0 C to 70 C MC68LC302RC20 40 C to 85 C MC68LC302CRC20 Surface Mount 16 67 0 C to 70 C MC68LC302PU16 PU Suffix 20 0 C to 70 C MC68LC302PU20 MOTOROLA MC68LC302 USER S MANUAL SUPPLEMENT 7 5 Mechanical Data and Ordering Information 7 6 MC68LC302 USER S MANUAL SUPPLEMENT MOTOROLA INDEX Address AS 3 25 Decode Conflict 2 4 Decode Conflict 3 3 3 4 Address Bus Pins 5 7 AS 3 3 3 25 5 9 AT command set 4 9 Autobaud Controller 4 9 Autobaud Command Descriptor 4 14 Autobaud Lookup Table Format 4 16 Autobaud Para
33. The transmitter is not used so this echoing method does not impact performance The smart echo or software transmit requires use of an additional clock and the transmitter so the overall performance could be affected if other SCCs are running This method requires an additional clock for sampling the incoming bit stream since the baud rate gener ator BRG must be used to provide the correct frequency for transmission The user needs to provide the sampling clock that will be used for the autobaud function on the RCLK pin for example a 1 8432 MHz clock for 115 2K The clock that will be used for the SCC trans mission can be provided to the BRG from the system clock or on TIN1 The TIN1 and RCLK1 pins can be tied together externally After the first two characters have been received and character length and parity determined the host programs the DSR to FFFF enables the transmitter by setting ENT and programs the transmit character descriptor overlays CON TROL Character 8 The host is interrupted after each character is transmitted For modem applications with the MC68L C302 SCC2 will be used as the DTE interface and autobauding to the DTE baud rate will often be required If use of the smart echo feature is desired the receive clock can be provided by the baud rate generator 2 BRG2 internally by resetting the RCS bit in the SCON register to zero The separate transmit clock can be provided externally to the TCLK2 pin through a hardwir
34. the FC pins are not present and are internally driven to 5 Since the user does not have any control over how the FC sig nals are driven it is recommended that the user write these bits to zero and write the CFC bit to zero to disable the FC comparison NOTE Do not assign this field to the M68000 core interrupt acknowledge space FC2 FCO 7 CFC Compare Function Code 0 The FC bits in the BAR are ignored Accesses to the IMP 4K byte block occur with out comparing the FC bits 1 The FC bits in the BAR are compared The address space compare logic uses the FC bits to detect address matches 2 4 MC68LC302 REFERENCE MANUAL MOTOROLA Configuration Clocking Low Power Modes and Internal Memory Bits 11 0 Address The high address field is contained in bit 11 0 of the BAR These bits are used to set the starting address of the dual port RAM The address compare logic uses only the most sig nificant bits to cause an address match within its block size Even though A23 20 are sig nals are not available they are driven internally by the core or driven to zeroes in disable CPU mode or when HALT has been asserted by an external master 2 3 SYSTEM CONFIGURATION REGISTERS A number of entries in the M68000 exception vectors table located in low RAM are reserved for the addresses of system configuration registers see Table 2 1 These regis ters have seven addresses within 0F0 0FF The MC68LC302 uses one of the
35. to sample each incoming bit in it s center Each bit received is stored to form an 8 bit character When the assembly process is completed a STOP bit is received the char acter is compared against two user defined characters If the received character does not match any of the two user defined characters the auto baud controller re enters the Enter Baud Hunt process The host is not notified until a match is encountered If a match is found the character is written to the received control character register RCCR with the corresponding status bit set in Rx BD7 The channel will generate the control char acter received CCR interrupt bit 3 in the SCCE if enabled If the character matched but a framing error was detected on the STOP bit the autobaud controller will also set the fram ing error status bit in Rx BD7 The autobaud controller then continues to assemble the incoming characters and to store them in the external data buffer The host receives a CCR interrupt after each character is received The host is responsible for determining the end of the incoming message for example a carriage return stopping the autobaud process and reprogramming the SCC to UART mode The autobaud controller returns the nominal START bit length value for the detected baud rate from the lookup table and a pointer to the last character received that was written to the external data buffer The host must be able to handle each character inter 4 10
36. 1 Option Register 1 Base Register 2 Option Register 2 Base Register 3 Option Register 3 Timer Unit 1 Mode Register Timer Unit 1 Reference Register Timer Unit 1 Capture Register Timer Unit 1 Counter Reserved Timer Unit 1 Event Register Watchdog Reference Register Watchdog Counter Reserved Timer Unit 2 Mode Register Timer Unit 2 Reference Register Timer Unit 2 Capture Register Timer Unit 2 Counter Reserved MOTOROLA MC68LC302 REFERENCE MANUAL 2 23 Configuration Clocking Low Power Modes and Internal Memory Table 2 6 Internal Registers Map Description Reset Value Timer Unit 2 Event Register Reserved SCC1 Configuration Register SCC1 Mode Register SCC1 Data Sync Register SCC1 Event Register Reserved SCC1 Mask Register Reserved SCC1 Status Register SCC2 Configuration Register SCC2 Mode Register SCC2 Data Sync Register SCC2 Event Register Reserved SPMODE SCP SMC Mode and Clock Control Register SIMASK Serial Interface Mask Register SIMODE Serial Interface Mode Register Reserved Base 8DC PNDNR 8 PIO Pin IO Data Direction Register 0000 8DE PNDAT 8 PIO Pin IO Data Register 0000 Base Reserved Base 8
37. 13 Bus Arbitration Logic 3 28 External Bus Arbitration 3 28 Internal Bus Arbitration 3 28 INDEX 1 Index Bus Arbitration Pins 5 10 Bus Control Pins 5 9 Bus States during Low power modes 68000 2 15 BUSW 2 1 5 7 C Changes to IMP CLKO Drive Options 2 6 Three state TCLK1 2 6 Three state RCLK1 2 6 Chip Select 2 4 AS 3 25 Base Address 3 27 Base Register 3 26 CS0 3 26 3 28 5 21 DTACK 3 26 Option Register 3 26 Chip Select Pins 5 21 Chip Select Registers 3 26 Chip Select Timing 6 24 CLKO Output Buffer Strength 2 11 CLKOMOD1 2 2 6 Clock CLKO 5 4 Clock Pins 5 4 CMOS Level 5 2 CMR 3 11 Communications Processor 4 1 Configuration MC68302 IMP Control 2 3 CQFP 7 2 Crystal Oscillator 2 8 Crystal Oscillator Circuit IMP 2 9 CS0 3 26 3 28 5 21 CS1 2 23 2 24 5 21 CS2 2 23 2 24 CS3 2 23 3 26 5 1 5 10 5 21 CS3 CS1 521 CSelect 2 7 CSR 3 13 D DAPR 3 13 Data Bus Pins 5 8 Default System Clock Generation 2 7 INDEX 2 MC68LC302 REFERENCE MANUAL DF0 3 2 10 Disable CPU 5 7 BG 3 28 BR 3 28 50 3 28 DTACK 3 28 EMWS 3 28 SAM 3 28 Disable CPU Logic 3 28 Disable SCC1 Serial Clocks Out 4 4 DISC 4 4 DISCPU 3 28 5 7 Divide by Two Block From Tin1 pin 4 5 DMA Control 3 10 DOZE 2 13 2 16 DRAM Refresh Buffer Descriptors 3 29 PB8 3 18 Drive 2 13 DSR 4 6 DTACK 3 4 3 26 3 28 5 10 5 12 Dynamic RAM Refresh Controller 3 29 E EMWS External Master Wait State 3 4 3 5 3 28 Enable Receiver 4 5
38. 2 CSIAKH 0 40 0 35 0 27 ns 152 CS Width Negated tcsH 60 50 40 ns 153 Clock High to DTACK Low 0 Wait State tCHDTKL 45 40 30 ns 154 to Low 1 6 Wait irr 30 25 20 ns 155 Clock Low to DTACK High tcLDTKH 40 35 27 ns 158 DTACK High to High Impedance 7 15 15 27 ns 171 Input Data Hold Time from S6 Low tipHCL 5 5 27 ns 172 CS Negated to Data Out Invalid Write tcSNDOI 10 10 10 ns 173 Address FC Valid to CS Asserted tAFVCSA 15 15 5 ns 174 CS Negated to Address FC Invalid tosNAFI 15 15 7 ns 175 CS Low Time 0 Wait States 120 100 15 ns 176 CS Negated to R W Invalid tcSNRWI 10 10 12 ns 177 CS Asserted to R W Low Write lcsARWL 10 10 80 ns 178 to Data In Invalid Hold Time iS SRI 0 0 e 7 m hs NOTE 1 This specification is valid only when the ADCE or WPVE bits in the SCR are set 2 For loading capacitance less than or equal to 50 pF subtract 4 ns from the maximum value given 3 Since AS and CS are asserted negated on the same CLKO edges no AS to CS relative timings can be specified However CS timings are given relative to a number of other signals in the same manner as AS See Figure 6 2 and Figure 6 3 for diagrams CLKO OUTPUT 50 53 6 7 53 55 gt gt 5
39. 4 4 2 2 Entering the STOP DOZE STAND BY Mode for an example instruction sequence for use with the STOP instruction 2 4 4 1 3 STAND BY Mode In STAND BY mode the oscillator is active and the IMP PLL if enabled is active but the IMP clock is not active and the IMP is shut down Current con MOTOROLA MC68LC302 REFERENCE MANUAL 2 13 Configuration Clocking Low Power Modes and Internal Memory sumption in STAND BY mode is less than less than 5mA The wake up time is a few IMP system clock cycles The STAND BY mode is entered by executing the STOP instruction with the 1 0 bits in the IOMCR register set to 01 Refer to 2 4 4 2 2 Entering the STOP DOZE STAND BY Mode for an example instruction sequence for use with the STOP instruction 2 4 4 1 4 SLOW GO Mode In the SLOW GO mode the IMP is fully operational but the IMP PLL divider has been programmed with a value that is dividing the IMP PLL VCO output to the system clock in order to save power The PLL output divider can only be used with the IMP PLL enabled The divider value is pro in the DF3 0 bits the IOMCR clock may be divided by a power of 2 20 219 No functionality is lost in SLOW GO mode 2 4 4 1 5 NORMAL Mode In NORMAL mode the IMP part is fully operational and the sys tem clock from the PLL is not being divided down 2 4 4 1 6 IMP Operation Mode Control Register IOMCR is a 8 bit read write register used to control the op
40. 401 then a standard 32 768 kHz crystal generates an initial general system clock of 13 14 MHz If the multiplication factor is 4 then a standard 4 192 MHz crystal generates an initial general system clock of 16 768 MHz The user would then write the MF bits or adjust the output frequency to the desired frequency NOTE Since the clock source for the periodic interrupt timer is CLKIN see Figure 2 2 the PIT timer is not disturbed when the IMP PLL is in the process of acquiring lock PEN PLL Enable Bit The PEN bit indicates whether the IMP PLL is operating This bit is written by the MC68LC302 based on the value of 5 during reset When the IMP PLL is disabled the VCO is not operating in order to minimize power consumption During hardware reset this bit is set if the VCCSYN pin specifies that the IMP PLL is enabled The only way to clear PEN is to hold the VCCSYN pin low during a hardware reset 0 The IMP is disabled Clocks are derived directly from the EXTAL pin 1 The IMP PLL is enabled Clocks are derived from the CLKOUT output of the PLL CLKODMO 1 CLKO Drive Mode 0 1 These bits control the output buffer strength of the CLKO pin Those bits can be dynami cally changed without generating spikes on the CLKO pin Disabling CLKO will save pow er and reduce noise 00 Clock Out Enabled Full Strength Output Buffer 01 Clock Out Enabled 2 3 Strength Output Buffer 10 Clock Out Enabled 1 3 Strength Output
41. 5 3 PIT Clock CLKIN is supplied to the periodic interrupt timer PIT submodule which allows the PIT clock to run independently of the system clock refer to Figure 2 2 and Section 3 System Integration Block SIB 2 4 3 6 IMP 5 The following pins are dedicated to the IMP operation 2 4 3 6 1 VCCSYN This pin is the Vcc dedicated to the analog IMP PLL circuits The volt age should be well regulated and the pin should be provided with an extremely low imped ance path to the Vcc power rail if the PLL is to be enabled VCCSYN should be bypassed to GNDSYN by a 0 1 uF capacitor located as close as possible to the chip package VCCSYN should be tied to ground if the PLL is to be disabled 2 4 3 6 2 GNDSYN This pin is the GND dedicated to the analog IMP PLL circuits The pin should be provided with an extremely low impedance path to ground GDNSYN should be bypassed to VCCSYN by a 0 1 uF capacitor located as close as possible to the chip pack age The user should also bypass GNDSYN to VCCSYN with a 0 01 uF capacitor as close as possible to the chip package 2 4 3 6 3 XFC This pin connects to the off chip capacitor for the PLL filter One terminal of the capacitor is connected to XFC the other terminal is connected to IQVCC 2 4 3 6 4 MODCLK MODCLK specifies what the initial VCO frequency is after a hardware reset if VOCSYN is tied high During the assertion of RESET the value of the VCCSYN and MODCLK input pins causes the PEN
42. 5 4 3 2 1 0 OFFSET 0 ID BR FR PR OV CD OFFSET 2 DATA LENGTH OFFSET 4 RX BUFFER POINTER 24 bits used upper 8 bits must 0 OFFSET 6 Figure 4 2 UART Receive Buffer Descriptor 4 3 8 4 UART TRANSMIT BUFFER DESCRIPTOR TX BD Data is presented to the CP for transmission on an SCC channel by arranging it in buffers referenced by the channel s Tx BD table The Tx BD shown in Figure 4 3 15 4 13 12 1 10 9 8 7 6 5 4 83 2 4 0 OFFSET 0 R X P OFFSET 2 LENGTH ES TX BUFFER POINTER 24 01 used upper 8 bits must be 0 Figure 4 3 UART Transmit Buffer Descriptor 4 8 MC68LC302 REFERENCE MANUAL MOTOROLA Communications Processor CP 4 3 8 5 UART EVENT REGISTER The SCC event register SCCE is called the UART event register when the SCC is operating as a UART 7 6 5 4 3 2 1 0 CTS IDL BRK CCR BSY TX RX 4 3 8 6 UART MASK REGISTER The SCC mask register SCCM is referred to as the UART mask register when the SCC is operating as a UART If a bit in the UART mask reg ister is a one the corresponding interrupt in the event register will be enabled If the bit is zero the corresponding interrupt in the event register will be masked This register is cleared upon reset 4 3 9 Autobaud Controller New The autobaud function determines the baud rate a
43. 5 Ring Oscillator Control Register RINGOCR 2 19 2 4 4 3 6 Ring Oscillator Event Register RINGOEVR 2 20 2 5 MC68LC302 Dual Port FAM Da ode adio oae 2 20 2 6 Internal Registers P RE NES RR OR Se ERREUR 2 23 Section 3 System Integration Block SIB 3 1 SOY SIGINI onem EE 3 1 3 1 1 System Control Register SOR iii e 3 2 3 1 2 System Stat s cc 3 3 3 1 3 SOV SLIT VASO MOU ENING I 3 3 3 1 4 Freeze 3 5 3 1 5 Hardware Watchdog ei Sra 3 5 3 2 Programmable Data Bus Size 3 6 3 2 1 Bus Switch Register BSH erectae cerise debeo take ne ned LI pennis 3 6 3 2 2 Basic PIOCCOUG dit du pod npn i Ul uda Ud 3 6 3 3 Load Boot Code from An SCC essent 3 7 3 4 dae edes a decet 3 10 3 4 1 MOBSEC302 oie e DEED EEUU 3 10 3 4 2 Registers Independent DMA Controller 3 11 3 4 2 1 Channel Mode Register 3 11 3 4 2 2 Source Address Pointer Register 3 13 3 4 2 3 Destination A
44. Array GNDP2 1 1 0 EXTAL FRZ AVEC CLKO O O O IPL1 XTAL DISCPU GNDSYN NC GNDQ1 IPL2 NC BUSW O CS1 CS2 PB10 NC HALT 2 VCCSYN O O A4 O GNDA2 1 O MC68LC302RC Bottom FC2 6 View A8 VCCA1 VCCA1 16 O O A12 A13 GNDAi 17 CD1 TXD2 14 18 GNDD1 D8 NC VCCD1 PA9 NC O 19 GNDD2 D2 D1 RCLK2 013 012 VCCQ2 GNDQ2 07 04 GNDQ4 51 O O O O 1 2 3 4 5 6 7 8 9 10 11 12 13 MOTOROLA MC68LC302 USER S MANUAL SUPPLEMENT Mechanical Data and Ordering Information 7 1 2 Surface Mount TQFP I lt z 5 521 DR PBO9 1 75 __ 16 8 __ 17 WDOG A18 TOUT2 _ 1 19 TIN2L_ __ 015 TIL 1014 1013 UDS WEH 1012 LDS WEL GNDD 2 1011 MC68LC302PU R W OEL_ 109 Top View GNDQ vcca2 BR IPLO GNDO2 BGACK IPLTL VCCD1 BG IPL2 __ 07 EXTALL__ 106 XTALL_ __ 05 __ 04 DISCPU GNDD2 BUSW D3 GNDSYN 02 XFCL 01 VCCSYNL 25 51 T gt 7 2 MC68LC302 USER S MANUAL SUPPLEMENT MOTOROLA Mechanical Data and Ordering Information 7 2 PACKAGE DIMENSIONS 7 2 1 Pin Grid Array PGA
45. Buffer 11 Clock Out Disabled CLKO is driven high by internal pullup NOTE These IMP bits are in a different address location than in the MC68302 where they are located at address FA bits 15 14 MOTOROLA MC68LC302 REFERENCE MANUAL 2 11 Configuration Clocking Low Power Modes and Internal Memory IPLWP IMP PLL Control Write Protect Bit This bit prevents accidental writing into the IPLCR After reset this bit defaults to zero to enable writing Setting this bit prevents further writing excluding the first write that sets this bit 2 4 3 5 IMP INTERNAL CLOCK SIGNALS The following paragraphs describe the IMP internal clock signals 2 4 3 5 1 IMP System Clock The IMP system clock is supplied to all modules on the IMP with the exception of the BRG clocks which are connected directly to the VCO output with the PLL enabled The IMP can be programmed to operate with or without IMP PLL If IMP PLL is active the system clock will be driven by PLL clock divider output If IMP PLL is not active the system clock will be driven by the PLL input clock CLKIN 2 4 3 5 2 BRG Clock The clock to the BRGs can be supplied from the IMP PLL input CLKIN when the IMP PLL is disabled or from the IMP PLL VCO output when the PLL is enabled The BRG prescaler input clock may be optionally programmed to be divided by 2 to allow very low baud rates to be generated from the system clock by setting the BCD bit in the IOMCR 2 4 3
46. DTACK OUTPUT 5 Figure 6 13 Internal Master Chip Select Timing Diagram 6 24 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 6 14 AC ELECTRICAL SPECIFICATIONS CHIP SELECT TIMING EXTERNAL MASTER see Figure 6 14 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol Min Max Min Max Min Unit 154 Clock Low to Low 1 6 Wait States tciprkL 30 25 20 ns 160 ASLow to CS Low 30 25 20 ns 161 ASHigh to CS High tasucsh 30 25 20 ns 162 Address Valid to AS Low tAVASL 15 12 10 ns 164 AS Negated to Address Hold Time tasHal 0 0 0 ns 165 AS Low to DTACK Low 0 Wait State tasLDTKL 45 40 30 ns 167 AS High to DIACK High tASHDTKH 30 25 20 ns S0 51 52 53 54 55 56 57 50 KAVA YY A23 A1 INPUT AS INPUT CS3 CS0 OE WEH WEL lt 5 RW INPUT DTACK OUTPUT BERR OUTPUT Figure 6 14 External Master Chip Select Timing Diagram MOTOROLA MC68LC302 REFERENCE MANUAL 6 25 Electrical Characteristics 6 15 AC ELECTRICAL SPECIFICATIONS PARALLEL I O see Figure 6 15 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol win Max Min Max Min Unit 180 Input Data Setup Time
47. IMP 32 bit reserved spaces for 3 registers added for the MC68L C302 These registers are used to con trol the PLL clock generation and low power modes See 2 4 Clock Generation and Low Power Control Table 2 1 System Configuration Registers Address Name Width Description Reset Value 16 Periodic Interrupt Timer Register 0000 0F2 BAR 16 Base Address Register BFFF 0F4 SCR 24 System Control Register 0000 OF 0F7 IWUCR 8 IMP Wake Up Control Register 00 0F8 IPLCR 16 IMP PLL Control Register 0FA IOMCR 8 IMP Operations Mode Control Register 00 0FB IPDR 8 IMP Power Down Register 00 0FC RES 32 Reserved 2 4 CLOCK GENERATION AND LOW POWER CONTROL The MC68LC302 includes a clock circuit that consists of crystal oscillator drive circuit capa ble of driving either an external crystal or accepting an oscillator clock a PLL clock synthe sizer capable of multiplying a low frequency clock or crystal such as a 32 kHz watch crystal up to the maximum clock rate of each processor and a low power divider which allows dynamic gear down and gear up of the system clock for each processor on the fly On Chip Clock Synthesizers with output system clocks Oscillator Drive Circuits and Pins PLL Clock Synthesizer Circuits with Low Power Output Clock Divider Block Low Power Control Of IMP Slow Go Modes using PLL Clock Divider Blocks Varied Low Power STOP Modes for Optimizin
48. Interrupt Controller Programming Model The user communicates with the interrupt controller using four registers The global interrupt mode register GIMR defines the interrupt controller s operational mode The interrupt pending register IPR indicates which INRQ interrupt sources require interrupt service The interrupt mask register IMR allows the user to prevent any of the INRQ interrupt sources from generating an interrupt request The interrupt in service register ISR provides a ca pability for nesting INRQ interrupt requests 3 5 2 1 Global Interrupt Mode Register GIMR The user normally writes the GIMR soon after a total system reset The GIMR is initially 0000 and is reset only upon a total system reset MOD 7 M1 ET7 V V5 RESERVED MOD Mode The Mode Should be set to Dedicated 0 Normal operational mode Interrupt request lines are configured as IPL2 IPLO 1 Dedicated operational mode Interrupt request lines are configured as IRQ7 IRQ6 and IRQ1 3 14 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB IV7 Level 7 Interrupt Vector Internal Vector Generation Should Be Used 0 Internal vector 1 External vector IV6 Level 6 Interrupt Vector Internal Vector Generation Should Be Used 0 Internal vector 1 External vector IV1 Level 1 Interrupt Vector Internal Vector Generation Should Be Used 0 Internal vector 1 External vector ET7
49. MOTOROLA Communications Processor CP M2 Match Character2 Bit 9 When this bit is set the character received matched the User Defined Character 2 The received character is written into the receive control character register M1 Match Character1 Bit 8 When this bit is set the character received matched the User Defined Character 1 The received character is written into the receive control character register EOT End Of Table bit 3 When this bit is set the autobaud controller measured start length exceeded the maxi mum start length of the last entry in the lookup table lowest baud rate NOTE The user must clear this bit when it is set OV Overrun bit 1 If this bit is set a receiver overrun occurred during autobaud reception NOTE The user must clear this bit when it is set CD Carrier Detect Lost bit 0 If this bit is set the carrier detect signal was negated during autobaud reception NOTE The user must clear this bit when it is set Lookup Table Size Lookup table size is the number of baud rate entries in the external lookup table Lookup Table Pointer The lookup table pointer is the address in the external RAM where the lookup table begins NOTE The lookup table cannot cross a 64k memory block boundary 4 3 9 4 4 Autobaud Lookup Table The autobaud controller uses an external lookup table to determine the baud rate while in the process of receiving
50. Multipro tocol Processor Product Brief provides a brief description of the MC68L C302 capabilities The MC68302 Integrated Multiprotocol Processor User s Manual is required since the MC68LC302 Low Power Integrated Multiprotocol Processor Reference Manual only de scribes the new features of the MC68L C302 This user s manual is organized as follows Section 1 Introduction Section 2 Configuration Clocking Low Power Modes and Internal Memory Map Section 3 System Integration Block SIB Section 4 Communications Processor CP Section 5 Signal Description Section 6 Electrical Characteristics Section 7 Mechanical Data And Ordering Information ELECTRONIC SUPPORT The Technical Support BBS known as AESOP Application Engineering Support Through On Line Productivity can be reach by modem or the internet AESOP provides commonly asked application questons latest device errata device specs software code and many other useful support functions Modem Call 1 800 843 3451 outside US or Canada 512 891 3650 on a modem that runs at 14 400 bps or slower Set your software to N 8 1 F emulating a vt100 Internet This access is provided by telneting to pirs aus sps mot com 129 38 233 1 or through the World Wide Web at http pirs aus sps mot com Sales Offices For questions or comments pertaining to technical information questions and applications please contact one of the following sales offices nearest you MC68LC3
51. a 16 bit option register OR e g BRO and ORO The BR should normally be programmed after the OR since the BR contains the chip select enable bit 3 8 1 1 Base Register BR3 BRO These 16 bit registers consist of a base address field a read write bit and a function code field FC2 FCO BASE ADDRESS A23 A13 RW EN FC2 FCO Function Code This field is contained in bits 15 13 of each BR These bits are used to set the address space function code Because of the priority mechanism and the EN bit only the CSO line is active after a system reset Bits 12 2 Base Address These bits are used to set the starting address of a particular address space RW Read Write 0 The chip select line is asserted for read operations only 1 The chip select line is asserted for write operations only EN Enable 0 The chip select line is disabled 1 The chip select line is enabled After system reset only CSO is enabled 51 are disabled In disable CPU mode 53 50 are disabled at system reset The chip select does not require disabling before changing its parameters 3 8 1 2 Option Registers These four 16 bit registers consist of a base address mask field a read write mask bit a compare function code bit and a DIACK generation field 15 13 12 2 1 0 DTACK BASE ADDRESS MASK V23 MI3 MRW CFC 3 26 MC68LC302 REFERENCE MANUAL MOTOROLA
52. a character The lookup table contains two entries for each supported baud rate The first entry is the maximum start length for the particular baud rate and the second entry is the nominal length for a 1 2 START bit To determine the two values for each table entry first calculate the autobaud sampling rate EQ 2 To do this EQ 1 must be used until EQ 2 is satisfied The sampling rate is the lowest speed baud rate that can be generated by the SCC baud rate generator that is over a thresh old defined in EQ 2 BRG Clk Rate System Clock or TINI Clock Divider bits in SCON 1 EQ 1 MOTOROLA MC68LC302 REFERENCE MANUAL 4 15 Communications Processor CP assuming that the DIV bit in SCON is set to 0 otherwise an additional divide by 4 must be included Sampling Rate BRG Clk Rate where BRG Clk rate gt Max Desired Baud Rate x 16 EQ 2 For instance if a 115 2K baud rate is desired with a 16 67 MHz system clock the minimum sampling rate possible is 1 843 MHz 115 2K x 16 This exact frequency can be input to RCLK1 or as the sample clock If the system clock is to be used a 16 67 MHz system clock cannot produce an exact baud rate clock of 1 843 MHz The lowest one that can be used is Baud Rate 16 67 MHz 7 1 2 083 MHz Thus 2 083 MHz is the sampling rate and the SCON should be set to 000E to produce this Once the sampling rate is known the other two equations follow easily The maximu
53. and Stop modes By programming this register it is possible to minimize power consumption due to external pul lups or pull downs or floating inputs LPDCR BAR 82A 7 6 5 4 3 2 1 0 LPAL LPDL LPDEN 0 0 0 0 0 0 0 Read Write LPDEN Low Power Drive Enable 0 The IMP 68000 data and address buses will be high impedance 1 The IMP 68000 data and address buses to be driven according to the LPDL bit LPDL Low Power Drive Data Low 0 The data bus will be driven high when the LPDEN bit is set 1 The data bus will be driven low when the LPDEN bit is set LPAL Low Power Drive Address Low 0 The address bus will be driven high when the LPDEN bit is set 1 The address bus will be driven low when the LPDEN bit is set 2 4 4 1 8 IMP Power Down Register IPWRD The IPWRD is a 8 bit read write register located at 0FB that is used to control the low power operation of the IMP This register must be written with the same operand as the STOP instruction that follows This tells the hard ware what level of interrupt and above will stop the MC68LC302 from entering low power if it occurs while the clocks are being stopped 2 4 4 1 9 Default Operation Modes See 2 4 2 1 Default System Clock Generation 2 4 4 2 LOW POWER SUPPORT The following sections describe how to enter the various low power modes 2 4 4 2 1 Enter the SLOW GO mode When the required IMP performance can be achieved with a lower c
54. damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and M are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer Literature Distribution Centers USA EUROPE Motorola Literature Distribution Box 20912 Arizona 85036 JAPAN Nippon Motorola Ltd 4 32 1 Nishi Gotanda Shinagawa ku Tokyo 141 Japan ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Center No 2 Dai King Street Tai Po Industrial Estate The complete documentation package for MC68LC302 consists of the MC68LC302RM AD MC68LC302 Low Power Integrated Multiprotocol Processor Reference Manual M68000PM AD MC68000 Family Programmer s Reference Manual MC68302UM AD MC68302 Integrated Multiprotocol Processor User s Manual and the MC68LC302 D MC68LC302 Low Power Integrated Multiprotocol Processor Product Brief The MC68LC302 Low Power Integrated Multiprotocol Processor Reference Manual de scribes the programming capabilities registers and operation of the MC68L C302 that differ from the original MC68302 the MC68000 Family Programmer s Reference Manual provides instruction details for the MC68LC302 and the MC68LC302 Low Power Integrated
55. derive the general system frequency of the IMP The IMP PLL is comprised of a phase detector loop filter voltage controlled oscillator VCO and multiplication block 2 4 3 4 FREQUENCY MULTIPLICATION The IMP PLL can multiply the CLKIN input fre quency by any integer between 1 and 4096 The multiplication factor may be changed to the desired value by writing the MF11 MFO bits in the When the IMP PLL multiplier is modified in software the IMP PLL will lose lock and the clocking of the IMP will stop until lock is regained worst case is 2500 EXTAL clocks If an alteration in the system clock rate is desired without losing IMP PLL lock the value in the low power clock divider can be to modified to lower the system clock rate dynamically The low power clock divider bits are located in the IOMCR register NOTE If IMP PLL is enabled the multiplication value must be large enough to result in the VCO clock being greater than 10 MHz MOTOROLA MC68LC302 REFERENCE MANUAL 2 9 Configuration Clocking Low Power Modes and Internal Memory 2 4 3 4 1 Low Power PLL Clock Divider The output of the IMP VCO is sent to a low power divider block The clock divider can divide the output frequency of the VCO before it generates the system clock The clock for the baud rate generators BRGs bypasses this clock divider The purpose of the clock divider is to allow the user to reduce and restore the operating fre quency of the IMP
56. lt 390 nF MOTOROLA MC68LC302 REFERENCE MANUAL 6 7 Electrical Characteristics 6 8 AC ELECTRICAL SPECIFICATIONS IMP BUS MASTER CYCLES see Figure 6 2 Figure 6 3 and Figure 6 4 16 67 MHz 20 MHz 25 MHz 95 0 V 95 0 V 95 0 V Num Characteristic Symbol Unit Min Max Min Max Min Max 6 Clock High to FC Address Valid tcurcApv 0 45 0 45 0 30 ns Clock High to Address Data Bus High Im 7 pedance Maximum 9 2 50 50 33 ns 8 acai High to Address FC Invalid Mini lenis 0 Ex 0 0 E ns 9 Clock High to AS DS Asserted see Note 1 tcusr 3 30 3 30 3 20 ns Address EC Valid to AS DS Asserted ER m 11 Read AS Asserted Write see Note 2 tarcvsL 15 15 10 ns 12 Clock Low to AS DS Negated see Note 1 30 30 20 ns 13 Nole gt Negated to Address FC Invalid see NS 15 25 15 10 AS DS Read Width Asserted see i4 A te 120 120 88 Ins 14A DS Width Asserted Write see Note 2 tps 60 60 40 ns 15 AS DS Width Negated see Note 2 tsu 60 60 40 ns 16 Clock High to Control Bus High Impedance tcucz 50 50 33 ns 17 AS DS Negated to RAW Invalid see Note 2 15 15 10 ns 18 Clock High to R W High see Note 1 tCHRH 30 30 20 ns 20 Clock High to R W Low see 1
57. ode db pn debt Durs 7 3 7 2 2 Surface Mount p ven vade 7 4 7 3 Ordering Information cde 7 5 MC68LC302 REFERENCE MANUAL MOTOROLA SECTION 1 INTRODUCTION Motorola has developed a low cost version of the well known MC68302 integrated multipro tocol processor IMP called the MC68L C302 Simply put the LC302 is a traditional 68302 minus the third serial communication controller SCC3 and has a new static 68000 core a new timer and low power modes It is packaged in a low profile 100 TQFP that reduces board space from the regular 68302 as well as making it suitable for use in height restricted applications such as PCMCIA The document fully describes all the differences between the LC302 and the regular 68302 Any feature not described in this document will operate as described in the MC68302 User s Manual In addition this document contains the full set of electrical descriptions for the LC302 even though most of them are exactly the same as the 68302 1 1 BLOCK DIAGRAM The block diagram is shown in Figure 1 1 TAUTA BR e Ue a E wies Pon eve Ade an e VS 1 LOW 1 GENERAL 3 TIMERS POWER INTERRUPT PURPOSE 4 CHIP SELECTS ROM CONTROL CONTROLLER DMA PIO CHANNEL SYSTEM CONTROL 68000 STATIC M68000 SYSTEM BUS CORE 20 ADDRESS a 8 16 DATA DUAL PORT CHANNELS RAM RISC PERIPHERAL BUS x CONTROLLER 2 SERIAL SCP CHANNELS SCC
58. of four programmable chip select signals Each chip select signal has an identical internal structure For each memory area the user may also define an in ternally generated cycle termination signal DTACK This feature eliminates board space that would be necessary for cycle termination logic The chip select logic is active for memory cycles generated by internal bus masters M68000 core IDMA SDMA DRAM refresh or external bus masters A23 A20 are driven to zero internally and FC2 0 are driven to 5 These signals are driven externally on the falling edge of AS and are valid shortly after AS goes low NOTE For more information on the operation of the Chip Selects please refer to Section 3 of the MC68302 Users Manual NOTE Internal Masters CPU and SDMA drive A23 A20 and FC2 FCO internally The CS logic compares the signals to the values programmed in the registers In Disable CPU mode or for External Bus Masters the A23 A20 signals are internally driven to zero so the user must program MOTOROLA MC68LC302 REFERENCE MANUAL 3 25 System Integration Block 518 the corresponding bits in the Chip Select registers to zero or mask off those address bits Also FC2 0 are driven to 5 so we suggest that the function code comparison be turned off 3 8 1 Chip Select Registers Each of the four chip select units has two registers that define its specific operation These registers are a 16 bit base register BR and
59. pin which is associated with the 32 kHz or 4 MHz PLL The MODCLK pin is sampled after reset and then becomes PA12 New VCCsyn GNDsyn and pins have been added in support of the on chip PLL For purposes of emulation support only a special 132 PGA version is supported This version adds back the FC2 0 IAC FRZ and AVEC pins The FC2 0 pins allow bus cy cles to be distinguished between program and data accesses interrupt cycles etc The IAC FRZ and AVEC pins are provided so that emulation vendors can quickly retrofit their existing 68302 emulator designs to support the L C302 MC68LC302 REFERENCE MANUAL MOTOROLA SECTION 2 CONFIGURATION CLOCKING LOW POWER MODES AND INTERNAL MEMORY MAP The MC68L C302 integrates high s peed M68000 processor with multiple communications peripherals The provision of direct memory access DMA control and link layer manage ment with the serial ports allows high throughput of data for communications intensive appli cations such as basic rate Integrated Services Digital Network ISDN The MC68L C302 can operate either in the full MC68000 mode with a 16 bit data bus or in the MC68008 mode with an 8 bit data bus by connecting the bus width BUSW pin low NOTE The BUSW pin is static and is not intended to be used for dy namic bus sizing Instead the BSW and BSWEN bits in the BSR register should be used to switch the bus width after reset 3 2 Programmable Data Bus Size Switch If the s
60. register refers to the protocol specific bits 15 6 of the SCC mode register when that SCC is configured for transparent mode The transparent mode register is cleared by reset All undefined bits should be written with zero 15 14 13 12 11 10 9 8 7 6 5 0 EXSYN 5 REVD COMMON SCC MODE BITS 4 3 12 3 TRANSPARENT RECEIVE BUFFER DESCRIPTOR RXBD The CP reports information about the received data for each buffer using BD The RxBD is shown in Figure 4 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 re ND mice eoe m ret ee OFFSET 2 DATA LENGTH OFFSET 4 RX BUFFER POINTER 24 bits used upper 8 bits must be 0 OFFSET 6 Figure 4 8 Transparent Receive Buffer Descriptor 4 24 MC68LC302 REFERENCE MANUAL MOTOROLA Communications Processor CP 4 3 12 4 TRANSPARENT TRANSMIT BUFFER DESCRIPTOR TX BD Data 15 sented to the CP for transmission on an SCC channel by arranging it in buffers referenced by the channel s Tx BD table The Tx BD is shown in Figure 4 9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 Tere pen e ven OFFSET 2 OFFSET 4 TX BUFFER POINTER 24 bits used upper 8 bits must be 0 OFFSET 6 Figure 4 9 Transparent Transmit Buffer Descriptor 4 3 12 5 TRANSPARENT EVENT REGISTER The SCC event register SCCE is referred to as the transparent event register w
61. the FC signals are internally driven to 5 for external master accesses to internal peripherals The 23 20 pins have been removed from the MC68L C302 These signals are still driven internally by the core and the internal peripherals The user must program the full 24 bit address in the chip select base registers option registers and in the pointers used by the internal DMA and SCCs In disable CPU mode and when HALT is asserted for external mas ters the A23 20 signals are driven to zero for all external master accesses The other signals removed from the MC68L C302 are IAC BERR FRZ BRG1 DREQ PA13 DACK PA14 DONE PA15 IACK7 PBO IACK6 PB1 IACK7 PB2 and TOUT 1 PBA The signals XFC and MODCLK multiplexed with PA12 have been added for use with the on chip phase lock loop For purposes of emulation support only a special 132 PGA version is supported This ver sion adds back the FC2 0 IAC FRZ and AVEC pins 2 2 IMP CONFIGURATION CONTROL A number of reserved entries in the external M68000 exception vector table are used as addresses for the internal system configuration registers See Table 2 1 2 2 MC68LC302 REFERENCE MANUAL MOTOROLA Configuration Clocking Low Power Modes and Internal Memory The BAR entry contains the BAR described in this section The SCR entry contains the SCR described in Section 3 System Integration Block SIB Figure 2 1 shows all the IMP on chip addressab
62. to Clock Low 30 25 20 ns 131 Clock Low to Data In Hold Time tci piH 15 12 10 ns NOTES 1 Synchronous specifications above are valid only when SAM 1 in the SCR 2 It is required that this signal not be asserted prior to the previous rising CLKO edge i e in the previous clock cycle It must be recognized by the IMP no sooner than the rising CLKO edge shown in the diagram MOTOROLA MC68LC302 REFERENCE MANUAL 6 19 Electrical Characteristics CLKO OUTPUT IAC OUTPUT UDS LDS INPUT RW INPUT D15 D0 OUTPUT DTACK OUTPUT INPUT T 19 mi lt 2 gt 19 123 2 Figure 6 9 External Master Internal Synchronous Read Cycle Timing Diagram 6 20 MC68LC302 REFERENCE MANUAL MOTOROLA CLKO OUTPUT 23 1 50 51 INPUT AS INPUT IAC OUTPUT INPUT RW INPUT D15 D0 OUTPUT DTACK OUTPUT Electrical Characteristics 52 53 54 Sw Sw S5 Figure 6 10 External Master Internal Synchronous Read Cycle Timing Diagram MOTOROLA One Wait State MC68LC302 REFERENCE MANUAL 6 21 Electrical Characteristics A23 A1 INPUT A8 INPUT IAC OUTPUT INPUT R W INPUT 00 015 INPUT DTACK OUTPUT Figure 6 11 External Master Internal Synchronous Write Cycle Timin
63. 0 The data bus pins are shown in Figure 5 5 When the MC68L C302 is in 8 bit data bus mode D15 D8 become general purpose 1 pins 15 8 00 07 D15 D8 PN15 8 Figure 5 5 Data Bus Pins This 16 bit bidirectional three state bus is the general purpose data path It can transmit and accept data in either word or byte lengths For all 16 bit LC302 accesses byte 0 the high order byte of a word is available on D15 D8 conforming to the standard M68000 for mat When working with an 8 bit bus BUSW is low the data is transferred through the low order byte 07 00 The high order byte 015 08 is not used for data transfer and those pins can be used as 8 general purpose ports PNIO 5 8 MC68LC302 REFERENCE MANUAL MOTOROLA Signal Description 5 7 BUS CONTROL PINS The bus control pins are shown in Figure 5 6 The signals shown in parentheses are only available in DISCPU mode AS gt OE RW UDS AO a gt WEL WE LDS DS gt DTACK IAC This pin is available in PGA Package only Figure 5 6 Bus Control Pins AS Address Strobe This bidirectional signal indicates that there is a valid address on the address bus This line is an output when the LC302 M68000 core SDMA or IDMA is the bus master and is an input otherwise OE R W Output Enable Read Write When the core is enabled this output is active during a read cycle and indicates that an external d
64. 00 core SDMA or IDMA is the bus master and are inputs otherwise The function codes output by the M68000 core are predefined whereas those output by the SDMA and IDMA are programmable The function code lines are inputs to the chip select logic and IMP internal register decoding in the BAR AVEC Autovector Input Interrupt Output In normal operation this signal functions as the input AVEC AVEC when asserted during an interrupt acknowledge cycle indicates that the M68000 core should use automatic vectoring for an interrupt This pin operates like VPA on the MC68000 but is used for au tomatic vectoring only AVEC instead of DTACK should be asserted during autovectoring and should be high otherwise 5 10 MC68L C302 BUS INTERFACE SIGNAL SUMMARY Table 5 3 and Table 5 4 summarize all bus signals discussed in the previous paragraphs They show the direction of each pin for the following bus masters M68000 core IDMA SDMA includes DRAM refresh and external bus masters When the core is enabled only the L C302 core has access to the internal memory When the core is disabled the IDMA SDMA and external bus masters can access either internal dual port RAM and registers or an external device or memory When an external bus master accesses the internal dual port RAM or registers the access may be synchronous or asynchronous External masters are only directly supported in the Disable CPU mode When the core is enabled and an externa
65. 000 core the communication processor and system integration block All M68000 bus timings are referenced to the CLKO signal CLKO supports both CMOS and TTL output levels The output drive capability of the CLKO signal is programmable to one third two thirds or full strength or this output can be disabled 5 4 MC68LC302 REFERENCE MANUAL MOTOROLA Signal Description XFC IMP External Filter Capacitor This pin is a connection for an external capacitor to filter the PLL MODCLK PA12 Clock Mode Select The state of this input signal along with VCCSYN during reset selects whether the PLL is enabled and the type of external clock that is used by the phase locked loop PLL in the clock synthesizer to generate the system clocks Table 5 2 shows the default values of the PLL When the PLL is disabled VOCCSYN 0 this pin functions as PA12 When the is enabled VCCSYN 1 this pin is sampled as MODCLK at reset This pin must be valid as long as RESET and HALT are asserted and have a hold time of 5ns after RESET and HALT are negated After reset MODCLK PA12 is a general purpose pin Table 5 2 Default Operation Mode of the PLL PLL Multi Factor EXTAL Freq CLKIN to the LC302 System VCCSYN MODCLK MF 1 examples PLL Clock 0 X Disabled EXTAL EXTAL 1 0 Enabled 4 4 192MHz 4 192MHz 16 768 MHz 1 1 Enabled 401 32 768KHz 32 768KHz 13 14 MHz VCCSYN Analog PLL Circuit Power
66. 02 REFERENCE MANUAL MOTOROLA Huntsville ARIZON goura Hills CALIFORNIA Los Angeles CALIFORNIA Irvine CALIFORNIA CALIFORNIA San Diego CALIFORNIA Sunnyvale Golorado Springs COLORADO D CONNECTICUT Wallingford FLORIDA Maitland FLORIDA kompano Beach Fort Lauderdal FLORIDA Clearwater GEORGIA arang IDAHO Boi ILLINOIS Chica o Hoffman Estates INDIANA Fort Wayne INDIANA Indianapolis INDIANA Kokomo ANS Cedar Rapids ANSAS Kansas City Mission MARYLAND Columbia CANADA BRITISH COLUMBIA Vancouver ONTARIO Toronto ONTARIO Ottawa QUEBEC Montreal INTERNATIONAL AUSTRALIA Melbourne AUSTRALIA Sydney BRAZIL Sao Paulo CHINA Beijing FINLAND Helsinki Car Phone FRANCE Paris Vanves GERMANY Langenhagen Hanover GERMANY Munich GERMANY Nuremberg GERMANY Sindelfingen GERMANY Wiesbaden HONG KONG Kwai Fong Tai Po INDIA Bangalore ISRAEL Tel Aviv ITALY Milan JAPAN Aizu JAPAN Atsugi JAPAN Kumagaya JAPAN Kyushu JAPAN Mito JAPAN Nagoya JAPAN Osaka JAPAN Sendai JAPAN Tachikawa JAPAN Tokyo JAPAN Yokohama KOREA Pusan KOREA Seoul MOTOROLA UNITED STATES 205 464 6800 602 897 5056 407 628 2636 486 9776 61 3 887 0711 61 2 906 3855 55 11 815 4200 86 505 2180 358 0 35161191 358 49 211501 33 1 40 955 900 49 511 789911 49 89 92103 0 49 911 64 3044 49 7031 69 910 49 611 761921 852 4808333 852 6668333 91 812 6
67. 05 lo 3 2 mA CLKO 0 4 Output Drive CLKO 50 Output Drive ISDN I F Mode 150 pF Output Drive All Other Pins 130 Output Drive Derating Factor for CLKO of 0 030 ns pF 20 50 Output Drive Factor for CLKO of 0 025 ns pF 50 130 Output Drive Derating Factor for All Other Pins 0 025 ns pF 20 100 Output Drive Derating Factor for All Other Pins 0 05 ns pF 100 200 Power 5 0 VolPat y 4 5 5 5 V 3 3 Volt Part DD 30 36 Vss 0 0 V NOTE The maximum for a given pin is one half the lo rating for that For an between 400 uA and loj 2 mA the minimum is calculated Vpp 1 05 400 mA MOTOROLA MC68LC302 REFERENCE MANUAL 6 5 Electrical Characteristics 6 6 DC ELECTRICAL CHARACTERISTICS NMSI1 IN IDL MODE Characteristic Symbol Min Max Unit Condition Input Pin Characteristics L1CLK L1SY1 L1RXD L1GR Input Low Level Voltage 10 20 V 96 of Vpp Input High Level Voltage Vin 20 10 Input Low Level Current Hl t 10 Vin Vss Input High Level Current 10 Output Pin Characteristics 1 1 5051 5062 L1RQ Output Low Level Voltage VoL 0 1 0 V lo 5 0 mA Output High Level Voltage Von Vpp 1 0 Vpp V 400 uA
68. 13 4 3 9 4 2 Enter Baud Hunt 4 14 4 3 9 4 3 Autobaud Command 0 4 14 4 3 9 4 4 Autobaud Lookup 4 15 4 3 9 5 Lookup Table 4 17 4 3 9 6 Determining Character Length and 4 17 4 3 9 7 Autobaud Reception Error Handling Procedure 4 18 4 3 9 8 Transmisslofi odere rente er ace ret mee wee bu edd 4 18 4 3 9 8 1 ECHO 5 RR 4 19 4 3 9 8 2 Smart ECNO atio 4 19 4 3 9 9 Reprogramming to UART Mode or Another Protocol 4 20 4 3 10 HDEG Conlrell tiu i cote a lie tab tice arate cera 4 20 4 3 10 1 HDLC Memory eiu nen abe rta ca ehe Su EN ace a 4 20 4 3 10 2 a I bk AE 4 20 4 3 10 3 HDLC Receive Buffer Descriptor Rx BD 4 21 4 3 10 4 HDLC Transmit Buffer Descriptor Tx 4 21 4 3 10 5 HDLC Event Register eessesssssssseeeeeeeeeeen nennen 4 21 4 3 10 6 HDLC Mask ede dep pn era sen ctetu e bed esos 4 21 4 3 11 BIS VYING
69. 2 21 2 3 26 Disable CPU Logic 68000 p Do udi e 3 28 Bus Arbitration eu ae Deb 3 28 Internal orit eoe Paru oe Fre ci 3 28 External Bus 3 28 Dynamic RAM Refresh 3 29 Section 4 Communications Processor CP MC68LC302 Key Differences from the 68302 4 1 Serial Channels Physical 4 2 Serial Interface 4404122 4 22 4 2 Serial Interface Mode Register SIMODE 4 2 Serial Interface Mask Register 1 4 4 Serial Communication Controllers 4 4 SCC Configuration Register 4 4 Divide by 2 Input Blocks New 4 4 Disable SCC1 Serial Clocks Out 015 4 4 RCLK1 and TCLK1 Pin 4 5 MC68LC302 REFERENCE MANUAL vii Table of Contents Paragraph Title Page Number Number 4 3 3 SCC Mode Register 5
70. 20 Instruction 2 3 Reset SMC Memory Structure 4 26 Total System 2 3 Revision Number 2 20 Ring Oscillator 2 18 Ringo 2 18 RINGOCR 2 19 RINGOEVR 2 20 RMC 3 4 MOTOROLA MC68LC302 REFERENCE MANUAL RXD1 L1RXD 5 15 S SAM 3 4 3 28 SAPR 3 13 SCC 2 20 Buffer Descriptor 4 6 DSR 4 6 Enable Receiver 4 5 Normal Operation 4 5 SCON 4 4 Software Operation 4 5 TIN1 TIN2 5 20 SCC Mode Register 4 5 SCC Parameter RAM 4 7 SCC Parameter RAM Memory Map 4 7 SCCs 4 4 SCIT 4 2 SCM 4 5 SCON 4 4 SCP 2 20 Serial Communication Port 4 25 SCP Port 5 19 SCR 3 2 SCR System Control Register 2 4 SCR Register Bits 3 2 Serial Channels Physical Interface 4 2 Serial Communication Controllers 4 4 Serial Communication Port 4 25 6 29 Serial Management Controllers 4 26 SMC1 Receive Buffer Descriptor 4 26 SMC1 Transmit Buffer Descriptor 4 26 SMC2 Receive Buffer Descriptor 4 27 SMC2 Transmit Buffer Descripto 4 27 Signals AS 3 3 3 25 BERR 2 4 3 3 3 4 3 5 3 6 BG 3 28 5 11 BGACK 5 11 BR 3 28 3 29 5 10 BUSW 2 1 5 7 CD1 5 16 CLKO 5 4 CS 2 4 3 3 CSO 3 26 3 28 5 21 CTS1 5 17 DISCPU 3 28 5 7 INDEX 5 Index DREQ 3 11 DTACK 3 4 3 26 3 28 5 12 EXTAL 5 2 5 4 FC2 FCO 5 12 GCI 5 15 HALT 2 4 5 6 IAC 5 10 IDL 5 15 5 17 ILPO 5 11 IRQ1 5 12 NMSI2 5 17 NMSI3 5 18 PCM Highway 5 15 Port A 5 17 5 18 Port B 5 20 RESET 2 3 5 6 5 20 RMC 3 4 RTS1 5 17 SCP 5 19 TIN1 TIN2 5 20 WDOG 3 18 5 20 XTAL 5 4 SI
71. 21 Rising Edde 50 10 40 7 35 7 08 RXD1 Hold Time from 322 RCLK1 Rising Edge see 10 50 7 40 7 35 ns 2 CD1 Setup Time to RCLK1 323 Rising Edge 50 10 40 7 35 7 08 5 1 The ratio CLKO TCLK1 CLKO RCLK1 must greater than or equal to 2 5 1 for external clock The input clock to the baud rate generator may be either an internal clock or TIN1 and may be as fast as EXTAL However the output of the baud rate generator must provide a CLKO TCLK1 a CLKO RCLK1 ratio greater than or equal to 3 1 In asynchronous mode UART the bit rate is 1 16 of the TCLK1 RCLK1 clock rate 3 Schmitt triggers used on input buffers 4 Where P 1 CLKO Thus for a 16 67 MHz CLKO rate P 60 ns 6 36 MC68LC302 REFERENCE MANUAL Also applies to CD hold time when CD is used as an external sync in BISYNC or totally transparent mode MOTOROLA Electrical Characteristics 02 MOTOROLA TCLK1 25 oS a3 n5 ta 22 Om Og 2 2 gt Figure 6 23 NMSI Timing Diagram MC68LC302 REFERENCE MANUAL Electrical Characteristics 6 38 MC68LC302 REFERENCE MANUAL MOTOROLA SECTION 7 MECHANICAL DATA AND ORDERING INFORMATION 7 1 PIN ASSIGNMENTS 7 1 1 Pin Grid
72. 22 Internal Registers Map 2 23 Interrupt Acknowledge 2 4 Control Pins 5 11 Controller 3 14 IPR 3 15 ISR 3 16 Interrupt Control Pins 5 11 Interrupt Controller 3 14 IOMCR 2 7 2 14 2 16 IPL 5 11 IPLO 5 11 IPL1 5 11 IPL2 5 11 IPL2 IPLO 5 11 IPLCR 2 7 2 10 IPR 3 15 IPWRD 2 15 IRQ1 5 12 ISDN 5 14 ISR 3 16 IWUCR 2 17 L Loopback Control 4 3 Loopback Mode Internal Loopback 4 3 Loopback Control 4 3 Loopback mode 4 5 Low Power 2 13 68000 bus 2 13 Low Power Drive Control Register 2 13 Low Power Drive Control Register LPDCR INDEX 3 Index 2 15 Low Power Modes IMP 2 13 Low Power Support 2 15 FAST WAKE UP 2 18 STOP DOZE STAND BY Mode 2 16 Wake Up from Low Power STOP Modes 2 17 Low Power Clock Divider 2 9 LPDCR 2 15 1 0 2 15 MC68000 MC68008 Modes 2 1 MC68LC302 System Clock Generation IOMCR 2 6 IPLCR 2 6 IWUCR 2 6 MODCLK 2 7 PITR 2 6 VCCSYN 2 7 MF 11 0 2 11 MODCLK 2 12 MODCLK PA12 5 5 MODCLK1 0 2 7 Multiplication Factor 2 11 N NMSI 4 2 5 14 CD1 5 16 CTS1 5 17 NMSI1 5 15 NMSI2 5 17 NMSI3 5 18 RTS1 5 17 SIMODE 4 2 NMSI1 or ISDN Interface Pins 5 14 NMSI2 Port or Port a Pins 5 17 Normal Operation 4 5 OE R W 5 9 3 26 Oscillator 2 8 INDEX 4 MC68LC302 REFERENCE MANUAL 3 19 PADDR 3 19 PAIO SCP Pins 5 18 Parallel 5 20 Parallel 1 Pins with Interrupt Capability 5 20 Parallel I O Port PB11 3 18 PB8 3 18 3 29 Po
73. 27094 972 3 753 8222 39 2 82201 81 241 272231 81 0462 23 0761 1 0485 26 2600 1 092 771 4212 1 0292 26 2340 81 052 232 1621 81 06 305 1801 81 22 268 4333 81 0425 23 6700 81 03 3440 3311 81 045 472 2751 82 51 4635 035 82 2 554 5188 MASSACHUSETTS Wao MASSACHUSETTS Woburn MICHIGAN Pr MINNESOTA Minnetonka MISSOURI St Louis NEW JERSEY Fairfield NEW YORK Fairport NEW YORK Haup ppaug NEW YORK Pou keepsie Fishkil NORTH CAROLINA Raleigh OHIO Cleveland OHIO Columbus Worthington OHIO payon OKLAHOMA Tulsa OREGON Portland PENNSYLVANIA Colmar Philadelphia Horsham SSEE Knoxville TEXAS Austin TEXAS Houston TEXAS Plano VIRGINIA Richmond WAS INGTON Bellevue Seattle Acc WISCONSIN Milwaukee Brookfield MALAYSIA Penang MEXICO Mexico City MEXICO Guadalajara Marketing Customer Service NETHERLANDS Best PUERTO RICO San Juan SINGAPORE SPAIN Madrid SWEDEN Solna SWITZERLAND Geneva SWITZERLAND Zurich TAIWAN Taipei THAILAND Bangkok UNITED KINGDOM Aylesbury 481 8100 932 9700 lt C20 C0 CO OxcO ANANO wo 2 a e e 622 9960 414 792 0122 60 4 374514 52 5 282 2864 52 36 21 8977 52 36 21 9023 52 36 669 9160 31 49988 612 11 809 793 2170 65 2945438 34 1 457 8204 4 1 457 8254 46 8 734 8800 41 22 7991111 41 1 730 4074 886 2 717 7089 66 2 254 4910 44 296 395 252 FULL LINE REPRESENTATIVES C
74. 538 M 302PU 20fE f AA MOTOROLA Microprocessors and Memory Technologies Group MC68L C302 Low Power Integrated Multiprotocol Processor Reference Manual Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs
75. 64 LICLK SCITMode 192 192 192 SDS1 SDS2 Active Delay from L1CLK Rising Edge 290 Gee Note 3 y 9 999 10 90 10 75 7 60 ns SDS1 SDS2 Active Delay from L1SY1 Rising Edge 291 ee Note 3 y 95008 10 90 10 75 7 60 ns 292 2051 SDS2 Inactive Delay from L1CLK Falling 10 90 10 75 7 60 293 GCIDCL Data Clock Active Delay 0 50 0 42 0 34 ns NOTES 1 The ratio CLKO L1CLK must be greater than 2 5 1 2 Condition 150 pF L1TD becomes valid after the L1CLK rising edge or L1SY1 whichever is later 3 SDS1 SDS2 become valid after the L1CLK rising edge L1SY1 whichever is later 4 Schmitt trigger used on input buffer 5 Where P 1 CLKO Thus for a 16 67 MHz CLKO rate P 60 ns 6 32 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 104110 10909 LMd_LNO 2808 1505 114110 HASHT 1 Figure 6 20 Timing Diagram 6 33 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 6 21 AC ELECTRICAL SPECIFICATIONS PCM TIMING There are two sync types 6 34 Short Frame Sync signals are one clock cycle prior to the data Long Frame Sync signals are N bits that envelope the data gt 0 see Figure 6 21 and Figure 6 22 16 67 MHz 20 MHz 25 MHz Num Characteristic Min Max Min
76. 8E Word Rx Temp SCC Base 90 Word Tx Internal State SCC Base 92 Byte Reserved SCC Base 93 TBD Byte Tx Internal Buffer Number SCC Base 94 2 Words Tx Internal Data Pointer SCC Base 98 Word Tx Internal Byte Count SCC Base 9A Word Tx Temp SCC Base 9C First Word of Protocol Specific Area SCC Base BF Last Word of Protocol Specific Area Should be initialized by the user M68000 core Modified by the CP following a CP or system reset 4 3 7 Interrupt Mechanism The interrupt mechanism for each SCC is the same as the MC68302 4 3 8 UART Controller The functionality of the UART controller has not changed The new Autobaud feature is dis cussed in 4 3 9 Autobaud Controller New For any additional information on parameters registers and functionality please refer to the MC68302 Users Manual 4 3 8 1 UART MEMORY MAP When configured to operate in UART mode the IMP over lays the structure see Table 4 2 onto the protocol specific area of that SCC s parameter RAM Refer to System Configuration Registers on page 5 for the placement of the three SCC parameter RAM areas and to Table 4 1 for the other parameter RAM values MOTOROLA MC68LC302 REFERENCE MANUAL 4 7 Communications Processor CP Table 4 2 UART Specific Parameter RAM Address Name i Description SCC Base 9C MAX IDL Maximum IDLE Characters Receive SCC Base 9E IDCC Temporary Receive IDLE Counter SCC Base A0 B
77. 8LC302 REFERENCE MANUAL 2 17 Configuration Clocking Low Power Modes and Internal Memory PB9Ev and are both set to one PB9Ev is cleared by writing a one writing a zero has no effect In modem applications RI should be connected to the PB9 pin PB10Ev PB10 Event This bit will be set to one when there is a high to low transition on the PB10 pin When PB10En is set and PB10Ev is set the IMP will wake up from the selected power down state and the PB10 Interrupt will be generated The IMP cannot enter the power down mode when PB10Ev and PB10En are both set to one PB10Ev is cleared by writing a one writing a zero has no effect In modem applications the DTE TxD line may be connected to the PB10 pin PITEv PIT Event This bit will be set to one when there is a time out on the periodic interrupt timer PIT When PITEn bit is set and a time out occurs PITEv is set the IMP will wake up from the selected power down and a PIT Interrupt will be generated The IMP cannot enter the power down mode if PITEv and PITEn are both set to one PITEv is cleared by writing a one writing a zero has no effect PB9En PB9 Enable This bit when set enables the IMP to wake up from power down mode and generate an interrupt when the PB9 Event bit becomes set PB10En PB10 Enable This bit when set enables the IMP to wake up from power down mode and generate an interrupt when the PB10 Event bit becomes set PITEn
78. 8LC302 REFERENCE MANUAL MOTOROLA Signal Description ji RXD1 LTRXD H TXD1 L1TXD RCLK1 L1CLK Be TCLK1 1590 5051 CD1 L1SY1 aL CTS1 L1GR RTS1 L1RQ GCIDCL Figure 5 9 NMSI1 or ISDN Interface Pins These seven pins can be used either as NMSI1 in nonmultiplexed serial interface NMSI mode or as an ISDN physical layer interface in IDL 1 and PCM highway modes The in put buffers have Schmitt triggers Table 5 8 shows the functionality of each pin in NMSI GCI IDL and PCM highway modes Table 5 8 Mode Pin Functions Signal Name NMSI1 GCI IDL PCM RXD1 L1RXD RXD1 L1RXD L1RXD L1RXD TXD1 L1TXD TXD1 L1TXD L1TXD L1TXD RCLK1 L1CLK RCLK1 L1CLK L1CLK L1CLK TCLK1 L1SYO TCLK1 5051 5051 L1SYO L1SYNC L1SYNC L1GR L1GR RTS1 L1RQ GCIDCL L1RQ NOTES 1 In IDL and GCI mode SDS2 is output on the PA7 pin 2 CD1 may be used as an external sync in NMSI mode 3 RTS is the RTS1 RTS2 or RTS3 pin according to which SCCs are connected to the PCM highway RXD1 L1RXD Receive Data Layer 1 Receive Data This input is used as the NMSI1 receive data NMSI mode and as the receive data input IDL GCI and PCM modes TXD1 L1TXD Transmit Data Layer 1 Transmit Data This output is used as NMSI1 transmit data in NMSI mode and as the transmit data output in IDL GCI and PCM modes TXD1 be configure
79. ANSMIT command is is sued The characters ABCHR1 and ABCHR2 are the autobaud characters that should be searched for by the autobaud controller Typically these are a and A i e 0061 and 0041 if using the Hayes command set These characters must be odd in order for the auto baud controller to correctly determine the length of the START bit Characters are transmit ted and received least significant bit first so the autobaud controller detects the end of the START bit by the least significant bit of the character being a 1 4 12 MC68LC302 REFERENCE MANUAL MOTOROLA Communications Processor CP The RxPTR is a 2 word location that contains a 32 bit pointer to a buffer in external memory used for assembling the received characters and must be initialized before the Enter Baud Hunt command is issued NOTE Since a length for this external buffer is not given the user must provide enough space in memory for characters to be assem bled and written until the autobaud process is to avoid overwrit ing other data in memory This location is not used as the CHARACTER7 value in the control character table until the channel operates in normal UART mode After reception begins in normal UART mode i e the A is found this entry is available again as a control character table entry The TxBD entry is used as the transmit character descriptor for smart echo or software transmit This location is not used as t
80. After system reset this bit defaults to zero ADCE Address Decode Conflict Enable 0 aninternal is not asserted by a conflict in the chip select logic when two or more chip select lines are programmed to overlap the same area 1 an internal BERR is asserted by a conflict in the chip select logic when two or more chip select lines are programmed to overlap the same area BCLM Bus Clear Mask 0 The arbiter does not use the M68000 core internal IPEND signal to assert the in ternal bus clear signals 1 The arbiter uses the M68000 core internal IPEND signal to assert the internal bus clear signals SAM Synchronous Access Mode Valid only in Disable CPU Mode This bit controls how external masters may access the IMP peripheral area This bit is not relevant for applications that do not have external bus masters that access the IMP In ap plications such as disable CPU mode in which the M68000 core is not operating the user should note that SAM may be changed by an external master on the first access of the IMP but that first write access must be asynchronous with three wait states If DTACK is used to terminate bus cycles this change need not influence hardware 0 Asynchronous accesses accesses to the IMP internal RAM and registers in cluding BAR and 5 by an external master are asynchronous 10 the IMP clock Read and write accesses are with three wait states and DTACK is asserted by the IMP ass
81. CLKO XFC MODCLK PA12 VCCSYN GNDSYN Figure 5 2 Clock Pins EXTAL External Clock Crystal Input This input provides two clock generation options crystal and external clock EXTAL may be used with XTAL to connect an external crystal to the on chip oscillator and clock gen erator If an external clock is used the clock source should be connected to EXTAL and XTAL should be left unconnected The oscillator uses an internal frequency equal to the external crystal frequency The frequency of EXTAL may range from 0 MHz to the Maxi mum Operating Frequency 25Mhz at the time this manual was written When an external clock is used it must provide a CMOS level at this input frequency The frequency range of the original MC68LC302 is 0 MHz to the Maximum Operating Fre quency In this manual many references to the frequency 16 67 MHz are made when the maximum operating frequency of the MC68LC302 is discussed When using faster versions of the MC68LC302 such as 20 MHz all references to 16 67 MHz may be re placed with 20 Note however that resulting parameters such as baud rates and timer periods change accordingly XTAL Crystal Output This output connects the on chip oscillator output to an external crystal If an external clock is used XTAL should be left unconnected CLKO Clock Out This output clock signal is derived from the on chip clock oscillator This clock signal is internally connected to the clock input of the M68
82. CM Each SCC has a mode register The functions of bits 5 0 are common to each protocol The function of the specific mode bits varies according to the protocol selected by the MODE1 bits They are described in the relevant sections for each protocol type Each SCM is a 16 bit memory mapped read write register The SCMs are cleared by reset Only the Mode bits have changed functionality For more information on the other bits please refer to the MC68302 Users Manual 15 6 5 4 3 2 1 0 DIAG1 DIAGO Diagnostic Mode 00 Normal operation CTS CD lines under automatic control 01 Loopback mode 10 Automatic echo 11 Software operation ENR Enable Receiver When ENR is set the receiver is enabled When it is cleared the receiver is disabled and any data in the receive FIFO is lost If ENR is cleared during data reception the receiver aborts the current character ENR may be set or cleared regardless of whether serial MOTOROLA MC68LC302 REFERENCE MANUAL 4 5 Communications Processor CP clocks are present To restart reception the ENTER HUNT MODE command should be issued before ENR is set again ENT Enable Transmitter When ENT is set the transmitter is enabled when ENT is cleared the transmitter is dis abled If ENT is cleared the transmitter will abort any data transmission clear the transmit data FIFO and shift register and force the TXD line high idle Data already in the trans mit s
83. D Figure 3 2 Parallel Port Registers 3 7 TIMERS The IMP includes four timer units two identical general purpose timers a software watch dog timer and a periodic interrupt timer PIT Each general purpose timer consists of a timer mode register TMR a timer capture regis ter TCR a timer counter TCN a timer reference register TRR and a timer event register TER The TMR contains the prescaler value programmed by the user The software watch dog timer which has a watchdog reference register WRR and a watchdog counter WCN uses a fixed prescaler value 3 7 1 MC68LC302 General Purpose Timer Difference The only difference between the MC68LC302 and the MC68302 general purpose timers is that Timer 1 output signal is not connected to the externally 3 7 2 General Purpose Timers Programming Mode 3 7 2 1 Timer Mode Register TMR1 TMR2 TMR1 and TMR2 are identical 16 bit registers TMR1 and TMR2 which are memory mapped read write registers to the user are cleared by reset 15 8 7 6 5 4 3 2 1 0 PRESCALER VALUE PS CE OM FRR RST RST Reset Timer 0 Reset timer software reset includes clearing the TMR TRR and TCN 1 Enable timer 3 20 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB ICLK Input Clock Source for the Timer 00 Stop count 01 Master clock Master clock divided by 16 Corresponding TIN pi
84. ERVED SOURCE ADDRESS PONTER The SAPR is a 32 bit register Note that A23 A20 must be initialized by the user They are driven internally by the IDMA and can be used by the chip selects for address comparison 3 4 2 3 Destination Address Pointer Register DAPR The DAPR is a 32 bit register 31 24 2 0 RESERVED DESTINATION ADDRESS POINTER Note that A23 A20 must be initialized by the user They are driven internally by the IDMA and can be used by the chip selects for address comparison 3 4 2 4 Function Code Register FCR The FCR is an 8 bit register 7 6 4 3 2 0 1 DFC 1 SFC The function codes must e initialized by the user The function code value programmed into the FCR is driven on the internal FC2 0 signals during a bus cycle to further qualify the ad dress bus value These values may be used by the chip selects for address matching NOTE This register is undefined following power on reset The user should always initialize it and should not use the function code value 111 in this register 3 4 2 5 Byte Count Register BCR This 16 bit register specifies the amount of data to be transferred by the IDMA up to 64K bytes BCR 0 is permitted 3 4 2 6 Channel Status Register CSR The CSR is an 8 bit register used to report events recognized by the IDMA controller On recognition of an event the IDMA sets its corresponding bit in the CSR regardless of the INTE and INTN b
85. G PER ANSI 25 TIPS A 0 20 0 008 11 N 2 CONTROLLING DIMENSION MILLIMETER 3 DATUM H IS LOCATED AT BOTTOM OF LEAD 100 76 AND IS COINCIDENT WITH THE LEAD WHERE THE PARRA AAA GAAS 11111111 LEAD EXITS THE PLASTIC BODY THE BOTTOM OF THE PARTING LINE 4 DATUMS L M AND N TO BE DETERMINED 1 75 AT DATUM H 221 5 DIMENSIONS S AND V TO BE DETERMINED SEATING PLANE T E 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD zz PROTRUSION ALLOWABLE PROTRUSION IS 0 250 0 100 PER SIDE DIMENSIONS AND B DO INCLUDE MOLD MISMATCH AND ARE L ZM DETERMINED AT DATUM 1 ZES 7 DIMENSION D DOES NOT INCLUDE DAMBAR 1 PROTRUSION DAMBAR PROTRUSION SHALL 7 NOT CAUSE THE LEAD WIDTH TO 0 350 eS B v SEX X A 0 014 MINIMUM SPACE BETWEEN PROTRUSION o E AND ADJACENT LEAD OR PROTRUSION 0 070 0 003 E Ex 3X VIEW Y B1 V1 MILLIMETERS INCHES DIM MIN MAX MIN MAX rr A 14 00 BSC 0 551 BSC i 1 7 00 BSC 0 276 BSC 5 51 B 14 008 0 551 BSC B1 7 00 BSC 0 276 BSC c 0 ows 2 4 2 50 0 05 015 0 002 0 006 xa ZN c2 135 145 0 053 0 057 A1 gt D 017 027 0 007 0011 E 045 075 0018 0 030 m S1 F 017 023 0 007 0 009 0 50 BSC 0 20 BSC J 009 020 0 004 0 008 5 gt K 0 50 REF 0 020 REF
86. Hz clock rate TIN1 and a maximum baud rate of 115 2K but this can change depending on the maximum baud rate and the EXTAL frequency 5 Write DSR of the SCC with the value 7FFF in order to detect the START bit 6 The host initiates the autobaud search process by issuing the Enter Baud Hunt com mand 7 Write the SCM of the SCC with 1133 to configure it for BISYNC mode with the REVD MOTOROLA MC68LC302 REFERENCE MANUAL 4 13 Communications Processor CP and RBCS bits set software operation mode and the transmitter disabled After a few characters have been received the transmitter can be enabled and the software echo function may be performed after issuing the RESTART TRANSMIT command In general the autobaud controller uses the same data structure as that of the UART con troller The first character if matched is stored in the receiver control character register and the external data buffer and the status of that character is reported in the autobaud com mand descriptor After the first character each incoming character is then stored in the buffer pointed to by RxPTR and the status is updated in the autobaud command autobaud descriptor The Tx internal data pointer at offset SCC Base 94 is updated to point to the last character stored in the external data buffer 4 3 9 4 2 Enter Baud Hunt Command This command instructs the autobaud controller to begin searching for the baud rate of a user predefined charac
87. IRQ7 Edge Level Triggered 0 Level triggered An interrupt is made pending when IRQ7 is low NOTE The M68000 always treats level 7 as an edge sensitive interrupt 1 Edge triggered An interrupt is made pending when IRQ7 changes from one to zero falling edge ET6 IRQ6 Edge Level Triggered 0 Level triggered An interrupt is made pending when IRQ6 is low 1 Edge triggered An interrupt is made pending when IRQ6 changes from one to zero falling edge ET1 IRQ1 Edge Level Triggered 0 Level triggered An interrupt is made pending when IRQ1 is low 1 Edge triggered An interrupt is made pending when IRQ1 changes from one to zero falling edge V7 V5 Interrupt Vector Bits 7 5 These three bits are concatenated with five bits provided by the interrupt controller which indicate the specific interrupt source to form an 8 bit interrupt vector number If these bits are not written the vector is provided NOTE These three bits should be greater than or equal to 010 in order to put the interrupt vector in the area of the exception vector ta ble for user vectors Bits 11 and 4 0 Reserved for future use 3 5 2 2 Interrupt Pending Register IPR Each bit in the 16 bit IPR corresponds to an INRQ interrupt source When an INRQ interrupt is received the interrupt controller sets the corresponding bit in the IPR MOTOROLA MC68LC302 REFERENCE MANUAL 3 15 System Integration Block 518 NOTE The ERR
88. K 57 6K 64K 96K 115 2K and 230K To estimate the performance of the autobaud mode the performance table in Appendix A can be used The maximum full duplex rate for a BISYNC channel is one tenth of the system clock rate So a 25 MHz IMP can support 230K autobaud rate with another low speed channel 50 kbps and a 20 MHz IMP can support 115 2K autobaud rate with 2 low speed channels The performance can vary depending on system loading configuration and echoing mode It is important that the highest priority SCC be used for the autobaud function since it is run ning at a very high rate Any SCC that is guaranteed to be idle during the search operation of the autobaud process will not impact the performance of autobaud in an application Idle is defined as not having any transmit or receive requests to from the SCC FIFOs 4 3 9 1 AUTOBAUD CHANNEL RECEPTION PROCESS The interface between the auto baud controller and the host processor is implemented with shared data structures in the MOTOROLA MC68LC302 REFERENCE MANUAL 4 9 Communications Processor CP SCC parameter RAM and in external memory and through the use of a special command to the SCC The autobaud controller uses receive buffer descriptor number 7 Rx BD7 for the autobaud command descriptor This Rx BD is initialized by the host to contain a pointer to a lookup table residing in the external RAM contains the maximum and nominal START bit length for each baud rate The hos
89. M68000 Bus Arbitration Logic with Low Interrupt Latency Support for internal DMA Hardware Watchdog for Monitoring Bus Activity DRAM Refresh Controller Programmable Bus Width Boot from SCC 3 1 SYSTEM CONTROL The IMP system functions are configured using the System Control Register SCR The fol lowing systems are configurated System Status and Control Logic MOTOROLA MC68LC302 REFERENCE MANUAL 3 1 System Integration Block 518 AS Control During Read Modify Write Cycles Disable CPU M68000 Logic Bus Arbitration Logic with Low Interrupt Latency Support Disable CPU only Hardware Watchdog Low Power Standby Modes Freeze Control Only supported in the PGA package 3 1 1 System Control Register SCR The SCR is a 32 bit register that consists of system status control bits a bus arbiter control bit and hardware watchdog control bits Refer to Figure 3 1 and to the following paragraphs for a description of each bit in this register The SCR is a memory mapped read write regis ter The address of this register is fixed at 0F4 in supervisor data space FC 5 4 31 30 29 28 27 26 25 24 Res 0 0 0 HWT WPV ADC F5 23 22 21 20 19 18 17 16 RME ERRE VGE WPVE RVCST EMWS ADCE BCLM F6 15 14 13 12 11 10 9 8 FRZ2 HWDEN HWDCN2 HWDCNO Figure 3 1 System Control Register Table 3 1 SCR Register Bits Bit Name
90. MASK 4 2 4 4 SIMODE 4 2 SLOW GO 2 10 2 13 2 14 2 15 SLOW GO Mode 2 14 SMC 2 20 Serial Management Controllers 4 26 SMC Memory Structure 4 26 Software Operation 4 5 Software Watchdog Timer 3 22 STAND BY 2 13 2 16 STAND BY Mode 2 13 STOP 2 13 2 16 STOP Mode 2 13 Supervisor Data Space 2 3 System Control Registers 5 2 4 System Clock IMP 2 12 System Control 3 1 System Control Bits 3 3 System Control Pins 5 5 System Control Register SCR 3 2 System Status Bits 3 3 INDEX 6 MC68LC302 REFERENCE MANUAL T TCLK1 Disabling 4 5 TCLK1 L1SYO SDS1 5 16 TCN1 TCN2 3 21 TCR1 TCR2 3 21 TER1 TER2 3 21 Thermal Characteristics 6 2 Timer PIT 3 22 Timer Pins 5 19 Timers 3 20 TIN1 TIN2 5 20 WDOG 3 18 3 22 TIN1 TIN2 5 20 TIN1 TIN2 See SCC TMR1 TMR2 3 20 Transparent Controller 4 23 Transparent Event Register 4 25 Transparent Mask Register 4 25 Transparent Mode Register 4 24 Transparent Receive Buffer Descriptor 4 24 Transparent Transmit Buffer Descriptor 4 25 TRR1 TRR2 3 21 TTL Levels 5 2 TXD1 L1TXD 5 15 U UART Controller 4 7 UART Event Register 4 9 UART Mask Register 4 9 UART Memory Map 4 7 UART Mode Register 4 8 UART Receive Buffer Descriptor 4 8 UART Transmit Buffer Descriptor 4 8 V VCCSYN 2 12 5 5 VCO 2 10 2 11 Vector Generation Enable 3 5 W Wake Up Clock cycles IMP 2 13 MOTOROLA Index Wake up PB10 2 18 PIT 2 18 PIT Event 2 18 Watchdog WDOG 3 18 5 20 Hardware 3 5 Timer 3 22 W
91. MC68LC302 REFERENCE MANUAL 4 25 Communications Processor CP 4 4 2 SCP Transmit Receive Buffer Descriptor The transmit receive BD contains the data to be transmitted written by the M68000 core and the received data written by the SCP The done D bit indicates that the received data is valid and is cleared by the SCP 15 14 8 7 0 D RESERVED DATA 4 5 SERIAL MANAGEMENT CONTROLLERS SMCS The functionality of the SMCs has not changed For any additional information on parame ters registers and functionality please refer to the MC68302 Users Manual 4 5 1 SMC Programming Model The operating mode of both SMC ports is defined by SMC mode which consists of the lower eight bits of SPMODE As previously mentioned the upper eight bits program the SCP 7 6 5 4 3 2 1 0 SMD8 SMD2 SMD1 SMDO LOOP 2 4 5 2 SMC Memory Structure and Buffers Descriptors The CP uses several memory structures and memory mapped registers to communicate with the M68000 core All the structures detailed in the following paragraphs reside in the dual port RAM of the IMP The SMC buffer descriptors allow the user to define one data byte at a time for each transmit channel and receive one data byte at a time for each receive channel 4 5 2 1 SMC1 RECEIVE BUFFER DESCRIPTOR The CP reports information about the received byte using this BD 15 14 13 12 11 10 9 8 7 0 L MS AB EB
92. MC68LC302 REFERENCE MANUAL MOTOROLA Communications Processor CP rupt in order to determine parity and character length this information may be overwritten when the next character interrupt is presented to the host The host uses the two received characters to determine 1 whether a properly formed at or AT was received and 2 the proper character format character length parity Once this is decided three possible actions can result First the host may decide that the data received was not a proper at or AT and issue the Enter Baud Hunt command to cause the autobaud controller to resume the search process Second the host may decide the at or is proper and simply continue to receive characters in BISYNC mode Third the M68000 core may decide that the at or AT is proper but a change in character length or parity is required 4 3 9 2 AUTOBAUD CHANNEL TRANSMIT PROCESS The autobaud microcode pack age supports two methods for transmission The first method is automatic echo which is sup ported directly in the SCC hardware and the second method is a smart echo or software transmit which is supported with an additional clock and software Automatic echo is enabled by setting the DIAG bits in the SCC mode register SCM to 10 and asserting the CD pin externally on SCC1 and on SCC2 and SCC3 either externally by leaving the pin as a general purpose input The ENT bit of the SCC should remain cleared
93. MC68LC302 UART must be sent 576 bytes of data from the external UART since the LC302 will not leave the boot mode until 576 bytes are received If the boot program is less than 576 bytes the user is suggested to write 00 into the remaining locations After 576 bytes are received the RISC programs the SCM register to 0 which clears the ENR and ENT bits to disable the UART returns to its reset value The RISC processor next negates the HALT signal to the core internally The 68000 then reads the reset vector from the first location of the dual port RAM In most cases the code that is downloaded will enable the chip selects of the MC68L C302 initialize MC68L C302 receive buffer descriptors of SCC1 to continue receiving additional boot code into external system RAM and re initialize the UART receiver NOTE The first 576 bytes also overlays the exception vector table meaning that exception vectors will not work unless the user carefully maps the code around certain desired vectors and points those vectors into the 576 byte code space In addition MOTOROLA MC68LC302 REFERENCE MANUAL 3 9 System Integration Block 518 the stack pointer must point into the 576 bytes if any exceptions are to be taken within the boot code All 68000 accesses to the dual port RAM are visible externally on the address and data pins so program execution in the 576 byte code space can be monitored After the boot process is completed by the user i
94. Nominal input frequency on EXTAL is 4 192 Mhz 1 Nominal input frequency on EXTAL is 32 768 Khz To enable the boot function the PA7 pin must be pulled low during system reset System reset is defined by the RESET and HALT pins being asserted The PA7 pin must be pulled high during system reset if boot mode is not to be enabled Once the MC68LC302 detects that the PA7 pin is asserted it internally keeps the HALT signal to the 68K core asserted after system reset is complete This action prevents the 68000 from fetching the reset vec tor NOTE PA7 needs to be either pulled UP or pulled DOWN Do not leave this pin floating during reset Once system reset is complete the RISC processor programs the BAR register to 0000 to place the dual port RAM at the low end of system memory It then samples the PA5 pin to determine the clock source for the UART NOTE 5 is expected to be valid for 100 clocks after the negation of RESET If PA5 is pulled high SCC1 is programmed for external clocks In this mode the user has to connect an external clock 16 the bit rate to TCLK1 and RCLK1 If PA5 is pulled low the SCC is programmed for internal clocks and the TCLK1 and RCLK1 pins are programmed to three state to avoid contention with user clocks The RISC proces sor then programs the SCON register of the SCC based on PA12 The PA12 value sampled during reset MODCLKO is decoded in order to provide 9600 bps with two input frequen c
95. OLORADO Grand Junction Cheryl Lee Whltely KANSAS Wichita Melinda Shores Kelly Greiving NEVADA Reno Galena Technology Group NEW MEXICO Albuquerque S amp S Technologies Inc UTAH Salt Lake City Utah Component Sales Inc WASHINGTON Spokane Doug Kenley ARGENTINA Buenos Aires Argonics S A 303 243 9658 316 838 0190 702 746 0642 505 298 7177 801 561 5099 509 924 2322 541 343 1787 HYBRID COMPONENTS RESELLERS Elmo Semiconductor Minco Technology Labs Inc Semi Dice Inc MC68LC302 REFERENCE MANUAL 818 768 7400 512 834 2022 810 594 4631 TABLE CONTENTS Paragraph Title Page Number Number Section 1 Introduction 1 1 9 a a a a a a aa aaa 1 1 1 2 aA e 1 2 1 3 LCZOZ Applications Cota dud 1 3 1 4 7302 E cel 1 3 Section 2 Configuration Clocking Low Power Modes and Internal Memory Map 2 1 MC68LC302 MC68302 Signal Differences 2 1 2 2 IMP Configuration Control iio eee to 2 2 2 2 1 Base Address Register o 25 2 4 2 3 System Configuration 2 5 2 4 Clock Generation and Low Power 2 5 2 4 1 PLL and Oscillator Changes to
96. OUS INPUTS NOTE 1 NOTES 1 Timing measurements are referenced to and from a low voltage of 0 8 volt and a high voltage of 2 0 volts unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between between 0 8 volt and 2 0 volts 2 Because of loading variations R W may be valid after AS even though both are initiated by the rising edge of S2 specification 420A 3 Each wait state is a full clock cycle inserted between S4 and S5 Figure 6 3 Write Cycle Timing Diagram MOTOROLA MC68LC302 REFERENCE MANUAL 6 11 Electrical Characteristics S0 51152 53 54 55 56 S7 S8 S9 510 611 S12 S13 S14 S15 S16 517 S18 519 CLKO AS NOTE 2 OUTPUT AS NOTE 3 OUTPUT UDS LDS OUTPUT RW OUTPUT DTACK D15 D0 DATA IN INDIVISIBLE CYCLE Figure 6 4 Read Modify Write Cycle Timing Diagram 6 12 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 6 9 AC ELECTRICAL SPECIFICATIONS DMA see Figure 6 5 and Figure 6 6 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol Min Max Min Max Min Unit 83 Clock High to BR Low see Notes and 4 30 25 20 ns Clock High to BR High Impedance see 4 Notes 3 and 4 20 30 25 20 ns BGACK L
97. P SYSTEM CLOCK CLK OUT IMP PLL 0 Max Operating Freq BRG CLOCK VCO OUT DIVIDE BY 2 PIT CLOCK Figure 2 2 MC68LC302 PLL Clock Generation Schematic 2 4 2 1 DEFAULT SYSTEM CLOCK GENERATION During the assertion of hardware reset the value of the MODCLK and VCCSYN input pins determine the initial PLL settings according to Table 2 2 After the deassertion of reset these pins are ignored The MODCLK and VCCSYN pins control the IMP clock selection at hardware reset The IMP PLL can be enabled or disabled at reset only and the multiplication factor preset to support different industry standard crystals After reset the multiplication factor can be changed in the IPLCR register and the IMP PLL divide factor can be set in the IOMCR register NOTE The IMP input frequency ranges are limited to between 25 kHz and the maximum operating frequency and the PLL output fre quency range before the low power divider is limited to between 10 MHz and the maximum system clock frequency 25 MHz Table 2 2 Default System Clock Generation VCCSYN IMP IMP CSelect MODCLK EXTAL Freq IMP PLL MF 1 IMP System Clock 0 0X 25 MHz Disabled x IMP EXTAL 0 10 4 192 MHz Enabled 4 IMP EXTALx4 0 11 32 768 kHz Enabled 401 IMP EXTALx401 Note By loading the IPLCR register the user can change the multiplication factor of the PLL after RESET
98. PB10 pins if these interrupts are en abled 3 A timeout of the periodic interrupt timer if the PIT interrupt is enabled When one of these events occur and the corresponding event bit is set the IMP low power controller will asynchronously restart the IMP clocks Then IMP low power control logic will release the 68000 bus and the IMP will return to normal operation If one of the above wake up events occurs during the execution of the STOP command the low power control logic will abort the power down sequence and return to normal operation NOTE The RI PB9 DTE PB10 and periodic interrupt timer timeout in terrupts conditions will generate level 4 interrupts The user should also set the 68000 interrupt mask in the status register SR to the appropriate level before executing the STOP com mand to ensure that the IMP will wake up to the desired events 2 4 4 2 4 IMP Wake Up Control Register IWUCR The IWUCR contains control for the wake up options This register can be read and written by the 68000 core IWUCR 0F7 7 6 5 4 3 2 1 0 0 PBIOE PBOEV 0 PBI0En PBOEn i 0 0 0 0 0 0 0 Read Write PB9Ev PB9 Event This bit will be set to one when there is a high to low transition on the PB9 pin When PB9En is set and PB9Ev is set the IMP will wake up from the selected power down state and a 9 Interrupt will be generated The IMP cannot enter the power down mode if MOTOROLA MC6
99. S High to R W High DSHRWH 0 0 0 ns 108 DSHigh to Data High Impedance 2 45 40 30 ns 108A DS High to Data Out Hold Time see 0 0 0 ns 109A Data Out Valid to DTACK Low tpovpkL 15 15 10 5 NOTE If AS is negated before DS the data bus could be three stated spec 126 before DS is negated 6 16 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics IAC OUTPUT DTACK CLKO RW INPUT 015 00 OUTPUT OUTPUT OUTPUT Figure 6 7 External Master Internal Asynchronous Read Cycle Timing Diagram MOTOROLA MC68LC302 REFERENCE MANUAL 6 17 Electrical Characteristics S7 S6 55 54 42 42 wn 42 42 wn 02 N 02 e 2 oc EE oc om E x6 lt x5 885 os oF gE 5 wc E 22 lt 5 a5 Figure 6 8 External Master Internal Asynchronous Write Cycle Timing Diagram 6 18 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 6 11 AC ELECTRICAL SPECIFICATIONS EXTERNAL MASTER INTERNAL SYNCHRONOUS READ WRITE CYCLES see Figure 6 9 Figure 6 10 and Figure 6 11
100. SIZE SWITCH The following procedure allows 68LC302 to be booted in an 8 or 16 bit bus width and then switched to 16 or 8 bit bus width for future accesses It does not implement true dynamic bus sizing but allows a software reconfiguration of the BUSW pin 3 2 1 Bus Switch Register BSR BSR Base 82 7 6 5 4 3 0 BSW BSWEN 0 0 0 0 0 0 BWSEN Bus Width Switch Enable When this bit is toggled from a zero to a one the bus width switch mechanism is enabled From the point this bit is toggled the bus width is determined by the BSW bit of this reg ister If another bus width switch is necessary this bit must be toggled back to zero and then one again Setting this bit implements a hardware state machine that arbitrates the internal bus away from the 302 core changes the BUSW pin internally and then gives the bus back to the 302 core BUSW Bus Width This bit determines the bus width after the bus width switch is performed 0 Data bus width is 8 bits 1 Data bus width is 16 bits 3 2 2 Basic Procedure The MC68LC302 is booted in its 8 bit mode by externally connecting the BUSW pin to GND It is expected that the MC68LC302 will be executing out of EPROM or flash at this time and that no external data memory is available in 8 bit mode The MC68LC302 initializes the BAR register to place the 4K block of dual port RAM and peripherals in an area that does not overlap the EPROM region Note that this is pa
101. T 4 HIGH ORDER DATA BUFFER POINTER only lower 8 bits use upper 8 bits must 0 OFFSET 6 LOW ORDER DATA BUFFER POINTER Figure 4 1 SCC Buffer Descriptor Format NOTE Even though the address bus is only 20 bits the full 32 bit point er must be Bits 24 32 must be zero and bits 20 23 are used in 4 6 MC68LC302 REFERENCE MANUAL MOTOROLA Communications Processor CP the Chip Select address comparison so they should be pro grammed to a value which will assert the desired chip select 4 3 6 SCC Parameter RAM Memory Map Each SCC maintains a section in the dual port RAM called the parameter RAM Each SCC parameter RAM area begins at an offset 80 from each SCC base area 400 or 500 and continues through offset BF Part of each SCC parameter RAM offset 80 9A which is identical for each protocol chosen is shown in Table 4 1 Offsets 9C BF comprise the protocol specific portion of the SCC parameter RAM The SCC parameters have not changed functionality from the MC68302 Table 4 1 SCC Parameter RAM Memory Map Address Name Width Description SCC Base 80 RFCR Byte Rx Function Code SCC Base 81 TFCR Byte Tx Function Code SCC Base 82 MRBLR ord Maximum Rx Buffer Length SCC Base 84 Word Rx Internal State SCC Base 86 Byte Reserved SCC Base 87 RBD Byte Rx Internal Buffer Number SCC Base 88 2 Words Rx Internal Data Pointer SCC Base 8C Word Rx Internal Byte Count SCC Base
102. addition to the internal dual port RAM a number of internal registers support the functions of the various M68000 core peripherals The internal registers see Table 2 6 are memory mapped registers offset from the BAR pointer and are located on the internal M68000 bus NOTE All undefined and reserved bits within registers and parameter RAM values written by the user in a given application should be written with zero to allow for future enhancements to the device 2 22 MC68LC302 REFERENCE MANUAL MOTOROLA Configuration Clocking Low Power Modes and Internal Memory 2 6 INTERNAL REGISTERS MAP Table 2 6 Internal Registers Map Address Name Width Block Description Reset Value Reserved Channel Mode Register Source Address Pointer Destination Address Pointer Byte Count Register Channel Status Register Reserved Function Code Register Reserved GIMR Int Cont Global Interrupt Mode Register IPR Int Cont Interrupt Pending Register IMR Int Cont Interrupt Mask Register ISR Int Cont In Service Register RINGOCR Int Cont Ring Oscillator Control Register RINGOEVR Int Cont Ring Oscillator Event Register RES Int Cont Reserved PACNT PIO Port A Control Register PADDR PIO Port A Data Direction Register PADAT PIO Port A Data Register PBCNT PIO Port B Control Register Port B Data Direction Register Port B Data Register Low Power Drive Control Register Bus Switch register Reserved Base Register 0 Option Register 0 Base Register
103. amage due to high static voltages or elec tric fields however it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated volt ages to his high impedance circuit Reliability of operation is hanced if unused inputs are tied to an appropriate logic voltage level e g either GND or Vpp MOTOROLA Electrical Characteristics 6 3 POWER CONSIDERATIONS The average chip junction temperature Ty in can be obtained from Pp 1 where Ambient Temperature Package Thermal Resistance Junction to Ambient C W Pint PINT X Watts Chip Internal Power Pio Power Dissipation on Input and Output Pins User Determined For most applications lt 0 3 Pint and can be neglected If Pyo is neglected an approximate relationship between Pp and Ty is Pp Tj 273 C 2 Solving equations 1 and 2 for K gives Ppe Ta 273 C Pp 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring Pp at equilibrium for a known Using this value of K the values of Pp and Ty can be obtained by solving equations 1 and 2 iteratively for any value of Ta MOTOROLA MC68LC302 REFERENCE MANUAL 6 3 Electrical Characteristics 6 4 POWER DISSIPATION 6 4 Note These values are pr
104. as an output enable OE signal instead of R W The OE signal indicates that the MC68LC302 expects an external device to drive data onto the data bus When the core is disabled OE becomes the R W signal The MC68LC302 in CPU enable mode does not have BR BG and BGACK pins Instead the HALT pin is used to force the MC68L C302 off of the bus see the HALT signal descrip tion in 5 4 System Control Pins While the MC68L C302 is halted the chip selects are still functional The external master will not be able to access the internal registers and dual port RAM When the core is disabled the IPLO IPL1 and IPL2 lines become the BR BG and BGACK signals The only external interrupts handled are PB8 PB9 PB10 and PB1 1 Two M6800 signals are omitted from the 68LC302 valid memory address VMA and enable E The valid peripheral address VPA signal which was used on the MC68302 as AVEC has been removed from the MC68LC302 The signals for the serial communications port SCP have been multiplexed with the PA8 PAS and PA10 pins and the signals for SCC3 have been removed The FC2 0 pins have been removed from the MC68LC302 These signals are still driven internally by the core depending on the type of bus cycle i e supervisor program space supervisor data space etc and the internal peripherals They can still be used for address comparison in the chip select registers In disable CPU mode and when HALT is asserted for external masters
105. atchdog WDOG See Signals Watchdog WDOG See Timers WCN 3 22 UDS A0 5 9 WEL LDS DS 5 10 Write Protect Violation 3 3 WRR 3 22 X XFC 2 12 5 5 XTAL 5 4 MOTOROLA MC68LC302 REFERENCE MANUAL INDEX 7 Index INDEX 8 MC68LC302 REFERENCE MANUAL MOTOROLA Copyright Each Manufacturing Company Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 10096 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
106. ation The External Bus Exceptions BERR and Retry have been removed Only HALT or an in ternal BERR generated by the Hardware Watchdog Timer is supported 3 10 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB The rest of the functionality remains the same as for the MC68302 For details on the bus operation please refer to the MC68302 User s Manual 3 4 2 IDMA Registers Independent DMA Controller The IDMA has six registers that define its specific operation These registers include a 32 bit source address pointer register SAPR a 32 bit destination address pointer register DAPR an 8 bit function code register FCR a 16 bit byte count register BCR a 16 bit channel mode register CMR and an 8 bit channel status register CSR 3 4 2 1 Channel Mode Register CMR The CMR a 16 bit register is reset to 0000 ECO NIN INTE REQG SAPI DAPI SSIZE DSIZE BT RST STR Bit 15 Reserved for future use ECO External Control Option NOT USED 0 If the request generation is programmed to be external in the REQG bits the con trol signals DACK and DONE are used in the source read portion of the transfer since the peripheral is the source 1 If the request generation is programmed to be external in the REQG bits the con trol signals and DONE are used in the destination write portion of the transfer since the peripheral is the destination INTN Interrup
107. ay be implemented by the parallel I O pins gt 15 69 SPCLK OUTPUT SA 65 lt SPRXD INPUT Figure 6 18 Serial Communication Port Timing Diagram MOTOROLA MC68LC302 REFERENCE MANUAL 6 29 Electrical Characteristics 6 19 AC ELECTRICAL SPECIFICATIONS IDL TIMING timing measurements unless otherwise specified are referenced to the L1CLK at 50 point of Vp see Figure 6 1 9 6 30 16 67 MHz 20 MHz 25 MHz Num Characteristic Min Min Unit 260 L1CLK IDL Clock Frequency see Note 1 6 66 8 10 MHz 261 L1CLK Width Low 55 45 37 ns 262 L1CLK Width High see Note 3 P410 P 10 10 ns 263 MTD L1RQ SDS1 SDS2 Rising Falling __ 20 17 14 T 264 sync Setup Time to L1CLK Falling 30 25 20 T L1SY1 sync Hold Time from L1CLK Fall 265 ing doo 50 40 34 266 L1SY1 sync Inactive Before 4th L1 CLK 0 0 0 ns 267 Edge Active Delay from L1CLK Rising 0 75 0 65 0 50 ns L1TxD to High Impedance from L1CLK Ris 268 ing Edge see Note 2 0 50 0 42 0 34 ns 269 L1RxD Setup Time to L1CLK Falling Edge 50 42 34 ns L1RxD Hold Time from L1CLK Fallin 270 Euge 9 50 42 34 271 Time Between Successive IDL syncs 20 20
108. be disabled by asserting the DISCPU pin high during a total system reset RESET and HALT asserted DISCPU may only be changed upon a total system reset The DISCPU pin for instance allows use of several LC302s to provide more than two SCC channels without the need for bus isolation techniques An external processor ser vices the other LC302s as peripherals with their respective cores disabled FRZ The FRZ pin is used to freeze the activity of selected peripherals This is useful for system debugging purposes Refer to 3 1 4 Freeze Control for more details FRZ should be con tinuously negated during total system reset 5 5 ADDRESS BUS PINS 19 1 The address bus pins are shown in Figure 5 4 A19 A1 Figure 5 4 Address Bus Pins MOTOROLA MC68LC302 REFERENCE MANUAL 5 7 Signal Description 19 1 form a 20 bit address bus when combined with WEH UDS The address bus is a bidirectional three state bus capable of addressing 1M bytes of data including the LC302 internal address space It provides the address for bus operation during all cycles except CPU space cycles In CPU space cycles the CPU reads a peripheral device vector number These lines are outputs when the LC302 M68000 core SDMA or IDMA is the bus master and are inputs otherwise in DISCPU only NOTE Since internally the CS logic compares also A23 A20 the effec tive address space for internal masters is 4 M bytes 5 6 DATA BUS PINS 015 0
109. bit parity 0 Even parity ITO Parity is indicated by which charac 1 8 bit Odd parity ters aFE interrupt Parity 0 5 8 bit Parity 1 Not Supported Case 1 This case cannot be supported because the autobaud can not separate the first character from the second character MOTOROLA MC68LC302 REFERENCE MANUAL 4 17 Communications Processor CP Case 2 As each character is assembled it is stored into a complete byte Assuming that the characters are ASCII characters with 7 bit codes the 8th bit of the byte will con tain the parity bit If the parity is either even or odd then after receiving an odd character and an even character the 8th bit should be different for the odd and even characters The parity can be determined by the setting of the parity bit for one of the two charac ters If the 8th bit is always a 1 this is the same as a 7 bit character no parity and at least 2 STOP bits or a 7 bit character with force 1 parity If the 8th bit is always a zero then either the character is a 7 bit character with force O parity or the character is a 8 bit character with no parity Case 3 This case is the same as 7 bit character with force O parity The 8th bit of the byte will always be zero Case 4 This case assumes a 8 bit character with the 8th bit of the character equal to a 0 ASCII character codes define the 8th bit as zero If the parity is either even or odd then after receiving an odd and a
110. bit and the MF11 0 bits of the IMP PLL and Clock Con trol Register IPLCR 0F8 to be appropriately written VCCSYN and MODCLK also deter mines if the oscillator s prescaler is used After RESET is negated the MODCLK pins is ignored and becomes PA12 Table 2 2 shows the combinations of VCCSYN and MODCLK pins with the corresponding default settings 2 12 MC68LC302 REFERENCE MANUAL MOTOROLA Configuration Clocking Low Power Modes and Internal Memory 2 4 4 IMP Power Management The IMP portion of the MC68L C302 has several low power modes from which to choose 2 4 4 1 IMP LOW POWER MODES The MC68LC302 provides a number of low power modes for the IMP section Each of the operation modes has different current consumption wake up time and functionality characteristics The state of the IMP s 68000 data and address bus lines can be either driven high low or high impedance during low power stop mode by programming the low power drive control register NOTE For lowest current consumption the SCCs and BRGs should be disabled before entering the low power modes Current con sumption for all operating modes is specified in Section 6 Elec trical Characteristics Table 2 3 IMP Low Power Modes IMP PLL Enabled Wake Up Current Mie Oscillator PLL IMP Clock Osc Clock Consumption Entry Approximate STOP Not Active Not active Not active lt 0 1
111. bit is set if the user drives the IPL2 IPLO lines to inter rupt level 4 and no INRQ interrupt is pending 15 14 13 12 11 10 9 8 amp c m 7 6 5 4 3 2 1 0 TMERE ma ER 3 5 2 3 Interrupt Mask Register IMR Each bit in the 16 bit IMR corresponds to an INRQ interrupt source The user masks an in terrupt source by clearing the corresponding bit in the IMR 15 14 13 12 11 10 9 8 11 10 260 SDMA IDMA 5002 TIMER1 7 6 5 4 3 2 1 0 TIMER2 SCP TIMERS SMC1 SMC2 m 3 5 2 4 Interrupt In Service Register ISR Each bit in the 16 bit ISR corresponds to an INRQ interrupt source In a vectored interrupt environment the interrupt controller sets the ISR bit when the vector number corresponding to the INRQ interrupt source is passed to the core during an interrupt acknowledge cycle The user s interrupt service routine should clear this bit during the servicing of the interrupt 3 16 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB 15 14 13 12 11 10 9 8 10 5001 SDMA IDMA 5002 1 7 6 5 4 3 2 1 0 PB9 TIMER2 SCP TIMERS SMC1 SMC2 PB8 0 3 6 PARALLEL I O PORTS The IMP supports three general purpose ports port port B and port whose pins can be general purpose l O pins or dedicated peripheral interface pins Some port B pins are always maintaine
112. c PLL Disabled Figure 2 2 shows the IMP system clocks schematic with the IMP PLL enabled Figure 2 3 shows the IMP system clocks schematic with the IMP PLL disabled The clock generation features of the IMP are discussed in the following paragraphs 2 4 3 2 ON CHIP OSCILLATOR A 32 768 kHz watch crystal provides an inexpensive ref erence but the EXTAL reference crystal frequency can be any frequency from 25 kHz to 6 0 2 8 MC68LC302 REFERENCE MANUAL MOTOROLA Configuration Clocking Low Power Modes and Internal Memory MHz Additionally the system clock frequency can be driven directly onto the EXTAL pin In this case the EXTAL frequency should be the exact system frequency desired 0 to Maxi mum Operating Frequency and the XTAL pin should be left floating Figure 2 4 shows all the external connections required for the on chip oscillator as well as the PLL VCC and GND connection VCC 390pf x MF 0 1uF CRYSTAL 20pf 822 20 0 01 20 EXTAL XTAL VCCSYN GNDSYN CRYSTAL OSCILLATOR VCC ICLVCC CLOCK GENERATION ICLGND 7 16 alls CLKO Figure 2 4 External Components 2 4 3 3 PHASE LOCKED LOOP PLL The IMP PLL s main function is frequency multipli cation The phase locked loop takes the CLKIN frequency and outputs a high frequency source used to
113. cations Processor CP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0 R X Ww L TB B BR TD TR UN CT OFFSET 2 DATA LENGTH OFFSET 4 TX BUFFER POINTER 24 bits used upper 8 bits must be 0 OFFSET 6 Figure 4 7 BISYNC Transmit Buffer Descriptor 4 3 11 5 BISYNC EVENT REGISTER The SCC event register SCCE is referred to as the BISYNC event register when the SCC is programmed as a BISYNC controller It is an 8 bit register used to report events recognized by the BISYNC channel and to generate inter rupts On recognition of an event the BISYNC controller sets the corresponding bit in the BISYNC event register Interrupts generated by this register may be masked in the BISYNC mask register A bit is cleared by writing a one More than one bit may be cleared at a time All unmasked bits must be cleared before the CP will negate the internal interrupt request signal This register is cleared at reset 7 6 5 4 3 2 1 0 5 TXE RCH BSY TX RX 4 3 11 6 BISYNC MASK REGISTER The SCC mask register SCCM is referred to as the BISYNC mask register when the SCC is operating as a BISYNC controller It is an 8 bit read write register that has the same bit format as the BISYNC event register If a bit in the BISYNC mask register is a one the corresponding interrupt in the event register will be enabled If the bit is zero the corresponding interrupt
114. cause a total MC68LC302 sys tem reset This signal is also used to force the LC302 off the bus if another bus master 5 6 MC68LC302 REFERENCE MANUAL MOTOROLA Signal Description requires the bus unless the LC302 core is disabled then the BR BG and BGACK pins should be used After asserting the HALT signal the external bus master must wait until AS is negated plus 2 additional clocks before accessing the bus to allow the L C302 to threestate all of the bus signals BUSW Bus Width Select This input defines the M68000 processor mode MC68000 or MC68008 and the data bus width 16 bits or 8 bits respectively BUSW may only be changed upon a total system reset In 16 bit mode all accesses to internal and external memory by the MC68000 core the IDMA SDMA and external master may be 16 bits according to the assertion of the UDS and LDS pins In 8 bit mode all M68000 core and IDMA accesses to internal and external memory are limited to 8 bits Also in 8 bit mode SDMA accesses to external memory are limited to 8 bits but CP accesses to the CP side of the dual port RAM con tinue to be 16 bits In 8 bit mode external accesses to internal memory are also limited to 8 bits at a time Low 8 bit data bus MC68008 core processor High 16 bit data bus MC68000 core processor DISCPU Disable CPU M68000 core The MC68LC302 can be configured to work solely with an external CPU In this mode the on chip M68000 core CPU should
115. d CONTROL Character3 SCC B6 CHARACTER4 Word CONTROL Character4 SCC 8 CHARACTERS Word CONTROL Character5 SCC Word CONTRChar6 MSW of pointer to external Rx Buffer SCC CHR7RxPTR Word CONTRChar7 LSW of pointer to external Rx Buffer SCC CHR8 TxBD Word CONTROL Character8 Transmit BD These values should be initialized by the user M68000 core Note the new parameters that have been added to the table They are MAX BIT NOM START ABCHR1 ABCHR2 RxPTR 2 words and TxBD These parameters are of special importance to the autobaud controller They must be written prior to issuing the Enter Baud Hunt command When the channel is operating in the autobaud hunt mode the MAX BIT parameter is used to hold the current maximum START bit length The NOM START location contains the cur rent nominal start from the lookup table After the autobaud is successful and the first char acter is matched the user should use the NOM START value from the autobaud specific parameter RAM to determine which baud rate from the lookup table was detected Also the Tx internal data pointer at offset SCC Base 94 will point to the last character received into external data buffer NOTE When the channel is operating in the UART mode the NOM START BRKCR is used as the break count register and must be initialized before a STOP TR
116. d as an open drain output NMSI mode L1TXD in IDL and PCM mode is a three state output In mode it is an open drain output MOTOROLA MC68LC302 REFERENCE MANUAL 5 15 Signal Description RCLK1 L1CLK Receive Clock Layer 1 Clock This pin is used as an bidirectional receive clock in NMSI mode or as an input clock in IDL GCI and PCM modes In NMSI mode this signal is an input when 5 1 is working with an external clock and is an output when SCC1 is working with its baud rate generator TCLK1 L1SYO SDS1 Transmit Clock PCM Sync Serial Data Strobe 1 This pin is used as an NMSI1 bidirectional transmit clock in NMSI mode as a sync signal in PCM mode or as the SDS1 output in IDL GCI modes In NMSI mode this signal is an input when SCC1 is working with an external clock and is an output when SCC1 is working with its baud rate generator NOTE When using SCC1 in the NMSI mode with the internal baud rate generator operating the TCLK1 and pins will always out put the baud rate generator clock unless disabled in the CKCR register Thus if a dynamic selection between an internal and external clock source is required in an application the clock pins should be disabled first in the CKCR register before switching the TCLK1 and RCLK1 lines On SCC2 contention may be avoided by disabling the clock line outputs in the PACNT regis ter In PCM mode L1SY1 L1S YO are encoded signals used to create channels that ca
117. d as four general purpose pins each with interrupt capability 3 6 1 PARALLEL I O PORT DIFFERENCES The following port pins were removed PA11 PA13 PA14 PA15 PBO PB1 PB2 and PB4 If these signals are programmed to be inputs the corresponding values in the data registers will be indeterminate If these pins are programmed to be output then the output value will be read back in the data register The SCP pins are now multiplexed onto PA8 PAY and PA10 The MODCLK pin is multiplexed with the PA12 port pin After reset this pin becomes a gen eral purpose pin An 8 bit port Port N has been added Port N is only available when the MC68LC302 is in 8 bit mode internal BUSW 0 3 6 2 Port A Each of the port A pins are independently configured as a general purpose I O pin if the cor responding port A control register PACNT bit is cleared Port A pins are configured as ded icated on chip peripheral pins if the corresponding PACNT bit is set When acting as a general purpose the signal direction for that pin is determined by the corresponding control bit in the port A data direction register PADDR The port I O pin is configured as an input if the corresponding PADDR bit is cleared it is configured as an output if the corre sponding PADDR bit is set The PADAT register is used to read and write values for the Port A pins All PACNT bits and PADDR bits are cleared on total system reset configuring all port A
118. d by software ona regular basis so that it never reaches its timeout value Upon reaching the timeout value the assumption may be made that a system failure has occurred and steps can be taken to re cover or reset the system No changes have been made to the Software Watchdog Timer Please refer to the MC68302 Users Manual for more information 3 7 3 1 Software Watchdog Reference Register WRR WRR is a 16 bit register containing the reference value for the timeout The EN bit of the register enables the timer WRR appears as a memory mapped read write register to the user 15 1 0 REFERENCE VALUE EN 3 7 3 2 Software Watchdog Counter WCN WON a 16 bit up counter appears as a memory mapped register and may be read at any time Clearing EN in WRR causes the counter to be reset and disables the count operation A read cycle to causes the current value of the timer to be read A write cycle to causes the counter and prescaler to be reset A write cycle should be executed on a regular basis so that the watchdog timer is never allowed to reach the reference value during normal program operation 3 7 4 Periodic Interrupt Timer PIT The MC68LC302 IMP provides a timer to generate periodic interrupts for use with a real time operating system or the application software The periodic interrupt time period can vary from 122 us to 128 s assuming a 32 768 kHz crystal is used to generate the general system clock Th
119. data rate x 2 The ratio CLKO L1CLK must be greater than 2 5 1 see Figure 6 20 16 67 MHz 20 MHz 25 MHz Num Characteristic Min Min Unit Nod Clock Frequency Normal Mode see 512 512 512 kHz 280 L1CLK Clock Period Normal Mode see Note 1 1800 2100 1800 2100 1800 2100 ns 281 L1CLK Width Low High Normal Mode 840 1450 840 1450 840 1450 ns 282 L1CLK Rise Fall Time Normal Mode see Note 4 ns L1CLK GCI Clock Period MUX Mode see Note 1 6 668 6 668 6 668 MHz 280 L1CLK Clock Period MUX Mode see Note 1 150 150 150 ns 281 L1CLK Width Low MUX Mode 55 55 55 ns 281A L1CLK Width High MUX Mode see Note 5 10 P 10 10 ns 282 L1CLK Rise Fall Time MUX Mode see Note 4 ns 283 L1SY1 Sync Setup Time to L1CLK Falling Edge 30 25 20 ns 284 L1SY1 Sync Hold Time from L1CLK Falling Edge 50 42 34 ns 285 NS Delay from L1CLK Rising Edge see 0 100 0 85 0 70 ns 286 Nota 2 e Delay from L1SY1 Rising Edge see 0 100 0 85 0 70 ns 287 L1RxD Setup Time to L1CLK Rising Edge 20 17 14 ns 288 L1RxD Hold Time from L1CLK Rising Edge 50 42 34 ns ogg Time Between Successive L1SY1in Normal 64 64
120. ddress Pointer Register 3 13 3 4 2 4 Function Code Register io eda ret 3 13 3 4 2 5 Byte Count Register esee uis dioses aset 3 13 3 4 2 6 Channel Status Register CSR 3 13 3 5 Interrupt Controller ss Ec 3 14 3 5 1 Interrupt Controller Key 4222 11 3 14 3 5 2 Interrupt Controller Programming 3 14 3 5 2 1 Global Interrupt Mode Register 3 14 3 5 2 2 Interrupt Pending Register 2 0 3 15 3 5 2 3 Interrupt Mask Register 3 16 3 5 2 4 Interrupt In Service Register 5 2 41 0 3 16 vi MC68LC302 REFERENCE MANUAL MOTOROLA Number MOTOROLA Table of Contents Title Page Number Parallel DC POLS corio CORTE o oS 3 17 Parallel o Port DIITereri 6S t 3 17 RN bati at BOR RR LAUR ST RM EN EM ERREUR RU RU Su RE 3 17 EDD Rete era te Seen ete Tron ee oe en eee 3 18 PB7 PBS e 3 18 E EA E EEEE 3 18 AN E E E E 3 19 Port Registers eit ceto a deae ec Ee e
121. designed to drive 50 pF GCI output pins drive 100 pF 5 2 POWER PINS The LC302 TQFP has 17 power supply pins Careful attention has been paid to reducing LC302 noise potential crosstalk and RF radiation from the output drivers Inputs may be 5 V when is 0 V without damaging the device Vpp 6 There are 6 power pins GND 11 There are 11 ground pins 5 2 MC68LC302 REFERENCE MANUAL MOTOROLA 511 ISDN I F RXD1 L1RXD TXD1 L1TXD RCLK1 L1CLK TCLK1 L1SYO SDS1 CDT L1SY1 CTST LTGR RTST L1RQ GCIDCL RXD2 PA0 NMSI2 RCLK2 PA2 TCLK2 PA3 CTS2 PA4 RTS2 PA5 CD2 PA6 BOOT BRG2 SDS2 PA7 SPRXD PA8 SPTXD PA9 PAIO SCP SPCLK PA10 MODCLKPA12 TIN1 PB3 TIMER PBIO TIN2 PB5 TOUT2 PB6 WDOG PB7 gt 9 10 11 FC2 0 4 FRZ lt Signal Description LC302 Signals Pins available in PGA Package XD lt gt D15 D8 PN15 8 Address Bus A1 A19 Chip Select CSO IOUT2 53 51 Data Bus Port 0 D7 Bus Control WEH A0 UDS AO WEL WE LDS DS R W System Control RESET HALT BUSW DISCPU Interrupt Control AVEC Note Pins in parenthesis are available in slave mode only Figure 5 1 LC 302 Functional Signal Groups MOTOROLA MC68LC302 REFERENCE MANUAL 5 3 Signal Description 5 3 CLOCK PINS The clock pins are shown in Figure 5 2 EXTAL XTAL
122. distinguish between close UART rates such as 64K and 57 6K However variations in RS232 driv ers of up to 496 plus nominal clocking rate variations of 396 plus 4 16 MC68LC302 REFERENCE MANUAL MOTOROLA Communications Processor CP the fact that the sampling rate may not perfectly divide into the desired UART rate can make this distinction difficult to achieve in some scenarios 4 3 9 5 LOOKUP TABLE EXAMPLE Table 4 6 is an example autobaud lookup table The maximum start and nominal start val ues are derived assuming a 1 8432 MHz sampling clock on TIN1 or RCLK and a shift factor of 595 Table 4 6 Lookup Table Example Desired Maximum Nominal Baud Rate Start Start 115200 17 8 57600 34 16 38400 50 24 28800 67 32 19200 101 48 14400 134 64 12000 161 77 9600 202 96 7200 269 128 4800 403 192 2400 806 384 1200 1613 768 600 3226 1536 300 6451 3072 110 17594 8378 4 3 9 6 DETERMINING CHARACTER LENGTH AND PARITY Table 4 7 shows the dif ferent possible character lengths and parity that will be discussed The following paragraphs will discuss for each case how to determine the parity Table 4 7 Character Lengths and Parity Cases Character Case Length Parity Notes 1 7 bit No parity 1 STOP bit Not Supported Even parity Odd parity Parity is indicated by the most signif 2 Parity 1 icant bit of the byte Parity 0 3 8 bit No parity Same as 7
123. dth 50 42 34 ns TIN Clock High Pulse Width and Input 202 Capture High Pulse Width 3 TICHT 2 2 2 ek 203 TIN Clock Cycle Time lcyc 3 3 3 clk 204 Clock High to TOUT Valid tcHTov 35 30 24 ns 205 FRZ Setup Time Clock High see 20 xn 20 25 14 2 ns Note 1 206 FRZ Input Hold Time from Clock High 10 10 7 ns NOTES 1 FRZ should be negated during total system reset 2 The TIN specs above do not apply to the use of TIN1 as a baud rate generator input clock In such a case specifications 1 3 may be used TOUT OUTPUT TIN INPUT FRZ INPUT Figure 6 17 Timers Timing Diagram 6 28 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 6 18 AC ELECTRICAL SPECIFICATIONS SERIAL COMMUNICATIONS PORT see Figure 6 18 16 67 MHz 20 MHz 25 MHz Num Characteristic Min Max Min Min Unit 250 SPCLK Clock Output Period 4 64 4 64 4 64 clks 251 SPCLK Clock Output Rise Fall Time 0 15 0 10 0 8 ns 252 Delay from SPCLK to Transmit see Note 1 0 40 0 30 0 24 ns 253 SCP Receive Setup Time see Note 1 40 30 24 ns 254 SCP Receive Hold Time see Note 1 10 8 7 ns NOTES 1 This also applies when SPCLK is inverted by CI in the SPMODE register 2 The enable signals for the slaves m
124. e connection The TCS bit in the SCON2 register should be set to one to enable the external clock source After autobauding is complete both the transmit and receive clock sources can be derived internally from BRG2 and the external pin connected to TCLK2 should be three stated to assure that it does not contend with the TCLK2 pin 4 3 9 3 AUTOBAUD PARAMETER RAM When configured to operate in the autobaud mode the IMP overlays some entries of the UART specific parameter RAM as illustrated in Table 4 3 MOTOROLA MC68LC302 REFERENCE MANUAL 4 11 Communications Processor CP Table 4 3 Autobaud Specific Parameter Address Name Width Description SCC 90 Word Maximum IDLE Characters SCC Base 9E MAX BIT Word Current Maximum START Bit Length SCC Base A0 NOM START Word Current Nom START Bit used to determine baud rate SCC Base A2 PAREC Word Receive Parity Error Counter SCC 4 Word Receive Framing Error Counter SCC NOSEC Word Receive Noise Counter SCC 8 BRKEC Word Receive Break Error Counter SCC AA 1 Word User Defined Character SCC Base ABCHR2 Word User Defined Character2 SCC Base AE RCCR Word Receive Control Character Register SCC 1 Word CONTROL Character1 SCC B2 CHARACTER2 Word CONTROL Character2 SCC 4 CHARACTER3 Wor
125. e device make it ideal for hand held or other low power applications The new 32 kHz or 4 MHz PLL option greatly reduces the total power budget of the designer s board and allows the L C302 to be an effective device in low power systems The LC302 can then optionally generate a full frequency clock for use by the rest of the board During low power modes the new periodic interrupt timer PIT allows the device to be woken up at regular intervals In addition two pins allow the device to be woken up from low power modes Third given that the LC302 is packaged in a 100TQFP package it allows the 68302 to be used in space critical applications as well as height critical applications such as PCMCIA cards Fourth since the disable CPU mode also known as slave mode is still retained the LC302 can function as a fully intelligent DMA driven peripheral chip containing serial channels tim ers and chip selects etc 1 4 LC302 DIFFERENCES The LC302 has some specific differences from the 68302 Most of these differences simply result from the reduction in pins from 132 on the original 68302 to 100 pins on the LC302 1 OMisatrademarkof Siemens AG MOTOROLA MC68LC302 REFERENCE MANUAL 1 3 Introduction The following features have been removed or modified from the 68302 in order to make the LC302 possible SCC3 and its baud rate generator BRG3 are removed External masters are not able to take the bus away from the LC302 except t
126. each transfer 1 SAP is incremented by one or two after each transfer according to the source size SSIZE bits and the starting address DAPI Destination Address Pointer DAP Increment 0 DAP is not incremented after each transfer 1 DAP is incremented by one or two after each transfer according to the destination size DSIZE bits and the starting address SSIZE Source Size 00 Reserved 01 Byte 10 Word 11 Reserved DSIZE Destination Size 00 Reserved 01 Byte 10 11 Reserved BT Burst Transfer 00 IDMA gets up to 75 of the bus bandwidth 01 IDMA gets up to 50 of the bus bandwidth 10 IDMA gets up to 25 of the bus bandwidth 11 IDMA gets up to 12 5 of the bus bandwidth RST Software Reset 0 2 Normal operation 1 Thechannel aborts any external pending or running bus cycles and terminates channel operation Setting RST clears all bits in the CSR and CMR STR Start Operation 0 Stop channel clearing this bit will cause the to stop transferring data at the end of the current operand transfer The IDMA internal state is not altered 1 Start channel setting this bit will allow the to start or continue if previously stopped transferring data NOTE STR is cleared automatically when the transfer is complete 3 12 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB 3 4 2 2 Source Address Pointer Register SAPR 31 24 23 0 RES
127. ecution bus pipes move b 6 000000 copy STOP operand high byte to addr 000000 stop gt SR 5 ae error routine NOTE The RI PB9 DTE PB10 and periodic interrupt timer timeout in terrupts conditions will generate level 4 interrupts The user should set the 68000 interrupt mask register to the appropriate level before executing this code IMP s low power control logic will 1 Detect the write cycle 2 Check if bit 5 1 supervisor space if it is 0 the low power request will be ignored 3 Sample the interrupt mask bits bits 0 2 If during this process of stopping the clocks 2 16 MC68LC302 REFERENCE MANUAL MOTOROLA Configuration Clocking Low Power Modes and Internal Memory an interrupt of higher level than the mask is asserted to the core this process will abort 4 Wait for 16 clocks to guarantee the execution of the STOP command by the core BG and BGACK will reset the 16 clock counter and it will restart its count 5 Assert bus request signal to the core 6 Wait for Bus Grant from the core 7 Force the IMP to the selected power down mode as defined in Table 2 3 2 4 4 2 3 IMP Wake Up from Low Power STOP Modes The IMP can wake up from STOP DOZE STAND BY mode to NORMAL SLOW mode in response to inputs from the following sources 1 Asserting both RESET and HALT hard reset pins 2 Asserting high to low transition either PB9 or
128. eliminary estimates Test values are TBD MC68LC302 REFERENCE MANUAL Characteristic Symbol 5v Typ 5v Max Unit Normal Mode at 20Mhz PD I 70 TBD mA Norlmal Mode at 16Mhz 60 Low Power Standby Mode PDSB I 7 TBD mA Lo Power Doze Mode 004 1 500 Low Power Stop Mode 20 100 MOTOROLA Electrical Characteristics 6 5 DC ELECTRICAL CHARACTERISTICS Characteristic Symbol Min Max Unit Input High Voltage Except pins noted below Vin 2 0 Vpp V STETE SUE Toe TIN2 TOUT2 WDOG PB8 PB11 RESET Yn 2 5 V These pins have schmitt trigger inputs Input Low Voltage Except EXTAL Vit Vss 0 3 0 8 V Input Undershoot Voltage 0 8 Input High Voltage EXTAL 3 3 Volt or 5 Volt Part 8 Vpp Vpp V Input Low Voltage EXTAL Vss 0 3 0 6 V Input Leakage Current 20 uA Input Capacitance All Pins 15 Three State Leakage Current 2 4 0 5 V 20 Open Drain Leakage Current 2 4 V lop 20 Output High Voltage 400 uA see Note Vpp 1 0 V Output Low Voltage VoL loj 3 2 mA 1 19 11 CS0 CS3 ER 0 5 BG RCLK1 2 TCLK1 TCLK2 RTS1 RTS2 SDS2 PA12 RXD2 CTS2 CD2 loj 5 3 mA AS WEH UDS WEL LDS OE R W 0 5 BGACK DTACK D0 D15 RESET 7 0 mA TXD1 TXD2 zx es lo 8 9 mA HALT BR as output
129. ems where External Masters take ownership of the bus CFC should be programmed to 0 MOTOROLA MC68LC302 REFERENCE MANUAL 3 27 System Integration Block 518 3 8 2 Disable CPU Logic M68000 The IMP can be configured to operate solely as a peripheral to an external processor In this mode the on chip M68000 CPU should be disabled by strapping DISCPU high during sys tem reset RESET and HALT asserted simultaneously The internal accesses to the IMP peripherals and memory may be asynchronous or synchronous During synchronous reads one wait state may be used if required EMWS bit set The following pins change their func tionality in this mode 1 THE pin becomes BR and is an output from the and SDMA to the external M68000 bus 2 The IPL2 pin becomes BG and is an input to the IDMA and SDMA from the external M68000 bus When BG is sampled as low by the IMP it waits for AS HALT and BGACK to be negated and then asserts BGACK and performs one or more bus cy cles 3 The IPL1 pin becomes BGACK and is an output from the IDMA and SDMA to indicate bus ownership 4 The IPL2 0 lines are no longer encoded interrupt lines The interrupt controller will out put the MC68LC302 s interrupt request on IOUT2 CSO which is multiplexed with IOUT2 is not available in this mode 5 The and WEL signals become UDS and LDS respectively 6 The OE becomes R W DISCPU should remain continuously high during disable CPU mode o
130. eration modes of the IMP The WP bit in IOMCR is used as a protect mechanism to prevent erroneous writing of IOMCR IOMCR 0FA 7 6 5 4 3 2 1 0 owe xw tM 0 0 0 0 0 0 0 Read Write IOMWP IMP Operation Mode Control Write Protect Bit This bit prevents accidental writing into the IOMCR After reset this bit defaults to zero to enable writing Setting this bit prevents further writing excluding the first write that sets this bit DF 3 0 Divide Factor The Divide Factor Bits define the factor of the low power divider of the PLL These bits specify a divide range between 2 215 Changing the value of these bits will not cause a loss of lock condition to the IMP PLL BCD BRG Clock Divide Control This bit controls whether the divide by two block shown in Figure 2 2 is enabled 0 The BRG clock is divided by 1 1 The BRG clock is divided by 2 2 14 MC68LC302 REFERENCE MANUAL MOTOROLA Configuration Clocking Low Power Modes and Internal Memory LPM Low Power Modes When the 68000 core executes the STOP instruction the IMP will enter the specified mode LPM1 0 00 Normal the IMP PLL and clock oscillator will continue to operate normally 01 Stand_by Mode 10 DOZE Mode 11 Stop Mode 2 4 4 1 7 Low Power Drive Control Register LPDCR This register controls the state of the IMP s 68000 address and data buses during the Standby Doze
131. errupt Timer Register PITR The PITR contains control for prescaling the periodic timer as well as the count value for the periodic timer This register can be read or written only during normal operational mode Bits 14 13 are not implemented and always return a zero when read A write does not affect these bits PITR 50 0 15 14 13 12 11 10 9 8 0 0 10 PITR9 PITR8 PITR7 RESET 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PITR6 PITR5 PITR4 PITR3 PITR2 PITR1 PITRO RES RESET 0 0 0 0 0 0 0 0 Read Write 3 24 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB PTEN Periodic Timer Enable This bit contains the enable control for the periodic timer 0 Periodic timer is disabled 1 Periodic timer is enabled PTP Periodic Timer Prescaler Control This bit contains the prescaler control for the periodic timer 0 Periodic timer clock is not prescaled 1 Periodic timer clock is prescaled by a value of 512 PITR10 0 Periodic Interrupt Timer Register Bits These bits of the PITR contain the remaining bits of the PITR count value for the periodic timer These bits may be written only when the PIT is disabled PTEN 0 to modify the PIT count value NOTE If the PIT is enabled with the PTP bit is set the first interrupt can be up to 512 clocks early depending on the prescaler counter value when the PIT is enabled 3 8 EXTERNAL CHIP SELECT SIGNALS AND WAIT STATE LOGIC The IMP provides a set
132. es serial data strobe 2 SDS2 in IDL and GCI modes In IDL GCI modes the 5052 5051 outputs may be used to route the B1 and or B2 channels to devices that do not support the IDL GCI buses This is configured in the SI MOTOROLA MC68LC302 REFERENCE MANUAL 5 17 Signal Description MODE and SIMASK registers If SCC2 is in NMSI mode this pin operates as BRG2 the out put of the SCC2 baud rate generator unless SDS2 is enabled to be asserted during the B1 or B2 channels of ISDN bits SDC2 SDC1 of SIMODE SDS2 BRG2 may be temporarily disabled by configuring it as a general purpose output pin The input buffers have Schmitt triggers TCLK2 acts as the SCC2 baud rate generator output if SCC2 is in one of the mul tiplexed modes RXD2 PAO TXD2 PA1 e RCLK2 PA2 e TCLK2 PAS3 e BOOT SDS2 PA7 BRG2 Table 5 10 Baud Rate Generator Outputs Source NMSI GCI IDL PCM SCC2 BRG2 TCLK2 TCLK2 TCLK2 NOTE In NMSI mode the baud rate generator outputs can also appear on the RCLK and TCLK pins as programmed in the SCON register NOTE PA7 and 5 pins are sampled at initialization to determine the boot mode To enable Boot from SCC2 mode PA7 has to be pulled LOW during Reset with 5ns hold time after negation of RESET and HALT If Boot mode is enabled determines the Clock source to SCC2 This pin has to be valid for 100 clocks after the negation of RESET and HALT The user can pull it HIGH or LOW with an external resisto
133. evice should place valid data on the bus When the LC302 is in Disable CPU mode this bidirectional signal defines the data bus transfer as a read or write cycle It is an output when the LC302 is the bus master and is an input otherwise UDS A0 Write Enable High Upper Data Strobe Address 0 When the core is enabled with a 16 bit data bus this output pin functions as WEH and is active during a write cycle to indicate that an external device should expect data on the D15 D8 of the data bus When the core is enabled with a 8 bit data bus this bidirectional pin functions as AO When the LC302 is in Disable CPU mode this bidirectional line functions as UDS and controls the flow of data on the data bus When using a 16 bit data bus this pin functions as an upper data strobe UDS When using an 8 bit data bus this pin functions as AO When used as i e the pin is low then the pin takes on the timing of the other address pins as opposed to the strobe timing This line is an output when the 1 C302 is the bus master and is an input otherwise MOTOROLA MC68LC302 REFERENCE MANUAL 5 9 Signal Description WEL LDS DS Write Enable Low Lower Data Strobe Data Strobe When the core is enabled this output pin functions as WEL and is active during a write cycle to indicate that an external device should expect data on the 07 00 of the data bus When the LC302 is in Disable CPU mode this bidirectional line f
134. g Diagram 6 22 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 6 12 AC ELECTRICAL SPECIFICATIONS INTERNAL MASTER INTERNAL READ WRITE CYCLES see Figure 6 12 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol Min Max Min Min Unit 140 Clock High to IAC High tCHIAH 40 35 27 ns 141 Clock Low to IAC Low tCLIAL m 40 35 27 ns 142 Clock High to DTACK Low tcHDTL 45 40 30 ns 143 Clock Low to DTACK High tci pTH 40 35 27 ns 144 Clock High to Data Out Valid tcupov 30 25 20 ns 145 AS High to Data Out Hold Time tASHDOH 0 0 0 ns S0 51 52 53 54 55 56 57 80 CLKO OUTPUT A23 A1 OUTPUT AS OUTPUT IAC OUTPUT UDS LDS OUTPUT R W OUTPUT D15 D0 OUTPUT DTACK OUTPUT Figure 6 12 Internal Master Internal Read Cycle Timing Diagram MOTOROLA MC68LC302 REFERENCE MANUAL 6 23 Electrical Characteristics 6 13 AC ELECTRICAL SPECIFICATIONS CHIP SELECT TIMING INTERNAL MASTER see Figure 6 13 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol win Min Min Max Unit Clock High to CS IACK OE WEL WEH 150 586 Note 2 tcucsiakL 0 40 0 35 0 27 ns Clock Low to CS OE WEL 151 High see Note
135. g Wake Up Time to Low Power Mode Power Consumption Stand By Doze and STOP 2 4 1 PLL and Oscillator Changes to IMP The oscillator that was on the MC68302 has been replaced by the new clock synthesizer described in this section The registers related to the oscillator have been either removed or MOTOROLA MC68LC302 REFERENCE MANUAL 2 5 Configuration Clocking Low Power Modes and Internal Memory changed according to the description below Several control bits are still available but have new locations The low power modes on the MC68302 have changed completely and will be discussed later in 2 4 4 1 IMP Low Power Modes 2 4 1 1 CLOCK CONTROL REGISTER The clock control register address FA is not implemented on the MC68L C302 This register location has been reassigned to the IOMCR and ICKCR registers The clock control register bits have been reassigned as follows CLKO Drive Options CLKOMOD1 2 These bits are now in the IMP clock control register IPLCR on the MC68L C302 see 2 4 3 4 2 IMP PLL and Clock Control Register IPLCR Three State TCLK1 TSTCLK1 This bit is now in the DISC register on the MC68LC302 see 4 3 2 Disable SCC1 Serial Clocks Out DISC Three State RCLK1 TSRCLK1 This bit is now in the DISC register on the MC68LC302 see 4 3 2 Disable SCC1 Serial Clocks Out DISC Disable BRG1 DISBRG1 This bit has been removed since the BRG1 pin was removed 2 4 2 MC68LC302 System Clock Generation
136. gnals require pullups since they are three stated by the MC68L C302 when they are not being driven Open drain signals always require pullups Unused inputs should not be left floating If they are input only they may be tied directly to Vcc ground or a pullup or pulldown resistor may be used Unused outputs may be left unconnected Unused I O pins may be configured as outputs after reset and left unconnect ed If the MC68L C302 is to be held in reset for extended periods of time in an application other than what occurs in normal power on reset or board test sequences due to a special appli cation requirement such as Vpp dropping below required specifications etc then three stated signals and inputs should be pulled up or down This decreases stress on the device transistors and saves power See the RESET pin description for the condition of all pins during reset MOTOROLA MC68LC302 REFERENCE MANUAL 5 21 Signal Description 5 22 MC68LC302 REFERENCE MANUAL MOTOROLA SECTION 6 ELECTRICAL CHARACTERISTICS The AC specifications presented consist of output delays input setup and hold times and signal skew times All signals are specified relative to an appropriate edge of the clock CLKO pin and possibly to one or more other signals The timing for the LC302 signals is the same as the corresponding signals of the 68302 MOTOROLA VERY IMPORTANT NOTE REGARDING SIGNALS A few signals have been added to and removed fr
137. he BRG is used to divide the second clock down to provide the clock used for transmit The second clock can be either the system clock or a clock connected to TIN1 The TIN1 and RCLK pins can be connected to each other externally After the first character is received the user must take the following steps 1 Determine the baud rate from the returned NOM START value and program SCON to input frequency baud rate 1 where the input frequency is either the system clock or the clock on TIN1 2 Program the DSR to FFFF The DSR will need to be programmed back to 7FFF be fore the Enter Baud Hunt command is issued again 3 Set the ENT bit in the mode register 4 Program the transmit character BD as show in Table 4 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CL PE PM CHAR Table 4 8 Transmit Character BD R ready bit 0 Character is not ready 1 Character is ready to transmit CL character len 0 7 bits parity or 8 bits with no parity 1 8 bits parity PE parity enable 0 No parity 1 MOTOROLA MC68LC302 REFERENCE MANUAL 4 19 Communications Processor CP PM parity mode 0 Even parity 1 Odd The autobaud controller issues Tx interrupt after each character is transmitted 4 3 9 9 REPROGRAMMING TO UART MODE OR ANOTHER PROTOCOL The following steps should be followed in order to switch the SCC from autobaud to UART mode or to another protocol
138. he CHARACTERS value in the control character table until the channel operates in normal UART mode After reception begins in normal UART mode i e the a or A is found this entry is available again as a control character table entry 4 3 9 4 AUTOBAUD PROGRAMMING MODEL The following sections describe the details of initializing the autobaud microcode preparing for the autobaud process and the memory structures used 4 3 9 4 1 Preparing for the Autobaud Process The host begins preparation for the auto baud process with the following steps Steps 1 and 2 are required if the SCC has been used after reset or after UART mode in order to re enable the process 1 Disable the SCC by clearing the ENR and ENT bits The host may wish to precede this action with the STOP TRANSMIT commands to abort transmission in an orderly way 2 Issue the ENTER HUNT MODE command to the SCC This ensures that an open buffer descriptor is closed 3 Setup all the autobaud parameters in the autobaud specific parameter RAM shown in Table 4 3 the autobaud command descriptor shown in Table 4 4 and the lookup table shown in Table 4 4 Of these three areas the autobaud controller only modifies the autobaud specific parameter RAM and the first word of the autobaud command de scriptor during its operation 4 Write the SCON to configure the SCC to use the baud rate generator clock of 16x the maximum supported baud rate A typical value is 4000 assuming a 1 8432 M
139. he IMP A bit set to one signifies that the corresponding B channel bit is used for transmission and reception on the B channel Note that the serial data strobes SD1 and SD2 are asserted for the entire 8 bit time slot inde pendent of the setting of the bits in the SIMASK register 15 8 7 0 OE Bit O of this register is the first bit transmitted or received on the IDL GCI channel 4 3 SERIAL COMMUNICATION CONTROLLERS SCCS The IMP contains two independent SCCs each of which can implement different protocols This configuration provides the user with options for controlling up to two independent full duplex lines implementing bridges or gateway functions or multiplexing both SCCs onto the same physical layer interface to implement a two channels on a time division multiplexed TDM bus Each protocol type implementation uses identical buffer structures to simplify programming 4 3 1 SCC Configuration Register SCON Each SCC controller has a configuration register that controls its operation and selects its clock source and baud rate This register has not been changed from the MC68302 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 EXTC TCS RCS 10 CD9 CD8 CD7 5 CDA CD2 CDI CDO DIV4 4 3 1 1 DIVIDE BY 2 INPUT BLOCKS NEW FEATURE The SCC Baud Rate Generators have 2 divide by 2 blocks added to them With the di
140. he corresponding interrupt in the event register will be masked This register is cleared upon reset MOTOROLA MC68LC302 REFERENCE MANUAL 4 21 Communications Processor CP 4 3 11 BISYNC Controller The functionality of the BISYNC controller has not changed For any additional information on parameters registers and functionality please refer to the MC68302 Users Manual 4 3 11 1 BISYNC MEMORY MAP When configured to operate in BISYNC mode the IMP overlays the structure listed in Table 4 10 onto the protocol specific area of that SCC param eter RAM Refer to System Configuration Registers on page 5 for the placement of the three SCC parameter RAM areas and Table 4 1 for the other parameter RAM values Table 4 10 BISYNC Specific Parameter RAM Address Name Width Description SCC Base 9C RCRC Word Temp Receive CRC SCC Base 9E CRCC Word CRC Constant SCC Base AO PRCRC Word Preset Receiver CRC 16 LRC SCC Base A2 TCRC Word Temp Transmit CRC SCC Base A4 PTCRC Word Preset Transmitter CRC 16 LRC SCC Base A6 RES Word Reserved SCC Base 8 RES Word Reserved SCC Base AA PAREC Word Receive Parity Error Counter SCC Base AC BSYNC Word BISYNC SYNC Character SCC Base AE BDLE Word BISYNC DLE Character SCC Base BO 1 Word CONTROL Character 1 SCC Base B2 CHARACTER2 Word CONTROL Character 2 SCC Base B4 Word CONTROL Character 3 SCC Base B6
141. hen the M68000 core accesses the dual port RAM the bus signals are driven externally Likewise in disable CPU mode when an external device accesses an area of external system memory the chip select logic can be used to generate the chip select signal and DTACK 5 1 FUNCTIONAL GROUPS The input and output signals of the MC68LC302 are organized into functional groups as shown in Table 5 1 and Figure 5 1 Table 5 1 Signal Definitions TQFP Functional Group Signals Number Clocks XTAL EXTAL CLKO VCCSYN 5 System Control RESET HALT BUSW DISCPU 4 Address Bus A19 A1 19 Data Bus PNIO PN15 PN8 D15 D8 8 Data Bus D7 DO 8 Bus Control AS OE R W WEH UDS AO WEL LDS DS DTACK 5 Interrupt Control Bus Arbitration IPL2 IPLO BR BG BGACK 3 NMSI1 ISDN I F RXD1 TXD1 RCLK1 TCLK1 CD1 CTS1 RTST 7 NMSI2 PAIO RXD2 TXD2 RCLK2 TCLK2 CD2 CTS2 RTS2 BRG2 8 PAIO SCP SPRXD SPTXD SPCLK MODCLK PA12 4 Timer PBIO TIN1 TIN2 TOUT2 WDOG 4 PBIO 11 8 4 Chip Select 53 050 4 6 GND 11 MOTOROLA MC68LC302 REFERENCE MANUAL 5 1 Signal Description All pins except EXTAL CLKO and the layer 1 interface pins in IDL mode support TTL levels EXTAL when used as an input clock needs a CMOS level CLKO supplies a CMOS level output The IDL interface is specified as a CMOS electrical interface All outputs except CLKO and the GCI pins drive 100 pF CLKO is
142. hen the SCC is programmed as a transparent control ler It is an 8 bit register used to report events recognized by the transparent channel and to generate interrupts On recognition of an event the transparent controller sets the corre sponding bit in the transparent event register A bit is cleared by writing a one writing a zero does not affect a bit s value This register is cleared at reset 7 6 5 4 3 2 1 0 5 TXE RCH BSY TX 4 3 12 6 TRANSPARENT MASK REGISTER The SCC mask register SCCM is referred to as the transparent mask register when the SCC is operating as a transparent controller It is an 8 bit read write register that has the same bit format as the transparent event regis ter If a bit in the transparent mask register is a one the corresponding interrupt in the event register will be enabled If the bit is zero the corresponding interrupt in the event register will be masked This register is cleared at reset 4 4 SERIAL COMMUNICATION PORT SCP The functionality of the SCP has not changed For any additional information on parameters registers and functionality please refer to the MC68302 Users Manual 4 4 1 SCP Programming Model The SCP mode register consists of the upper eight bits of SPMODE The SCP mode regis ter an internal read write register that controls both the SCP operation mode and clock source is cleared by reset 14 13 1 11 1 15 2 0 9 8 MOTOROLA
143. hese four pins can be used either as a dedicated timer function or as a general purpose port B I O port pin Note that the timers do not require the use of external pins The input buffers have Schmitt triggers TIN1 PB3 Timer 1 Input This input is used as a timer clock source for timer 1 or as a trigger for the timer 1 capture register TIN1 may also be used as the external clock source for any SCC baud rate gen erators TIN2 PB5 Timer 2 Input This input can be used as a timer clock source for timer 2 or as a trigger for the timer 2 capture register TOUT2 PB6 Timer 2 Output This output is used as an active low pulse timeout or as an event overflow output toggle from timer 2 WDOG PB7 Watchdog Output This active low open drain output indicates expiration of the watchdog timer WDOG is asserted for a period of 16 clock CLKO cycles and may be externally connected to the RESET HALT pins to reset the MC68LC302 The WDOG pin function is enabled after a total system reset It may be reassigned as the I O pin the PBCNT register 5 17 PARALLEL I O PINS WITH INTERRUPT CAPABILITY The four parallel I O pins with interrupt are shown in Figure 5 13 Figure 5 13 Port B Parallel I O Pins with Interrupt PB11 PB8 Port B Parallel I O pins These four pins may be configured as a general purpose parallel I O ports with interrupt ca pability Each of the pins can be configured either as an input or an o
144. hift register will not be transmitted ENT may be set or cleared regardless of whether serial clocks are present MODE1 MODE0 Channel Mode 00 HDLC 01 Asynchronous UART 10 Reserved 11 BISYNC Promiscuous Transparent and Autobaud 4 3 4 SCC Data Synchronization Register DSR Each DSR is a 16 bit memory mapped read write register DSR specifies the pattern used in the frame synchronization procedure of the SCC in the synchronous protocols In the UART protocol it is used to configure fractional stop bit transmission After reset the DSR defaults to 7E7E two FLAGs thus no additional programming is necessary for the HDLC protocol For BISYNC the contents of the DSR should be written before the channel is enabled 15 8 7 0 SYN2 SYN1 4 3 5 Buffer Descriptors Table Data associated with each SCC channel is stored in buffers Each buffer is referenced by a buffer descriptor BD BDs are located in each channel s BD table located in dual port RAM There are two such tables for each SCC channel one is used for data received from the serial line the other is used to transmit data The format of the BDs is the same for each SCC mode of operation HDLC UART BISYNC and transparent and for both transmit or receive Only the first field containing status and control bits differs for each protocol The BD format is shown in Figure 4 1 15 0 0 STATUS AND CONTROL OFFSET 2 DATA LENGTH OFFSE
145. hrough a simple scheme using the HALT pin This restriction does not apply to using the L C302 in CPU disabled mode slave mode in which case BR BG and BGACK are all avail able they replace the IPL2 0 pins Although the Independent DMA IDMA is still available the external IDMA request pins DREQ DACK and DONE have been eliminated Four address lines have been eliminated giving a total of 20 address lines However the LC302 supports more than a 1 MB addressing range since each of the four chip selects still decodes a 24 bit address This allows a total of 4 MB to be addressed Since the function code pins and AVEC have been removed interrupt acknowledgment to external devices is only provided on levels one six and seven The DDCMP and V 110 protocols have been removed The total list of pins removed is A23 A20 FC2 FCO AVECT RMC IACT BERR BR BG BGACK BCLR IACK1 IACK6 IACK7 DREQ DONE BRG1 7 TOUT1 NC1 TCLK3 RTS3 CTS3 plus 5 power and ground pins NOTE Signals marked with are available in the PGA Package The SCP pins are now muxed with PA8 PAY and PA10 The TXD3 RXD3 and RCLK3 functions associated with SCC3 are eliminated The UDS LDS and R W pins are not available except in slave mode where they re place the WEH WEL and OE pins Instead the new pins WEH WEL and OE have been defined for glueless interfacing to memory PA12 is now muxed with the MODCLK
146. ies 4 192 Mhz and 32 768 Khz If MODCLKO GND SCONI is programmed to 0 0008 3 8 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB If MODCLKO VCC SCON1 is programmed to 0 00 8 The following baud rates are achieved as a function of 5 MODCLK and input clock VCCSYN MODCLK 00 20 Mhz 11467 bps SCON1 0x00D8 10 4 192 Mhz 9614 bps SCON1 0x00D8 10 4 8 Mhz 11009 bps SCON1 0x00D8 11 32 768 Khz 9662 bps SCON1 0x00A8 The following paragraphs explain the boot process for the 32 768 Khz case in detail If the clock provided to the MC68LC302 is 32 768 KHz the system frequency is multiplied by 401 to 13 139968 MHz The CD10 CDO bits of the SCON are programmed to 84 decimal giv ing a UART frequency of 9662 In summary 13 139968 MHz 84 1 16 9662 If the starting frequency is exactly 32 000 KHz the UART frequency is 9435 NOTE The autobaud function cannot be used in the boot download pro cess Values in bit CD10 0 in SCON are not relevant if PA5 1 The RISC processor then programs the SCM register to 013D to program the SCC to UART mode with both the receiver and the transmitter enabled software operation mode CD and CTS are don t cares 8 bit data characters and no parity The RISC processor then begins receiving data into the dual port RAM beginning with location 0 of the dual port RAM Every character that is received is echoed back out of the TXD1 pin The
147. if enabled Any of these errors will cause the channel to abort reception In order to resume autobaud operation after an error condition the M68000 should clear the status bits and issue the Enter Baud Hunt command again 4 3 9 8 AUTOBAUD TRANSMISSION The autobaud package supports two methods for echoing characters or transmitting characters The two methods are automatic echo and smart echo 4 18 MC68LC302 REFERENCE MANUAL MOTOROLA Communications Processor 4 3 9 8 1 Automatic Echo This method uses the SCC hardware to automatically echo the characters back on the TxD pin The automatic echo is enabled by setting the DIAG bits in the SCM to 10 The transmitter should not be enabled The hardware echo is done auto matically The CD pin needs to be asserted in order for the characters to be transmitted back On SCC1 the external CD pin must be tied low On SCC2 and SCC3 either the exter nal CD pin must be tied low or the CD pins should be left configured as general purpose input pins the CD signal to the SCC is then connected to ground internally Using the automatic echo the receiver still autobauds correctly and performance is not affected The SCC echoes the received data with a few nanoseconds delay 4 3 9 8 2 Smart Echo This method requires addition hardware and software to implement The user must provide two clock sources One clock source is the sample clock which is input on RCLK and cannot be divided down T
148. in the event register will be masked This register is cleared upon reset 4 3 12 Transparent Controller The functionality of the BISYNC controller has not changed For any additional information on parameters registers and functionality please refer to the MC68302 Users Manual 4 3 12 1 TRANSPARENT MEMORY MAP When configured to operate in transparent mode the IMP overlays the structure illustrated in Table 4 11 onto the protocol specific area of that SCC parameter RAM Refer to Table 2 6 for the placement of the three SCC param eter RAM areas and Table 4 1 for the other parameter RAM values MOTOROLA MC68LC302 REFERENCE MANUAL 4 23 Communications Processor CP Table 4 11 Transparent Specific Parameter RAM Address Description SCC BASE 9C Reserved SCC 9E Reserved SCC BASE A0 Reserved SCC BASE Reserved SCC A4 Reserved SCC Reserved SCC BASE A8 Reserved SCC BASE AA Reserved SCC BASE AC Reserved SCC AE Reserved SCC Reserved SCC B2 Reserved SCC BASE B4 Reserved SCC B6 Reserved SCC B8 Reserved SCC Reserved SCC Reserved SCC BASE BE RES WORD Reserved 4 3 12 2 TRANSPARENT MODE REGISTER Each SCC mode register is a 16 bit mem ory mapped read write register that controls the SCC operation The term transparent mode
149. inimum RESET length is 2 3 seconds An internally generated reset from the M68000 RESET instruction causes the RESET line to become an output for 124 clocks In this case the M68000 core is not reset how ever the communication processor is fully reset and the system integration block is al most fully rese The user may also use the RESET output signal in this case to reset all external devices During a total system reset the address data and bus control pins are all three stated except for 53 50 WEL and OE which are high and IAC which is low The BG pin output is the same as that on the BR input The general purpose 1 pins are config ured as inputs except for WDOG which is an open drain output The NMSI1 pins are all inputs except for RTS1 and TXD1 which output a high value CLKO is active Besides the total system reset and the RESET instruction some of the MC68LC302 pe ripherals have reset bits in one of their registers that cause that particular peripheral to be reset to the same state as a total system reset or the RESET instruction Reset bits may be found in the CP in the CR the IDMA in the CMR timer 1 in the TMR1 and timer 2 in the TMR2 HALT Halt When this bidirectional open drain signal is driven by an external device it will cause the LC302 bus master M68000 core SDMA or IDMA to stop at the completion of the current bus cycle This signal is asserted with the RESET signal to
150. is function can be disabled 3 22 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB 3 7 4 1 Overview The periodic interrupt timer consists of an 11 bit modulus counter that is loaded with the val ue contained in the PITR The modulus counter is clocked by the CLKIN signal derived from the IMP EXTAL pin See Figure 2 2 The clock source is divided by four before driving the modulus counter PITCLK When the modulus counter value reaches zero an interrupt request signal is generated to the IMP in terrupt controller The value of bits 11 1 in the PITR is then loaded again into the modulus counter and the counting process starts over A new value can be written to the PITR only when the PIT is disabled The PIT interrupt replaces the IMP PB8 interrupt and is mapped to the PB8 interrupt priority level 4 The PIT Interrupt is maskable by setting bit1 PB8 in the IMR register NOTE When the PIT is enabled PB8 can still be used as parallel I O pin or as DRAM refresh controller request pin but PB8 will not be capable of generating interrupts 3 7 4 2 Periodic Timer Period Calculation The period of the periodic timer can be calculated using the following equation PITR count value 1 CEXTAL 107512 4 periodic interrupt timer period Solving the equation using a crystal frequency of 32 768 kHz with the prescaler disabled gives PITR count value 1 32768 1 22 periodic interrupt timer period
151. its in the CMR 7 4 3 2 1 0 mE oe Bits 7 4 These bits are reserved for future use MOTOROLA MC68LC302 REFERENCE MANUAL 3 13 System Integration Block 518 DNS Done Not Synchronized NOT USED BES Bus Error Source This bit indicates that the IDMA channel terminated with an error during the read cycle BED Bus Error Destination This bit indicates that the IDMA channel terminated with an error during the write cycle DONE Normal Channel Transfer Done This bit indicates that the IDMA channel has terminated normally 3 5 INTERRUPT CONTROLLER The IMP interrupt controller accepts and prioritizes both internal and external interrupt re quests and generates a vector number during the CPU interrupt acknowledge cycle 3 5 1 Interrupt Controller Key Differences Since the function code pins are not connected externally the MC68LC302 with the core enabled should be programmed to Dedicated Mode and to internally generate the vectors for Levels 1 6 and 7 An external device will not be able to decode an IACK cycle and pro vide an vector back to the MC68LC302 In Disable CPU mode the IRQ6 and IRQ7 become the BR BGACK and BG signals With the core disabled the MC68LC302 will not be able to decode an external CPU s inter rupt acknowledge cycle The user must poll the Interrupt Pending Register IPR during in terrupt handling to determine which peripheral caused the interrupt 3 5 2
152. l bus master needs the bus then the HALT pin must be asserted to the LC302 to halt the part 5 12 MC68LC302 REFERENCE MANUAL MOTOROLA Table 5 3 Signal Summary Core and External Master Signal Description M68000 Core Master External Master Access To Access To Signal Name Pin Type Internal External Internal External Memory Memory Memory Memory Space Space Space Space 19 1 5 005 LDS RW WEH WEL OE O 015 00 Read 015 00 Write DTACK a BR Open Drain NA NA N A N A BG HALT Open Drain y o RESET Open Drain y o y o IPL2 IPLO 10072 External Masters only directly supported in Disable CPU mode Signal Names in parentheses are only available in Disable CPU mode WEH WEL OE are threestate when External Master Acquires the Bus with HALT lf DTACK is generated automatically internally by the chip select logic then it is an output Otherwise it is an input Table 5 4 Bus Signal Summary IDMA and SDMA IDMA Master SDMA Master Access To Access To Signal Name Internal External Internal External Memory Memory Memory Memory Space Space Space Space 19 1 5 UDS LDS RW
153. le locations and how they are mapped into system memory SYSTEM MEMORY MAP EXCEPTION 256 VECTOR ENTRIES 0 8 0FA 0FB IMP POWER DOWN 4K BLOCK BASE 0 SYSTEM RAM DUAL PORT xxx000 BASE 4K BLOCK BASE 400 PARAMETER RAM DUAL PORT BASE 800 INTERNAL REGISTERS BASE FFF Figure 2 1 IMP Configuration Control The on chip peripherals including those peripherals in both the communications processor CP and system integration block SIB require a 4K byte block of address space This 4K byte block location is determined by writing the intended base address to the BAR in super visor data space FC 5 The FC2 0 pins are internally driven by MC68L C302 to visor data space After a total system reset the on chip peripheral base address is undefined and it is not possible to access the on chip peripherals at any address until BAR is written The BAR and the SCR can always be accessed at their fixed addresses NOTE The BAR and SCR registers are internally reset only when a to tal system reset occurs by the simultaneous assertion of RESET MOTOROLA MC68LC302 REFERENCE MANUAL 2 3 Configuration Clocking Low Power Modes and Internal Memory and HALT The chip select CS lines are not asserted on ac cesses to these locations Thus it is very helpful to use CS lines to select external ROM RAM that overlaps the BAR and SCR register locations since this prevents
154. ller CP Including Main Controller RISC Processor Two Independent Full Duplex Serial Communications Controllers SCCs Supporting Various Protocols High Level Synchronous Data Link Control HDLC SDLC Universal Asynchronous Receiver Transmitter UART Binary Synchronous Communication BISYNC Transparent Modes Autobaud Support Instead of DDCMP and V 110 Boot from SCC Capability MC68LC302 REFERENCE MANUAL MOTOROLA Introduction Four Serial DMA Channels for the Two SCCs Flexible Physical Interface Accessible by SCCs Including Motorola Interchip Digital Link IDL General Circuit Interface GCI Also Known as 2 Pulse Code Modulation PCM Highway Interface Nonmultiplexed Serial Interface NMSI Implementing Standard Modem Signals SCP for Synchronous Communication Two Serial Management Controllers SMCs To Support IDL and GCI Auxiliary Channels e 100 Pin Thin Quad Flat Pack TQFP Packaging 1 3 LC302 APPLICATIONS The LC302 excels in several applications areas First any application using the 68302 but not needing all three serial channels is a potential candidate for the LC302 Note however that LC302 sacrifices most of the provision for external bus mastership thus the LC302 may not be appropriate where the 68302 is used as part of larger systems Second the LC302 excels in low power and portable applications The inclusion of a static 68000 core coupled with the low power modes built into th
155. lock rate the user can reduce power consumption by dividing IMP MOTOROLA MC68LC302 REFERENCE MANUAL 2 15 Configuration Clocking Low Power Modes and Internal Memory PLL output clock that provides the IMP system clock Switching between the NORMAL and SLOW modes is achieved by changing the DF3 0 field in the IOMCR register to non zero value The IMP PLL will not lose lock when the DF3 0 field in the IOMCR register is changed 2 4 4 2 2 Entering the STOP DOZE STAND BY Mode Entering the STOP DOZE STAND BY mode is achieved by the 68000 core executing the following code nop move b 6 000000 copy STOP operand high byte to addr 000000 stop gt SR This code is position independent The core must in the supervisor state to execute the STOP instruction therefore the write to 000000FB must be done in the supervisor state function code 5 supervisor data The core trace exception should be disabled otherwise the low power control will not enter the STOP mode To guarantee supervisor state and trace exceptions disabled this code should be part of a TRAP routine Upon entering the trap routine examine the stacked status register If it indi cates the supervisor state then execute this code to enter STOP mode If not supervisor do NOT execute this code could perform some application specific error TRAP x btst b 5 supervisor beq s NO_STOP nop flush ex
156. m START bit length is calculated by the following equation Maximum start length Sampling Rate Recognized baud rate x 1 05 EQ 3 Thus for the first entry in the table the maximum start length is 1 8432 Mhz 115200 x 1 05 17 for an external sample clock The value 1 05 is a suggested margin that allows char acters 596 larger than the nominal character rate to be accepted In effect the margin deter mines the split point between what is considered to be a 56 7K character rate and what is a 38 4K character rate The margin should not normally be less than 1 03 due to clocking differences between UARTSs The nominal START bit length is calculated by Nominal start length Sampling Rate Recognized baud rate 2 EQ 4 For the 115 2K example in the first table entry this would be 1 8432 MHz 115 2K 2 8 The structure of the lookup table is shown in Table 4 5 The table starts with the maximum UART baud rate supported and ends with the minimum UART baud rate supported Table 4 5 Autobaud Lookup Table Format OFFSET from Lookup Table Pointer Description 0 Maximum Start Length 2 Nominal Start Length 4 Maximum Start Length 6 Nominal Start Length Maximum Start Length Nominal Start Length Lookup Table Size 1 4 Maximum Start Length Lookup Table Size 1 4 2 Nominal Start Length NOTE If less margin is used in the calculation of the maximum start length above it is possible to
157. meter RAM 4 11 Autobaud Sampling Rate 4 15 Autobaud Transmission 4 18 Automatic Echo 4 19 Carrier Detect Lost 4 18 Channel Reception Process 4 9 Determining Character Length and Parity 4 17 End Of Table Error 4 18 Enter Baud Hunt Command 4 14 Lookup Table 4 15 Lookup Table Example 4 17 Lookup Table Pointer 4 15 Lookup Table Size 4 15 Maximum START bit length 4 16 Overrun Error 4 18 Performance 4 9 Preparing for the Autobaud Process 4 13 Programming Model 4 13 Reception Error Handling Procedure 4 18 Reprogramming to UART Mode or another protocol 4 20 Smart Echo 4 11 4 19 Smart Echo Hardware Setup 4 11 START bit 4 9 Transmit Process 4 11 Automatic echo 4 5 MOTOROLA MC68LC302 REFERENCE MANUAL B Base Address Regisrter 2 4 Baud Rate Generator 5 18 BCR 3 13 BERR 24 3 3 3 4 3 5 3 6 BERR See Signals BG 3 28 5 11 BGACK 5 11 BISYNC Controller 4 22 BISYNC Event Register 4 23 BISYNC Mask Register 4 23 BISYNC Memory Map 4 22 BISYNC Mode Register 4 22 BISYNC Receive Buffer Descriptor 4 22 BISYNC Transmit Buffer Descriptor 4 22 Bootstrap 3 7 BR 3 28 3 29 5 10 3 26 BRG 2 12 BRG Clock 2 12 Divide by two System Clock 2 14 BSR 3 6 Buffer Buffer Descriptor 4 6 Descriptors 2 20 3 29 Buffer Descriptor 4 6 Buffer Descriptors Table 4 6 Bus Arbitration 3 28 5 11 Bandwidth 3 12 Error 2 4 Grant BG 5 11 Grant Acknowledge BGACK 5 11 Master 3 28 Request BR 5 10 Signal Summary 5
158. n TIN1 or TIN2 falling edge FRR Free Run Restart 0 Free run timer count continues to increment after the reference value is reached 1 Restart timer count is reset immediately after the reference value is reached ORI Output Reference Interrupt Enable 0 Disable interrupt for reference reached 1 Enable interrupt upon reaching the reference value OM Output Mode Only available for Timer 1 0 Active low pulse for one CLKO clock cycle 60 ns at 16 67 MHz 1 Toggle output CE Capture Edge and Enable Interrupt 00 Capture function is disabled 01 Capture on rising edge only and enable interrupt on capture event Capture on falling edge only and enable interrupt on capture event 11 Capture on any edge and enable interrupt on capture event PS Prescaler Value The prescaler is programmed to divide the clock input by values from 1 to 256 The value 00000000 divides the clock by 1 the value 11111111 divides the clock by 256 3 7 2 2 Timer Reference Registers TRR1 TRR2 Each TRR is a 16 bit register containing the reference value for the timeout TRR1 and TRR2 are memory mapped read write registers 3 7 2 3 Timer Capture Registers TCR1 TCR2 Each TCR is a 16 bit register used to latch the value of the counter during a capture opera tion when an edge occurs on the respective TIN1 or TIN2 pin TCR1 and TCR2 appear as memory mapped read only registers to the user 3 7 2 4 Timer Co
159. n be in dependently routed to the SCCs Table 5 9 PCM Mode Signals LISY1 115 0 Data L1RXD L1TXD is Routed to SCC 0 0 L1TXD is Three Stated L1RXD is Ignored 0 1 CH 1 1 0 CH 2 1 1 CH 3 NOTE CH 1 2 and 3 are connected to the SCCs as determined in the SIMODE register In IDL GCI modes the 5052 5051 outputs be used to route the B1 and or B2 chan nels to devices that do not support the IDL or GCI buses This is configured in the serial in terface mode SIMODE and serial interface mask SIMASK registers CD1 L1SY1 Carrier Detect Layer 1 Sync This input is used as the NMSI1 carrier detect CD pin in NMSI mode as a PCM sync signal in PCM mode and as an L1SYNC signal in IDL GCI modes If the CD1 pin has changed for more than one receive clock cycle the LC302 asserts the appropriate bit in the SCC1 event register If the SCC1 channel is programmed not to sup port CD1 automatically in the SCC1 mode register then this pin may be used as an ex ternal interrupt source The current value of CD1 may be read in the SCCS1 register See 5 16 MC68LC302 REFERENCE MANUAL MOTOROLA Signal Description MC68302 User s Manual for details CD1 may also be used as an external sync in NMSI mode CTS1 L1GR Clear to Send Layer 1 Grant This input is the NMSI1 CTS signal in the NMSI mode or the grant signal in the IDL GCI mode If this pin is not used as a grant signal in GCI mode it should be c
160. n even character a framing error FE interrupt should have been generated for one of them the interrupt is generated when the parity bit is zero The user can determine the parity by which character generated a FE interrupt if the odd character did then the parity is odd If a framing error occurs on every char acter then the character is 8 bits with force 0 parity If no framing error occurs than this is the same as Case 5 Case 5 This case is not supported because it can not be differentiated from 7 bit force 0 parity and 8 bit no parity If the 9th bit is a 1 then it will be interpreted as a STOP bit 4 3 9 7 AUTOBAUD RECEPTION ERROR HANDLING PROCEDURE The autobaud controller reports reception error conditions using the autobaud command descriptor Three types of errors are supported Carrier Detect Lost during reception When this error occurs and the channel is not programmed to control this line with software the channel terminates reception sets the carrier detect lost CD bit in the command descriptor and generates the CCR interrupt if enabled CCR is bit 3 of the SCCE register Overrun Error When this error occurs the channel terminates reception sets the overrun OV bit in the command descriptor and generates the CCR interrupt if enabled End Of Table Error When this error occurs the channel terminates reception sets the end of table EOT bit in the command descriptor and generates the CCR interrupt
161. n this bit is set further accesses to the IPLCR will be blocked IMP PLL and Clock Control Register IPLCR 0F8 15 14 13 12 11 10 9 8 RESET 0 0 0 VCCSYN 0 0 0 VOCSYNMODOLK 7 6 5 4 3 2 1 0 7 MF6 MF5 MF4 2 FESET VOCSYNMODQLKT 0 0 VOCSYNMODOLK 0 0 Read Write 2 10 MC68LC302 REFERENCE MANUAL MOTOROLA Configuration Clocking Low Power Modes and Internal Memory MF 11 0 Multiplication Factor These bits define the multiplication factor that will be applied to the IMP PLL input frequen The multiplication factor can be any integer from 1 to 4096 The system frequency is MF bits 1 x EXTAL The multiplication factor must be chosen to ensure that the re sulting VCO output frequency will be in the range from 10 MHz to the maximum allowed clock input frequency e g 20 MHz for a 20 MHz IMP The value 000 results in a multiplier value of 1 The value FFF results in a multiplier value of 4096 Any time a new value is written into the MF11 MFO bits the IMP PLL will lose the lock condition and after a delay of 2500 EXTAL clocks will relock When the IMP PLL loses its lock condition all the clocks that are generated by the IMP PLL are disabled After hardware reset the 11 bits default to either 0 3 or 400 190 hex depending on the MODCLK and VCCSYN pins giving a multiplication factor of 1 4 or 401 If the mul tiplication factor is
162. nd format of an asynchronous data stream starting with a known character This controller may be used to implement the stan dard AT command set or other characters In order to use the autobaud mode the serial communication controller SCC is initially pro grammed to BISYNC mode The SCC receiver then synchronizes on the falling edge of the START bit Once a START bit is detected each bit received is processed by the autobaud controller The autobaud controller measures the length of the START bit to determine the receive baud rate and compares the length to values in a user supplied lookup table After the baud rate is determined the autobaud controller assembles the character and compares it against two user defined characters If a match is detected the autobaud controller inter rupts the host and returns the determined nominal start value from the lookup table The autobaud controller continues to assemble the characters and interrupt the host until the host stops the reception process The incoming message should contain a mixture of even and odd characters so that the user has enough information to decide on the proper char acter format length and parity The host then uses the returned nominal start value from the lookup table modifies the SCC configuration register SCON to generate the correct baud rate and reprograms the SCC to UART mode Many rates are supported including 150 300 600 1200 2400 4800 9600 14 4K 19 2K 38 4
163. nnel s Tx BD table The Tx BD is shown in Figure 4 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 L TC UN CT OFFSET 2 DATA LENGTH OFFSET 4 TX BUFFER POINTER 24 bits used upper 8 bits must be 0 OFFSET 6 Figure 4 5 HDLC Transmit Buffer Descriptor 4 3 10 5 HDLC EVENT REGISTER The SCC event register SCCE is called the HDLC event register when the SCC is operating as an HDLC controller It is an 8 bit register used to report events recognized by the HDLC channel and to generate interrupts Upon recog nition of an event the HDLC controller sets its corresponding bit in the HDLC event register Interrupts generated by this register may be masked in the HDLC mask register A bit is cleared by writing a one writing a zero does not affect a bit s value All unmasked bits must be cleared before the CP will clear the internal interrupt request This register is cleared at reset 7 6 5 4 3 2 1 0 CTS IDL BSY 4 3 10 6 HDLC 5 REGISTER The SCC mask register is referred to as the HDLC mask register when the SCC is operating as an HDLC controller It is an 8 bit read write register that has the same bit formats as the HDLC event register If a bit in the HDLC mask register is a one the corresponding interrupt in the event register will be enabled If the bit is zero t
164. ol Parameters 5 1 4 0 Reserved Not Implemented Base 4FF Base 500 4 Word SCC2 Rx Base 508 4 Word SCC2 Rx BD 1 Base 510 4 Word SCC2 Rx BD 2 Base 518 4 Word 5 2 Rx BD 3 Base 520 4 Word SCC2 Rx BD4 Base 528 4 Word SCC2 Rx BD 5 Base 530 4 Word SCC2 Rx BD 6 Base 4 538 4 Word 5 2 Rx BD7 Base 540 4 Word SCC2 Tx 0 548 4 Word 5 2 1 550 4 Word SCC2 Tx BD 2 Base 558 4 Word SCC2 Tx BD 3 Base 560 4 Word 5 2 Tx BD 4 568 4 Word 5 2 Tx BD 5 Base 570 4 Word SCC2 Tx BD 6 DRAM Refresh Base 578 4 Word SCC2 Tx BD 7 DRAM Refresh Base 580 SCC2 d Specific Protocol Parameters Base 5 2 Base 5 0 Reserved Not Implemented Base 600 Not Used by 48 Words Available to User Base 65F Base 660 3 Word SMC Reserved Base 666 Word SMC1 Rx BD Base 668 Word SMC1 Tx BD Base 66A Word SMC2 Rx BD Base 66C Word SMC2 Tx BD Base 66E 6 Word SMC1 SMC2 Internal Use Base 67A Word Rx Tx BD Base 67C Word SCC1 SCC3 BERR Channel Number Base 67E Word CP MC68PM302 Revision Number Base 680 Reserved 6BF 6 0 Reserved Not Implemented Base 7FF Modified by the CP after CP or system reset MOTOROLA MC68LC302 REFERENCE MANUAL 2 21 Configuration Clocking Low Power Modes and Internal Memory In
165. om the 68LC302 or their functionality has changed Several signals are only available when 68302 is in CPU disable mode The IAC 2 AVEC and FRZ signals are only available on the PGA IACK7 DREQ DONE BRG1 TOUT1 NC1 NC3 TCLK3 8753 CTS3 signals have been removed UDS LDS R W BR BG BGACK are available only in Slave Mode The following diagrams and tables show the timing for all avail able signals For complete information on which signals are available in which modes CPU disable please refer to Section 5 of this Addendum MC68LC302 REFERENCE MANUAL 6 1 Electrical Characteristics 6 1 MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage 0 310 7 0 V Input Voltage Vin 0 3 to 7 0 V Operating Temperature Range Ta MC68302 0 to 70 MC68302C 40 to 85 Storage Temperature Range Tstg 55 to 150 C 6 2 THERMAL CHARACTERISTICS Characteristic Symbol Value Unit OJA 25 C W Thermal Resistance for PGA 2 C W JA TBD C W Thermal Resistance for TQFP C W Ty Ta Pp a Pp Ipp Pro where Pyo is the power dissipation on pins For 70 C and 0 W 16 67 MHz 5 5 V and CQFP package the worst case value of Ty is Ty 70 C 5 5 V 30 mA 40 C W 98 65 6 2 MC68LC302 REFERENCE MANUAL This device contains circuitry to protect the inputs against d
166. onnected To NMSI1 7 SCC1 Controller ISDN Interface SCC1 SCC2 NMSI 8 SCC2 Controller PIO Port A Parallel I O PAIO SCP 3 SCP Controller PIO Port A Parallel I O NOTE Each one of the parallel I O pins can be configured individually 5 12 TYPICAL SERIAL INTERFACE PIN CONFIGURATIONS Table 5 5 shows typical configurations of the physical layer interface pins for an ISDN envi ronment Table 5 7 shows potential configurations of the physical layer interface pins for a non ISDN environment The timer pins can be used in all applications either as dedicated functions or as PIO pins Table 5 6 Example ISDN Configuration Used As SCC1 Used as ISDN D ch SCC2 Used as ISDN B ch Pins Connected To NMSI1 or ISDN I F SCC1 and SCC2 12 8 PIO PAIO or SCP or SCP Status Control Exchange NOTES 1 ISDN environment with SCP port for status control exchange and with existing terminal for rate adaption 2 D ch is used for signaling 3 B ch is used for voice external CODEC required or for data transfer Table 5 7 Typical Generic Configurations Pins Connected To Used As NMSI1 or ISDN I F 5 1 Terminal with Modem NMSI2 SCC2 Terminal with Modem PAIO SCP SCP Status Control Exchange NOTE Generic environment with two SCC ports any protocol and the SCP port 5 13 NMSI1 OR ISDN INTERFACE PINS The NMSI1 or ISDN interface pins are shown in Figure 5 9 MC6
167. onnected to Vpp If the CTS1 pin has changed for more than one transmit clock cycle the LC302 asserts the appropriate bit in the SCC1 event register and optionally aborts the transmission of that frame If SCC1 is programmed not to support CTS1 in the SCC1 mode register then this pin may be used as an external interrupt source The current value of the CTS1 pin may be read in the SCCS1 register See the MC68302 User s Manual for details RTS1 L1RQ GCIDCL Request to Send Layer 1 5 Clock Out This output is the NMSI1 RTS signal in NMSI mode or PCM Highway mode the IDL re quest signal in IDL mode or the GCI data clock output in GCI mode In PCM Highway mode RTS1 is asserted high HTS1 is asserted when SCC1 in NMSI mode has data or pad flags or syncs to transmit In GCI mode this pin is used to output the GCI data clock 5 14 NMSI2 PORT OR PORT A PINS The NMSI2 port or port A pins are shown in Figure 5 10 a RXD2 PAO lt q TXD2 PA1 gt RCLK2 PA2 gt TCLK2 PA3 52 4 a RTS2 PA5 a CD2 PA6 a BRG2 SDG2 PA7 Figure 5 10 NMSI2 Port or Port A Pins These eight pins be used either as the NMSI2 port or as a general purpose parallel I O port Each one of these pins can be configured individually to be general purpose pins or a dedicated function in NMSI2 When they are used as NMSI2 pins they function exactly as the NMSI1 pins in NMSI mode The PA7 signal in dedicated mode becom
168. or Counter SCC Base AC ABTSC Abort Sequence Counter SCC Base AE NMARC Nonmatching Address Received Counter SCC Base RETRC Frame Retransmission Counter Max Frame Length Register Max Length Counter SCC Base B6 SCC B8 SCC Base BA HADDR2 SCC Base BC HADDR3 SCC Base BE HADDR4 Should be initialized by the user M68000 core User Defined Frame Address 4 3 10 2 HDLC MODE REGISTER Each SCC mode register is a 16 bit memory mapped read write register that controls the SCC operation The read write HDLC mode register is cleared by reset 4 20 MC68LC302 REFERENCE MANUAL MOTOROLA Communications Processor CP 15 14 13 12 11 10 9 8 7 6 5 0 NOF3 2 NOF1 C32 FSE RTE FLG ENC COMMON SCC MODE BITS 4 3 10 3 HDLC RECEIVE BUFFER DESCRIPTOR RX BD The HDLC controller uses the Rx BD to report information about the received data for each buffer The Rx BD is shown in Figure 4 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E Xx WT 1 tT T T no AB ev OFFSET 2 OFFSET 4 OFFSET 6 BUFFER POINTER 24 bits used upper 8 bits must 0 Figure 4 4 HDLC Receive Buffer Descriptor 4 3 10 4 HDLC TRANSMIT BUFFER DESCRIPTOR TX BD Data is presented to the HDLC controller for transmission on an SCC channel by arranging it in buffers referenced by the cha
169. ose 1 O pins and therefore not referenced in the PBCNT PB8 operates like 11 9 ex cept that it can also be used as the DRAM refresh controller request pin as selected in the system control register SCR 3 18 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB NOTE If the PIT is enabled then the PB8 pin will not generate an inter rupt since the PIT uses the PB8 interrupt in the IPR IMR and ISR The direction of each pin is determined by the corresponding bit in the PBDDR The port pin is configured as an input if the corresponding PBDDR bit is cleared it is configured as an output if the corresponding PBDDR bit is set PBDDR11 PBDDRS are cleared on total sys tem reset configuring all PB11 PB8 pins as general purpose input pins When a 11 8 pin is configured as an input a high to low change will cause an interrupt request signal to be sent to the IMP interrupt controller 3 6 4 Port N When the LC302 is in 8 bit mode internal BUSW 0 8 more general purpose 1 pins are available The signal direction for each pin is determined by the corresponding control bit in the port data direction register PNDDR The port I O pin is configured as an input if the corresponding PNDDR bit is cleared it is configured as an output if the corresponding PND DR bit is set The PNDAT register is used to read and write values for the Port N pins 3 6 5 Port Registers The 1 port consis
170. ow to BR High Impedance see 85 30 25 20 ns 86 Clock High to BGACK Low tCHBKL 30 25 20 ns AS and BGACK High the Latest One to 2 5 2 5 2 5 clks 97 BGACK Low when BG Is Asserted tapHBKL 15 15 25 15 20 BG Low to BGACK Low No Other Bus 2 5 2 5 2 5 clks 88 Master see Notes 3 4 1 5 1 5 25 15 420 89 Impedance to BG High see Notes feeds 0 0 0 x 4 ns Clock on which BGACK Low to Clock on 90 which AS Low tCLBKLAL 2 2 2 2 2 2 clks 91 Clock High to BGACK High tCHBKH 30 25 20 ns 92 Clock Low to BGACK High Impedance 7 15 15 10 ns NOTES 1 BR will not be asserted while AS HALT or BERR is asserted 2 Specifications are for DISABLE CPU mode only 3 DMA and SDMA read and write cycle timing is the same as that for the M68000 core MOTOROLA MC68LC302 REFERENCE MANUAL 6 13 Electrical Characteristics P GINE INE ONIWIL ONY S IVN9IS SNE ma 3194 3LIHM 00089 33S 15 95 95 75 65 5 05 15 95 0 Adde jou op ur og pue 71 ONY 5 5 SNE 4 3104 QV3H 00089 335 SS 75 55 28 SALON 14110 4110 xovod
171. p 56 refers to the minimum pulse width required to reset the processor If the asynchronous input setup 47 requirement is satisfied for DTACK the DTACK asserted to data setup time 31 requirement can be ignored The data must only satisfy the data in to clock low setup time 27 for the following clock cycle When AS and R W are equally loaded 20 subtract 5 ns from the values given in these columns MOTOROLA MC68LC302 REFERENCE MANUAL 6 9 Electrical Characteristics 6 10 S0 1 S2 S3 54 55 56 57 J J VI NI VT Nu FC2 FCO X 08 23 1 T 3 6 DATA IN HALT RESET ASYNCHRONOUS INPUTS NOTE 1 NOTES 1 Setup time for the asynchronous inputs 2 0 guarantees their recognition at the next falling edge of the clock 2 BR need fall at this time only to insure being recognized at the end of the bus cycle 3 Timing measurements are referenced to and from a low voltage of 0 8 volt and a high voltage of 2 0 volts unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0 8 volts and 2 0 volts Figure 6 2 Read Cycle Timing Diagram MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics 23 1 LDS UDS DATA OUT HALT RESET ASYNCHRON
172. pedance See tenci ud 30 lt 30 20 ris Note 10 NOTES 1 For loading capacitance of less than or equal to 50 pF subtract 4 ns from the value given in the maximum columns 2 Actual value depends on clock period since signals are driven latched on different CLKO edges To calculate the 6 actual spec for other clock frequencies the user may derive the formula for each specification First derive the margin factor as 2 Sa where N is the number of one half CLKO periods between the two events as derived from the timing diagram is the rated clock period of the device for which the specs were derived e g 60 ns with a 16 67 MHz device or 50 ns with a 20 MHz device and Sa is the actual spec in the data sheet Thus for spec 14 at 16 67 MHz M 5 60 ns 2 120 ns 30 ns Once the margin M is calculated for a given spec a new value of that spec Sn at another clock frequency with period Pa is calculated as Sn N Pa 2 M Thus for spec 14 at 12 5 MHz Sn 5 80 ns 2 30 ns 170 ns These two formulas assume a 50 duty cycle Otherwise if N 15 odd the previous values N P 2 and N Pa 2 must be reduced by X where X is the difference between the nominal pulse width and the minimum pulse width of the EXTAL input clock for that duty cycle For power up the MC68302 must be held in the reset state for 100 ms or 2 3sec if 401 to allow stabilization of on chip circuit After the system is powered u
173. peration Although the CSO pin is not available as an output from the device in disable CPU mode it may be en abled to provide DTACK generation In disable CPU mode BRO is initially 000 In disable CPU mode accesses by an external master to the IMP RAM and registers may be asynchronous or synchronous to the IMP clock See the SAM and EMWS bits in the SCR for details 3 8 3 Bus Arbitration Logic Both internal and external bus arbitration are discussed in the following paragraphs 3 8 3 1 Internal Bus Arbitration The IMP bus arbiter supports three bus request sources in the following standard priority 1 External bus master BR pin only in Disable CPU mode 2 SDMA for the SCCs six channels 3 IDMA one channel 3 8 3 2 External Bus Arbitration When the CPU is enabled an external bus master may gain ownership of the M68000 bus by asserting the HALT signal This will cause the LC302 bus master M68000 core SDMA or IDMA to stop at the completion of the current bus cycle After asserting the HALT signal the external bus master must wait until AS is negated plus 2 additional system clocks before accessing the bus to allow the LC302 to threestate all of the bus signals After gaining own 3 28 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB ership the external master can not access the internal IMP registers or RAM Chip selects and system control functions such as the hard
174. pins as general purpose input pins MOTOROLA MC68LC302 REFERENCE MANUAL 3 17 System Integration Block 518 Table 3 2 Port A Pin Functions PACNT Bit 1 PACNT Bit 0 Input to Pin Function Pin Function SCC2 SCC3 IDMA RXD2 PAO GND TXD2 PA1 RCLK2 PA2 GND TCLK2 RCLK2 st CTS2 4 GND RTS2 PA5 CD2 PA6 GND SDS2 BRG2 PA7 SPRXD PA8 GND SPTXD 9 SPCLK PA10 GND NA PA12 Allows a single external clock source on the RCLK pin to clock both the SCC receiver and transmitter 3 6 3 Port B Port B has 12 pins however only eight are connected externally 3 6 3 1 PB7 PB3 Each port B pin may be configured as a general purpose I O pin or as a dedicated peripheral interface pin PB7 PB3 is controlled by the port B control register PBCNT the port B data direction register PBDDR and the port B data register PBDAT and PB7 is configured as an open drain output WDOG upon total system reset Table 3 3 shows the dedicated function of each pin The third column shows the input to the peripheral when the pin is used as a general purpose l O pin Table 3 3 Port B Pin Functions PBCNT Bit 1 PBCNT Bit 0 Input to Interrupt Pin Function Pin Function Control and Timers TIN1 GND TIN2 PB5 GND TOUT2 PB6 WDOG PB7 3 6 3 2 11 8 11 8 are four general purpose I O pins continuously available as general purp
175. potential bus contention NOTE In 8 bit system bus operation IMP accesses are not possible un til the low byte of the BAR is written Since the MOVE W instruc tion writes the high byte followed by the low byte this instruction guarantees the entire word is written Do not assign other devices on the system bus an address that falls within the address range of the peripherals defined by the BAR If this happens an internal is generated to the core if the address decode conflict enable ADCE bit is set and the address decode conflict ADC bit in the SCR is set 2 2 1 Base Address Register The BAR is a 16 bit memory mapped read write register consisting of the high address bits the compare function code bit and the function code bits Upon a total system reset its value may be read as BFFF but its value is not valid until written by the user The address of this register is fixed at 0F2 in supervisor data space BAR cannot be accessed in user data space BASE ADDRESS Bits 15 13 FC2 FCO The 2 field is contained in bits 15 13 of the BAR These bits are used to set the address space of 4K byte block of on chip peripherals The address compare logic uses these bits dependent upon the bit to cause an address match within its address space When the core is enabled the function code bits will be driven by the core to indi cate the type of cycle in process In disable CPU mode
176. r If Boot mode is not en abled 5 is not sampled at initialization 5 15 PAIO SCP PINS The NMSI3 port or port A pins SCP pins are shown in Figure 5 11 5 18 MC68LC302 REFERENCE MANUAL MOTOROLA Signal Description SPRXD PA8 SPTXD PA9 SPCLK PA10 PA12 Figure 5 11 PAIO SCP Pins These four pins can be used either as the SCP port or parallel I O pins If the SCP is enabled EN bit in SPMODE register is set then the three lines must be connected to the SCP port by setting the appropriate bits in the Port A Control Register Otherwise they are connected to the general purpose Three of the port A I O pins can be configured individually to be general purpose pins or a SCP pin SPRXD PA8 SCP Receive Serial Data Port A pin 8 This signal functions as the SCP receive data input or may be used as a general purpose pin SPTXD PA9 SCP Transmit Serial Data Port A pin 9 This output is the SCP transmit data output or may be used as a general purpose pin SPCLK CD3 SCP Clock NMSI3 CD Pin This bidirectional signal is used as the SCP clock output or may be used as a general pur pose 1 pin MODCLK PA12 After Total System Reset this pin functions as bit 12 of port A 5 16 TIMER PINS The timer pins are shown in Figure 5 12 TIN1 PB3 TIN2 PB5 TOUT PB6 WDOG 7 Figure 5 12 Timer Pins 5 19 MC68LC302 REFERENCE MANUAL MOTOROLA Signal Description Each of t
177. reak Count Register Transmit SCC Base A2 Receive Parity Error Counter SCC Base A4 Receive Framing Error Counter SCC Base A6 Receive Noise Counter SCC Base A8 Receive Break Condition Counter SCC Base AA UADDR1 UART ADDRESS Character 1 SCC Base AC UADDR2 UART ADDRESS Character 2 SCC AE RCCR Word Receive Control Character Register SCC Base BO 1 Word CONTROL Character 1 SCC B2 CHARACTER2 Word CONTROL Character 2 SCC Base B4 CHARACTER3 Word CONTROL Character 3 SCC Base B6 4 Word CONTROL Character 4 SCC Base B8 CHARACTER5 Word CONTROL Character 5 SCC BA 6 Word CONTROL Character 6 SCC Base BC 7 Word CONTROL Character 7 SCC BE 8 Word CONTROL Character 8 Initialized by the user M68000 core 4 3 8 2 UART MODE REGISTER Each SCC mode register is a 16 bit memory mapped read write register that controls the SCC operation The read write UART mode register is cleared by reset 15 14 13 12 11 10 9 8 7 6 5 0 1 RPM PEN UM1 UMO FRZ CL RTSM SL COMMON SCC MODE BITS 4 3 8 3 UART RECEIVE BUFFER DESCRIPTOR RX BD The CP reports information about each buffer of received data by its BDs The Rx BD is shown in Figure 4 2 15 14 13 12 11 10 9 8 7 6
178. rior to 8 Bit Data MOTOROLA MC68LC302 REFERENCE MANUAL 6 35 Electrical Characteristics 6 22 AC ELECTRICAL SPECIFICATIONS NMSI TIMING The NMSI mode uses two clocks one for receive and one for transmit Both clocks can be internal or external When t he clock is internal it is generated by the internal baud rate gen erator and it is output on TCLK or RCLK All the timing is related to the external clock pin The timing is specified for NMSI1 It is also valid for NMSI2 and NMSI3 see Figure 6 23 16 67 MHz 16 67 MHz 20 MHz 20 MHz 25 MHz 25 MHz Num Characteristic Internal External Internal External Internal External Clock Clock Clock Clock Clock Clock Unit Min Max Min Max Min Max Min Max Min Max Min Max RCLK1 and TCLK1 Fre 315 quency see Note 1 5 55 6 668 6 66 8 8 33 10 MHz RCLK1 and TCLK1 Low 316 see Note 4 65 P410 55 P410 45 P410 ns 316a RCLK1 and TCLK1 High 65 55 55 45 45 35 ns RCLK1 Rise Fall 317 Time see Note 3 4 ram sa ee de TXD1 Active Delay from 318 TCLK1 Falling 0 40 0 70 0 30 0 50 0 25 0 40 ns 2151 Active Inactive Dela CTS1 Setup Time to TCLK1 320 Rising 50 10 40 7 35 7 08 RXD1 Setup Time to RCLK1 3
179. rite Cycles o adele panelled er ee ee 6 19 6 12 AC Electrical Specifications Internal Master Internal Read Write 6 23 6 13 AC Electrical Specifications Chip Select Timing Internal Master 6 24 6 14 AC Electrical Specifications Chip Select Timing External Master 6 25 6 15 AC Electrical Specifications Parallel 6 26 6 16 AC Electrical Specifications lInterrupts 6 26 6 17 AC Electrical 6 28 6 18 AC Electrical Specifications Serial Communications Port 6 29 6 19 AC Electrical Specifications IDL 6 30 6 20 AC Electrical Specifications GCl 6 32 6 21 AC Electrical Specifications PCM 6 34 6 22 AC Electrical Specifications NMSI 6 36 Section 7 Mechanical Data and Ordering Information 7 1 Pin Assignments pa ee el a 7 1 7 1 1 Pin Grid Array ete ice peas ttp cct ae bee i 7 1 7 1 2 Surface Mount TQFP cassis de op 7 2 7 2 Package carton Eo Ee e gr Que I sep eoe DO 7 3 7 2 1 Pin Gd PO seras
180. roller RISC Processor Four Serial Direct Memory Access SDMA Channels A Command Set Register Serial Channels Physical Interface Including Motorola Interchip Digital Link IDL General Circuit Interface GCI Also Known as 2 Pulse Code Modulation PCM Highway Interface Nonmultiplexed Serial Interface NMSI Implementing Standard Modem Signals Two Independent Full Duplex Serial Communication Controllers SCCs Supporting the Following Protocols AHigh Level Synchronous Data Link Control HDLC SDLC Universal Asynchronous Receiver Transmitter UART Autobaud Function to Detect Baud Rate of the Incoming Asynchronous Bit Stream Binary Synchronous Communication BISYNC Transparent Modes Serial Communication Port SCP for Synchronous Communication Two Serial Management Controllers SMCs to Support the IDL and GCI Management Channels MC68LC302 KEY DIFFERENCES FROM THE MC68302 SCC3 Was Removed The SCP Is Now Multiplexed with the PA8 PA9 and PA10 Pins The DDCMP and V 110 Protocols Were Removed The Autobaud Function Was Added for Detecting the Baud Rate of the Incoming Asyn chronous Bit Stream 4 This section only presents a description of features and registers that have changed or been added Features that have not changed such as UART HDLC BIYSYNC transparent the SMCs and the SCP will not be discussed For more information on any function not dis cussed in this sec
181. rt A 3 17 5 17 5 18 Control Register 3 17 Data Direction Register PADDR 3 17 Port B 3 17 5 20 Control Register 3 18 Parallel I O Ports 3 17 Parameter RAM 2 21 PB11 3 18 PB11 See DRAM Refresh PB11 See Parallel I O Port PB8 3 18 3 29 PBCNT 3 18 3 19 PBDAT 3 20 PBDDR 3 18 3 20 PCM 4 2 PCM Highway 5 14 5 15 SIMODE 4 2 Periodic Timer Period Calculation 3 23 Physical Layer Serial Interface Pins 5 14 Pin Assignments 7 1 Pin Grid Array 7 1 PIT 2 11 2 12 3 22 As a Real Time Clock 3 24 Period Calculation 3 23 PIT Clock 2 12 PITR 3 24 PLL 2 10 PLL and Oscillator Changes to IMP 2 5 CLKO Drive Options 2 6 Three State RCLK1 2 6 Three State TCLK1 2 6 PLL Clock Divider 2 10 PLL External Components 2 9 PLL Pins pgnd 5 5 pinit 2 7 MOTOROLA Index PNDAT 3 20 PNDDR 3 20 Port A 3 17 Port A Pin Functions 3 18 Port A Pin Functions 3 18 Port A B Parallel I O 3 17 Port B 3 18 Port B Pin Functions 3 18 Port N 3 19 PADAT 3 19 Power Dissipation 6 4 Power Pins 5 2 Programmable Data Bus Size Switch 3 6 Protocol Parameters 2 20 Pullup Resistors 5 21 R RCLK1 Disabling 4 5 RCLK1 L1CLK 5 16 Read Modify Write Cycle 6 12 Real Time Clock 3 24 Registers Internal 2 22 Interrupt In Service ISR 3 16 Interrupt Pending IPR 3 15 Port A Control PACNT 3 17 Data Direction PADDR 3 17 Port B Data Direction Register PBDDR 3 18 System Control SCR 2 4 Reprogramming to UART Mode or Another Protocol 4 20 RESET 5 6 5
182. rt of a normal 302 initialization sequence Also note that the CFC bit of the BAR register should NOT be set it must be cleared 3 6 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB At this time other desired initialization should be completed on the MC68L C302 No bus masters IDMA SDMA or external should be enabled While in 8 bit mode the MC68L C302 should initialize the external memory registers that control the16 bit external memory space External memory refresh is not enabled at this time but all other desired external memory control features should be enabled Note that the MC68LC302 does not access the external memory itself yet only the external memory control registers The 302 based device now copies a special boot code to the user area of the internal dual port RAM of the 302 and then jumps to the start of that code This code is copied as data to the dual port RAM To summarize the procedure is then Boot up 302 derivative Perform required 8 bit operations Write code to the dual port RAM for the bus width change Jump to code in the dual port RAM When ready to use 16 bit bus width set the BUSW bit to 1 Toggle the BWSEN bit from zero to one Allow time for bus arbitration and the instruction pipeline to clear Initialize external memory Copy boot code from EPROM to external memory space Execute code from external memory space NOTE The stack which is shared by both codes sho
183. s 2 SMCs 1 1 1 1 1 1 4 SDMA 1152 BYTES PIT 1 1 1 1 1 1 1 1 1 1 1 68LC302 Figure 1 1 MC68LC302 Block Diagram MOTOROLA MC68LC302 REFERENCE MANUAL 1 1 Introduction 1 2 FEATURES The features of the LC302 are as follows The items in bold face type show major differenc es from the MC68302 although a complete list of differences is given in 1 4 LC302 Differ ences On Chip Static 68000 Core Supporting a 16 or 8 Bit M68000 Family System SIB Including Independent Direct Memory Access IDMA Controller Interrupt Controller with Two Modes of Operation Parallel Input Output Ports some with Interrupt Capability Parallel Input Output I O Ports on D15 D8 in 8 bit mode On Chip 1152 Byte Dual Port RAM Three Timers Including a Watchdog Timer New Periodic Interrupt Timer PIT Four Programmable Chip Select Lines with Wait State Generator Logic Programmable Address Mapping of the Dual Port RAM and IMP Registers On Chip Clock Generator with Output Signal On Chip PLL Allows Operation with 32kHz or 4MHz Crystals Glueless Interface to EPROM SRAM Flash EPROM and EEPROM Allows Boot in 8 bit Mode and Running Switch to 16 bit Mode System Control System Status and Control Logic Disable CPU Logic Slave Mode Operation Hardware Watchdog New Low Power Standby Modes With Wake up From 2 Pins or PIT Freeze Control for Debugging Available Only in the PGA Package DRAM Refresh Contro
184. ser cannot operate the system at the Ringo frequency 2 4 4 3 5 Ring Oscillator Control Register RINGOCR RINGOCR BAR 81A 7 6 5 4 3 2 1 0 RINGOEN RESET 0 0 0 0 0 0 0 0 Read Write RINGOEN Ring Oscillator Enable 0 Ring oscillator is not used 1 Ring oscillator is enabled RECLMODE Real Clock Mode 00 Do not enable the real clock 01 Enable the real clock and switch the system clock from Ringo to the real clock once it is stable 10 Enable the real clock and generate an interrupt to the CPU after the switch occurs 11 Reserved MOTOROLA MC68LC302 REFERENCE MANUAL 2 19 Configuration Clocking Low Power Modes and Internal Memory RICR Ring Oscillator Interrupt Control 00 Connect Ringo Interrupts to 68k interrupt request level 1 01 Connect Ringo Interrupts to 68k Interrupt request level 6 10 Connect Ringo Interrupts to 68k interrupt request level 7 11 Reserved 2 4 4 3 6 Ring Oscillator Event Register RINGOEVR RINGOEVR BAR 81B 7 6 2 1 0 RESERVED RECLSEV RESET 0 0 0 0 0 Read Write RECLSEV Real Clock Switch Event 0 Event has not occurred 1 Real clock is now the system clock This bit is reset by writing 1 Bits 7 1 Reserved 2 5 MC68LC302 DUAL PORT RAM The internal 1152 byte dual port RAM has 576 bytes of system RAM see Table 2 4 and 576 bytes of parameter RAM see Table 2 5 Table 2 4 System RAM
185. stem reset this bit defaults to zero FRZW Freeze Watchdog Timer Enable 0 Freeze Watchdog Timer Logic is disabled 1 Freeze Watchdog Timer Logic is enabled After system reset this bit defaults to zero 3 1 5 Hardware Watchdog The hardware watchdog logic is used to assert an internal BERR and set HWT when a bus cycle is not terminated by and after a programmable number of clock cycles has elapsed The hardware watchdog logic uses four bits in the SCR HWDEN Hardware Watchdog Enable 0 The hardware watchdog is disabled 1 The hardware watchdog is enabled After system reset this bit defaults to one to enable the hardware watchdog MOTOROLA MC68LC302 REFERENCE MANUAL 3 5 System Integration Block 518 HWDCN HWDCNO Hardware Watchdog Count 2 0 000 an internal is asserted after 128 clock cycles 8 us 16 MHz clock 001 an internal BERR is asserted after 256 clock cycles 16 us 16 MHz clock 010 an internal BERR is asserted after 512 clock cycles 32 us 16 MHz clock 011 an internal BERR is asserted after 1K clock cycles 64 us 16 MHz clock 100 an internal BERR is asserted after 2K clock cycles 128 16 MHz clock 101 an internal BERR is asserted after 4K clock cycles 256 us 16 MHz clock 110 an internal BERR is asserted after 8K clock cycles 512 us 16 MHz clock 111 internal BERR is asserted after 16K clock cycles 1 ms 16 MHz clock 3 2 PROGRAMMABLE DATA BUS
186. t Normal 0 When the channel has completed an operand transfer without error conditions the channel does not generate an interrupt request to the IMP interrupt controller The DONE bit remains set in the CSR 1 When the channel has completed an operand transfer without error conditions the channel generates an interrupt request to the IMP interrupt controller and sets DONE in the CSR INTE Interrupt Error Only the internal BERR signal will be used 0 If a bus error occurs during an operand transfer either on the source read BES or the destination write BED the channel does not generate an interrupt to the IMP interrupt controller The appropriate bit remains set in the CSR 1 Ifa bus error occurs during an operand transfer either on BES or BED the channel generates an interrupt to the IMP interrupt controller and sets the appropriate bit BES or BED in the CSR REQG Request Generation External request is not supported 00 Internal request at limited rate limited burst bandwidth set by burst transfer BT bits Internal request at maximum rate one burst External request burst transfer mode DREQ level sensitive 11 External request cycle steal DREQ edge sensitive MOTOROLA MC68LC302 REFERENCE MANUAL 3 11 System Integration Block 518 NOTE The settings 10 and 11 will not work since the DREQ pin is not present SAPI Source Address Pointer SAP Increment 0 SAP is not incremented after
187. t a 1 lt gt FC2 4 AVEC Those pins are available in PGA Package only Figure 5 8 Interrupt Control Pins These inputs have dual functionality IPL2 IRQ7 Interrupt Priority Level 2 0 Interrupt Request 1 6 7 As IPL2 IPLO normal mode these input pins indicate the encoded priority level of the external device requesting an interrupt Level 7 is the highest nonmaskable priority whereas level 0 indicates that no interrupt is requested The least significant bit is IPLO and the most significant bit is IPL2 These lines must remain stable until the M68000 core MOTOROLA MC68LC302 REFERENCE MANUAL 5 11 Signal Description signals an interrupt acknowledge through A19 A16 to ensure that the interrupt is properly recognized As IRQ6 and IRQ7 dedicated mode these inputs indicate to the 681 C302 that an external device is requesting an interrupt Level 7 is the highest level and cannot be masked Level 1 is the lowest level Each one of these inputs except for level 7 can be programmed to be either level sensitive or edge sensitive The M68000 always treats a level 7 interrupt as edge sensitive FC2 FCO Function Codes 2 0 These bidirectional signals indicate the state and the cycle type currently being executed The information indicated by the function code outputs is valid whenever AS is active These lines are outputs when the IMP M680
188. t also prepares two characters against which the autobaud control ler will compare the received character usually these characters are a and A and the host initializes a pointer to a buffer in external memory where the assembled characters will be stored until the host stops the autobaud process Finally the host initializes the SCC data synchronization register DSR to 7FFF in order to synchronize on the falling edge of the START bit Once the data structures are initialized the host programs the SCON register to provide a sampling clock that is 16X the maximum supported baud rate The host then issues the Enter Baud Hunt command and enables the SCC in the BISYNC mode The autobaud controller reception process begins when the START bit arrives The auto baud controller then begins to measure the START bit length With each byte received from the SCC that belongs to the START bit the autobaud controller increments the start length counter and compares it to the current lookup table entry If the start length counter passed the maximum bit length defined by the current table entry the autobaud controller switches to the next lookup table entry the next slower baud rate This process goes on until the autobaud controller recognizes the end of the START bit Then the autobaud controller starts the character assembly process The character assembly process uses the nominal bit length taken from the current lookup table entry
189. t is suggested that the user issue the CP Reset command to the CP command register CR before reinitializing the SCCs This will return the CP to its original state and eliminate any possible inconsistencies in the initializa tion process The RISC cannot return to boot mode unless a system reset is executed with the PA7 pin asserted low Toggling of the PA7 pin when the device is not in system reset is allowed and in this mode the PA7 pin can be used in its alternate functions NOTE The user may wish to disable the software watchdog timer Tim er 3 in the initial boot code if a long delay i e more than 10 sec onds can occur between the initial boot download and the rest of the download process At the end of the Boot from SCC function the following registers contain values that differ from their default reset values ICR 0 000 BAR 0x0000 SCON1 depends on mode The SCM1 register is reprogrammed to its reset value of 0x0 NOTE During the Boot from SCC procedure no external master should acquire the bus 3 4 DMA CONTROL The IMP includes seven on chip DMA channels six serial DMA SDMA channels for the three serial communications controllers SCCs and one IDMA The SDMA channels are discussed in the MC68302 User s Manual The IDMA is discussed in the following para graphs 3 4 14 MC68LC302 Differences The DREQ DACK and DONE pins have been removed The user must not program the IDMA for external request gener
190. tate of the BUSW pin is changed during operation of the MC68L C302 erratic op eration may occur Refer to the MC68000UM AD M68000 8 16 32 Bit Microprocessors User s Manual and the MC68302UM AD MC68302 Integrated Multiprotocol Processor User s Manual for com plete details of the on chip microprocessor including the programming model and instruction set summary Throughout this manual references may use the notation M68000 meaning all devices belonging to this family of microprocessors or the notation MC68000 MC68008 meaning the specific microprocessor products This section is intended to describe configuration of the MC68L C302 and the differences between C302 and the MC68000 and the MC68302 This section also includes tables that show the registers of the IMP portion of the MC68L C302 All of the registers are memory mapped into the 68000 space 2 1 MC68LC302 AND MC68302 SIGNAL DIFFERENCES The MC68LC302 in CPU enable mode has Write Enable WE signals instead of UDS and LDS signal The Write Enable High WEH AO signal indicates that most significant data byte will be accessed and the Write Enable Low WEL DS indicates that the least significant data byte will be accessed When the core is disabled and WEL DS become UDS 0 LDS DS respectively MOTOROLA MC68LC302 REFERENCE MANUAL 2 1 Configuration Clocking Low Power Modes and Internal Memory The MC68LC302 in CPU enable mode h
191. ter Prior to issuing the com mand the M68000 prepares the autobaud command descriptor to contain the lookup table size and pointer The Enter Baud Hunt uses the command with 10 and the channel number set for the corresponding SCC For example with SCC1 the value written to the command register would be 61 4 3 9 4 3 Autobaud Command Descriptor The autobaud controller uses the receive buffer descriptor number 7 Rx BD7 as an autobaud command descriptor The autobaud command descriptor is used by the M68000 core to transfer command parameters to the autobaud controller and by the autobaud controller to report information concerning the received character The structure of the autobaud command descriptor for the autobaud process is shown in Table 4 4 The first word of the descriptor or the status word is updated after every character is received Table 4 4 Autobaud Command Descriptor Offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 M2 1 EOT CD Lookup Table Size 2 4 Function Code 8 Lookup Table Pointer FE Framing Error Bit 10 If this bit is set a character with a framing error was received A framing error is detected by the autobaud controller when no STOP bit is detected in the received data FE will be set for 9 bit character 8 bits parity if the parity bit is 0 NOTE The user must clear this bit when it is set 4 14 MC68LC302 REFERENCE MANUAL
192. tion please refer to the MC68302 User s Manual This section assumes that the user is familiar with the different protocols For more informa tion on a specific protocol implementation please refer to the MC68302 User s Manual MOTOROLA MC68LC302 REFERENCE MANUAL 4 1 Communications Processor CP 4 2 SERIAL CHANNELS PHYSICAL INTERFACE The serial channels physical interface joins the physical layer serial lines to the two SCCs and the two SMCs The separate three wire SCP interface is described in Serial Commu nication Port SCP on page 25 The IMP supports five different external physical interfaces from the SCCs 1 NMSI Nonmultiplexed Serial Interface 2 PCM Pulse Code Modulation Highway 3 IDL Interchip Digital Link 4 GCI General Circuit Interface 4 2 1 Serial Interface Registers There are two serial interface registers SIMODE and SIMASK The SIMODE register is a 16 bit register used to define the serial interface operation modes The SIMASK register is a 16 bit register used to determine which bits are active in the B1 and B2 channels of ISDN 4 2 1 1 SERIAL INTERFACE MODE REGISTER SIMODE If the IDL or GCI mode is used this register allows the user to support any or all of the ISDN channels independently Any extra SCC channel can then be used for other purposes in NMSI mode The SIMODE register is a memory mapped read write register cleared by reset The changes to this reg ister are marked in BOLD
193. to Clock Low tpsu 20 20 14 ns 181 Input Data Hold Time from Clock Low 10 10 19 ns Clock High to Data out Valid 182 CPU Whites Data Control or Direction 35 30 24 ns DATA IN DATA OUT CPU WRITE S6 OF PORT DATA CONTROL OR DIRECTION REGISTER Figure 6 15 Parallel I O Data In Data Out Timing Diagram 6 16 AC ELECTRICAL SPECIFICATIONS INTERRUPTS see Figure 6 16 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol Min Min Max Min Max Unit Interrupt Pulse Width Low IRQ Edge Trig 190 gered Mode ipw 50 42 34 ns 191 Minimum Time Between Active Edges tAEMT 3 3 3 clk NOTE Setup time for the asynchronous inputs IPL2 IPLO and AVEC guarantees their recognition at the next falling edge of the clock 6 26 MC68LC302 REFERENCE MANUAL MOTOROLA Electrical Characteristics IRQ INPUT 491 Figure 6 16 Interrupts Timing Diagram MOTOROLA MC68LC302 REFERENCE MANUAL 6 27 Electrical Characteristics 6 17 AC ELECTRICAL SPECIFICATIONS TIMERS NOTE The FRZ pin is not implemented on the LC302 see Figure 6 17 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol win Min Max Min Unit 200 Timer Input Capture Pulse Width ttpw 50 42 34 ns 201 TIN Clock Low Pulse Wi
194. ts of three memory mapped read write 16 bit registers for port A and three memory mapped read write 16 bit registers for port B Refer to Figure 3 2 Parallel 1 Port Registers for the I O port registers The reserved bits are read as zeros Port A Control Register PACNT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CA CA CA CA CA CA CA CA CA CA CA CA 0 1 Peripheral Port A Data Direction Register PADDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DA DA DA DA DA DA DA DA DA DA DA DA 0 Input 1 Port Data Register PADAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA PA PA PA PA PA PA PA PA PA PA PA Port B Control Register PBCNT 15 8 7 6 5 4 3 2 1 0 RESERVED CB CB CB 0 1 Peripheral MOTOROLA MC68LC302 REFERENCE MANUAL 3 19 System Integration Block 518 Port B Data Direction Register PBDDR 15 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DB DB DB DB DB DB DB DB 0 Input 1 Output Port B Data Register PBDAT 15 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PB PB PB PB PB PB PB PB Port Data Direction Register PNDDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DN DN DN DN DN DN DN DN RESERVED 0 Input 1 Output Port N Data Register PNDAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PN PN PN PN PN RESERVE
195. u 3 19 THREE 3 20 MC68LC302 General Purpose Timer Difference 3 20 General Purpose Timers Programming 3 20 Timer Mode Register TMR1 2 3 20 Timer Reference Registers TRR1 2 3 21 Timer Capture Registers TCR1 2 3 21 Timer Counter TCN1 2 3 21 Timer Event Registers TER1 2 3 21 Timer Software Watchdog 3 22 Software Watchdog Reference Register 3 22 Software Watchdog Counter 3 22 Periodic Interrupt Timer 3 22 oM eA eM LH ADI AA 3 23 Periodic Timer Period 3 23 Using the Periodic Timer As a Real Time Clock 3 24 Periodic Interrupt Timer Register 3 24 External Chip Select Signals and Wait State Logic 3 25 Chip Select 0004 00 3 26 Base Register 0 24 3 26 Option Registers 0 2 2
196. uld be placed in the dual ported RAM Copy the stack to dual port RAM after switch ing to the second RAM and change the stack pointer 3 3 LOAD BOOT CODE FROM AN SCC The MC68LC302 provides the capability of downloading program code into SCC1 and beginning program execution in the dual port RAM The boot function has two clocking options external and internal In the first mode the user provides the chip with an external clock 16 the desired baud rate In the second mode the RISC processor programs the SCC into UART mode running at approximately 9600 baud assuming the frequency of the clock to the chip has one of two nominal values 32 768 Khz or 4 192 Mhz The first 576 bytes that are received into SCC1 are stored in the dual port RAM No error checking is performed on the incoming serial bit stream The 68000 processor then begins MOTOROLA MC68LC302 REFERENCE MANUAL 3 7 System Integration Block 518 executing from the first location of the dual port RAM to complete the boot process This function is not supported for SCC2 Three pins are sampled to determine the mode of operation and clock of the boot function PA7 Sampled during Hard Reset RESET and HALT asserted 0 Boot from SCC is enabled 1 Boot from SCC is disabled PA5 Sampled within 100 clocks from the negation of RESET 0 Internal Clock 1 External Clock 16 the bit rate on TCLK1 and RCLK1 PA12 MODCLKO Sampled during Hard Reset RESET and HALT asserted 0
197. uming three wait state accesses This is the default value 3 4 MC68LC302 REFERENCE MANUAL MOTOROLA System Integration Block SIB 1 Synchronous accesses All accesses to the IMP internal RAM and registers in cluding BAR and SCR must be synchronous to the IMP clock Synchronous read accesses may occur with one wait state if EMWS is also set to one Microcode Enable This bit is used to initiate the execution of Communication Processor microcode that has been loaded into the dual port RAM See Appendix C in MC68302UM AD VGE Vector Generation Enable Not supported by the MC68LC302 This bit must be written to zero Since the MC68L C302 cannot decode an interrupt ac knowledge cycle from an external processor without the FC pins the user should provide either an autovector signal or a vector back to the host processor during an interrupt ac knowledge cycle for the MC68LC302 The user should then read the IPR to determine which the interrupt source 3 1 4 Freeze Control Used to freeze the activity of selected peripherals FRZ is useful for system debugging pur poses For more information on these bits please refer to the MC68302 Users Manual FRZ1 Freeze Timer 1 Enable 0 Freeze Timer 1 Logic is disabled 1 Freeze Timer 1 Logic is enabled After system reset this bit defaults to zero FRZ2 Freeze Timer 2 Enable 0 Freeze Timer 2 Logic is disabled 1 Freeze Timer 2 Logic is enabled After sy
198. unctions as LDS and con trols the flow of data on the data bus When using a 16 bit data bus this pin functions as lower data strobe LDS When using an 8 bit data bus this pin functions as DS This line is an output when the LC302 M68000 core SDMA or IDMA is the bus master and is an input otherwise DTACK Data Transfer Acknowledge This bidirectional signal indicates that the data transfer has been completed DIACK can be generated internally in the chip select logic either for an LC302 bus master or for an external bus master access to an external address within the chip select ranges It will also be generated internally during any access to the on chip dual port RAM or internal registers If DIACK is generated internally then it is an output It is an input when the LC302 accesses an external device not within the range of the chip select logic or when programmed to be generated externally 4 Access The IAC signal is only available in the PGA package This output indicates that the current bus cycle accesses an on chip location This includes the on chip 4K byte block of internal RAM and registers both real and reserved locations and the system configuration reg isters 80F0 0FF The above mentioned bus cycle may originate from the M68000 core the IDMA or an external bus master Note that if the SDMA accesses the internal dual port RAM it does so without arbitration on the M68000 bus therefore the
199. unter TCN1 TCN2 TCN1 and TCN2 are 16 bit up counters Each is memory mapped and can be read and writ ten by the user A read cycle to TCN1 and TCN2 yields the current value of the timer and does not affect the counting operation 3 7 2 5 Timer Event Registers TER1 TER2 Each TER is an 8 bit register used to report events recognized by any of the timers On rec ognition of an event the timer will set the appropriate bit in the TER regardless of the cor responding interrupt enable bits ORI and CE in the TMR TER1 and TER2 which appear MOTOROLA MC68LC302 REFERENCE MANUAL 3 21 System Integration Block 518 to the user as memory mapped registers may be read at any time A bit is cleared by writing a one to that bit writing a zero does not affect a bit s value 7 2 1 0 RESERVED REF CAP CAP Capture Event The counter value has been latched into the TCR The CE bits in the TMR are used to enable the interrupt request caused by this event REF Output Reference Event The counter has reached the TRR value The ORI bit in the TMR is used to enable the interrupt request caused by this event Bits 7 2 Reserved for future use 3 7 3 Timer 3 Software Watchdog Timer A watchdog timer is used to protect against system failures by providing a means to escape from unexpected input conditions external events or programming errors Timer 3 may be used for this purpose Once started the watchdog timer must be cleare
200. ute channel to SCC3 Not Supported in the MCMC68LC302 B1RB B1RA B1 Channel Route in IDL GCI Mode or CH 2 Route in PCM Mode 00 Channel not supported 01 Route channel to SCC1 Route channel to SCC2 if MSC2 is cleared Route channel to SCC3 Not Supported in the MCMC68LC302 DRB DRA D Channel Route in IDL GCI Mode or CH 1 Route in PCM Mode 00 Channel not supported Route channel to SCC1 10 Route channel to SCC2 if MSC2 is cleared Route channel to SCC3 Not Supported in the MC68LC302 e MSC3 SCC3 Connection Not Supported in the MC68L C302 MSC2 SCC2 Connection 0 SCC2 is connected to the multiplexed serial interface PCM IDL or chosen in 51 50 NMSI2 pins are all available for other purposes 1 SCC2 is not connected to a multiplexed serial interface but is either connected di rectly to the NMSI2 pins or not used The choice of general purpose I O port pins versus SCC2 functions is made in the port A control register MS1 MS0 Mode Supported 00 NMSI Mode 01 PCM Mode 10 IDL Mode 11 GCI Interface MOTOROLA MC68LC302 REFERENCE MANUAL 4 3 Communications Processor CP 4 2 1 2 SERIAL INTERFACE MASK REGISTER SIMASK The SIMASK register a memory mapped read write register is set to all ones by reset SIMASK is used in IDL and GCI to determine which bits are active in the B1 and B2 channels Any combination of bits may be chosen A bit set to zero is not used by t
201. utput When configured as an input each pin can generate a separate maskable interrupt on a high to low transi tion PB8 may also be used to request a refresh cycle from the DRAM refresh controller rath er than as an I O pin The input buffers have Schmitt triggers 5 20 MC68LC302 REFERENCE MANUAL MOTOROLA Signal Description 5 18 CHIP SELECT PINS The chip select pins are shown in Figure 5 14 4 5 2 4 53 51 Figure 5 14 Chip Select Pins CS0 IOUT2 Chip Select 0 Interrupt Output 2 In normal operation this pin functions as CSO CSO is one of the four active low output pins that function as chip selects for external devices or memory It does not activate on accesses to the internal RAM or registers including the BAR SCR or CKCR registers When the M68000 core is disabled this pin operates as IOUT2 10072 provides the in terrupt request output signal from the LC302 interrupt controller to an external CPU when the M68000 core is disabled This signal is asserted if an internal interrupt of level 4 6 7 is generated CS3 CS1 Chip Selects 3 1 These three active low output pins function as chip selects for external devices or mem CS8 CS0 do not activate on accesses to the internal RAM or registers including the BAR SCR or CKCR registers 5 19 WHEN TO USE PULLUP RESISTORS Pins that are input only or output only do not require external pullups The bidirectional bus control si
202. ve an external oscillator connected in order to shorten the wake up time There are two possible interrupts to the CPU from the Ringo logic Interrupt when Ringo is enabled the CPU is always interrupted when Ringo starts oscillating RINGOEN bit enables both ring oscillator and enables the interrupt to the CPU Event bits for this interrupt are all wake up events Maskable interrupt when the system clock switches to the real clock The event bit for this interrupt is in the ring oscillator event register The Ringo interrupts can be either at level 1 6 or 7 according to RICR bits If the CPU de termines that the system needs the real clock it programs the RECLMODE bits which en ables the oscillator and PLL and interrupts if necessary if it decides that the system can go back to sleep it executes the normal power down sequence which turns off Ringo Upon switching to the real clock the CPU can be interrupted by programming the RICR bits Note that Ringo is turned off either at the end of a power down sequence or when the PLL has gained lock If the RECLMODE bits are programmed to enable the PLL and the oscillator the user is allowed to enter low power mode after the real clock has resumed The chip will not operate correctly if the CPU enters the low power sequence while the PLL is waking up Resetting of the RINGOEN bit is allowed only if the system is clocked by the real clock The CLKO signal can be disabled by software if the u
203. vide by 2 blocks enabled the VCO Out put from the PLL and the TIN1 input clock can be divided by 2 before they are used by the BRG to generate the serial clocks The divide by two blocks can be enabled by setting the BCD bit in the IOMCR register if the BRG clock source is derived from the IMP system clock or by setting the BRGDIV bit in the DISC register if the BRG clock source is derived from the TIN pin 4 3 2 Disable SCC1 Serial Clocks Out DISC The Disable SCC1 Serial Clocks Out DISC is an 16 bit read write register The upper 8 bits control 1 enabling the divide by 2 prescaler for the baud rate generator from the TIN1 pin and 2 options for three stating theTCLK1 and RCLK1 pins 4 4 MC68LC302 REFERENCE MANUAL MOTOROLA Communications Processor CP DISC Base 8EE 15 14 13 12 11 10 9 8 TSTCLK1 TSRCLK1 BRGDIV 220 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 4 3 2 1 RCLK1 AND TCLK1 OPTIONS TSRCLK1 0 RCLK1 is driven on its pin when SCC1 is the baud rate generator output 1 is three state TSTCLK1 0 is driven on its pin when SCC1 RCLK is the baud rate generator output 1 is three state BRGDIV Enables and disables the divide by two block between the TIN1 pin and the BRG1 pres caler input 0 The divide by two block is disabled 1 The divide by two block is enabled 4 3 3 SCC Mode Register S
204. ware watchdog continue to operate When an external master desires to gain ownership the following bus arbitration protocol should be used 1 Assert HALT Wait two system clocks If AS is negated go to step 5 Wait for AS negation Then wait two additional system clocks Execute Access now the bus is guaranteed to be threestated When done threestate bus and negate HALT NOTE The RMCST bit in the SCR should be zero for this arbitration procedure to work correctly C Also the external master cannot access the internal address space of the MC68L C302 Bus Arbitration is not supported when the MC68L C302 is in one of the low power modes The chip does not release the address and data lines 3 9 DYNAMIC RAM REFRESH CONTROLLER The communications processor CP main RISC controller may be configured to handle the dynamic RAM DRAM refresh task without any intervention from the M68000 core Use of this feature requires a timer or SCC baud rate generator either from the IMP or external ly the I O pin PB8 and two transmit buffer descriptors from SCC2 Tx BD6 and Tx BD7 No changes have been made to the DRAM controller For more information please refer to the MC68302 Users Manual MOTOROLA MC68LC302 REFERENCE MANUAL 3 29 System Integration Block 518 3 30 MC68LC302 REFERENCE MANUAL MOTOROLA SECTION 4 COMMUNICATIONS PROCESSOR CP The CP includes the following modules Main Cont
205. wever if BCLM is cleared no additional action needs to be taken in the interrupt handler HWT Hardware Watchdog Timeout This bit is set when the hardware watchdog see 3 1 5 Hardware Watchdog reaches the end of its time interval an internal BERR is generated following the watchdog timeout even if this bit is already set WPV Write Protect Violation This bit is set when a bus master attempts to write to a location that has RW set to zero read only in its associated base register 0 ADC Address Decode Conflict This bit is set when a conflict has occurred in the chip select logic because two or more chip select lines attempt assertion in the same bus cycle 3 1 3 System Control Bits The system control logic uses six control bits in the SCR WPVE Write Protect Violation Enable 0 an internal BERR is not asserted when write protect violation occurs 1 aninternal BERR is asserted when write protect violation occurs After system reset this bit defaults to zero NOTE WPV will be set regardless of the value of WPVE RMCST RMC Special Treatment 0 The locked read modify write cycles of the TAS instruction will be identical to the M68000 AS and CS will be asserted during the entire cycle The arbiter will issue MOTOROLA MC68LC302 REFERENCE MANUAL 3 3 System Integration Block 518 BG regardless of the M68000 core RMC If an IMP chip select is used then the DTACK generator
206. will insert wait states on the read cycle only 1 The IMP uses the internal RMC to negate AS and CS at the end of the read portion of the RMC cycle and reasserts AS and CS at the beginning of the write portion BG will not be asserted until the end of the write portion If an IMP chip select is used the DTACK generator will insert wait states on both the read and write portion of the cycles The assertion of the internal RMC by the M68000 core is seen by the arbiter and will pre vent the arbiter from issuing bus grants until the completion of M68000 initiated locked read modify write activity After system reset this bit defaults to zero EMWS External Master Wait State EMWS VALID only in Disable CPU Mode When EMWS is set and an external master is using the chip select logic for DTACK gen eration or is synchronously reading from the internal peripherals SAM 1 one additional wait state will be inserted in every memory cycle to external memory peripherals and al SO in every cycle to internal memory and peripherals When EMWS is cleared all syn chronous internal accesses will be with zero wait states and the chip select logic will generate DTACK after the exact programmed number of wait states The chip select lines are asserted slightly earlier for internal master memory cycles than for an external master EMWS should be set whenever these timing differences will necessitate an additional wait state for external masters
207. without losing the IMP s PLL lock Using the clock divider the user can still obtain full IMP operation but at a slower frequency The BRG is not affected by the low power divider circuitry so previous BRG divider settings will not have to be changed when the divide factors are changed When the PLL low power divider bits DFO 3 are programmed to a non zero value the IMP is in SLOW mode The selection and speed of the SLOW mode may be changed at any time with changes occurring immediately NOTE The IMP low power clock divider is active only if the IMP PLL is active The low power divider block is controlled in the IOMCR The default state of the low power divider is to divide all clocks by 1 If the low power divider block is not used and the user is concerned that errant software could accidentally write the IOMCR the user may set a write protection bit in IOMCR to pre vent further writes to the register 2 4 3 4 2 IMP PLL and Clock Control Register IPLCR IPLCR is a 16 bit read write reg ister used to control the IMP s PLL multiplication factor and CLKO drive strength This reg ister is mapped in the 68000 bus space at address 0 8 If the 68000 bus is set to 8 bits BUSW grounded at reset during 8 bit accesses changes to the IPLCR will take effect in the IMP PLL after loading the high byte of IPLCR the low byte is written first The WP bit in IPLCR is used as a protect mechanism to prevent erroneous writing Whe

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