MAXIM MAX8550/MAX8551 handbook
Contents
1. 1 5A lyrrg 15 Vpp 5V 12A lyr 1 5 lyrra 15mA 12A i OUT OUT lyrr 1 5 Vout 1V div 1V div 2V div oV VIT VIT VIT 2V div 2V div 1V div 0v 7 VITR VITR 1V div 1Vidiv EE 0v ee VIN SHDNA SHDNB ov 10V div 5V div 0v 200us div 200us div 1ms div Vppa STARTUP AND SHUTDOWN INTO LIGHT LOAD DISCHARGE ENABLED VIT STARTUP AND SHUTDOWN MAX8550 51 toc16 8550 51 toc17 lyr 1 5A I 15mA R oap 102 d VIT Ryrr 200 1V div 1V div VITR 1V div VIT 1V div SHDNB SHDNA SHDNB 5V div 5V div POK1 5V div 2ms div 200us div LSS8XVW 0SS8XVIN MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards Typical Operating Characteristics continued 20us div ILOAD 10A div 10V div 400us div 12V VouT 2 5V TON GND SKIP AVpp circuit of Figure 8 TA 25 C unless otherwise noted 10A div 10V div 400us div MAXIM Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards Pin Description FUNCTION On Time Selection Control Input This four level logic input sets the nominal DH on time Connect to GND REF AVpp or leave TON unconnected to select the following nominal switching frequencies TON AVpp 200kHz TON OPEN 300kHz TON REF 450kHz TON GND 600kHz UVP2. 1 8V 2 5V 12 T Chip Information TRANSISTOR COUNT 5100 PROCESS BiCMOS MAKIM LG668XVNW 0S5S8XV M MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards _ Package Information The package drawing s in this data sheet may not reflect the most current specifications For the latest package outline information go to www maxim ic com packages 2x Afs c D ILI 2X Slo fefe QFN THIN EPS MARKING PIN 1 I D 0 35 45 A DETAIL B R IS OPTIONAL PKG CORNERS ONLY 4x APPLICABLE TO 4mm PITCH PKG ONLY T 8 LN TERMINAL Bl I PLANE EVEN TERMINAL ODD TERMINAL 25 PALLAS 16 20 28 321 THIN QFN 5x5x0 8mm DOCUMENT CONTROL R amp V 1 28 MAKIN Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards COMMON DIMENSIONS SYMBOL wi NOW MA wi NOM wax vin Now wa vow uc o oo2 oos o 0 02 0 05 o 002 05 0 02 o o5 e 0 25 o5 o5 0 25 0 20 o25 0 30 D 490 500 5 10490 500 s 10 4 90 5 00 s 10 4 90 500 10 E iso 500 5 10490 5 00 s 10 4 90 5 00 5 10 4 80 50 5 10 e oesssc osossc osossc oss oss ha 0 65 0 45 0 JEDEC WHHB WHHC WHHD 1 WHHD 2 1 DIMENSIONING amp TOLERANCING CONFORM TO ASME Y14 5M 1994 2 ALL DIMENS
3. IREF 0 to 50A Hysteresis 300 mV Reference Load Regulation REF Undervoltage Lockout FAULT DETECTION OVP Trip Threshold Referred to Nominal VouT UVP Trip Threshold 70 75 Referred to Nominal UVP OVP AVDD Note 4 POK1 Trip Threshold Lower level falling edge 1 hysteresis 90 93 Referred to Nominal Vout Upper level rising edge 1 hysteresis 110 113 POK2 Trip Threshold Lower level falling edge 1 hysteresis 90 92 5 Referred to Nominal VyrTS 96 and VyTTR Upper level rising edge 1 hysteresis 110 112 5 UVP Blanking Time From rising edge of SHDNA 20 40 ms OVP UVP POK Propagation Delay POK Output Low Voltage ISINK 4mA ILIM Adjustment Range VILIM 2 00 ILIM Input Leakage Current 0 1 a Current Limit Threshold Fixed mV PGND1 to LX Current Limit Threshold Adjustable PGND1 to LX Current Limit Threshold Negative Direction PGND1 to LX Current Limit Threshold Negative Direction PGND1 to LX Zero Crossing Detection Threshold PGND1 to LX Thermal Shutdown Threshold Thermal Shutdown Hysteresis OVP not applicable in MAX8551 Hs VILIM 2V SKIP AVpp Note 4 SKIP AVpp VILIM 2V Note 4 MAXIM _ 0 0 3 LSS8XVW O0SS8XVIN MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards ELECTRICAL CHARACTERISTICS continued VIN 15V Vpp AVpp VSHDNA VSHDNB VBST
4. 5V VREFIN VvtTI 2 5V UVP OVP STBY FB SKIP GND PGND1 PGND2 LX GND TON OPEN Wtts Wrr TA 40 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS MOSFET DRIVERS DH Gate Driver On Resistance Vest Mx 5V DL Gate Driver On Resistance in High State DL Gate Driver On Resistance in Low State Dead Time Additional to Adaptive Delay INPUTS AND OUTPUTS DH falling to DL rising DL falling to DH rising Logic Input Threshold SHDN_ STBY SKIP Note 4 Logic Input Current SHDN_ STBY SKIP Note 4 Rising edge Hysteresis Dual Mode Input Logic Levels FB Input Bias Current FB Low 2 5V output High 1 8V output Four Level Input Logic Levels TON OVP UVP Note 4 High Floating REF Low Logic Input Current TON OVP UVP Note 4 OUT Input Resistance FB GND FB FB adjustable mode OUT Discharge Mode On Resistance Note 4 DL Turn On Level During Discharge Mode Measured at OUT Note 4 Dual Mode is a trademark of Maxim Integrated Products Inc MAXIM Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards ELECTRICAL CHARACTERISTICS continued VIN 15V Vpp AVpp VSHDNA VSHDNB VBST 5V VoUT VREFIN 2 5V UVP OVP
5. MAX8550 N C MAX8551 Overvoltage Undervoltage Protection Control Input This four level logic input enables or disables the overvoltage and or undervoltage protection The overvoltage limit is 116 of the nominal output voltage The undervoltage limit is 70 of the nominal output voltage Discharge mode is enabled when OVP is also enabled Connect the OVP UVP pin to the following pins for the desired function OVP UVP AVpp Enable OVP and discharge mode enable UVP OVP UVP OPEN Enable OVP and discharge mode disable UVP OVP UVP REF Disable OVP and discharge mode enable UVP OVP UVP GND Disable OVP and discharge mode disable UVP Do not connect leave open REF 2 0V Reference Voltage Output Bypass to GND with a 0 1uF min capacitor REF can supply 500A for external loads Can be used for setting voltage for ILIM REF turns off when SHDNA SHDNB and STBY are low Valley Current Limit Threshold Adjustment for Buck Regulator The current limit threshold across PGND and LX is 0 1 times the voltage at ILIM Connect ILIM to a resistive divider typically from REF to GND to set the current limit threshold between 25mV and 200mvV This corresponds to a 0 25V to 2V range at ILIM Connect ILIM to AVpp to select the 50mV default current limit threshold See the Setting the Current Limit section Buck Power Good Open Drain Output POK1 is low when the buck output voltage is more than 1096 above or below the normal
6. 2525 4 660 2 2500 H lt 1 650 2 515 E 640 2 510 j 1 SKIP GND lLoap 0A 630 2 505 480 1 Am 460 620 2 500 SKIP App 440 420 610 2 495 400 600 2 490 4 6 8 10 12 14 16 18 20 22 24 26 28 40 25 10 5 20 35 50 65 80 0 2 4 6 8 10 12 14 Vin V TEMPERATURE C ILoAp A VIT VOLTAGE VTTR VOLTAGE LINE REGULATION vs VIT CURRENT vs VITR CURRENT vs VIN 28 1 28 7 3 127 27 5 1 26 26 i 1 25 25 5 gt 5124 E 24 1 23 23 4 22 22 1 21 21 1 20 20 3 2 4 0 1 2 3 15 0 5 0 5 10 15 4 6 8 10 12 14 16 18 20 22 24 26 28 A mA Vin V Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards Typical Operating Characteristics continued 12V Vour 2 5V TON GND SKIP AVpp circuit of Figure 8 TA 25 C unless otherwise noted LOAD TRANSIENT BUCK LOAD TRANSIENT VTT 1 5A TO 1 5A LOAD TRANSIENT VTT 3A TO 3 MAX8550 51 toc10 MAX8550 51 toc11 MAX8550 51 toc12 1 5A 15mA Eu M Your Vour 100mV div SomVidiv 50mV div VIT VIT 100mV div 50mV div 50mV div VTTR VTTR VTTR 100mV div 50mV div 50mV div ILOAD 10Adiv 0A 2N div 5A div 20us div 40us div 40us div Vppa STARTUP AND SHUTDOWN INTO POWER UP WAVEFORMS POWER DOWN WAVEFORMS HEAVY LOAD DISCHARGE DISABLED MAX8550 51 10 13 MAX8550 51 toc14 MAX8550 51 toc15 5V ILoap 12A
7. Both VTTR and VTT are high impedence in shutdown see Table 2 AVLAZXL VI Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards torr MAXIM MAX8550 ONE SHOT MAX8551 INTREF 1 16 x INTREF OVP UVP N C IN MAX8551 BUCK ON OFF SKIP 1 IN MAX8551 deny BIAS ON OFF _ MUST BE CONNECTED TO GND ZERO CROSSING 0 7 x INTREF VITON OFF LOGIC INTREF 10 INTREF 10 HI DISCHARGE Y 10kQ REFIN 2 10 REFIN 2 10 POWER DOWN VITILIM CURRENT LIMITS VITRILIM 1 POWER DOWN T FORCES POK2 LOW REFIN 2 10 REFIN 2 10 AND VTT TO HIGH IMPEDANCE Figure 1 Functional Diagram MAAXIAA 7 LG668XVM 05S8XVM MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards Detailed Description The MAX8550 MAX8551 combine a synchronous buck PWM controll
8. STBY FB SKIP GND PGND1 PGND2 LX GND TON OPEN VWrrs Wrr Ta 40 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS LINEAR REGULATORS VTTR AND VTT VTTI Input Voltage Range Supply Current IvrT lvrrR 0 VTTI Shutdown Current SHDNA SHDNB GND REFIN Input Impedance VREFIN 2 5V REFIN Range VREFIN VREFIN rising Hysteresis Soft Start Charge Current Vss 0 VTT Internal MOSFET High Side 100mA Wrri 1 5V On Resistance AVpp 4 5V VIT Internal MOSFET Low Side On Resistance REFIN Lockout Threshold 100mA AVpp 4 5V VREFIN 1 5V or 2 5 1 VREFIN 2 5 0 to 1 5 VREFIN 1 5 0 to 1A VTT Current Limit VTT O or VTTI VITS Input Current VVTTS 1 5V VIT open VTTR Output Error Referred to VREFIN 2 VTTR Current Limit VyTTR 0 or VTT Load Regulation VREFIN 1 5V or 2 5V 0 Note 1 Specifications to 40 C are guaranteed by design not production tested Note 2 When the inductor is in continuous conduction the output voltage has a DC regulation level higher than the error compara tor threshold by 5096 of the ripple In discontinuous conduction the output voltage has a DC regulation level higher than the trip level by approximately 1 5 due to slope com
9. Typical Applications Circuit Figure 8 Once VPGND VLX drops below 5 of the current limit threshold 2 5mV for the default 50mV current limit threshold the com parator forces DL low Figure 1 This mechanism caus es the threshold between pulse skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor current operation also known as the critical conduction point The load current level at which PFM PWM crossover occurs ILOAD SKIP is equal to half the peak to peak ripple current which is a function of the inductor value Figure 2 This threshold is rela tively constant with only a minor dependence on the input voltage VIN Vout x KY Vin V ILOAD SKIP IN our where K is the on time scale factor see Table 1 For example in the Typical Applications Circuit of Figure 8 1 7us VOUT 2 5V VIN 12V and L 1H the pulse skipping switchover occurs at i x uem 2 5V J te 2 x uH 12V The crossover point occurs at an even lower value if a swinging soft saturation inductor is used The switch ing waveforms can appear noisy and asynchronous when light loading causes pulse skipping operation but this is a normal operating condition that results in high light load efficiency Trade offs in PFM noise vs Table 1 Approximate K Factor Errors MINIMUM Vin AT TYPICAL Vout 2 5V K piedi h 1 5 SEE THE FACTOR 94 DROPOUT us PE
10. frequency is also a moving target due to rapid improvements in MOSFET technology that are making higher frequen cies more practical Inductor Operating Point This choice provides trade offs size vs efficiency and transient response vs out put ripple Low inductor values provide better transient response and smaller physical size but also result in lower efficiency and higher output ripple due to increased ripple currents The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction where the inductor current just touches zero with every cycle at maximum load Inductor values lower than this grant no further size reduction benefit The optimum operating point is usually found between 20 and 50 ripple current When pulse skipping SKIP low at light loads the inductor value also determines the load current value at which PFM PWM switchover occurs 18 Setting the Output Voltage Buck Preset Output Voltages The MAX8550 MAX8551s Dual Mode operation allows the selection of common voltages without requiring external components Figure 5 Connect FB to GND for a fixed 2 5V output to AVpp for a fixed 1 8V output or connect FB directly to OUT for a fixed 0 7V output Setting the Buck Regulator Output VouT with a Resistive Voltage Divider at FB The buck regulator output voltage can be adjusted from 0 7V to 5 5V using a resistive voltage divider Figure 6 The MA
11. of 60pF is needed to stabilize the VTT output for load currents up to 1 5A This value of capaci tance limits the regulator s unity gain bandwidth frequen cy to about 700kHz typ to allow adequate phase margin for stability To keep the capacitor acting as a capacitor within the regulator s bandwidth it is important that ceramic caps with low ESR and ESL be used Since the gain bandwidth is also determined by the transconductance of the output FETs which increases with load current the output capacitor needs to be greater than 6OpF if the load current exceeds 1 5A but be smaller than 60uF if the maximum load current is less than 1 5A As a rule choose the minimum capacitance and maximum ESR for the output capaci tor using the following ILOAD 60uF x j OUT_MIN u 15A 1 5A ILOAD RESR_ MAX 5mQ x RESR value is measured at the unity gain bandwidth frequency given by approximately 40 LOAD COUT 1 5A faBw Once these conditions for stability are met additional capacitors including those of electrolytic and tantalum types can be connected in parallel to the ceramic capacitor if desired to further suppress noise or volt age ripple at the output MAALM Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards VTTR Output Capacitor Selection LDO The VTTR buffer is a scaled down version of the VTT regulator with much smaller output transconductance Its compensatio
12. voltage at BST to the LX voltage and this exceeds the absolute maximum rating of 6V The boost capacitor should be 0 1uF to 4 7uF depending on the input and output volt ages external components and PC board layout The boost capacitance should be as large as possible to prevent it from charging to excessive voltage but small enough to adequately charge during the minimum low side MOSFET conduction time which happens at maxi mum operating duty cycle this occurs at minimum input voltage In addition ensure that the boost capac itor does not discharge to below the minimum gate to source voltage required to keep the high side MOSFET 23 LSS8XVW 0OSS8XVIN MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards HET A 125V 10mA 4 5V BIAS SUPPLY Vw 45V TO 28V 187kQ 41 2kQ 470uF OPTIONAL IRF7821 N CHANNEL 30V 9mW TOKO FDA1254 1R0M 1 0uH 21A 1 6mQ Y Y Y ee 25V 12A c12 17832 IN N CHANNEL o C13 L1 SUNT 150uF pa F i C11 C12 150mF 4V 25mW LOW ESR POS CAPACITOR D2E SANYO 4TPE150M Figure 8 Typical Applications Circuit fully enhanced for lowest on resistance This minimum gate to source voltage VGS MIN is determined by Qc X VGS MIN where Vpp is 5V is the total gate charge
13. 19 3173 Rev 2 9 04 MAALAA Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards General Description The MAX8550 MAX8551 integrate a synchronous buck PWM controller to generate a sourcing and sinking LDO linear regulator to generate Vtr and a 10mA refer ence output buffer to generate VrrR The buck controller drives two external N channel MOSFETs to generate out put voltages down to 0 7V from a 2V to 28V input with out put currents up to 15A The LDO can sink or source up to 1 5A continuous and 3A peak current Both the LDO out put and the 10mA reference buffer output can be made to track the REFIN voltage These features make the MAX8550 MAX8551 ideally suited for DDR memory appli cations in desktops notebooks and graphic cards The PWM controller in the MAX8550 MAX8551 utilizes Maxim s proprietary Quick PWM architecture with pro grammable switching frequencies of up to 600kHz This control scheme handles wide input output voltage ratios with ease and provides 100ns response to load tran sients while maintaining high efficiency and a relatively constant switching frequency The MAX8550 offers fully programmable UVP OVP and skip mode options ideal in portable applications Skip mode allows for improved efficiency at lighter loads The MAX8551 which is tar geted towards desktop and graphic card applications does not offer the pulse skip feature The VTT VTTR outputs track to wi
14. C of temperature rise The minimum current limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value The val ley of the inductor current occurs at ILOAD MAX minus half the ripple current therefore ILOAD MAX X ILIM VAL gt LOAD MAX gt 2 where ILIM VAL equals the minimum valley current limit threshold voltage divided by the on resistance of Q2 RDS ON Q2 For the 50mV default setting connect ILIM to AVpp In adjustable mode the valley current limit threshold is precisely 1 10th the voltage seen at ILIM For an adjustable threshold connect a resistive divider from REF to GND with ILIM connected to the center tap The external 250mV to 2V adjustment range corresponds to a 25mV to 200 valley current limit threshold When adjusting the current limit use 196 tolerance resistors and the negative direction the adjustable current limit is typically 1 8th the voltage seen at ILIM MAALM Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards a divider current of approximately 10 to prevent signifi cant inaccuracy in the valley current limit tolerance Foldback Current Limit Alternately foldback current limit can be implemented if the UVP latch option is not available Foldback cur rent limit reduces the power dissipation of external components so they can withstand indefinite overload and short ci
15. IONS ARE IN MILLIMETERS ANGLES ARE IN DEGREES 3 NIS THE TOTAL NUMBER OF TERMINALS THE TERMINAL 1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95 1 SPP 012 DETAILS OF TERMINAL 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED THE TERMINAL 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE Package Information continued The package drawing s in this data sheet may not reflect the most current specifications For the latest package outline information go to www maxim ic com packages EXPOSED PAD VARIATIONS 30 320 Frans 396 3 6 529 06 536 520 YES 3 25 35 28552 280 270 280280 270 280 120554 280 270 280 20 270 280 YES 128555 3 5 325 335 3 5 325 335 no 2855 8 3 15 3 25 335 3 15 325 335 0 40 Y Pras 348 122812381312 teas least Ee a 8 132554 300 320 300 3 10 320 no 15255w 00 320 s20 NO SEE COMMON DIMENSIONS TABLE A DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0 25 mm AND 0 30 mm FROM TERMINAL TIP ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH AND E SIDE RESPECTIVELY 7 DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION A COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS 9 DRAWING CONFORMS TO JEDEC MO220 EXCEPT EXPOSED PAD DIMENSION FOR T2855 1 T2855 3 AND T2855 6 10 WA
16. LX to the input side of the inductor LX is used for both current limit and the return supply of the DH driver Boost Flying Capacitor Connection Connect to an external capacitor and diode according to the Typical Applications Circuit Figure 8 See the Boost Supply Diode and Capacitor Selection section DL Synchronous Rectifier Gate Driver Output Swings from PGND to Vpp VDD Supply Input for the DL Gate Drive Connect to the 4 5V to 5 5V system supply voltage Bypass to PGND1 with a 1uF min ceramic capacitor PGND1 Power Ground for Buck Controller Connect PGND1 externally to the underside of the exposed pad GND Analog Ground for Both Buck and LDO Connect GND externally to the underside of the exposed pad SKIP MAX8550 Pulse Skipping Control Input Connect to AVpp for low noise forced PWM mode Connect to GND to enable pulse skipping operation 1 MAX8551 In the MAX8551 this pin is a test pin and must be connected to GND pin 24 Analog Supply Input for Both Buck and LDO Connect to the 4 5V to 5 5V system supply voltage with a series 10Q resistor Bypass to GND with a 1 or greater ceramic capacitor 10 Shutdown Control Input A Use to control buck output A rising edge on SHDNA clears the overvoltage and undervoltage protection fault latches see Tables 2 and 3 Connect to AVpp for normal operation Shutdown Control Input B Use to control VTT and VTTR outputs
17. RFORMANCE SECTION TON SETTING 200 TON AVpp 3 15 300 TON OPEN 450 TON REF 600 TON GND 13 LSS8XVW OSS8XVIN MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards light load efficiency are made by varying the inductor value Generally low inductor values produce a broad er efficiency vs load curve while higher values result in higher full load efficiency assuming that the coil resis tance remains fixed and less output voltage ripple Penalties for using higher inductor values include larger physical size and degraded load transient response especially at low input voltage levels DC output accuracy specifications refer to the thresh old of the error comparator When the inductor is in continuous conduction the MAX8550 MAX8551 regu late the valley of the output ripple so the actual DC out put voltage is higher than the trip level by 50 of the output ripple voltage In discontinuous conduction SKIP GND and ILOAD lt ILOAD SKIP the output volt age has a DC regulation level higher than the error comparator threshold by approximately 1 5 due to slope compensation Forced PWM Mode SKIP AVpp in MAX8550 Only The low noise forced PWM mode SKIP AVpp dis ables the zero crossing comparator which controls the low side switch on time This forces the low side gate drive waveform to constantly be the complement of the hi
18. RPAGE SHALL NOT EXCEED 0 10 mm VAN MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY 12 NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY DRAWING NOT TO SCALE JV 16 20 28 321 THIN QFN 5x5x0 8mm DOCUMENT CONTROL NO REV Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 29 2004 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products LSS8XVW OSS8XVIN
19. SFET 2Q RGATE x Ves few x Raate where Vas Vpp 5V In addition to the losses above allow about 20 more for additional losses because of MOSFET output capacitances and low side MOSFET body diode reverse recovery charge dissipated in the high side MOSFET that is not well defined in the MOSFET data sheet Refer to the MOSFET data sheet for thermal resistance specifications to calculate the PC board area needed to maintain the desired maximum operating junction temperature with the above calculat ed power dissipations To reduce EMI caused by switching noise add a 0 1uF ceramic capacitor from the high side switch drain to the low side switch source or add resistors in series with DH and DL to slow down the switching transitions Adding series resistors increases the power dissipation of the MOSFET so ensure that this does not overheat the MOSFET MOSFET Snubber Circuit Buck Fast switching transitions cause ringing because of a resonating circuit formed by the parasitic inductance and capacitance at the switching nodes This high fre quency ringing occurs at LX s rising and falling transi tions and can interfere with circuit performance and generate EMI To dampen this ringing an optional series RC snubber circuit is added across each switch Below is a simple procedure for selecting the value of the series RC of the snubber circuit 1 Connect a scope probe to measure Vi x to PGND1 and ob
20. VIN MIN is greater than the required minimum input voltage then the operating frequency must be reduced or output capacitance added to obtain an acceptable Vsaa If operation near dropout is anticipated calculate VsAG to be sure of adequate transient response A dropout design example follows VOUT 2 5V fsw 600kHz K 1 7us tOFF MIN 450ns VDROP1 VDROP2 100mV h 1 5 2 5V 0 1V E O AV 43V analy 1 5V 450ns 1 7us Voltage Positioning Buck In applications where fast load transients occur the output voltage changes instantly by RESR x COUT x AlLOAD Voltage positioning allows the use of fewer out put capacitors for such applications and maximizes the output voltage AC and DC tolerance window in tight tolerance applications Figure 9 shows the connection of OUT and FB in a volt age positioned circuit In nonvoltage positioned cir cuits the MAX8550 MAX8551 regulate at the output capacitor In voltage positioned circuits the MAX8550 MAX8551 regulate on the inductor side of the voltage positioning resistor VouT is reduced to VourvPS VouT INO_LOAD Rpos X lLoAD 25 L668XVW 085S8XV M MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards VOLTAGE POSITIONED OUTPUT Figure 9 Voltage Positioned Output PC Board Layout Guidelines Careful PC board layout is critical to achieve low switching losses and clean stable operat
21. X8550 MAX8551 regulate FB to a fixed refer ence voltage 0 7V The adjusted output voltage is Rp 2 where Vrg is 0 7V Rc and Rp are shown in Figure 6 and VRIPPLE is LIR lloAp MAX X ResR Setting the VTT and VTTR Voltages LDO The termination power supply output VTT can be set by two different methods First the VTT output can be con nected directly to the VTTS input to force VTT to regulate to VREFIN 2 Secondly VTT can be forced to regulate higher than VREFIN 2 by connecting a resistive MAXIM TO MAX8550 ERROR 4 AMPLIFIER FIXED 2 Ta 18V Figure 5 Dual Mode Feedback Decoder MAXIA Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards MAXIM MAXB551 Figure 6 Setting VOUT with a Resistive Voltage Divider divider from VTT to VITS The maximum value for VIT is VDROPOUT Where VDROPOUT lvrr x 0 30 max at TA 85 C The termination reference voltage VTTR tracks 1 2 VREFIN Inductor Selection Buck The switching frequency and inductor operating point determine the inductor value as follows Vout Vour L SS Vin fsw X l oap MAx X LIR For example ILOAD MAX 12A VIN 12V VOUT 2 5V fsw 600kHz 30 ripple current or LIR 0 3 2 5V 12V 2 5V StH 12V x 600kHz x 12A x 0 3 Find a low loss inductor with the lowest possible DC resistance that fits in
22. arge rate is determined by the load current and its output capacitance The buck regulator detects and latches the discharge mode state set by the OVP UVP setting on startup For the MAX8551 the OVP UVP is internally connected to REF which permanently enables the output dis charge feature see Table 1 SHDNB and STBY The SHDNB input corresponds to the VTT and outputs and when driven low places the linear regula tor portion of the IC in a low power mode see the Electrical Characteristics table When SHDNB is pulled low VTT and VTTR are high impedance The STBY input is an active high input that is used to shut down only the VTT output When STBY is high VIT is high impedance The STBY input overrides the SHDNB input so even with SHDNB high if STBY is high then the VTT output is inactive Power OK POK2 POK2 is the open drain output for a window compara tor that continuously monitors the VTTS input and output POK2 is pulled low when REFIN is less than 0 8V or when SHDNB is pulled low POK2 is high impedance as long as the output voltage is within 10 of the nominal regulation voltage as set by REFIN When Vyrrs VyTTR rises 10 above or 10 below its nominal regulation voltage the MAX8550 MAX8551 pull POK2 low For logic level output volt ages connect an external pullup resistor between POK2 and AVpp A 100 resistor works well in most applications Table 2 Shutdown and Standby Contr
23. ations Circuit and fsw is the switching frequency Free Running Constant On Time PWM The Quick PWM control architecture is a pseudo fixed frequency constant on time current mode regulator with voltage feed forward Figure 1 This architecture relies on the output filter capacitors ESR to act as a current sense resistor so the output ripple voltage pro vides the PWM ramp signal The control algorithm is simple the high side switch on time is determined solely by a one shot whose pulse width is inversely pro portional to input voltage and directly proportional to the output voltage Another one shot sets a minimum off time of 300ns typ The on time one shot is trig gered if the error comparator is low the low side switch current is below the valley current limit threshold and the minimum off time one shot has timed out On Time One Shot TON The heart of the PWM core is the one shot that sets the high side switch on time This fast low jitter adjustable one shot includes circuitry that varies the on time in response to input and output voltages The high side switch on time is inversely proportional to the input volt age VIN and is proportional to the output voltage Vour X Ros onjaz ton K x where K the switching period is set by the TON input connection Table 1 and Rps ON qz2 is the on resis tance of the synchronous rectifier Q2 in the Typical Applications Circuit Figure 8 This algorithm res
24. e drive loss PLSDR 2 Hscc our X loAp x Rps oN Use RDS ON at TJ MAX Bspc 2lLoap Ve tpt fsw where Vr is the body diode forward voltage drop tpT is the dead time 30ns and fsw is the switching fre quency Because of the zero voltage switch operation the low side MOSFET gate drive loss occurs as a result of charging and discharging the input capacitance Ciss This loss is distributed among the average DL gate driver s pullup and pulldown resistance RDL 1Q and the internal gate resistance RGATE of the MOSFET 220 The drive power dissipated is given by RGATE 2 Fispr Ciss Vas few Reate Rp The high side MOSFET operates as a duty cycle control switch and has the following major losses The channel conduction loss PHSCC The VI overlapping switching loss PHSSw The drive loss PHSDR The high side MOSFET does not have body diode conduction loss because the diode never conducts current 2 X loAp Rps oN V Pasce IN Use RDS ON at TJ MAX 21 LSS8XVW OSS8XVIN MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards Passw MN lioap X fsw x Qas Qan IGATE where IGATE is the average DH driver output current determined by 2 5V RpH HGATE IGATE ON where RpH is the high side MOSFET driver s on resis tance 10 typ and Raate is the internal gate resis tance of the MO
25. e output filter capacitor must have low enough equiv alent series resistance RESR to meet output ripple and load transient requirements yet have high enough ESR to satisfy stability requirements For processor core voltage converters and other appli cations in which the output is subject to violent load transients the output capacitors size depends on how much Resp is needed to prevent the output from dip ping too low under a load transient Ignoring the sag due to finite capacitance VSTEP ESOS 2 LOAD MAX In applications without large and fast load transients the output capacitor s size often depends on how much REsR is needed to maintain an acceptable level of out put voltage ripple The output ripple voltage of a step down controller is approximately equal to the total inductor ripple current multiplied by the output capaci tors Resr Therefore the maximum Resp required to meet ripple specifications is VRIPPLE 5 2 ILOAD MAX 19 LSS8XVW 0OSS8XVIN MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards The actual capacitance value required relates to the physical size needed to achieve low ESR as well as to the chemistry of the capacitor technology Thus the capacitor is usually selected by ESR and voltage rating rather than by capacitance value this is true of tanta OSCONSs polymers and other electrolytics When using low capac
26. er an LDO linear regulator and a 10mA ref erence output buffer The buck controller drives two exter nal N channel MOSFETs to deliver load currents up to 12A and generate voltages down to 0 7V from a 2V to 28V input The LDO linear regulator can sink and source up to 1 5A continuous and 3A peak current with relatively fast response These features make the MAX8550 MAX8551 ideally suited for DDR memory applications The MAX8550 MAX8551 buck regulator is equipped with a fixed switching frequency of up to 600kHz using Maxim s proprietary constant on time Quick PWM architecture This control scheme handles wide input output voltage ratios with ease and provides 100ns instant on response to load transients while maintaining high efficiency with relatively constant switching frequency The buck controller LDO and a reference output buffer are provided with independent current limits Lossless foldback current limit in the buck regulator is achieved by monitoring the drain to source voltage drop of the low side FET The ILIM input is used to adjust this current limit Overvoltage protection if selected is achieved by latching the low side synchro nous FET on and the high side FET off when the output voltage is over 116 of its set output It also features an optional undervoltage protection by latching the MOSFET drivers to the OFF state during an overcurrent condition when the output voltage is lower than 7096 of the regulated
27. gh side gate drive waveform so the inductor current reverses at light loads while DH maintains a duty factor of VouT Vin Forced PWM mode keeps the switching frequency fairly constant However forced PWM opera tion comes at a cost where the no load Vpp bias cur rent remains between 2mA and 20mA due to the external MOSFET s gate charge and switching frequen cy Forced PWM mode is most useful for reducing audio frequency noise improving load transient response and providing sink current capability for dynamic output voltage adjustment Current Limit Buck Regulator ILIM Valley Current Limit The current limit circuit for the buck regulator portion of the MAX8550 MAX8551 employs a unique valley cur rent sensing algorithm that senses the voltage drop across LX and PGND1 and uses the on resistance of the rectifying MOSFET Q2 in the Typical Applications Circuit Figure 8 as the current sensing element If the magnitude of the current sense signal is above the val ley current limit threshold the PWM controller is not allowed to initiate a new cycle Figure 4 With valley 14 current limit sensing the actual peak current is greater than the valley current limit threshold by an amount equal to the inductor current ripple Therefore the exact current limit characteristic and maximum load capability are a function of the current sense resistance inductor value and input voltage When combined with the undervoltage protection c
28. he point that it triggers its thermal fault the buck regulator continues to function Design Procedure Firmly establish the input voltage range ViN and maxi mum load current ILOAD in the buck regulator before choosing a switching frequency and inductor operating point ripple current ratio or LIR The primary design trade off lies in choosing a good switching frequency and inductor operating point and the following four fac tors dictate the rest of the design Input Voltage Range The maximum value VIN MAX must accommodate the worst case voltage The mini mum value must account for the lowest voltage after drops due to connectors and fuses If there is a choice lower input voltages result in better efficiency Maximum Load Current There are two values to con sider The peak load current IPEAK determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selec tion inductor saturation rating and the design of the current limit circuit The continuous load current ILOAD determines the thermal stresses and thus drives the selection of input capacitors MOSFETs and other critical heat contributing components Switching Frequency This choice determines the basic trade off between size and efficiency The opti mal frequency is largely a function of maximum input voltage due to MOSFET switching losses proportion al to frequency and VIN The optimum
29. ion The switching power stage requires particular attention If possible mount all of the power components on the top side of the board with their ground terminals flush against one another Follow these guidelines for good PC board layout Keep the high current paths short especially at the ground terminals This practice is essential for sta ble jitter free operation Keep the power traces and load connections short This practice is essential for high efficiency Using thick copper PC boards 202 vs 102 can enhance full load efficiency by 196 or more Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters where a single mQ of excess trace resistance caus es a measurable efficiency penalty The LX and PGND1 connections to the low side MOSFET for current sensing must be made using Kelvin sense connections When trade offs in trace lengths must be made it is preferable to allow the inductor charging path to be made longer than the discharge path For example it is better to allow some extra distance between the input capacitors and the high side MOSFET than to allow distance between the inductor and the low 26 side MOSFET or between the inductor and the out put filter capacitor Route high speed switching nodes BST LX DH and DL away from sensitive analog areas REF FB and ILIM Input ceramic capacitors must be placed as close as possib
30. ircuit this current limit method is effective in almost every circumstance In forced PWM mode the MAX8550 MAX8551 also implement a negative current limit to prevent excessive reverse inductor currents when the buck regulator output is sinking current The negative current limit threshold is set to approximately 120 of the positive current limit and tracks the positive current limit when is adjust ed The current limit threshold is adjusted with an exter nal resistor divider at ILIM 2uA to 20p4A divider current is recommended for accuracy and noise immunity The current limit threshold adjustment range is from 25mV to 200mV In the adjustable mode the current limit threshold voltage from PGND1 to LX is precisely 1 10th the voltage seen at ILIM The threshold defaults to 50mV when ILIM is connected to AVpp The logic threshold for switchover to the 50mV default value is approximately AVpp 1V Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the differ ential current sense signals seen between LX and GND Al L Vin Vout AC L Figure 2 Pulse Skipping Discontinuous Crossover Point MAKII Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards TOPWM CONTROLLER SEE FIGURE 1 A MAAIM ILOAD MAX aval 1 2 ED XlioAp Figure 4 Valley Current Limit Threshold POR UVLO and Soft Start Internal power on
31. ise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS MAIN PWM CONTROLLER VIN Input Voltage Range VDD AVDD Output Adjust Range FB OUT FB GND FB Vpp Soft Start Ramp Time tss Rising edge of SHDNA to full current limit TON GND 600kHz xe ex Mart y TON REF 450kHz TON OPEN 300kHz Note 3 TON AVpp 200kHz Output Voltage Accuracy Note 2 Minimum Off Time toFF MIN Note 3 ViN Quiescent Supply Current ViN Shutdown Supply Current SHDNA SHDNB GND All on PWM VTT and on A GND only VTT and VTTR on AVpp only VTTR and PWM on SHDNB GND only PWM on AVpp Quiescent Supply Current AVpp Vpp Shutdown Supply Current AVpp Undervoltage Lockout Rising edge of Threshold Hysteresis Vpp Quiescent Supply Current Set 0 8V SHDNA SHDNB GND 2 AVLAXL VI Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards ELECTRICAL CHARACTERISTICS continued VIN 15V Vpp AVpp VSHDNA VSHDNB VBST 5V VREFIN 2 5V UVP OVP STBY FB SKIP GND PGND1 PGND2 LX GND TON OPEN VWrrs Wrr TA 40 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX REFERENCE Reference Voltage VREF AVpp 4 5V to 5 5V Ingr 0 1 98 2 02
32. ity filter capacitors such as ceramic capacitors size is usually determined by the capacity needed to prevent VsAG and Vsoar from causing problems during load transients Generally once enough capacitance is added to meet the over shoot requirement undershoot at the rising load edge is no longer a problem see the VsAG and VSOAR equa tions in the Transient Response section However low capacity filter capacitors typically have high ESR zeros that can affect the overall stability see the Stability Requirements section Stability Requirements For Quick PWM controllers stability is determined by the value of the ESR zero relative to the switching fre quency The boundary of instability is given by the fol lowing equation f S where f FSR Pm x Resa Cour If CouT consists of multiple same value capacitors as in the Typical Applications Circuit of Figure 8 the fEsR remains the same as that of a single capacitor For a typical 600kHz application the ESR zero frequen cy must be well below 190kHz preferably below 100kHz Two 150uF 4V Sanyo POS capacitors are used to provide 12mQ max of Resp This results in a zero at 42kHz well within the bounds of stability Do not put high value ceramic capacitors directly across the feedback sense point without taking precau tions to ensure stability Large ceramic capacitors can have a high ESR zero freq
33. k regu lator s output Soft start in the LDO section can be realized by con necting a capacitor between the SS pin and ground When SHDNB is driven low or during thermal shut down of the LDOs the SS capacitor is discharged When SHDNB is driven high or when the thermal limit is removed an internal 4 typ current charges the SS capacitor The resulting ramp voltage on SS linearly increases the current limit comparator thresholds to both the VTT and VTTR outputs until full current limit is 15 LSS8XVW OSS8XVIN MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards attained when SS reaches approximately 1 6V This lowering of the current limit during startup limits the ini tial inrush current peaks particularly when driving capacitors Choose the value of the SS cap appropri ately to set the soft start time window Leave SS floating to disable the soft start feature Power OK POK1 POK1 is an open drain output for a window comparator that continuously monitors VouT POK1 is actively held low when SHDNA is low and during the buck regulator outputs soft start After the digital soft start terminates POK1 becomes high impedance as long as the output voltage is within 10 of the nominal regulation voltage set by FB When Vour drops 10 below or rises 10 above the nominal regulation voltage the MAX8550 MAX8551 pull POK1 low Any fault condition forces POK1 low until the fault
34. latch is cleared by toggling SHDNA or cycling AVpp power below 1 For logic level output voltages connect an external pullup resistor between POK1 and AVpp A 100kQ resistor works well in most applications Note that the POK1 window detec tor is completely independent of the overvoltage and undervoltage protection fault detectors and the state of VITS and VTTR SHDNA and Output Discharge The SHDNA input corresponds to the buck regulator and places the buck regulator s portion of the IC in a low power mode see the Electrical Characteristics table SHDNA is also used to reset a fault signal such as an overvoltage or undervoltage fault When output discharge is enabled OVP UVP AVpp or open SHDNA and SHDNB are pulled low or if UVP is enabled OVP UVP AVpp and Vour falls to 70 of its regulation set point the MAX8550 dis charges the buck regulator output through the OUT input through an internal 100 switch to ground While the output is discharging DL is forced low and the PWM controller is disabled but the reference remains active to provide an accurate threshold Once the out put voltage drops below 0 3V the MAX8550 shuts down the reference and pulls DL high effectively clamping the buck output and LX to ground When output discharge is disabled OVP UVP REF or GND the controller does not actively discharge the buck output and the DL driver remains low Under these conditions the buck output disch
35. le to the high side MOSFET drain and the low side MOSFET source Position the MOSFETs so the impedance between the input capacitor termi nals and the MOSFETS is as low as possible Special Layout Considerations for LDO Section The capacitor or capacitors at VTT should be placed as close to VIT and PGND2 pins 12 and 11 as possi ble to minimize the series resistance inductance of the trace The PGND2 side of the capacitor must be short with a low impedance path to the exposed pad under neath the IC The exposed pad must be star connected to GND pin 24 PGND1 pin 23 and PGND2 pin 11 A narrower trace can be used to connect the output voltage on the VTT side of the capacitor back to VITS pin 9 However keep this trace well away from poten tially noisy signals such as PGND1 or PGND2 This prevents noise from being injected into the error ampli fier s input For best performance the VTTI bypass capacitor must be placed as close to VTTI pin 13 as possible REFIN pin 14 should be separately routed with a clean trace and adequately bypassed to GND Refer to the MAX8550 evaluation kit data sheet for PC board guidelines MAKIN Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards Typical Operating Circuit VIT 09V 125V 15A 7 5V BIAS SUPPLY MAXIM MAXB5EO L 0 9V 1 25V 10mA 55 Vin 4 5V TO 28V OVP UVP 11
36. logic level N channel MOSFETs as the circuit switch elements The key selection parameters On resistance RDS ON the lower the better Maximum drain to source voltage Vpss should be at least 20 higher than input supply rail at the high side MOSFET s drain Gate charges Qc the lower the better Choose MOSFETs with rated Rps ON at Vas 4 5V For a good compromise between efficiency and cost choose the high side MOSFET that has a conduction loss equal to its switching loss at nominal input voltage and maximum output current see below For the low side MOSFET make sure that it does not spuriously turn on because of dV dt caused by the high side MOSFET turning on as this results in shoot through current degrading efficiency MOSFETs with a lower to ratio have higher immunity to dV dt For proper thermal management design calculate the power dissipation at the desired maximum operating junction temperature maximum output current and worst case input voltage For the low side MOSFET the worst case is at VIN MAX For the high side MOSFET the worst case could be at either VIN MIN VIN MAX The high side MOSFET and low side MOSFET have dif ferent loss components due to the circuit operation The low side MOSFET operates as a zero voltage switch therefore major losses are The channel conduction loss PLSCC The body diode conduction loss lt The gat
37. n cap can therefore be smaller and its ESR larger than what is required for its larger counter part For typical applications requiring load current up to 20mA a ceramic cap with a minimum value of 1uF is recommended REsR lt 0 30 Connect this between VTTR and the analog ground plane VTTI Input Capacitor Selection LDO Both the VTT and VTTR output stages are powered from the same VTTI input Their output voltages are ref erenced to the same REFIN input The value of the VTTI bypass capacitor is chosen to limit the amount of rip ple noise at VTTI or the amount of voltage dip during a load transient Typically VTTI is connected to the output of the buck regulator which already has a large bulk capacitor Nevertheless a ceramic capacitor of at least 10uF must be used and must be added and placed as close as possible to the VTTI pin This value must be increased with larger load current or if the trace from the VTTI pin to the power source is long and has signifi cant impedance Furthermore to prevent undesirable VTTI bounce from coupling back to the REFIN input and possibly causing instability in the loop the REFIN pin should ideally tap its signal from a separate low impedance DC source rather than directly from the VTTI input If the latter is unavoidable increase the amount of bypass capacitance at the VTTI input and add additional bypass at the REFIN pin MOSFET Selection Buck The MAX8550 MAX8551 drive external
38. nd VTTR Capability VTT has 3A Sourcing Sinking Capability VTT and VTTR Outputs Track VnEFIN 2 All Ceramic Output Capacitor Designs 1 0V to 2 8V Input Voltage Range Power Good Window Comparator Ordering Information TEMP RANGE 40 C to 85 C MAX8550ETI 40 C to 85 C 8551 40 C to 85 C Denotes lead free package PART 8550 PIN PACKAGE 28 5mm x 5mm TQFN 28 5mm x 5mm TQFN 28 5mm x 5mm TQFN Pin Configuration TOP VIEW TON 15 OvP UVP N C FOR 21 MAX8551 gr 37 f4 51 Poe 6 r or 10 10 5mm x 5mm Thin QFN Typical Operating Circuit appears at end of data sheet Quick PWM is a trademark of Maxim Integrated Products Inc Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com LG68XVNW 0SS8XV I MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards ABSOLUTE MAXIMUM RATINGS VIN to GND 0 3V to 30V VETS to 0 3V to AVpp 0 3V Vpp AVpp VITI to 2 22 000 0 3V to 6V PGND1 PGND2 to GND 0 3V to 0 3V SHDNA SHDNB REFIN to GND 0 3V to 6V REF Sho
39. ng DL high can cause the output voltage to go slightly negative due to energy stored in the output LC circuit at the instant the OVP occurs If the load can not tolerate a negative voltage place a power Schottky diode across the output to act as a reverse polarity clamp Toggle SHDNA or cycle AVpp below 1V to clear Table 3 OVP UVP Fault Protection the fault latch and restart the controller OVP is dis abled when OVP UVP is connected to REF or GND see Table 3 OVP only applies to the buck output The VIT and VTTR outputs do not have overvoltage protection Undervoltage Protection UVP When the output voltage drops below 70 of its regula tion voltage while UVP is enabled the controller sets the fault latch and begins the discharge mode see the Shutdown and Output Discharge section When the output voltage drops to 0 3V the synchronous rectifier Q2 in the Typical Applications Circuit turns on and clamps the buck output to GND UVP is ignored for at least 10ms min after startup or after a rising edge on SHDNA Toggle SHDNA or cycle AVpp power below 1V to clear the fault latch and restart the controller UVP is disabled when OVP UVP is left open or connected to GND see Table 3 UVP only applies to the buck out put The VIT outputs do not have undervolt age protection Thermal Fault Protection The MAX8550 MAX8551 feature two thermal fault pro tection circuits One monitors the buck regulator por ti
40. of the high side MOSFET and CBoosr is the boost capacitor 24 value where Cpoosr is C7 in the Typical Applications Circuit Figure 8 Transient Response Buck The inductor ripple current also affects transient response performance especially at low Vin VouT dif ferentials Low inductor values allow the inductor current to slew faster replenishing charge removed from the output filter capacitors by a sudden load step MAKII Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards The output sag is also a function of the maximum duty factor which can be calculated from the on time and minimum off time Vour x K L Vin de torr Vn Vout 2CouT vour teu tOFF MIN where tOFF MIN is the minimum off time see the Electrical Characteristics and is from Table 1 The overshoot during a full load to no load transient due to stored inductor energy can be calculated as 2 AlioapMAx L 2xCour VSOAR Applications Information Dropout Performance Buck The output voltage adjustable range for continuous conduction operation is restricted by the nonadjustable minimum off time one shot For best dropout perfor mance use the slower 200kHz on time setting When working with low input voltages the duty factor limit must be calculated using worst case values for on and off times Manufacturing tolerances and internal propa gation delay
41. ol Logic BUCK OUTPUT 16 AVLAZXL VI Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards Current Limit LDO for VTT and VTTR Buffer The VTT output is a linear regulator that regulates the input VTTI to half the VREFIN voltage The feedback point for VIT is at the VTTS input Figure 1 VIT is capable of sinking and sourcing at least 1 5A of continu ous current and 3A peak current The current limit for VTT and VTTR is typically 5 and 40mA respective ly When the current limit for either output is reached the outputs regulate the current not the voltage Fault Protection The MAX8550 MAX8551 provide overvoltage undervolt age fault protection in the buck controller Select OVP UVP to enable and disable fault protection as shown in Table 3 Once activated the controller contin uously monitors the output for undervoltage and over voltage fault conditions Overvoltage Protection OVP When the output voltage rises above 116 of the nomi nal regulation voltage MAX8550 only and OVP is enabled OVP UVP AVpp or open the OVP circuit sets the fault latch shuts down the PWM controller and immediately pulls DH low and forces DL high This turns on the synchronous rectifier MOSFET Q2 in the Typical Applications Circuit of Figure 8 with a 10096 duty cycle rapidly discharging the output capacitor and clamping the output to ground Note that immedi ately latchi
42. on of the IC and the other monitors the linear regulator VTT and the reference buffer output VTTR When the junction temperature of the buck regulator portion of the MAX8550 MAX8551 rises above 160 C a thermal sensor activates the fault latch pulls POK1 low and shuts down the buck controller output using discharge mode regardless of the OVP UVP setting Toggle SHDNA or cycle AVpp below 1V to reactivate the con troller after the junction temperature cools by 15 C If the VIT and VTTR regulator portion of the IC has its die temperature rise above 160 C then VTT and VITR OVP UVP DISCHARGE Yes DL forced high when SHDNA and SHDNB are low Yes DL forced high when SHDNA and SHDNB are low No DL forced low when SHDNA is low UVP PROTECTION Enabled Discharge sequence activated DL forced high when shut down Disabled Enabled Discharge sequence activated DL forced high when shut down OVP PROTECTION Enabled DH pulled low and DL forced high Enabled DH pulled low and DL forced high Disabled DL forced low when SHDNA is low Disabled Disabled 17 LSS8XVW OSS8XVIN MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards shut off go high impedance and restart after the die portion of the IC cools by 15 C Both thermal faults are independent For example if the VTT output is over loaded to t
43. output This helps minimize power dissi pation during a short circuit condition The current limit in the LDO and buffered reference out put buffer is 5A and 40mA respectively and neither have the over or undervoltage protection When the current limit in either output is reached the output no longer regulates the voltage but regulates the current to the value of the current limit 45V Bias Supply VDD and AVDD The MAX8550 MAX8551 require an external 5V bias supply in addition to the input voltage ViN Keeping the bias supply external to the IC improves the efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and the gate drivers If stand alone capabili ty is needed then the 5V supply can be generated with an external linear regulator such as the MAX1615 Vpp and IN can be connected together if the input source is a fixed 4 5V to 5 5V supply 12 Vpp is the supply input for the buck regulators MOSFET drivers and AVpp supplies the power for the rest of the IC The current from the AVpp and Vpp power supply must supply the current for the IC and the gate drive for the MOSFETs This maximum current can be estimated as Bias lavbp faw X Qa1 where lypp are the quiescent supply currents into Vpp and AVpp QG1 and Qa are the total gate charges of MOSFETs Q1 and Q2 at Vas 5V in the Typical Applic
44. pensation Note 3 On time and off time specifications are measured from 50 point to 50 point at the DH pin with LX GND VBsr 5V and a 250pF capacitor connected from DH to LX Actual in circuit times may differ due to MOSFET switching speeds Note 4 Not applicable to the MAX8551 MAXIM 77777777 0 5 LSS8XVW 0OSS8XVIN MAX8550 MAX8551 Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards Typical Operating Characteristics 12V VouT 2 5V TON GND SKIP AVpp circuit of Figure 8 TA 25 C unless otherwise noted TON GND 700 650 E 600 550 4 2 lt 500 1 450 H 5 5 400 350 1 250 4 200 1 SKIP GND 150 KIP GND 100 SKIP GND T T T SKP AVpp SKIP AVpp 50 SKP AVpp 0 0 01 0 1 10 100 0 2345 67 8 9 10 11 12 lLoAp A LoaD A SWMTCHNGFREGUENCY vs TEMPERATURE OUTPUT VOLTAGE TON GND vs LOAD CURRENT 700 8 2 540 E 690 i 2 535 Vin 15V i TON GND 8 680 2 530 H 1 F F 670
45. r Desktops Notebooks and Graphic Cards Pin Description continued FUNCTION Power Ground for VTT Connect PGND2 externally to the underside of the exposed pad Termination Power Supply Output Connect VTT to VTTS to regulate to VREFIN 2 Power Supply Input Voltage for VTT and VTTR Normally connected to the output of the buck regulator for DDR application External Reference Input This is used to regulate the and VTTR outputs to VREFIN 2 Feedback Input for Buck Output Connect to AVpp for a 1 8V fixed output or to GND for a 2 5V fixed output For an adjustable output 0 7V to 5 5V connect FB to a resistive divider from the output voltage FB regulates to 0 7V Output Voltage Sense Connection Connect to the positive terminal of the buck output filter capacitor OUT senses the output voltage to determine the on time for the high side switching MOSFET Q1 in the Typical Applications Circuit OUT also serves as the buck output s feedback input in fixed output modes When discharge mode is enabled by OVP UVP the output capacitor is discharged through an internal 10Q resistor connected between OUT and GND Input Voltage Sense Connection Connect to input power source VIN is used only to set the PWM s on time one shot timer IN voltage range is from 2V to 28V High Side Gate Driver Output Swings from LX to BST DH is low when in shutdown or UVLO External Inductor Connection Connect
46. rcuit with automatic recovery after the over load or short circuit is removed To implement foldback current limit connect a resistor from Vour to ILIM R6 in Figure 7 and the Typical Applications Circuit in addition to the resistor divider network R4 and R5 used for setting the adjustable current limit as shown in Figure 7 The following is a procedure for calculating the value of R4 R5 and R6 1 Calculate the voltage VILIM NOM required at ILIM when the output voltage is at nominal LIR MuiM NoM 10 lLoAD MAX X lt gt 2 Pick a percentage of foldback PFB from 15 to 40 3 Calculate the voltage ViLim ov when the output is shorted 0 REF MAXIM MAX8550 551 Figure 7 Foldback Current Limit MAXIM PFB X 4 The value for R4 can be calculated as 2V MiIM OV R4 5 The parallel combination of R5 and R6 denoted R56 is calculated as 122 6 Then R6 be calculated as R6 Vout R4 x R56 Muwov x R4 iLiwov R56 7 Then R5 is calculated as _R6 x R56 5 R6 R56 Boost Supply Diode and Capacitor Selection Buck A low current Schottky diode such as the CMDSH 3 from Central Semiconductor works well for most appli cations Do not use large power diodes because high er junction capacitance can charge up the
47. regulation point or during soft start POK1 is high impedance when the output is in regulation and the soft start circuit has terminated POK1 is low in shutdown LDO Power Good Open Drain Output In normal mode POK2 is low when either VTTR or VTTS is more than 10 above or below the normal regulation point which is typically REFIN 2 In standby mode POK2 responds only to the VTTR input POK2 is low in shutdown and when VngrIN is less than 0 8 Standby Connect to high for low quiescent mode where the output is disabled but the buffer is kept alive if SHDNB is high POK2 takes input from only VTTR in this mode PWM output can be on or off depending on the state of SHDNA Soft Start Control for VTT and Connect a capacitor C9 in the Typical Applications Circuit from SS to ground see the Soft Start Capacitor Selection section Leave SS open to disable soft start SS discharges to ground when SHDNB is low See the POR UVLO and Soft Start section Sensing Pin for Termination Supply Output Normally connected to VTT pin to allow accurate regulation to half the REFIN voltage Connected to a resistive divider from VTT to GND to regulate VTT to higher than half the REFIN voltage Termination Reference Voltage VTTR tracks VREFIN 2 The MAX8551 has no OVP or discharge mode feature Only UVP is available LSS8XVW 0OSS8XVIN MAX8550 MAX8551 Integrated DDR Power Supply Solutions fo
48. reset POR occurs when AVpp rises above approximately 2V resetting the fault latch and the soft start counter powering up the reference and preparing the buck regulator for operation Until AVDD reaches 4 25V typ AVpp undervoltage lockout UVLO circuitry inhibits switching The controller inhibits switching by pulling DH low and holding DL low when OVP and shutdown discharge are disabled MAKIM OVP UVP REF or GND or forcing DL high when OVP and shutdown discharge are enabled OVP UVP AVpp or OPEN See Table 3 for a detailed truth table for OVP UVP and shutdown settings When AVpp rises above 4 25V the controller activates the buck regulator and initializes the internal soft start The buck regulator s internal soft start allows a gradual increase of the current limit level during startup to reduce the input surge currents The MAX8550 MAX8551 divide the soft start period into five phases During the first phase the controller limits the current limit to only 2096 of the full current limit If the output does not reach regulation within 425us soft start enters the second phase and the current limit is increased by another 20 This process repeats until the maximum current limit is reached after 1 7ms or when the output reaches the nominal regulation voltage whichever occurs first Adding a capacitor in parallel with the external ILIM resistors creates a continuously adjustable analog soft start function for the buc
49. rt Circuit to GND Continuous SS POK1 POK2 SKIP ILIM FB to GND 0 3V to 6V Continuous Power Dissipation TA 70 C STBY TON REF UVP OVP to GND 0 3V to AVpp 0 3V 28 Pin 5mm x 5mm TQFN derate 35 7mW C OUT VTTR to GND 0 3V to AVpp 0 3V E7096 ae dint tea eene 2 86W DLE to PGND31 3 iet 0 3V to Vpp 0 3V Operating Temperature Range 40 C to 85 C DEMO EX iiiter 0 3V to VBsT 0 3V Junction 4 0 0000 150 C LX to BST 6V to 0 3V Storage Temperature Range 65 C to 165 C EX to GND irises RR 2V to 30V Lead Temperature soldering 105 300 C VTT to GND eee 0 3V to Vyrri 0 3V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS 15V Vpp AVpp VSHDNA VSHDNB VBST 5V VouT VREFIN Vvrri 2 5V UVP OVP STBY FB SKIP GND PGND1 PGND2 LX GND TON OPEN VWrrs Wrr TA 40 C to 85 C unless otherw
50. s introduce an error to the TON K factor This error is greater at higher frequencies see Table 1 Also keep in mind that transient response perfor mance of buck regulators operated too close to dropout is poor and bulk output capacitance must often be added see the equation in the Design Procedure section The absolute point of dropout is when the inductor cur rent ramps down during the minimum off time AIDOWN as much as it ramps up during the on time Alup ratio h AlUP AIDOWN indicates the controller s ability to slew the inductor current higher in response to increased load and must always be greater than 1 As h approaches 1 the absolute minimum dropout point the inductor current cannot increase as much during each switching cycle and VsaG greatly increases unless additional output capacitance is used A reasonable minimum value for h is 1 5 but adjusting this up or down allows trade offs between VsAG output capacitance and minimum operating voltage For a given value of h the minimum operating voltage can be calculated as Gaines Vour m X tOFF MIN VpRoP2 VbROPI K where VpROP1 and Vpnore are the parasitic voltage drops in the discharge and charge paths see the On Time One Shot TON section toFF MIN is from the Electrical Characteristics and K is taken from Table 1 The absolute minimum input voltage is calculated with hs 1 If the calculated
51. serve the ringing frequency fR 2 Estimate the circuit parasitic capacitance CPAn at LX by first finding a capacitor value which when connected from LX to PGND1 reduces the ringing frequency by half CPAR can then be calculated as 1 8rd the value of the capacitor value found 22 3 Estimate the circuit parasitic capacitance from the equation 1 LPAR 5 21 xfg x CpAR 4 Calculate the resistor for critical dampening RSNUB from the equation RSNUB 2 fR x LPAR Adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion 5 The capacitor CSNUB should be at least 2 to 4 times the value of Cpar to be effective The power loss of the snubber circuit PRSNUB is dissi pated in the resistor and can be calculated as 2 PRsNUB CsnuB X MN fsw where VIN is the input voltage and fsw is the switching frequency Choose an RsNuB power rating that meets the specific application s derating rule for the power dissipation calculated Setting the Current Limit Buck The current sense method used in the MAX8550 MAX8551 makes use of the on resistance RDS ON of the low side MOSFET Q2 in the Typical Applications Circuit When calculating the current limit use the worst case maximum value for RDS ON from the MOSFET data sheet and add some margin for the rise in RDS ON with temperature A good general rule is to allow 0 5 addi tional resistance for each 1
52. the allotted dimensions Ferrite cores are often the best choice although powdered iron is inexpensive and can work well at frequencies up to 200kHz The core must be large enough not to satu rate at the peak inductor current IPEAK LIR ILoAD MAX 1 os Most inductor manufacturers provide inductors in stan dard values such as 1 0uH 1 5uH 2 2uH 3 3pH etc MAKIM Also look for nonstandard values which can provide a better compromise in LIR across the input voltage range If using a swinging inductor where the no load induc tance decreases linearly with increasing current evalu ate the LIR with properly scaled inductance values Input Capacitor Selection Buck The input capacitor must meet the ripple current requirement IRMS imposed by the switching currents Vour Vin Vour MN IRMs loAD IRMS has a maximum value of ILOAD 2 when VN 2 For most applications nontantalum capacitors ceramic aluminum POS or OSCON are preferred due to their resistance to power up surge currents typi cal of systems with a mechanical switch or connector in series with the input If the MAX8550 MAX8551 are operated as the second stage of a two stage power conversion system tantalum input capacitors are acceptable In either configuration choose a capacitor that has less than 10 C temperature rise at the RMS input current for optimal reliability and lifetime Output Capacitor Selection Buck Th
53. thin 1 of VREFIN 2 The high bandwidth of this LDO regulator allows excel lent transient response without the need for bulk capac itors thus reducing cost and size The buck controller and LDO regulators are provided with independent current limits Adjustable lossless foldback current limit for the buck regulator is achieved by monitor ing the drain to source voltage drop of the low side MOS FET Additionally overvoltage and undervoltage protection mechanisms are built in Once the overcurrent condition is removed the regulator is allowed to enter soft start again This helps minimize power dissipation during a short circuit condition The MAX8550 MAX8551 allow flexible sequencing and standby power manage ment using the SHDNA SHDNB and STBY inputs Both the MAX8550 and MAX8551 are available in a small 5mm x 5mm 28 pin thin QFN package Applications DDR I and DDR Il Memory Power Supplies Desktop Computers Notebooks and Desknotes Graphic Cards Game Consoles RAID Networking MAXIM Features Buck Controller Quick PWM with 100ns Load Step Response Up to 95 Efficiency 2V to 28V Input Voltage Range 1 8V 2 5V Fixed or 0 7V to 5 5V Adjustable Output Up to 600kHz Selectable Switching Frequency Programmable Current Limit with Foldback Capability 1 7ms Digital Soft Start and Independent Shutdown Overvoltage Undervoltage Protection Option Power Good Window Comparator LDO Section Fully Integrated VTT a
54. uency and cause erratic unstable operation However it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point which should be as close as possible to the inductor Unstable operation manifests itself in two related but distinctly different ways double pulsing and fast feed back loop instability Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage 20 signal This fools the error comparator into triggering a new cycle immediately after the 400ns minimum off time period has expired Double pulsing is more annoying than harmful result ing in nothing worse than increased output ripple However it can indicate the possible presence of loop instability due to insufficient ESR Loop instability can result in oscillations at the output after line or load steps Such perturbations are usually damped but can cause the output voltage to rise above or fall below the tolerance limits The easiest method for checking stabil ity is to apply a very fast zero to max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing It can help to simultaneously monitor the inductor current with an AC current probe Do not allow more than one cycle of ringing after the initial step response under overshoot VTT Output Capacitor Selection LDO A minimum value
55. ults in a nearly constant switching frequency despite the lack of a fixed frequency clock generator The benefits of a constant switching frequency are twofold 1 The frequency can be selected to avoid noise sensi tive regions such as the 455kHz IF band MAALM Integrated DDR Power Supply Solutions for Desktops Notebooks and Graphic Cards 2 The inductor ripple current operating point remains relatively constant resulting in an easy design methodology and predictable output voltage ripple The on time one shot has good accuracy at the operat ing points specified in the Electrical Characteristics table approximately 12 5 at 600kHz and 450kHz and 10 at 200kHz and 300kHz On times at operat ing points far removed from the conditions specified in the Electrical Characteristics table can vary over a wider range For example the 600kHz setting typically runs approximately 1096 slower with inputs much greater than 5V due to the very short on times required The constant on time translates only roughly to a con stant switching frequency The on times guaranteed in the Electrical Characteristics table are influenced by resistive losses and by switching delays in the high side MOSFET Resistive losses which include the inductor both MOSFETs the output capacitor s ESR and any PC board copper losses in the output and ground tend to raise the switching frequency as the load increases The dead time effect increases the effecti
56. ve on time reducing the switching frequency as one or both dead times are added to the effective on time The dead time occurs only in PWM mode SKIP and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents With reversed inductor current the induc tors EMF causes LX to go high earlier than normal extending the on time by a period equal to the DH rising dead time For loads above the critical conduction point where the dead time effect is no longer a factor the actual switching frequency is Vout VoRoPt toN MN VoRoP2 few where VpRoP1 is the sum of the parasitic voltage drops in the inductor discharge path including the synchro nous rectifier the inductor and any PC board resis tances is the sum of the resistances in the charging path including the high side switch Q1 in the Typical Applications Circuit the inductor and any PC board resistances and toN is the one shot on time see the On Time One Shot TON section Automatic Pulse Skipping Mode SKIP GND In skip mode SKIP GND an inherent automatic switchover to PFM takes place at light loads Figure 2 This switchover is affected by a comparator that trun cates the low side switch on time at the inductor cur rent s zero crossing The zero crossing comparator MAKIM differentially senses the inductor current across the synchronous rectifier MOSFET Q2 in the
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MAXIM MAX8550/MAX8551 handbook