MAXIM MAX1226/MAX1228/MAX1230 handbook
Contents
1. SELO 7 MSB 6 Set to 1 to select setup register CKSEL1 Clock mode and CNVST configuration Resets to 1 at power up CK Set to zero to select setup register Clock mode and CNVST configuration REFSEL1 Reference mode configuration REFSELO 5 4 3 2 Reference mode configuration DIFFSEL1 CKSEL1 1 CKSELO Unipolar bipolar mode register configuration for differential mode CONVERSION CLOCK Internal ACQUISITION SAMPLING Internally timed DIFFSELO O LSB Unipolar bipolar mode register configuration for differential mode See below for bit details CNVST CONFIGURATION CNVST Internal Externally timed through CNVST CNVST Internal Internally timed AIN15 11 7 MAX 1 226 MAX 1228 MAX1230 REFSELO External 4 8MHz max VOLTAGE REFERENCE Internal Externally timed through SCLK AutoShutdown Reference off after scan need wake up delay AIN15 11 7 REF CONFIGURATION AIN14 10 6 External single ended Reference off no wake up delay AIN14 10 6 DIFFSEL1 DIFFSELO Internal External differential Reference always on no wake up delay Reference off no wake up delay FUNCTION AIN14 10 6 No data follows the setup byte Unipolar mode and bipolar mode registers remain unchanged No data follows the setup byte Unipolar mode and bipolar mode registers remain unchanged One byte of d2. 1350 Shutdown During temp sense fSAMPLE 300ksps 0 2 1650 1250 5 2300 1500 Shutdown 0 2 5 Power Supply Rejection Note 1 Tested at Vpp 5V unipolar input mode Note 2 Offset nulled Vpp 4 75V to 5 25V full scale input Note 3 Time for reference to power up and settle to within 1 LSB Note 4 Conversion time is defined as the number of clock cycles multiplied by the clock period clock has 50 duty cycle Note 5 The operational input voltage range for each individual input of a differentially configured pair is from GND to Vpp The operational input voltage difference is from VREF 2 to VREF 2 Note 6 See Figure 3 Input Equivalent Circuit and the Sampling Error vs Source Impedance curve in the Typical Operating Characterisitcs section Note 7 Fast automated test excludes self heating effects Note 8 Supply current is specified depending on whether an internal or external reference is used for voltage conversions Temperature measurements always use the internal reference 0 2 1 2 MAXIM 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference TIMING CHARACTERISTICS Figure 1 PARAMETER SYMBOL CONDITIONS Externally clocked conversion Data I O SCLK Clock Period SCLK Duty Cycle SCLK Fall to DOUT Transition CLOAD 30pF CS Rise to DOUT Disable CLOAD 30pF CS Fall to DOUT Enable CLoabD 30pF DIN to SCLK Rise Setup
3. DIN data is latched into the serial interface on the rising edge of SCLK Serial Data Output Data is clocked out on the falling edge of SCLK High impedance when CS is connected to Vpp End of Conversion Output Data is valid after EOC pulls low MAXIM 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference SERIAL INTERFACE E OSCILLATOR CONTROL FIFO AND ACCUMULATOR MAXIM MAX1226 MAX1228 MAX1230 Figure 2 Functional Diagram Detailed Description The MAX1226 MAX1228 MAX1230 are low power seri al output multichannel ADCs with temperature sensing capability for temperature control process control and monitoring applications These 12 bit ADCs have inter nal track and hold T H circuitry that supports single ended and fully differential inputs Data is converted from an internal temperature sensor or analog voltage sources in a variety of channel and data acquisition MAXIM INTERNAL REFERENCE configurations Microprocessor uP control is made easy through a 3 wire SPI QSPI MICROWIRE compati ble serial interface Figure 2 shows a simplified functional diagram of the MAX1226 MAX1228 MAX1230 internal architecture The MAX1226 has eight single ended analog input channels or four differential channels The MAX1228 has 12 single ended analog input channels or six differ en
4. For the latest package outline information go to www maxim ic com packages 32L QFN EPS OEZ LX VIN 82C LGS LX A Jammen i D2 02 2 SEE DETAIL A Ne 1 Xe REF Ar T Cr SCALE NONE TERMINAL TIP IDRALLAS AVLAXL VI FOR ODD TERMINAL SIDE mme PACKAGE OUTLINE 16 20 28 32L QFN 5x5x0 90 MM CONTROL NO 21 0091 Mpe MAXIM 23 MAX 1 226 MAX 1228 MAX1230 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference Package Information continued The package drawing s in this data sheet may not reflect the most current specifications For the latest package outline information go to www maxim ic com packages COMMON DIMENSIONS PKG es 20L 5x5 28L 5x5 ease EXPOSED PAD VARIATIONS ECH ee LPL 475esc_ 4758sc_ 475esc_ mee e osoesc oe _osoesc Loose Lk Last ozs Iesst Last o 3s oss 075 035 055 0 75 0 35 0 55 0 75 0 30 0 40 0 50 n EE o ee ees ee ee ee eee no La Le LI Le k EE Se E eee E EEN EES KEE LE ooo 0 42 0 60 0 00 0 42 oso 0 00 0 42 060 0 00 0 42 0 60 fe lol ele elei pet of z DIE THICKNESS ALLOWABLE IS 0 305mm MAXIMUM 012 INCHES MAXIMUM 2 DIMENSIONING amp TOLERANCES CONFORM TO ASME Y14 5M 1994 3 N IS THE NUMBER OF TERMINALS Nd IS THE NUMBER OF TERMINALS IN X DIRECTION amp Ne IS THE NUMBER OF TERMINALS IN Y DIRECTION AX DIMENSION b APPLIES TO PLATED TERMINAL
5. s complement in bipolar mode See the transfer function graphs Figures 8 and 9 In single ended mode the MAX1226 MAX1228 MAX1230 always operate in unipolar mode The analog inputs are internally referenced to GND with a full scale input range from O to VREF True Differential Analog Input T H The equivalent circuit of Figure 3 shows the MAX1226 MAX1228 MAX1230s input architecture In track mode a positive input capacitor is connected to AINO AIN15 in single ended mode and AINO AIN2 AIN4 AIN14 in differential mode A negative input capacitor is connected to GND in single ended mode or AIN1 AIN3 AIN5 AIN15 in differential mode For external track and hold timing use clock mode 01 After the T H enters hold mode the difference between the sampled positive and negative input voltages is converted The time required for the T H to acquire an input signal is determined by how quickly its input capacitance is charged If the input signal s source impedance is high the required acquisition time length ens The acquisition time taca is the maximum time needed for a signal to be acquired plus the power up time It is calculated by the following equation taQc 9 x Rs Rin x 24pF tpwr MAXIM where RIN 1 5kQ Rs is the source impedance of the input signal and tpwrR 1us the power up time of the device The varying power up times are detailed in the explanation of the clock mode conversions taca
6. the pair is ignored BIT 3 BIT 2 BIT 1 BITO Conversion CHSEL3 CHSEL2 CHSEL1 CHSELO SCAN1 SCANO TEMP Setup 1 CKSEL1 CKSELO REFSEL1 REFSELO DIFFSEL1 DIFFSELO Averaging AVGON NAVG1 NAVGO NSCAN1 NSCANO Reset UCHO 1 BCHO 1 UCH2 3 BCH1 2 UCH4 5 BCH4 5 Unipolar mode setup Bipolar mode setup UCH6 7 BCH6 7 1 RESET X X X 8 9 UCH10 11 UCH12 13 UCH14 15 8 9 BCH10 11 BCH12 13 BCH14 15 Unipolar bipolar channels 8 15 are only valid on the MAX1228 and MAX 1230 Unipolar bipolar channels 12 15 are only valid on the MAX 1230 X Don t care 12 MAXIM 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference Table 2 Conversion Register BIT FUNCTION Set to 1 to select conversion register Analog input channel select 6 5 Analog input channel select 4 Analog input channel select Analog input channel select SCAN1 2 Scan mode select SCANO 1 Scan mode select Set to 1 to take a single temperature measurement The first conversion result of a scan contains temperature information TEMP 0 LSB See below for bit details SELECTED CHANNEL N NO CHSEL3 CHSEL2 CHSEL1 CHSELO ojo ojojojojojo i 10 0 0 O0 J O O lO O 8 0 1 1 0 0 1 1 0 0 1 1 0
7. 1226 MAX 1228 MAX1230 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference Package Information The package drawing s in this data sheet may not reflect the most current specifications For the latest package outline information go to www maxim ic com packages QSOP EPS S INCHES MILLIMETERS DIM MIN MAX MIN MAX A 061 068 155 173 I l I I A1 004 0098 0 102 0 249 A 055 061 1 40 155 B 008 012 0 20 0 30 H E RIATIONS 0 VARIATIONS INCHES MILLIMETERS MIN MAX MIN MAX N S 0020 0070 0 05 0 18 ita tas E S 0500 0550 1270 1 397 C D D 337 344 8 56 874 24 S 0250 0300 0 635 0 762 D 386 393 9 80 9 98 28 S 0250 _ 0300 0 635 0 762 NOTES 1 D amp E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS 2 MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 006 PER SIDE IBDALLAS al AIX L VI SEMICONDUCTOR 23 CONTROLLING DIMENSIONS INCHES PROPRIETARY INFORMATION 4 MEETS JEDEC M0137 TITLE PACKAGE OUTLINE QSOP 150 025 LEAD PITCH APPROVAL DOCUMENT CONTROL NO REV 21 0055 E KA 22 MAXIN 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference Package Information continued The package drawing s in this data sheet may not reflect the most current specifications
8. AND IS MEASURED BETWEEN 0 20 AND 0 25mm FROM TERMINAL TIP A THE PIN 1 IDENTIFIER MUST BE EXISTED ON THE TOP SURFACE OF THE PACKAGE BY USING INDENTATION MARK OR INK LASER MARKED DETAILS OF PIN 1 IDENTIFIER IS OPTIONAL BUT MUST BE LOCATED WITHIN ZONE INDICATED EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL ALL DIMENSIONS ARE IN MILLIMETERS PACKAGE WARPAGE MAX 0 05mm APPLIED FOR EXPOSED PAD AND TERMINALS EXCLUDE EMBEDDED PART OF EXPOSED PAD FROM MEASURING B DALLAS Ki MEETS JEDEC M0220 EXCEPT DIMENSION b SEMICONDUCTOR L VIAAI vl PROPRIETARY INFORMATION APPLIED FOR EXPOSED PAD AND TERMINALS EXCLUDE EMBEDDING PART OF EXPOSED PAD MME PACKAGE OUTLINE 16 20 28 32L QFN FROM MEASURING 5x5x0 90 MM Sie t THIS PACKAGE OUTLINE APPLIES TO ANVIL SINGULATION STEPPED SIDES TE SOON Ei xX S 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 24 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2003 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products
9. Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference MAX1230 MAX1230 MAX1228 MAX1226 Pin Description FUNCTION N C No Connection Not internally connected AINO 13 AINO 5 Analog Inputs Analog Inputs Analog Inputs REF AIN14 Negative Input for External Differential Reference Analog Input 14 See Table 3 for details on programming the setup register REF AIN10 Negative Input for External Differential Reference Analog Input 10 See Table 3 for details on programming the setup register Negative Input for External Differential Reference Analog Input 6 See Table 3 for details on programming the setup register Active Low Conversion Start Input Analog Input 15 See Table 3 for details on programming the setup register Active Low Conversion Start Input Analog Input 11 See Table 3 for details on programming the setup register Active Low Conversion Start Input Analog Input 7 See Table 3 for details on programming the setup register Positive Reference Input Bypass to GND with a 0 1uF capacitor Ground Power Input Bypass to GND with a 0 1uF capacitor Serial Clock Input Clocks data in and out of the serial interface Duty cycle must be 40 to 60 See Table 3 for details on programming the clock mode Active Low Chip Select Input When CS is low the serial interface is enabled When CS is high DOUT is high impedance Serial Data Input
10. DU 1 1 DH eek SCAN MODE CHANNEL N IS SCANQ SELECTED BY BITS CHSEL3 CHSEL0 Scans channels 0 through N Scans channels N through the highest numbered channel Scans channel N repeatedly The averaging register sets the number of results No scan Converts channel N once only MAXIM Select scan mode 00 or 01 to return one result per sin gle ended channel and one result per differential pair within the requested range plus one temperature result if selected Select scan mode 10 to scan a single input channel numerous times depending on NSCAN1 and NSCANO in the averaging register Table 6 Select scan mode 11 to return only one result from a single channel Setup Register Write a byte to the setup register to configure the clock reference and power down modes Table 3 details the bits in the setup register Bits 5 and 4 CKSEL1 and CKSELO control the clock mode acquisition and sam pling and the conversion start Bits 3 and 2 REFSEL1 and REFSELO control internal or external reference use Bits 1 and O DIFFSEL1 and DIFFSELO address the unipolar mode and bipolar mode registers and configure the analog input channels for differential operation Unipolar Bipolar Registers The final 2 bits LSBs of the setup register control the unipolar bipolar mode address registers Set bits 1 and O DIFFSEL1 and DIFFSELO to 10 to write to the unipo lar mode register Set bits 1 and O to 11 to
11. FIFO Temp Sensor Internal Reference CONVERSION BYTE TLLLLLLL1 ACQUISITION1 a lt i S souk PULLELELIDIP Lan CONVERSIONI _ ACQUISITION2 Onnnnnnn bg nnnnninan Hnnnnnnn EXTERNALLY TIMED ACQUISITION SAMPLING AND CONVERSION WITHOUT CNVST Figure 7 Clock Mode 11 Initiate a conversion by writing a byte to the conversion register followed by 16 SCLK cycles If CS is pulsed high between the eighth and ninth cycles the pulse width must be less than 100us To continuously con vert at 16 cycles per conversion alternate 1 byte of zeros between each conversion byte If reference mode 00 is requested or if an external ref erence is selected but a temperature measurement is being requested wait 65us with CS high after writing the conversion byte to extend the acquisition and allow the internal reference to power up To perform a tem perature measurement write 24 bytes 192 cycles of zeros after the conversion byte The temperature result appears on DOUT during the last 2 bytes of the 192 cycles Partial Reads and Partial Writes If the first byte of an entry in the FIFO is partially read CS is pulled high after fewer than eight SCLK cycles the second byte of data that is read out contains the next 8 bits not b7 b0 The remaining bits are lost for that entry If the first byte of an entry in the FIFO is read out fully but the second byte is read out partially the re
12. SCLK Rise to DIN Hold CS to SCLK Rise Setup SCLK Rise to CS Hold CKSEL 00 CKSEL 01 temp sense CKSEL 01 voltage conversion CNVST Pulse Width Temp sense CS or CNVST Rise to EOC Low Note 9 Voltage conversion Reference power up Note 9 This time is defined as the number of clock cycles needed for conversion multiplied by the clock period If the internal refer ence needs to be powered up the total time is additive The internal reference is always used for temperature measurements Typical Operating Characteristics Vpp 5V VREF 4 096V fscLk 4 8MHz CLoaD 30pF Ta 25 C unless otherwise noted INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY vs OUTPUT CODE vs OUTPUT CODE SINAD vs FREQUENCY 1 0 5 1 0 100 z 0 8 z 0 8 90 3 S ao S S 0 6 S 2 06 _ 80 S 04 2 E 04 S 70 z Z 0 2 3 S 60 z 5 S z 0 S 50 titi ot enn 2 02 z e 4 ZS T 04 SE 5 30 E oi Z 06 0 6 20 A 0 8 0 8 10 1 0 1 0 0 0 1024 2048 3072 4096 0 1024 2048 3072 4096 04 1 10 100 1000 OUTPUT CODE OUTPUT CODE FREQUENCY kHz MAXIM 5 OEZ LX VIN 827 LK XVN MAX 1226 MAX 1228 MAX1230 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference SFDR AMPLITUDE dB SFDR
13. reconstructed from digital samples signal to noise ratio SNR is the ratio of the full scale analog input RMS value to the RMS quanti zation error residual error The ideal theoretical mini mum analog to digital noise is caused by quantization error only and results directly from the ADC s resolution N bits SNR 6 02 x N 1 76 dB 20 PUT CODE FS ee Vcom ZS COM FS Ka Voom _ REF COM INPUT VOLTAGE LSB Voom 2 VREF 2 Figure 9 Bipolar Transfer Function Full Scale FS VREF 2 In reality there are other noise sources besides quanti zation noise including thermal noise reference noise clock jitter etc Therefore SNR is calculated by taking the ratio of the RMS signal to the RMS noise which includes all spectral components minus the fundamen tal the first five harmonics and the DC offset Signal to Noise Plus Distortion Signal to noise plus distortion SINAD is the ratio of the fundamental input frequency s RMS amplitude to the RMS equivalent of all other ADC output signals SINAD dB 20 x log SignalRms NoiseRms Effective Number of Bits Effective number of bits ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate An ideal ADC error consists of quantiza tion noise only With an input range equal to the full scale range of the ADC calculate the effective number of bits as follows ENOB SI
14. vs FREQUENCY Typical Operating Characteristics continued SUPPLY CURRENT vs SAMPLING RATE e 1200 r 1200 S 1000 3 S e 2 a150 E E Z 800 a DS BE Si 5 1100 600 a a oe D Kei Kei 1050 400 200 1000 01 0 100 000 1 10 100 000 FREQUENCY kHz SAMPLING RATE ksps SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE VDD 5V VREF 4 096V fscLK 4 8MHz CLOAD 30pF TA 25 C unless otherwise noted SUPPLY CURRENT vs SUPPLY VOLTAGE MAX1226 28 30 toc06 4 75 4 85 4 95 5 05 5 15 5 25 SUPP LY VOLTAGE V SUPPLY CURRENT vs TEMPERATURE MAX1226 28 30 toc08 TEMPERATURE C 40 15 10 35 60 8 5 INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE MAX1226 28 30 toc10 0 6 e 300 05 s 250 S CO L E 04 1200 o a z T 03 S 1150 B gt un 1100 a 3 5 ZG 01 050 0 000 Am 485 4985 505 515 523 SUPPLY VOLTAGE V SHUTDOWN SUPPLY CURRENT vs TEMPERATURE 0 6 z 4 0500 S g 2 3 05 g 40499 bs S 04 S 4 0498 Oo Lu z 2 T 03 D 4 0497 3 3 z 02 4 0496 EX a E 5 0 Z 40495 0 4 0494 40 Ap 10 35 60 85 TEMPERATURE C 4 75 4
15. 0 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference CNVST lt P 1 e et CONVERSION2 ACQUISITIONI ACQUISITION2 cs i a a S S e wm sic ae FULL nnn DOUT MSB1 LSB1 MSB2 E0G LI i REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION Figure 5 Clock Mode 01 lt CONVERSION BYTE gt lt lt UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS THE CONVERSION BYTE BEGINS THE ACQUISITION CNVST IS NOT REQUIRED Figure 6 Clock Mode 10 Initiate a scan by writing a byte to the conversion regis ter The MAX1226 MAX1228 MAX1230 then power up scan all requested channels store the results in the FIFO and shut down After the scan is complete EOC is pulled low and the results are available in the FIFO If a temperature measurement is requested the tempera ture result precedes all other FIFO results EOC stays low until CS is pulled low again 18 Externally Clocked Acquisitions and Conversions Using the Serial Interface Performing Conversions in Clock Mode 11 In clock mode 11 acquisitions and conversions are ini tiated by writing to the conversion register and are per formed one at a time using the SCLK as the conversion clock Scanning and averaging are disabled and the conversion result is available at DOUT during the con version See Figure 7 for clock mode 11 timing MAXIM 12 Bit 300ksps ADCs with
16. 26 MAX1228 MAX1230 feature a serial interface compatible with SPI QSPI and MICROWIRE devices For SPI QSPI ensure the CPU serial interface runs in master mode so it generates the serial clock signal Select the SCLK frequency of 10MHz or less and set clock polarity CPOL and phase CPHA in the uP control registers to the same value The MAX1226 MAX1228 MAX1230 operate with SCLK idling high or low and thus operate with CPOL CPHA 0 or CPOL CPHA 1 Set CS low to latch input data at DIN on the rising edge of SCLK Output data at DOUT is updated on the falling edge of SCLK Bipolar true dif ferential results and temperature sensor results are available in two s complement format while all others are in binary Serial communication always begins with an 8 bit input data byte MSB first loaded from DIN Use a second byte immediately following the setup byte to write to the unipolar mode or bipolar mode registers see Tables 1 3 4 and 5 A high to low transition on CS ini tiates the data input operation The input data byte and the subsequent data bytes are clocked from DIN into the serial interface on the rising edge of SCLK 10 Tables 1 7 detail the register descriptions Bits 5 and 4 CKSEL1 and CKSELO respectively control the clock modes in the setup register see Table 3 Choose between four different clock modes for various ways to start a conversion and determine whether the acquisi tions are internally or exte
17. 85 4 95 5 05 SUPPLY VOLTAGE V 515 5 25 MAKIM 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference Typical Operating Characteristics continued VDD 5V VREF 4 096V fscLK 4 8MHz CLOAD 30pF TA 25 C unless otherwise noted INTERNAL REFERENCE VOLTAGE OFFSET ERROR OFFSET ERROR vs TEMPERATURE vs SUPPLY VOLTAGE vs TEMPERATURE 4 051 z 0 3 a 0 3 2 SS J 0 2 0 2 S 4 050 Z 3 S S 5 5 4 049 S 0 0 SS i E 2 2 z ZS 0 1 ZS 01 E 4 048 a 0 2 0 2 4 047 0 3 0 3 40 Ap 10 35 60 85 Am 485 495 505 515 5 25 40 15 10 35 60 85 TEMPERATURE C SUPPLY VOLTAGE V TEMPERATURE C GAIN ERROR vs SUPPLY VOLTAGE GAIN ERROR vs TEMPERATURE 05 z 0 5 2 0 S 0 ao oO 8 E ai Pai Gs SA amp 0 5 05 Lu Lu z z Es ve Oo oO 1 0 1 0 1 5 1 5 Am 485 495 505 5145 5235 40 Ap 10 35 60 85 SUPPLY VOLTAGE V TEMPERATURE C TEMPERATURE SENSOR ERROR SAMPLING ERROR vs TEMPERATURE vs SOURCE IMPEDANCE 1 00 e 2 s _ 075 g 3 S g 0 S 050 z oO GRADE A i Z y 4 025 z O CG 3 S a 0 oo Lu 5 0 25 a Zi 050 GRADE B a 8 0 75 1 00 10 40 15 10 35 60 85 0 2 4 6 8 10 TEMPERATURE C SOURCE IMPEDANCE kQ MAXIM 7 OEZ LXVIN 827 LGS XVN MAX 1 226 MAX 1228 MAX1230 12
18. AJM AX1226AC EE T M H 19 2852 Rev 1 7 03 TION KIT A ABLE VALU S AVAILABL General Description The MAX1226 MAX1228 MAX1230 are serial 12 bit ana log to digital converters ADCs with an internal reference and an internal temperature sensor These devices fea ture on chip FIFO scan mode internal clock mode inter nal averaging and AutoShutdown The maximum sampling rate is 300ksps using an external clock The MAX1230 has 16 input channels the MAX1228 has 12 input channels and the MAX1226 has 8 input channels All input channels are configurable for single ended or differential inputs in unipolar or bipolar mode All three devices operate from a 5V supply and contain a 10MHz SPI QSPI MICROWIRE compatible serial port The MAX1230 is available in 28 pin 5mm x 5mm QFN with exposed pad and 24 pin QSOP packages The MAX1226 MAX1228 are only available in QSOP pack ages All three devices are specified over the extended 40 C to 85 C temperature range Applications System Supervision Data Acquisition Systems Industrial Control Systems Patient Monitoring Data Logging Instrumentation AutoShutdown is a trademark of Maxim Integrated Products Inc SPI QSPI are trademarks of Motorola Inc MICROWIRE is a trademark of National Semiconductor Corp TOP VIEW REF AA CNVST A Pin Configurations continued at end of data sheet MAXIM MA AALS 12 Bit 300ksps ADCs with FIFO Temp Sensor I
19. NAD 1 76 6 02 MAXIM 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference Total Harmonic Distortion Ordering Information continued Total harmonic distortion THD is the ratio of the RMS sum of the first five harmonics of the input signal to the PART TEMP RANGE PIN PACKAGE fundamental itself This is expressed as MAX1226BCEE T 0 C to 70 C 16 QSOP MAX1226BEEE T 40 C to 85 C 16 QSOP THD 20x log Ju DAME v v MAX1228ACEP T 0 C to 70 C 20 QSOP MAX1228AEEP T 40 C to 85 C 20 QSOP MAX1228BCEP T 20 QSOP MAX1228BEEP T 20 QSOP MAX1230ACEG T 24 QSOP Spurious Free Dynamic Range MAX1230AEEG T 24 QSOP Spurious free dynamic range SFDR is the ratio of the 7 RMS amplitude of the fundamental maximum signal e SN component to the RMS value of the next largest distor tion component 1230BCGI T 28 QFN EP 1230BEGI T 28 QFN EP Future product contact factory for availability EP Exposed paddle connect to GND where V1 is the fundamental amplitude and V2 V5 are the amplitudes of the first five harmonics Chip Information TRANSISTOR COUNT 30 889 PROCESS BiCMOS OEZ EXVIN 827 LXO LX Pin Configurations continued TOP VIEW MAXUM 21 CS a MAX1230 MAAKI CNVST AIN15 gt SF SSS Ss EF AIN14 N13 z z N12 CNVST AIN15 MAKINI 21 MAX
20. N_ CNVST AIN_ EE 40 C to 85 C DEER to GND we rege teovansictaefeberacnes 0 3V to Vpp 0 3V Storage Temperature Range 60 C to 150 C Maximum Current into Any Pin 50mA Junction Temperature 150 C Continuous Power Dissipation TA 70 C Lead Temperature soldering 1Oei 300 C 16 Pin QSOP derate 8 3mW C above 70 C 667mW 20 Pin QSOP derate 9 1mW C above 70 C 727mMW 24 Pin QSOP derate 9 5mW C above 70 C 762mW 28 Pin QFN 5mm x 5mm derate 20 8mMW C above 3007 1667mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS Vpp 5V 5 fsAMPLE 300kHZz fscLk 4 8MHz 50 duty cycle VReF 4 096V Ta Tmin to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER SYMBOL CONDITIONS MIN TYP DC ACCURACY Note 1 Resolution RES 12 INL Integral Nonlinearity 1 0 LSB Differential Nonlinearity DNL No missing codes over temperature 1 0 LSB LSB Offset Error 0 5 Gain Error Offset Error Temperature Coefficient Gain Temperature Coefficient Channel to Channel Offs
21. Table 5 Bipolar Mode Register Addressed Through Setup Register BIT NAME BCH0 1 BCH2 3 6 BCH4 5 5 BCH6 7 4 BCH8 9 BCH10 11 BCH12 13 BCH14 15 BIT 7 MSB FUNCTION 1 to configure AINO and AIN1 for bipolar differential conversion 1 to configure AIN2 and AIN3 for bipolar differential conversion 1 to configure AIN4 and AIN5 for bipolar differential conversion Set to 1 to configure AIN6 and AIN7 for bipolar differential conversion 1 to configure AIN8 and AIN9 for bipolar differential conversion MAX1228 MAX1230 only 1 to configure AIN10 and AIN11 for bipolar differential conversion MAX1228 MAX1230 only 1 to configure AIN12 and AIN13 for bipolar differential conversion MAX1230 only 1 to configure AIN14 and AIN15 for bipolar differential conversion MAX1230 only MAXIM 15 MAX 1 226 MAX 1228 MAX1230 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference Table 6 Averaging Register BIT NAME FUNCTION Set to zero to select averaging register Set to zero to select averaging register Set to 1 to select averaging register AVGON Set to 1 to turn averaging on Set to zero to turn averaging off NAVG1 Configures the number of conversions for single channel scans NAVGO Configures the number of conversions for single channel scans NSCAN1 Single channel scan count Scan mode 10 only NSCANO Single channel scan count Scan mode 10 on
22. ata follows the setup byte and is written to the unipolar mode register 14 One byte of data follows the setup byte and is written to the bipolar mode register MAXIM 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference Reset Register Write to the reset register as shown in Table 7 to clear the FIFO or to reset all registers to their default states Set the RESET bit to 1 to reset the FIFO Set the reset bit to zero to return the MAX1226 MAX1228 MAX1230 to its default power up state Power Up Default State The MAX1226 MAX1228 MAX1230 power up with all blocks in shutdown including the reference All registers power up in state 00000000 except for the setup regis ter which powers up in clock mode 10 CKSEL1 1 Temperature Measurements The MAX1226 MAX1228 MAX1230 perform tempera ture measurements with an internal diode connected transistor The diode bias current changes from 68yA to 4uA to produce a temperature dependent bias volt age difference The second conversion result at 4A is subtracted from the first at 68UA to calculate a digital value that is proportional to absolute temperature The output data appearing at DOUT is the above digital code minus an offset to adjust from Kelvin to Celsius The reference voltage used for the temperature mea surements is derived from the internal reference source to ensure a resolution of 1 8 of a degree Output Data Format Figures 4 7 illustrate the con
23. between two analog inputs eliminating common mode DC offsets and noise IN and IN are selected from the following pairs AINO AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 and AIN14 AIN15 AINO AIN7 are available on the MAX1226 MAX1228 and MAX1230 AIN8 AIN11 are only available on the MAX1228 and MAX1230 AIN12 AIN15 are only available on the MAX1230 See Tables 2 5 for more details on configuring the inputs For the inputs that can be configured as CNVST or an analog input only one can be used at a time For the inputs that can be configured as REF or an analog input the REF configuration excludes the analog input Unipolar Bipolar Address the unipolar and bipolar registers through the setup register bits 1 and 0 Program a pair of analog channels for differential operation by writing a 1 to the MAXIM 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference AINO AIN15 SINGLE ENDED AINO AIN2 AINA ANA DIFFERENTIAL COMPARATOR GND SINGLE ENDED AIN1 ANS ANS AINTS DIFFERENTIAL Figure 3 Equivalent Input Circuit appropriate bit of the bipolar or unipolar register Unipolar mode sets the differential input range from O to VREF A negative differential analog input in unipolar mode causes the digital output code to be zero Selecting bipolar mode sets the differential input range to VREF 2 The digital output code is binary in unipo lar mode and two
24. et Matching DYNAMIC SPECIFICATIONS 10kHz sine wave input 4 096Vp p 300ksps fscLk 4 8MHz Signal to Noise Plus Distortion SINAD Total Harmonic Distortion THD Up to the 5th harmonic Spurious Free Dynamic Range SFDR Intermodulation Distortion fint 9 9kHz fin2 10 2kHz Full Power Bandwidth 3dB point Full Linear Bandwidth S N D gt 68dB 2 MAXIM 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference ELECTRICAL CHARACTERISTICS continued VDD 5V 5 fSAMPLE 300kHZz fscLk 4 8MHz 50 duty cycle VREF 4 096V TA TmIN to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER SYMBOL CONDITIONS MIN TYP MAX CONVERSION RATE External reference 0 8 Power Up Time Internal reference Note 3 65 Acquisition Time i Internally clocked 3 5 Conversion Time Externally clocked Note 4 Externally clocked conversion 4 8 Data I O 10 SCLK Duty Cycle 60 Aperture Delay ns Aperture Jitter lt 50 ps ANALOG INPUT Bipolar Note 5 VREF 2 Input Leakage Current Vin VDD 0 01 1 External Clock Frequency Input Voltage Range Input Capacitance During acquisition time Note 6 INTERNAL TEMPERATURE SENSOR Grade A TA 25 C Grade A TA 20 C to 85 C Measurement Error Note 7 Grade A Ta TmIN to TMAX Grade B Ta 25 C Grade B Ta TmIN to TMAX Temperature Measurement Noise Te
25. for clock mode 00 timing Initiate a scan by setting CNVST low for at least 40ns before pulling it high again The MAX1226 MAX1228 MAX1230 then wake up scan all requested channels store the results in the FIFO and shut down After the scan is complete EOC is pulled low and the results are available in the FIFO Wait until EOC goes low before pulling CS low to communicate with the serial interface EOC stays low until CS or CNVST is pulled low again A temperature measurement result if requested pre cedes all other FIFO results Do not initiate a second CNVST before EOC goes low otherwise the FIFO can become corrupted Externally Timed Acquisitions and Internally Timed Conversions with CNVST Performing Conversions in Clock Mode 01 In clock mode 01 conversions are requested one at a time using CNVST and performed automatically using the internal oscillator See Figure 5 for clock mode 01 timing Setting CNVST low begins an acquisition wakes up the ADC and places it in track mode Hold CNVST low for at least 1 4us to complete the acquisition If internal ref erence needs to wake up an additional 65us is required for the internal reference to power up If a tem perature measurement is being requested reference power up and temperature measurement are internally timed In this case hold CNVST low for at least 40ns Set CNVST high to begin a conversion After the con version is complete the ADC_shu
26. ined by number of channels being scanned by NSCAN1 NSCANO trs time required for temperature measurement set to zero if temp measurement is not requested tRP internal reference wake up set to zero if internal reference is already powered up or external reference is being used Table 1 Input Data Byte MSB First REGISTER NAME BIT 6 BIT 5 BIT 4 In clock mode 01 the total conversion time depends on how long CNVST is held low or high including any time required to turn on the internal reference Conversion time in externally clocked mode CKSEL1 CKSELO 11 depends on the SCLK period and how long CS is held high between each set of eight SCLK cycles Conversion Register Select active analog input channels scan modes and a single temperature measurement per scan by writing to the conversion register Table 2 details channel selection the four scan modes and how to request a temperature measurement Request a scan by writing to the conversion register when in clock mode 10 or 11 or by applying a low pulse to the CNVST pin when in clock mode 00 or 01 A conversion is not performed if it is requested on a channel that has been configured as CNVST or REF Do not request conversions on channels 8 15 on the MAX1226 and channels 12 15 on the MAX1228 Set CHSEL3 CHSELO to the lower channel s binary value If the last two channels are configured as a differential pair and one of them has been reconfigured as CNVST or REF
27. inter nal oscillator which is accurate within 10 of the 4 4MHz nominal clock rate The internal oscillator is active in clock modes 00 01 and 10 Read out the data at clock speeds up to 10MHz See Figures 4 7 for details on timing speci fications and starting a conversion Applications Information Register Descriptions The MAX1226 MAX1228 MAX1230 communicate between the internal registers and the external circuitry through the SPI QSPl compatible serial interface Table 1 details the registers and the bit names Tables 2 7 show the various functions within the conversion register setup register averaging register reset regis ter unipolar register and bipolar register 11 OEZ LX VIN 827 LK XVN MAX 1226 MAX 1228 MAX1230 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference Conversion Time Calculations The conversion time for each scan is based on a num ber of different factors conversion time per sample samples per result results per scan if a temperature measurement is requested and if the external refer ence is in use Use the following formula to calculate the total conver sion time for an internally timed conversion in clock modes 00 and 10 see the Electrical Characteristics section as applicable total conversion time tenv X Navg X Nresult tTS Ip where Lon tacq max tconv max Navg samples per result amount of averaging Nresult number of FIFO results requested determ
28. is never less than 1 4us and any source imped ance below 300Q does not significantly affect the ADC s AC performance A high impedance source can be accommodated either by lengthening taco or by placing a 1uF capacitor between the positive and neg ative analog inputs Internal FIFO The MAX1226 MAX1228 MAX1230 contain a FIFO buffer that can hold up to 16 ADC results plus one tem perature result This allows the ADC to handle multiple internally clocked conversions and a temperature mea surement without tying up the serial bus If the FIFO is filled and further conversions are request ed without reading from the FIFO the oldest ADC results are overwritten by the new ADC results Each result contains 2 bytes with the MSB preceded by 4 leading zeros After each falling edge of CS the oldest available byte of data is available at DOUT MSB first When the FIFO is empty DOUT is zero The first 2 bytes of data read out after a temperature mea surement always contain the temperature result preceded by 4 leading zeros MSB first If another temperature mea surement is performed before the first temperature result is read out the old measurement is overwritten by the new result Temperature results are in degrees Celsius two s complement at a resolution of 1 8 of degree See the Temperature Measurements section for details on converting the digital code to a temperature Internal Clock The MAX1226 MAX1228 MAX1230 operate from an
29. ly See below for bit details FUNCTION Performs 1 conversion for each requested result Performs 4 conversions and returns the average for each requested result 1 0 0 1 U 1 Performs 8 conversions and returns the average for each requested result 1 1 0 pa WE oe o Performs 16 conversions and returns the average for each requested result 1 1 1 Performs 32 conversions and returns the average for each requested result NSCAN1 NSCANO FUNCTION APPLIES ONLY IF SCAN MODE 10 IS SELECTED 0 0 Scans channel N and returns 4 results Scans channel N and returns 8 results 1 0 Scans channel N and returns 12 results 1 Scans channel N and returns 16 results FUNCTION Set to zero to select reset register Set to zero to select reset register Set to zero to select reset register Set to 1 to select reset register Set to zero to reset all registers Set to 1 to clear the FIFO only Reserved Don t care Reserved Don t care Reserved Don t care 16 MAXIM 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference Internally Timed Acquisitions and Conversions Using CNVST Performing Conversions in Clock Mode 00 In clock mode 00 the wake up acquisition conversion and shutdown sequences are initiated through CNVST and performed automatically using the internal oscilla tor Results are added to the internal FIFO to be read out later See Figure 4
30. ly noise rejection If the power sup ply is very noisy connect a 10Q resistor in series with the supply to improve power supply filtering For the QFN package connect its exposed pad to ground Definitions Integral Nonlinearity Integral nonlinearity INL is the deviation of the values on an actual transfer function from a straight line This straight line can be either a best straight line fit or a line drawn between the end points of the transfer func tion once offset and gain errors have been nullified INL for the MAX1226 MAX1228 MAX1230 is measured using the end point method 19 OEZ LX VIN 827 LK LX MAX 1 226 MAX 1228 MAX1230 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference OUTPUT CODE FULL SCALE TRANSITION FS VREF Vcom ZS Voom 1 LSB VREE 4096 INPUT VOLTAGE LSB FS 3 2 LSB Figure 8 Unipolar Transfer Function Full Scale FS VREF Differential Nonlinearity Differential nonlinearity DNL is the difference between an actual step width and the ideal value of 1 LSB A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function Aperture Jitter Aperture jitter taJ is the sample to sample variation in the time between the samples Aperture Delay Aperture delay taD is the time between the rising edge of the sampling clock and the instant when an actual sample is taken Signal to Noise Ratio For a waveform perfectly
31. mperature Resolution Power Supply Rejection 0 3 INTERNAL REFERENCE EF Output Voltage 4 024 4 096 4 168 Grade A 8 Grade B EF Temperature Coefficient TCREF F Output Noise utput Resistance F Power Supply Rejection TERNAL REFERENCE INPUT F Input Voltage Range EF Input Voltage Range d VDD 50mV VREF 4 096V fsamPLE 300ksps VREF 4 096V fsamPLE 0 EF Input Current MAKIM 3 OEZ EX VIN 827 LK LX 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference ELECTRICAL CHARACTERISTICS continued VDD 5V 5 fSAMPLE 300kHZz fscLk 4 8MHz 50 duty cycle VREF 4 096V TA TMIN to Tmax unless otherwise noted Typical values are at TA 25 C PARAMETER SYMBOL DIGITAL INPUTS SCLK DIN CS CNVST Input Voltage Low VIL V 0 8 V Input Voltage High IH 2 0 V VHYST Input Leakage Current IIN CONDITIONS MIN TYP MAX UNITS Input Hysteresis VIN 0 or VpD Input Capacitance CIN DIGITAL OUTPUTS DOUT EOC 2mA Output Voltage Low SNK ISINK 4mA ISOURCE 1 5mA CS Vpp CS Vpp Output Voltage High Tri State Leakage Current Tri State Output Capacitance POWER REQUIREMENTS Supply Voltage 5 25 3100 2300 2400 1950 During temp sense MAX 1 226 MAX 1228 MAX1230 Supply Current Note 8 Internal reference Externa reference fSAMPLE 300ksps fSAMPLE O REFon 1000
32. nternal Reference Features Internal Temperature Sensor 1 C Accuracy 16 Entry First In First Out FIFO Analog Multiplexer with True Differential Track Hold 16 12 8 Channel Single Ended 8 6 4 Channel True Differential Unipolar or Bipolar Accuracy 1 LSB INL 1 LSB DNL No Missing Codes Over Temperature Scan Mode Internal Averaging and Internal Clock Low Power Single 5V Operation 1 9mA at 300ksps Internal 4 096V Reference or External Differential Reference 10MHz 3 Wire SPI QSPI MICROWIRE Compatible Interface Space Saving 28 Pin 5mm x 5mm QFN Package Ordering Information PART MAX1226ACEE T TEMP RANGE 0 C to 70 C 40 C to 85 C PIN PACKAGE 16 QSOP 16 QSOP MAX1226AEEE T Future product contact factory for availability Ordering Information continued at end of data sheet Pin Configurations REF CNVST AIN11 REF AIN10 e 2 e e 2 2 e e e Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com OEZ LX VIN 827 LGS LX MAX 1 226 MAX 1228 MAX1230 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference ABSOLUTE MAXIMUM RATINGS Kier 0 3V to 6V Operating Temperature Ranges CS SCLK DIN EOC DOUT to GND 0 3V to VDD 0 3V MAX 2s IG E 0 C to 70 C AINO AIN13 REF AI
33. rnally timed Select clock mode 00 to configure CNVST AIN_ to act as a conver sion start and use it to request the programmed inter nally timed conversions without tying up the serial bus In clock mode 01 use CNVST to request conversions one channel at a time controlling the sampling speed without tying up the serial bus Request and start inter nally timed conversions through the serial interface by writing to the conversion register in the default clock mode 10 Use clock mode 11 with SCLK up to 4 8MHz for externally timed acquisitions to achieve sampling rates up to 300ksps Clock mode 11 disables scanning and averaging See Figures 4 7 for timing specifica tions and how to begin a conversion These devices feature an active low end of conversion output EOC goes low when the ADC completes the last requested operation and is waiting for the next input data byte for clock modes 00 and 10 In clock mode 01 EOC goes low after the ADC completes each requested operation EOC goes high when CS or CNVST goes low EOC is always high in clock mode 11 Single Ended Differential Input The MAX1226 MAX1228 MAX1230 use a fully differen tial ADC for all conversions The analog inputs can be configured for either differential or single ended con versions by writing to the setup register see Table 3 Single ended conversions are internally referenced to GND Figure 3 In differential mode the T H samples the difference
34. st of the entry is lost The remaining data in the FIFO is uncorrupted and can be read out normally after tak ing CS low again as long as the 4 leading bits nor mally zeros are ignored Internal registers that are written partially through the SPI contain new values starting at the MSB up to the point that the partial write is stopped The part of the register that is not written contains previously written values If CS is pulled low before EOC goes low a conversion cannot be com pleted and the FIFO is corrupted MAXIM Transfer Function Figure 8 shows the unipolar transfer function for single ended or differential inputs Figure 9 shows the bipolar transfer function for differential inputs Code transitions occur halfway between successive integer LSB values Output coding is binary with 1 LSB VREF 4096V for unipolar and bipolar operation and 1 LSB 0 125 C for temperature measurements Layout Grounding and Bypassing For best performance use PC boards Do not use wire wrap boards Board layout should ensure that digital and analog signal lines are separated from each other Do not run analog and digital especially clock signals parallel to one another or run digital lines underneath the MAX1226 MAX1228 MAX1230 package High frequen cy noise in the VDD power supply can affect perfor mance Bypass the Vpp supply with a 0 1uF capacitor to GND close to the Vpp pin Minimize capacitor lead lengths for best supp
35. tial channels The MAX1230 has 16 single ended analog input channels or eight differential channels OEZ EX VIN 827 LK XVN MAX 1 226 MAX 1228 MAX1230 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference Converter Operation The MAX1226 MAX1228 MAX1230 ADCs use a fully dif ferential successive approximation register SAR con version technique and an on chip T H block to convert temperature and voltage signals into a 12 bit digital result Both single ended and differential configurations are supported with a unipolar signal range for single ended mode and bipolar or unipolar ranges for differ ential mode Input Bandwidth The ADC s input tracking circuitry has a 1MHz small signal bandwidth so it is possible to digitize high speed transient events and measure periodic signals with bandwidths exceeding the ADC s sampling rate by using undersampling techniques Anti alias prefiltering of the input signals is necessary to avoid high frequen cy signals aliasing into the frequency band of interest Analog Input Protection Internal ESD protection diodes clamp all pins to VDD and GND allowing the inputs to swing from GND 0 3V to VDD 0 3V without damage However for accurate conversions near full scale the inputs must not exceed Vpp by more than 50mV or be lower than GND by 50mV If an off channel analog input voltage exceeds the supplies limit the input current to 2mA 3 Wire Serial Interface The MAX12
36. ts down and pulls EOC low EOC stays low until CS or CNVST is pulled low again Wait until EOC goes low before pulling CS or CNVST low If averaging is turned on multiple CNVST pulses need to be performed before a result is written to the FIFO Once the proper number of conversions has been per formed to generate an averaged FIFO result as speci fied by the averaging register the scan logic automatically switches the analog input multiplexer to the next requested channel If a temperature measure ment is programmed it is performed after the first rising edge of CNVST following the input data byte written to the conversion register The result is available on DOUT once EOC has been pulled low Internally Timed Acquisitions and Conversions Using the Serial Interface Performing Conversions in Clock Mode 10 In clock mode 10 the wake up acquisition conversion and shutdown sequences are initiated by writing an input data byte to the conversion register and are per formed automatically using the internal oscillator This is the default clock mode upon power up See Figure 6 for clock mode 10 timing r UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERS L SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION Figure 4 Clock Mode 00 MAXIM 17 OEZ LX VIN 827 LXO LX MAX 1 226 MAX 1228 MAX123
37. version timing for the MAX1226 MAX1228 MAX1230 The 12 bit conversion result is output in MSB first format with 4 leading zeros DIN data is latched into the serial interface on the rising edge of SCLK Data on DOUT transitions on the falling edge of SCLK Conversions in clock modes 00 and 01 are initiated by CNVST Conversions in clock modes 10 and 11 are initiated by writing an input data byte to the conversion register Data is binary for unipolar mode and two s complement for bipolar mode Table 4 Unipolar Mode Register Addressed Through Setup Register BIT NAME BIT FUNCTION UCHO 1 7 MSB Set to 1 to configure AINO and AIN1 for unipolar differential conversion CH2 3 Set to 1 i i UCH2 to con 2 and AIN3 for un polar differential conversion UCH4 5 Set to 1 to confi 4 and AIN5 for uni polar differential conversion UCH6 7 Set to 1 to confi 6 and AIN7 for uni polar differential conversion 8 and AIN9 for uni polar differential conversion MAX1228 MAX1230 only OEZ LX VIN 827 EXVIN 9SCELXVIN Se UCH10 11 2 Set to 1 to configure AIN10 and AIN11 for unipolar differential conversion MAX1228 MAX1230 only Set to 1 i to con 12 and AIN13 for unipolar differential conversion MAX1230 only 14 and AIN15 for unipolar differential conversion MAX1230 only Set to 1 to confi fig o fig o fig o fig UCH8 9 o 1 to config o fig o fig fig
38. write to the bipolar mode register In both cases the setup byte must be followed immediately by 1 byte of data written to the unipolar register or bipolar register Hold CS low and run 16 SCLK cycles before pulling CS high If the last 2 bits of the setup register are 00 or 01 neither the unipolar mode register nor the bipolar mode register is written Any subsequent byte is recognized as a new input data byte See Tables 4 and 5 to program the unipolar and bipolar mode registers If a channel is configured as both unipolar and bipolar the unipolar setting takes precedence In unipolar mode AIN can exceed AIN by up to VREF The out put format in unipolar mode is binary In bipolar mode either input can exceed the other by up to VREF 2 The output format in bipolar mode is two s complement Averaging Register Write to the averaging register to configure the ADC to average up to 32 samples for each requested result and to independently control the number of results requested for single channel scans Table 2 details the four scan modes available in the con version register All four scan modes allow averaging as long as the AVGON bit bit 4 in the averaging register is set to 1 Select scan mode 10 to scan the same channel multiple times Clock mode 11 disables averaging 13 OEZ EXVIN 827 LGS LX 12 Bit 300ksps ADCs with FIFO Temp Sensor Internal Reference BIT NAME BIT Table 3 Setup Register FUNCTION
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MAXIM MAX1226/MAX1228/MAX1230 handbook