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MICROCHIP PIC12C67X handbook

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1. Device Program Memory Data Memory RAM Non Volatile Memory EEPROM PIC12C671 1K x 14 128x8 PIC12C672 2K x 14 128x8 PIC12CE673 1K x 14 128x8 16x8 PIC12CE674 2K x 14 128x8 16x8 13 8 GPIO Data Bus Program Counter lt x GPO ANO SA HN GP1 AN1 VREF RAM Y t X GP2 TOCKI AN2 INT Memory 8 Level Stack 128 bytes LR GP3 MCLR VPP 13 bit File I1 X GP4 OSC2 ANS CLKOUT Registers 1X GP5 OSC1 CLKIN Program Bus 7 4 RAM Adar 1 4 9 3 E d o a Addr MUX o o Instruction reg 7 Indirect Direct Addr T 8 Addr 16x8 EEPROM FSR reg ay Data PIC12CE673 Memory PIC12CE674 gt STATUS reg 8 3 Power up Timer Fl instruction Oscillator ecode es Start up Timer Control B BE Watchdog 8 Timer l Timing cd OSC1 CLKIN 7 a Power on W OSC2 CLKOUT lt A gt Generation Reset da Internal H li 4 MHz Clock MGLR Timer0 VDD Vss A D Note 1 Higher order bits are from the STATUS Register DS30561B page 8 1999 Microchip Technology Inc PIC12C67X TABLE 3 1 PIC12C67X PINOUT DESCRIPTION Name DIP Pin HOP Type Buffer Type Description GPO ANO 7 VO TTL ST Bi directional VO port serial programming data analog input 0 Can be software programmed for internal weak pull up and interrupt on pin change This buffer is a Schmitt Trigger input when used in serial programming mode GP1 AN1 VR
2. Param Sym Characteristic Min Typt Max Units Conditions No A01 NR Resolution 8 bits bit VREF VDD 5 12V Vss lt VAIN lt VREF A02 EABS Total absolute error t1 LSb VREF VDD 5 12V VSS lt VAIN lt VREF A03 E Integral linearity error t1 LSb VREF VDD 5 12V VSS lt VAIN lt VREF A04 EDL Differential linearity error t1 LSb VREF VDD 5 12V VSS lt VAIN lt VREF A05 Ers Full scale error lt 1 LSb VREF VoD 5 12V Vss lt VAIN lt VREF A06 EoFF Offset error EI LSb VREF VDD 5 12V Vss lt VAIN lt VREF A10 Monotonicity guaranteed VSS lt VAIN lt VREF Note 3 A20 VREF Reference voltage 2 5V VDD 0 3 V A25 VAIN Analog input voltage Vss 0 3 VREF 0 3 V A30 ZAIN Recommended impedance of 10 0 KO analog voltage source A40 IAD A D conversion PIC12C67X 180 MA Average current con current VDD PIC12LC67X 90 uA Sumption when A D is on Note 1 A50 IREF VREF input current Note 2 10 1000 HA During VAIN acquisition Based on differential of VHOLD to VAIN to charge CHOLD see Section 8 1 10 HA During A D Conversion cycle These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design
3. Chip_Reset R Q P chip E gt 10 bit Ripple counter Enable PWRT See Table 9 4 for time out situations Enable OST Note 1 This is a separate oscillator from the RC oscillator of the CLKIN pin n rn SSS 1999 Microchip Technology Inc DS30561B page 57 PIC12C67X 9 4 Power on Reset POR Power up Timer PWRT and Oscillator Start up Timer OST 9 4 1 POWER ON RESET POR The on chip POR circuit holds the chip in reset until VDD has reached a high enough level for proper opera tion To take advantage of the POR just tie the MCLR pin through a resistor to VDD This will eliminate exter nal RC components usually needed to create a Power on Reset A maximum rise time for VDD is specified See Electrical Specifications for details When the device starts normal operation exits the reset condition device operating parameters voltage freguency temperature must be met to ensure operation If these conditions are not met the device must be held in reset until the operating conditions are met For additional information refer to Application Note AN607 Power up Trouble Shooting 9 4 POWER UP TIMER PWRT The Power up Timer provides a fixed 72 ms nominal time out on power up only from the POR The Power up Timer operates on an internal RC oscillator The chip is kept in r
4. Value n Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other Resets Oth TMRO TimerO modules register XXXX XXXX UUUU uuuu OBh 8Bh INTCON GIE PEIE TOIE INTE GPIE TOIF INTF GPIF 0000 000x 0000 000u 81h OPTION GPPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 85h TRIS TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRISO 11 1111 11 1111 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by Timer0 1999 Microchip Technology Inc DS30561B page 43 PIC12C67X NOTES EEE DS30561B page 44 1999 Microchip Technology Inc PIC12C67X 8 0 ANALOG TO DIGITAL CONVERTER A D MODULE The Analog To Digital A D converter module has four analog inputs The A D allows conversion of an analog input signal to a corresponding 8 bit digital number refer to Applica tion Note AN546 for use of A D Converter The output of the sample and hold is the input into the converter which generates the result via successive approxima tion The analog reference voltage is software select able to either the device s positive supply voltage VDD or the voltage level on the GP1 AN1 VREF pin The A D converter has a unique feature of being able to operate while the device is in SLEEP mode The A D module has three registers These registers are A D Result Register ADRES A D Control Register 0 ADCONO
5. MUX a PSA T WDT Note PSA and PS lt 2 0 gt are bits in the OPTION register Time out TABLE 9 8 SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config bits MCLRE CP1 CPO PWRTE WDTE FOSC2 FOSC1 FOSCO 81h OPTION GPPU INTEDG TOCS TOSE PSA PS2 PS1 PSO Legend Shaded cells are not used by the Watchdog Timer Note 1 See Register 9 1 for operation of these bits Not all CPO and CP1 bits are shown 1999 Microchip Technology Inc DS30561B page 65 PIC12C67X 9 8 Power down Mode SLEEP Power down mode is entered by executing a SLEEP instruction If enabled the Watchdog Timer will be cleared but keeps running the PD bit STATUS lt 3 gt is cleared the TO STATUS lt 4 gt bit is set and the oscillator driver is turned off The I O ports maintain the status they had before the SLEEP instruction was executed driving high low or hi impedance For lowest current consumption in this mode place all VO pins at either VDD or Vss ensure no external cir cuitry is drawing current from the I O pin power down the A D and disable external clocks Pull all VO pins that are hi impedance inputs high or low externally to avoid switching currents caused by floating inputs The TOCKI input if enabled should also be at VDD or Vss for lowest current consumption The contribution from on chip pull ups
6. FIGURE 13 9 lor vs VOL VDD 5 5 V FIGURE 13 10 VTH INPUT THRESHOLD VOLTAGE OF GPIO PINS vs VDD 55 Max 40 C 1 8 50 16 Max 40 to 125 45 9 S 14 40 E 12 Typ 25 85 Typ 25 C Min 40 to 125 1 0 E 30 is 0 8 25 20 Min 85 C 0 6 0 is 2 5 3 5 4 5 5 5 Min 125 C VDD Volts 0 0 25 0 5 0 75 1 0 VOL Volts kya II v l DS30561B page 112 1999 Microchip Technology Inc PIC12C67X FIGURE 13 11 Vi VIH OF NMCLR AND TOCKI vs VDD 8 5 VIH Max 40 to 125 VIH Typ 25 3 0 VIH Min 40 to 125 ViL VIH Volts D c1 ViL Max 40 to 125 ViL Typ 25 ss d VIL Min 40 to 125 1 0 0 5 2 5 3 5 4 5 5 5 VoD Volts 1999 Microchip Technology Inc DS30561B page 113 PIC12C67X NOTES PE muu DS30561B page 114 1999 Microchip Technology Inc PIC12C67X 14 0 PACKAGING INFORMATION 14 1 Package Marking Information 8 Lead PDIP 300 mil Example MMMMMMMM 12CE674 XXXXXCDE 04 PSAZ AABB 9925 Facs B 8 Lead SOIC 208 mil Example MMMMMMM 12C671 XXXXXXX 041 SM AABBCDE 9924SAZ NI S 8 Lead Windowed Ceramic Side Brazed 300 mil Example UJ QO KEN MM QN JW
7. 8 P Ground reference for logic and VO pins Legend input O output VO input output P power not used TTL TTL input ST Schmitt Trigger input 1999 Microchip Technology Inc DS30561B page 9 PIC12C67X 3 1 The clock input from OSC1 is internally divided by four to generate four non overlapping quadrature clocks namely Q1 Q2 Q3 and O4 Internally the pro gram counter PC is incremented every O1 and the instruction is fetched from the program memory and latched into the instruction register in Q4 The instruc tion is decoded and executed during the following Q1 through O4 The clocks and instruction execution flow is shown in Figure 3 2 Clocking Scheme Instruction Cycle 3 2 An Instruction Cycle consists of four Q cycles Q1 Q2 Q3 and Q4 The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle However due to the pipelining each instruction effectively executes in one cycle If an instruction causes the program counter to change i e GOTO then two cycles are required to complete the instruction Example 3 1 Instruction Flow Pipelining A fetch cycle begins with the program counter PC incrementing in Q1 In the execution cycle the fetched instruction is latched into the Instruction Register IR in cycle Q1 This instruction is then deco
8. SIMICE is an entry level hardware development sys tem designed to operate in a PC based environment with Microchip s simulator MPLAB SIM Both SIMICE and MPLAB SIM run under Microchip Technology s MPLAB Integrated Development Environment IDE software Specifically SIMICE provides hardware sim ulation for Microchip s PIC12C5XX PIC12CE5XX and PIC16C5X families of PICmicro 8 bit microcontrollers SIMICE works in conjunction with MPLAB SIM to pro vide non real time I O port emulation SIMICE enables a developer to run simulator code for driving the target system In addition the target system can provide input to the simulator code This capability allows for simple and interactive debugging without having to manually generate MPLAB SIM stimulus files SIMICE is a valu able debugging tool for entry level system develop ment 11 13 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 is a simple board which demonstrates the capabilities of several of Microchip s microcontrol lers The microcontrollers supported are PIC16C5X PIC16C54 to PIC16C58A PIC16C61 PIC16C62X PIC16C71 PIC16C8X PIC17C42 PIC17C43 and PIC17C44 All necessary hardware and software is included to run basic demo programs The users can program the sample microcontrollers provided with the PICDEM 1 board on a PROMATE Il or PICSTART Plus programmer and easily test firm ware The user can also connect the PICDEM 1 board to the MP
9. 9Eh Unimplemented 9Fh ADCON1 PCFG2 PCFG1 PCFGO 000 000 Legend x unknown u unchanged q value depends on condition unimplemented read as 0 Shaded locations are unimplemented read as 0 Note 1 These registers can be addressed from either bank 2 The upper byte of the program counter is not directly accessible PCLATH is a holding register for the PC lt 12 8 gt whose con tents are transferred to the upper byte of the program counter 3 Other non power up resets include external reset through MCLR and Watchdog Timer Reset 4 The IRP and RP1 bits are reserved on the PIC12C67X always maintain these bits clear 5 The SCL GP7 and SDA GP6 bits are unimplemented on the PIC12C671 672 and read as 0 DS30561B page 14 1999 Microchip Technology Inc PIC12C67X 4 2 2 1 STATUS REGISTER The STATUS Register shown in Register 4 1 contains the arithmetic status of the ALU the RESET status and the bank select bits for data memory The STATUS Register can be the destination for any instruction as with any other register If the STATUS Register is the destination for an instruction that affects the Z DC or C bits then the write to these three bits is disabled These bits are set or cleared according to the device logic Furthermore the TO and PD bits are not writable Therefore the result of an instruction with the STATUS Register as destination may be different tha
10. IORWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example MOVLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Inclusive OR W with f label IORWF fd O lt f lt 127 de 0 1 W OR f gt dest 7 00 0100 dfff ffff Inclusive OR the W register with register f If d is 0 the result is placed in the W register If d is 1 the result is placed back in regis ter f 1 1 IORWF RESULT 0 Before Instruction RESULT 0x13 W 0x91 After Instruction RESULT 0x13 W 0x93 z 1 Move Literal to W label MOVLW k 0 lt k lt 255 k W None 11 00xx kkkk kkkk The eight bit literal is loaded into W register The don t cares will assemble as O s 1 1 MOVLW Ox5A After Instruction 0x5A MOVF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example MOVWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Move f label MOVF fd O lt f lt 127 de 0 1 f dest Z 00 1000 dfff fff The contents of register f are moved to a destination dependant upon the status of d If d 0 des tination is W register If d 1 the destination is file register f itself d 1 is useful to test a file register since
11. Reset Conditions for Special Registers 59 RETEFIE Iristr ctioni oreet 78 RETLW Instruction S SEEVAL Evaluation and Programming System 86 Services One Time Programmable OTP Quick Turnaround Production QTP E Serialized Quick Turnaround Production SQTP 5 dre M LEE 70 SFR As Source Destination sess 70 SLEEP ss ME Lm 53 56 Software Simulator MPLAB SIM 84 Special Features of the CDU 53 Special Function Register PICI2C 67 si a aa nn 13 Special Function Registers esses 70 Special Function Registers Section 12 ijr Jd e EE RE LE DE EN Overflows Underflow STATUS Register eese 15 SUBLW Instructions bleu a Seet DE D 80 SUBWF Instruction SWAPF Instruction T TOCS DIE OGE SEE EE RA 16 IERE ES 49 Timer0 RIGE SEE EN EE NE Ge Ee ee Ee ah 59 Timers Timer0 Block Diagram ese seen External Clock see External Clock Timing Increment Delay te INTO PT ia tev nce tn a Interrupt Timing seen Prescaler m Prescaler Block Diagram SOCUON i i tre tese e edens Switching Prescaler Assignment ia Synchronization ee TOCK hetdie pep GA Gidh ua s Timing
12. A D Control Register 1 ADCON1 REGISTER 8 1 The ADCONO Register shown in Figure 8 1 controls the operation of the A D module The ADCON1 Regis ter shown in Figure 8 2 configures the functions of the port pins The port pins can be configured as analog inputs GP1 can also be a voltage reference or as dig ital VO Note 1 If the port pins are configured as analog inputs reset condition reading the port MOVF GPIO W results in reading 0 s 2 Changing ADCON1 Register can cause the GPIF and INTF flags to be set in the INTCON Register These interrupts should be disabled prior to modifying ADCON1 ADCONO REGISTER ADDRESS 1Fh R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 ADCS1 ADCSO reserved CHS1 CHSO GO DONE reserved ADON R Readable bit bit7 00 Fosc 2 01 FOSC 8 10 Fosc 32 bit 5 Reserved bit 4 3 CHS 1 0 Analog Channel Select bits 00 channel 0 GPO ANO 01 channel 1 GP1 AN1 10 channel 2 GP2 AN2 11 channel 3 GP4 AN3 bit 2 GO DONE A D Conversion Status bit If ADON 1 is complete bit 1 Reserved bit0 ADON A D on bit 1 A D converter module is operating bit 7 6 ADCS lt 1 0 gt A D Conversion Clock Select bits 11 FRC clock derived from an RC oscillation 1 A D conversion in progress setting this bit starts the A D conversion 0 A D conversion not in progress this bit is automatically cl
13. 6 1 3 STOP DATA TRANSFER C A LOW to HIGH transition of the SDA line while the clock SCL is HIGH determines a STOP condition All operations must be ended with a STOP condition 6 1 4 DATA VALID D The state of the data line represents valid data when after a START condition the data line is stable for the duration of the HIGH period of the clock signal The data on the line must be changed during the LOW period of the clock signal There is one bit of data per clock pulse Each data transfer is initiated with a START condition and terminated with a STOP condition The number of the data bytes transferred between the START and STOP conditions is determined by the available data EEPROM space 1999 Microchip Technology Inc DS30561B page 33 PIC12C67X 6 1 5 ACKNOWLEDGE The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a The EEPROM when addressed will generate an way that the SDA line is stable LOW during the HIGH acknowledge after the reception of each byte The pro period of the acknowledge related clock pulse Of cessor must generate an extra clock pulse which is course setup and hold times must be taken into associated with this acknowledge bit account The processor must signal an end of data to the EEPROM by not generating an acknowledge bit on the last byte that has been clocked out of the EEPROM In this case the EEPROM must leave the data line H
14. FIGURE 9 5 EXTERNAL RC OSCILLATOR MODE VDD RExr Internal EET PIC12C67X Vss Fosc 4 OSC2 CLKOUT 1999 Microchip Technology Inc DS30561B page 55 PIC12C67X 9 2 5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz nom inal system clock at VDD 5V and 25 C See Section 13 0 for information on variation over voltage and temperature In addition a calibration instruction is programmed into the last address of the program memory which contains the calibration value for the internal RC oscillator This value is programmed as a RETLW XX instruction where XX is the calibration value In order to retrieve the cali bration value issue a CALL YY instruction where YY is the last location in program memory O3FFh for the PIC12C671 and the PIC12CE673 O7FFh for the PIC12C672 and the PIC12CE674 Control will be returned to the user s program with the calibration value loaded into the W register The program should then perform a MOVWF OSCCAL instruction to load the value into the internal RC oscillator trim register OSCCAL when written to with the calibration value will trim the internal oscillator to remove process variation from the oscillator frequency Bits lt 7 4 gt CAL lt 3 0 gt are used for fine calibration while bit 3 CALFST and bit 2 CALSLW are used for more coarse adjustment Adjust ing CAL lt 3 0 gt from 0000 to 1111 yields a higher
15. Voo GPPU MCLREN U Input Pin x Vss en en Schmitt Trigger Input Buffer Program Mode HV Detect TTL Input Buffer Data Bus ES Q D co EN RD PORT gt RD TRIS Vss GP3 INT Note 1 Wake up on pin change interrupt for GP3 DS30561B page 28 1999 Microchip Technology Inc PIC12C67X FIGURE 5 4 BLOCK DIAGRAM OF GP4 0SC2 AN3 CLKOUT PIN INTRC or EXTRC w CLKOUT CLKOUT Fosc 4 gt 0 Data Bus From OSC1 Oscillator e D Q Circuit Ge vom WR PORT GN a ZN UO Pin Data Latch i Dx k N Y Vss INTRC Vss 1 D Q EXTRC WR TRIS a INTRC or EXTRC Spor a Ise w o CLKOUT TRIS Latch Analog Input TTL Mode Input Buffer RD TRIS Q D ENd RD PORT po To A D Converter SSS DS30561B page 29 1999 Microchip Technology Inc PIC12C67X FIGURE 5 5 BLOCK DIAGRAM OF GP5 OSC1 CLKIN PIN To OSC2 Oscillator Data Bus Circuit disi Voo von WR PORT EN NN G e 24 p Data Latch ZN VO Pin e Ld HB Ac DD Q Y WR TRIS ENA G INTRC Vss Vss TRIS Latc
16. FEES PIBUBEGISTEB Note Interrupt flag bits get set when an interrupt This register contains the individual flag bits for the condition occurs regardless of the state of Peripheral interrupts its corresponding enable bit or the global enable bit GIE INTCON 7 User soft ware should ensure the appropriate inter rupt flag bits are clear prior to enabling an interrupt REGISTER 4 5 PIR1 REGISTER ADDRESS oCh U 0 R W 0 U 0 U 0 U 0 U 0 U 0 U 0 ADIF R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 Unimplemented Read as 0 bit 6 ADIF A D Converter Interrupt Flag bit 1 An A D conversion completed must be cleared in software 0 The A D conversion is not complete bit 5 0 Unimplemented Read as 0 Eh 1999 Microchip Technology Inc DS30561B page 19 PIC12C67X 4 2 2 6 PCON REGISTER The Power Control PCON Register contains a flag bit to allow differentiation between a Power on Reset POR an external MCLR Reset and a WDT Reset REGISTER 4 6 PCON REGISTER ADDRESS 8Eh U 0 U 0 U 0 U 0 U 0 U 0 R W 0 U 0 POR R Readablebit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 2 Unimplemented Read as 0 bit1 POR Power on R
17. Internal aa POR e 2 PWRT Timeout 32 OSC gt Timeout i Internal s RESET i Watchdog ass Timer i i RESET 134 N 36 h 31 gt i Co VO Pins N TABLE 12 4 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER POWER UP TIMER Parameter Sym Characteristic Min Typt Max Units Conditions No 30 TmcL MCLR Pulse Width low 2 us VDD DN 40 C to 125 C 31 Twdt Watchdog Timer Time out Period 7 18 33 ms VDD 5V 40 C to 125 C No Prescaler 32 Tost Oscillation Start up Timer Period 1024Tosc Tosc OSC1 period 33 Tpwrt Power up Timer Period 28 72 132 ms VDD DN 40 C to 125 C 34 TIOZ VO Hi impedance from MCLR 2 1 us Low or Watchdog Timer Reset i These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1999 Microchip Technology Inc DS30561B page 103 PIC12C67X FIGURE 12 8 TIMERO CLOCK TIMINGS I GP2 TOCKI N J P 40 sl I TMRO Note Refer to Figure 12 4 for load conditions TABLE 12 5 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 40 TtOH TOCKI High Pulse Width No Prescaler 0 5Tcy 20 ns Must also meet With Prescaler 10 EET ns Parameter 42 41 TtOL TO
18. 5 0 a 6 0 EEPROM Peripheral Operation U U trees reada tre U U u u FRA ee nnne ee ee 33 POBRE ITO TEE sa a usa 39 8 0 Analog to Digital Converter A D Module 9 0 Special Features of the CPU 10 0 Instruction Set Summary 69 11 0 Development Suppo fer eter EE re PANT ttt e a Ene EN URS RM ERU 83 12 0 El ctrical Sp cifications u ee EE perenne tme gne A RE ER Nee 89 13 0 DC and AC Characteristics 109 14 0 Packaging Information 115 Appendix A Compatibility sese 119 Appendix B Code for Accessing EEPROM Data Memory iii 119 IN On Line Support Reader Response PIC12C67X Product Identification System sisi 127 To Our Valued Customers Most Current Data Sheet To automatically obtain the most up to date version of this data sheet please register at our Worldwide Web site at http Awww microchip com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page The last character of the literature number is the version number e g DS30000A is version A of document DS30000 New Customer Notification System Register on our web site www microchip com cn to receive the most current information on our products Errata An errata sheet may exist for current devices describing minor operational differences from the data
19. After power up CLRWDT instruction or SLE 1 After power up or by the CLRWDT instruction Writable bit Unimplemented bit read as 0 Value at POR reset bit0 c iow H II IRP Register Bank Select bit used for indirect addressing The IRP bit is reserved always maintain this bit clear RP lt 1 0 gt Register Bank Select bits used for direct addressing Each bank is 128 bytes The RP1 bit is reserved always maintain this bit clear EP instruction 1 The result of an arithmetic or logic operation is zero 0 The result of an arithmetic or logic operation is not zero DC Digit Carry borrow bit ADDWF ADDLW SUBLW SUBWF instructions for borrow the polarity is reversed 1 A carry out from the 4th low order bit of the result occurred 0 No carry out from the 4th low order bit of the result C Carry borrow bit ADDWF ADDLW SUBLW SUBWF instructions 1 A carry out from the most significant bit of the result occurred 0 No carry out from the most significant bit of the result occurred For borrow the polarity is reversed A subtraction is executed by adding the two s complement of the sec ond operand For rotate RRF RLF instructions this bit is loaded with either the high or low order bit of 1999 Microchip Technology Inc DS30561B page 15 PIC12C67X 4 2 2 2 OPTION REGISTER Note To achieve a 1 1 prescaler assignment for the TMRO register assign the
20. Bit Test Skip if Clear label BTFSC fb 0 lt f lt 127 0 lt b lt 7 skip if f lt b gt 0 None 01 10bb bfff ffff If bit b in register f is 0 then the next instruction is skipped tion fetched during the current instruction execution is discarded and a NOP is executed instead making this a 2 cycle instruction 1 1 2 HERE BTFSC FLAG 1 FALSE GoTo PROCESS CO TRUE DE Before Instruction C address HERE After Instruction if FLAG lt 1 gt 0 PC address TRUE if FLAG lt 1 gt 1 PC address FALSE DECH 1999 Microchip Technology Inc DS30561B page 73 PIC12C67X BTFSS Syntax Operands Operation Status Affected Encoding Description Words Cycles Example CALL Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Bit Test f Skip if Set label BTFSS fb 0 lt f lt 127 0 lt b lt 7 skip if f lt b gt 1 None 01 11bb bfff ffff If bit b in register f is 1 then the next instruction is skipped tion fetched during the current instruction execution is discarded and a NOP is executed instead making this a 2 cycle instruction 1 1 2 HERE BTFSS FLAG 1 FALSE GoTo PROCESS CO TRUE DE Before Instruction PC addess HERE After Instruction if FLAG lt 1 gt 0 PC address FALSE if FLAG lt 1 gt 1 PC address TRUE Call Subroutine label CALL k 0
21. C 9 After Instruction REG1 1 W 2 C 1 result is positive Before Instruction REG1 2 W 2 C st 79 After Instruction REG1 0 W 2 C 1 result is zero Before Instruction REG1 1 w 2 C EU After Instruction REG1 OxFF W 2 C 0 result is negative DS30561B page 80 1999 Microchip Technology Inc PIC12C67X SWAPF Swap Nibbles in f Syntax label SWAPF f d Operands 0 lt f lt 127 de 0 1 Operation f lt 3 0 gt dest lt 7 4 gt f lt 7 4 gt dest lt 3 0 gt Status Affected None Encoding 00 1110 dfff ffff Description The upper and lower nibbles of register f are exchanged If d is 0 the result is placed in W regis ter If d is 1 the result is placed in register f Words 1 Cycles 1 Example SWAPF REG 0 Before Instruction REG O0xA5 After Instruction REG1 OXA5 W 0x5A TRIS Load TRIS Register Syntax label TRIS f Operands 5 lt f lt 7 Operation W TRIS register f Status Affected None Encoding 00 0000 0110 Offf Description The instruction is supported for code compatibility with the PIC16C5X products Since TRIS registers are readable and writ able the user can directly address them Words 1 Cycles 1 Example To maintain upward compatibility with future PIC12C67X products do not use this instruction XORLW Syntax Operands Operation Status Affec
22. MMMMMM CE674 Legend MM M Microchip part number information XX X Customer specific information AA Year code last 2 digits of calendar year BB Week code week of January 1 is week 01 C Facility code of the plant at which wafer is manufactured O Outside Vendor C 5 Line S 6 Line H 8 Line D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note In the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information Standard OTP marking consists of Microchip part number year code week code facility code mask rev and assembly code For OTP marking beyond this certain price adders apply Please check with your Microchip Sales Office For QTP devices any special marking adders are included in QTP price 1999 Microchip Technology Inc DS30561B page 115 PIC12C67X 8 Lead Plastic Dual In line P 300 mil PDIP IR E1 r I i i D C J 2 nr 4 1 2 Y Lg E m dB Lag eB Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN
23. Return from Interrupt label RETFIE None TOS gt PC 1 GIE None 00 0000 0000 1001 Return from Interrupt Stack is POPed and Top of Stack TOS is loaded in the PC Interrupts are enabled by setting Global Inter rupt Enable bit GIE INTCON lt 7 gt This is a two cycle instruction 2 RETFIE After Interrupt PC GIE TOS Return with Literal in W label RETLW k 0 lt k lt 255 k gt W TOS PC None 11 Olxx kkkk kkkk The W register is loaded with the eight bit literal k The program counter is loaded from the top of the stack the return address This is a two cycle instruction 1 2 CALL TABLE W contains table offset value W now has table value ADDWF PC W offset RETLW k1 Begin table RETIWK2 RETLW kn End of table Before Instruction W 0x07 After Instruction W value of k8 DS30561B page 78 1999 Microchip Technology Inc PIC12C67X RETURN Syntax Operands Operation Status Affected Encoding Description Words Cycles Example RLF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Return from Subroutine label RETURN None TOS PC None 00 0000 0000 1000 Return from subroutine The stack is POPed and the top of the stack TOS is loaded into the program counter This is a two cycle instruct
24. Type Freq C1 ES XT 455kHz 22 100 as Hot 2 0 MHz 1 15 68 pF sh 15 68 pF pF 15 68 pF HS 4 AN da 10 68 pF 10 68 pF Ke Z 10 22 pF 10 22 pF ea lues are for design guidance only Since each resonator has its own characteristics the user should consult the resonator manufacturer for appropriate values of external components TABLE 9 2 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR PIC12C67X Osc Resonator Cap Range Cap Range Type Freg C1 C2 LP 32 kHz 15 pF 15 pF XT 100 kHz 15 30 pF 100kHz 15 30 pF 30 47 200kHz 15 30 pF 163 pF 0 F 200kHz 15 00 pF 455 kHz E 15 100 pF 1 MHz 15 30 pF N 30 pF 15 30 pF 8 MHz 15 30 pF 15 30 pF 10 MHz 15 30 pF 15 30 pF Z 15 47 pF 15 47pF OS Z 15 30pF 15 30pF Note 1 For VDD gt 4 5V C1 C2 30 pF is recommended These values are for design guidance only Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specifi cation Since each crystal has its own characteris tics the user should consult the crystal manufacturer for appropriate values of external components DS30561B page 54 1999 Microchip Technology Inc PIC12C67X 9 2 23 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a pre packaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit Pre packaged oscillators provide
25. d is 0 the result is placed in the W register If d is 1 the result is placed back in reg ister f 1 1 INCF CNT 1 Before Instruction CNT OxFF Z 0 After Instruction 0x00 Z INCFSZ Syntax Operands Operation Status Affected Encoding Description Words Cycles Example IORLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Increment f Skip if 0 label INCFSZ f d O lt f lt 127 de 0 1 f 1 dest skip if result 0 None 00 1111 dfff EEEE The contents of register f are incremented If d is 0 the result is placed in the W register If d is 1 the result is placed back in reg ister f If the result is 0 the next instruc tion which is already fetched is discarded A NOP is executed instead making it a two cycle instruction 1 1 2 HERE INCFSZ CNT 1 GOTO LOOP CONTINUE Before Instruction PC address HERE After Instruction CNT CNT 1 if CNT 0 PC address CONTINUE if CNT 0 PC address HERE 1 Inclusive OR Literal with W label IORLW k 0 lt k lt 255 W OR k gt W Z 11 1000 kkkk kkkk The contents of the W register are OR ed with the eight bit literal k The result is placed in the W reg ister 1 1 IORLW 0x35 Before Instruction W Ox9A After Instruction W OxBF 1 Z 1999 Microchip Technology Inc PIC12C67X
26. unless otherwise specified DC CHARACTERISTICS Operating temperature 0 C lt TA 70 C commercial 40 C lt TA lt 85 C industrial Param Characteristic Sym Min Typt Max Units Conditions No DOO1 Supply Voltage VDD 2 5 5 5 V D002 RAM Data Retention VDR 1 5 V Device in SLEEP mode Voltage D003 VDD Start Voltage to VPOR Vss V See section on Power on Reset for details ensure Power on Reset D004 VDD Rise Rate to ensure SVDD 0 05 V ms See section on Power on Reset for details Power on Reset DO10 Supply Current IDD 0 4 2 1 mA Fosc 4MHz VDD 2 5V XT and EXTRC mode Note 4 DO10C 0 4 2 1 mA Fosc 4MHz VDD 2 5V INTRC mode Note 6 D010A 15 33 uA Fosc 32kHz VDD 2 5V WDT disabled LP mode Industrial Temperature D020 Power down Current PD D021 0 2 5 HA VDD 2 5V Commercial D021B 0 2 6 HA VDD 2 5V Industrial Watchdog Timer Current AIWDT 2 0 4 HA VDD 2 5V Commercial 2 0 6 HA VDD 2 5V Industrial LP Oscillator Operating Fosc 0 200 kHz All temperatures Frequency INTRC EXTRC Oscillator 4 6 MHz All temperatures Operating Frequency XT Oscillator Operating 0 4 MHz All temperatures Frequency HS Oscillator Operating 0 10 MHz All temperatures Frequency These parameters are characterized but not tested Note 1 Data in Typical Typ column is based on characterizat
27. 0 8VDD VDD V D042A OSC1 XT HS and LP 0 7VDD VDD V Note 1 D043 OSC1 in EXTRC mode 0 9Vpp VDD V Input Leakage Current Notes 2 3 D060 VO ports liL 1 uA Vss lt VPIN lt VDD Pin at hi impedance D061 GP3 MCLR Note 5 30 uA Vss lt VPIN lt VDD D061A GP3 Note 6 5 HA Vss lt VPIN lt VDD D062 GP2 TOCKI 45 HA Vss lt VPIN lt VDD D063 OSC1 5 HA Vss lt VPIN lt VDD XT HS and LP osc configuration D070 GPIO weak pull up current Note 4 IPUR 50 250 400 HA VDD DN VPIN VSS MCLR pull up current 30 HA VDD 5V VPIN Vss Output Low Voltage D080 VO ports VOL 0 6 V loL 8 5 mA VDD 4 5V 40 C to 85 C DOBOA 0 6 V loi 7 0 mA VDD 4 5V 40 C to 125 C D083 OSC2 CLKOUT 0 6 V dor TBD Vpp 4 5V 40 C to 85 C D083A 0 6 V lot TBD VoD 4 5V 40 C to 125 C T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In EXTRC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC12C67X be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent nor mal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as
28. 44 pin PLCC microcontrollers with a LCD Module All the neces sary hardware and software is included to run the basic demonstration programs The user can pro gram the sample microcontrollers provided with the PICDEM 3 board on a PRO MATE II program mer or PICSTART Plus with an adapter socket and easily test firmware The MPLAB ICE emulator may also be used with the PICDEM 3 board to test firm ware Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket s Some of the features include an RS 232 interface push button switches a potenti ometer for simulated analog input a thermistor and separate headers for connection to an external LCD module and a keypad Also provided on the PICDEM 3 board is an LCD panel with 4 commons and 12 seg ments that is capable of displaying time temperature and day of the week The PICDEM 3 provides an addi tional RS 232 interface and Windows 3 1 software for showing the demultiplexed LCD signals on a PC A sim ple serial interface allows the user to construct a hard ware demultiplexer for the LCD signals 1999 Microchip Technology Inc DS30561B page 85 PIC12C67X 11 16 PICDEM 17 The PICDEM 17 is an evaluation board that demon strates the capabilities of several Microchip microcon trollers including PIC17C752 PIC17C756 PIC17C762 and PIC17C766 All necessary hardware is included to run basic demo programs whi
29. A D MINIMUM CHARGING TIME VHOLD VREF VREF 512 1 eC T CHOLD Ric Rss Rs or Tc 51 2 pF 1 KO Rss Rs In 1 511 Example 8 1 shows the calculation of the minimum required acquisition time TACQ This calculation is based on the following system assumptions Rs 10 ka 1 2 LSb error VDD 5V gt Rss 7 ko Temp system max 50 C VHOLD 0 t 0 TACQ Internal Amplifier Settling Time Holding Capacitor Charging Time Temperature Coefficient TACQ 5 us Tc Temp 25 C 0 05 us C TC CHOLD Ric Rss Rs In 1 512 51 2 pF 1 KO 7 kO 10 kQ In 0 0020 51 2 pF 18 kQ In 0 0020 0 921 us 6 2146 5 724 us Taca 5 us 5 724 us 50 C 25 C 0 05 us C 10 724 us 1 25 us 11 974 us FIGURE 8 2 ANALOG INPUT MODEL VDD T Sampling DENERI Vr 0 6V EOM Rs RAX Ric 1k SS Rss M t W M i ba RE aha EE ee CHOLD va CPN L ste L DAC capacitance Di BpF vr oev S RODA 51 2 pF vss Legend CPIN input capacitance L VT threshold voltage SE lleakage leakage current at the pin due to VDD 4V various junctions 3V RIC interconnect resistance 2V SS sampling switch MEE EE EE k s CHOLD sample hold capacitance from DAC 567891011 Sampling Switch KO DS30561B page 48 1999 Microchip Technology Inc PIC12C67X 8 2 Selecting the A D Conversion Clock The A D conversion
30. FCLK 100 kHz 4 5V lt Vcc lt 5 5V E Temp range 100 3 0V lt Vcc lt 4 5V 400 4 5V Vcc lt 5 5V Clock high time THIGH 4000 ns 4 5V lt Vcc lt 5 5V E Temp range 4000 3 0V lt Vcc lt 4 5V 600 4 5V lt Vcc lt 5 5V Clock low time TLOW 4700 ns 4 5V lt Vcc lt 5 5V E Temp range 4700 3 0V lt Vcc lt 4 5V 1300 4 5V Vcc lt 5 5V SDA and SCL rise time TR 1000 ns 4 5V lt Vcc lt 5 5V E Temp range Note 1 1000 3 0V lt Vcc lt 4 5V 300 4 5V Vcc lt 5 5V SDA and SCL fall time TF 300 ns Note 1 START condition hold time THD STA 4000 ns 4 5V lt Vcc lt 5 5V E Temp range 4000 3 0V lt Vcc lt 4 5V 600 4 5V Vcc lt 5 5V START condition setup time Tsu STA 4700 ns 4 5V lt Vcc lt 5 5V E Temp range 4700 3 0V lt Vcc lt 4 5V 600 4 5V Vcc lt 5 5V Data input hold time THD DAT 0 CE ns Note 2 Data input setup time TSU DAT 250 ns 4 5V lt Vcc lt 5 5V E Temp range 250 3 0V lt Vcc lt 4 5V 100 4 5V Vcc lt 5 5V STOP condition setup time TSU STO 4000 ns 4 5V lt Vcc lt 5 5V E Temp range 4000 3 0V lt Vcc lt 4 5V 600 4 5V lt Vcc lt 5 5V Output valid from clock TAA 3500 ns 4 5V lt Vcc lt 5 5V E Temp range Note 2 3500 3 0V lt Vcc lt 4 5V 900 4 5V lt Vcc lt 5 5V Bus free time Time the bus must TBUF 4700 ns 4 5V lt Vcc lt 5 5V E Temp range be free bef
31. Fax 61 2 9868 6755 China Beijing Microchip Technology Consulting Shanghai Co Ltd Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg No 6 Chaoyangmen Beidajie Beijing 100027 No China Tel 86 10 85282100 Fax 86 10 85282104 China Chengdu Microchip Technology Consulting Shanghai Co Ltd Chengdu Liaison Office Rm 2401 24th Floor Ming Xing Financial Tower No 88 TIDU Street Chengdu 610016 China Tel 86 28 6766200 Fax 86 28 6766599 China Fuzhou Microchip Technology Consulting Shanghai Co Ltd Fuzhou Liaison Office Unit 28F World Trade Plaza No 71 Wusi Road Fuzhou 350001 China Tel 86 591 7503506 Fax 86 591 7503521 China Shanghai Microchip Technology Consulting Shanghai Co Ltd Room 701 Bldg B Far East International Plaza No 317 Xian Xia Road Shanghai 200051 Tel 86 21 6275 5700 Fax 86 21 6275 5060 China Shenzhen Microchip Technology Consulting Shanghai Co Ltd Shenzhen Liaison Office Rm 1315 13 F Shenzhen Kerry Centre Renminnan Lu Shenzhen 518001 China Tel 86 755 2350361 Fax 86 755 2366086 Hong Kong Microchip Technology Hongkong Ltd Unit 901 6 Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong N T Hong Kong Tel 852 2401 1200 Fax 852 2401 3431 India Microchip Technology Inc India Liaison Office Divyasree Chambers 1 Floor Wing A A3 A4 No 11 O Shaugnessey Road Bangalore 560 025 India Tel 91 80 2290061 Fax 91 80 22900
32. HS INTRC EP XT a aaa re need i Oscillator Configurations 54 Oscillator Types EXT RG ahead iate aie ie 54 Package Marking Information 115 Packaging Information PCL Register POLATH ZS SA de ee a le oe ee latata ala PICDEM 1 Low Cost PICmicro Demo Board PICDEM 2 Low Cost PIC16CXX Demo Board oa PICDEM 3 Low Cost PIC16CXXX Demo Board 85 PICSTART Plus Entry Level Development System 85 PIET Redistef ies er eis u ee dee FEE SEAS 18 Pinout Description PIC12CE67X 9 PIR1 Register 19 POP 22 Oscillator Start up Timer OST 59 58 Power Control Register PCON 58 Power on Reset POR Power up Timer PWRT Power Up Timer PWRT eene Time out Sequencoe Time out Sequence on Power up 1999 Microchip Technology Inc PIC12C67X Power down Mode SLEEP sese Prescaler Switching Between Timer0 and WDT PRO MATES II Universal Programmer Program Branches eeen Program Memory MT 16 PS1 bit 16 RG OSCAR EE Read Modify Write AA Read Modify Write adel EE Na teva Registers Map
33. High High BUF Bus free Low Low Tcc st I2C specifications only CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 12 4 LOAD CONDITIONS Load condition 1 VDD 2 o RL Pin CL v Vss RL 464Q CL 50 pF forall pins except OSC2 15pF for OSC2 output Load condition 2 1999 Microchip Technology Inc DS30561B page 99 PIC12C67X 12 6 Timing Diagrams and Specifications FIGURE 12 5 EXTERNAL CLOCK TIMING Q Gi 4 Q Q Q4 Gr d H isa 2 B CLKOUT TABLE 12 1 CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No Fosc External CLKIN Frequency DC 4 MHz XT and EXTRC osc mode Note 1 DG 4 MHz HS osc mode PIC12CE67X 04 DC 10 MHz HS osc mode PIC12CE67X 10 DC 200 kHz LP osc mode Oscillator Frequency DC 4 MHz EXTRC osc mode Note 1 455 4 MHz XT osc mode 4 4 MHz HS osc mode PIC12CE67X 04 4 10 MHz HS osc mode PIC12CE67X 10 5 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 ns XT and EXTRC osc mode Note 1 250 ns HS osc mode PIC12CE67X 04 100 ns HS osc mode PIC12CE67X 10 5 us LP osc mode Oscillator Period 250 ns EXTRC osc mode Note 1 250 10 000 ns XT osc mode 250 250 ns HS osc mode PIC12CE67X 04 100
34. Microchip Technology Inc DS30561B page 47 PIC12C67X Sch A D Sampling Requirements Note 1 The reference voltage VREF has no For the A D converter to meet its specified accuracy effect on the equation since it cancels the charge holding capacitor CHOLD must be allowed itself out a See s e de SE E The 2 The charge holding capacitor CHOLD is i ap MOCE IS SNOWN AE cia goire not discharged after each conversion impedance RS and the internal sampling switch RSS impedance directly affect the time reguired to charge 3 The maximum recommended impedance the capacitor CHOLD The sampling switch Rss for analog sources is 10 k This is impedance varies over the device voltage VDD see required to meet the pin leakage specifi Figure 8 2 The maximum recommended imped cation ance for analog sources is 10 ko After the analog 4 After a conversion has completed a input channel is selected changed this acquisition 2 0 TaD delay must complete before must be done before the conversion can be started acquisition can begin again During this To calculate the minimum acquisition time Equation 8 1 time the holding capacitor is not con may be used This equation assumes that 1 2 LSb error nected to the selected A D input channel is used 512 steps for the A D The 1 2 LSb erroristhe maximum error allowed for the A D to meet its specified EXAMPLE 8 1 CALCULATING THE resolution MINIMUM REQUIRED SAMPLE TIME EQUATION 8 1
35. Nota physical register DS30561B page 12 1999 Microchip Technology Inc PIC12C67X TABLE 4 1 PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on all other Reset Resets Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory not a physical register 0000 0000 0000 0000 01h TMRO Timer0 modules register XXXX XXXX uuuu uuuu o2h PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 03h STATUS IRP RP1 4 RPO TO PD 7 DC C 0001 1xxx 0004 quuu o4h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h GPIO SCLG6 spAO GP5 GP4 GP3 GP2 GP1 GPO llxx xxxx lluu uuuu 06h Unimplemented 07h Unimplemented 08h Unimplemented 09h Unimplemented DANI PCLATH Write Buffer for the upper 5 bits of the Program Counter 0 0000 0 0000 ogn INTCON GIE PEIE TOIE INTE GPIE TOIF INTF GPIF 0000 000x 0000 000u OCh PIR1 ADIF 0 0 ODh Unimplemented OEh Unimplemented OFh Unimplemented 10h Unimplemented 11h Unimplemented See 12h Unimplemented 13h Unimplement
36. a circular buffer This means that after the stack has been PUSHed eight times the ninth push overwrites the value that was stored from the first push The tenth push overwrites the second push and so on Note 1 There are no status bits to indicate stack overflow or stack underflow conditions 2 There are no instructions mnemonics called PUSH or POP These are actions that occur from the execution of the CALL RETURN RETLW and RETFIE instructions or the vectoring to an inter rupt address 4 4 Program Memory Paging The PIC12C67X ignores both paging bits PCLATH lt 4 3 gt which are used to access program memory when more than one page is available The use of PCLATH 4 3 as general purpose read write bits for the PIC12C67X is not recommended since this may affect upward compatibility with future products DS30561B page 22 1999 Microchip Technology Inc PIC12C67X 4 5 Indirect Addressing INDF and FSR Registers The INDF Register is not a physical register Address ing the INDF Register will cause indirect addressing Any instruction using the INDF register actually accesses the register pointed to by the File Select Reg ister FSR Reading the INDF Register itself indirectly FSR 0 will read 00h Writing to the INDF Register indirectly results in a no operation although status bits may be affected An effective 9 bit address is obtained by concatenating the 8 bit FSR Register
37. an impact on the current consumption a The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all VO pins tristated pulled to Vss TOCKI VDD MCLR VDD WDT disabled b For standby current measurements the conditions are the same except that the device is in SLEEP mode 4 For EXTRC osc configuration current through REXT is not included The current through the resistor can be estimated by the formula Ir VDD 2REXT mA with REXT in kOhm 5 The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VDD or Vss 6 INTRC calibration value is for 4MHz nominal at 5V 25 C DS30561B page 92 1999 Microchip Technology Inc PIC12C67X Standard Operating Conditions unless otherwise specified DC CHARACTERISTICS Operating Temperature 0 C lt TA lt 70 C commercial 40 C lt TA lt 85 C industrial 40 C lt TA lt 125 C extended Parm Characteristic Sym Min Typ Max Units Conditions No LP Oscillator Operating Fosc 0 200 kHz All temperatures Frequency INTRC EXTRC Oscillator 46 MHz All temperatures Operating Frequency XT Oscillator Operating 0 4 MHz All temperatures Frequency HS Oscillator Operating 0 10 MHz All temperatures Frequency Thes
38. current 30 MA VDD 5V VPIN Vss Output Low Voltage D080 I O ports VOL 0 6 V lot 8 5 mA VDD 4 5V 40 C to 85 C DO80A 0 6 V IoL 7 0 mA VDD 4 5V 40 C to 125 C D083 OSC2 CLKOUT 0 6 V loi 1 6 mA VDD 4 5V 40 C to 85 C D083A 0 6 V loc 1 2 mA VDD 4 5V 40 C to 125 C T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In EXTRC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC12C67X be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin 4 Does not include GP3 For GP3 see parameters D061 and DO61A 5 This spec applies to GP3 MCLR configured as external MCLR and GP3 MCLR configured as input with internal pull up enabled 6 This spec applies when GP3 MCLR is configured as an input with pull up disabled The leakage current of the MCLR circuit is higher than the standard I O logic 1999 Microchip Technology Inc DS30561B page 95 PIC12C67X Standard Operating Conditions unless otherwise specified Operating temperature 0 C lt TA
39. defined as input inputs are at hi impedance since the UO control registers are all set 5 1 GPIO GPIO is an 8 bit I O register Only the low order 6 bits are used GP lt 5 0 gt Bits 6 and 7 SDA and SCL respectively are used by the EEPROM peripheral on the PIC12CE673 674 Refer to Section 6 0 and Appendix B for use of SDA and SCL Please note that GP3 is an input only pin The configuration word can set several l O s to alternate functions When acting as alternate functions the pins will read as 0 during port read Pins GPO GP1 and GP3 can be configured with weak pull ups and also with interrupt on change The interrupt on change and weak pull up functions are not pin selectable If pin 4 GP3 is configured as MCLR a weak pull up is always on Interrupt on change for this pin is not set and GP3 will read as 0 Interrupt on change is enabled by setting bit GPIE INTCON lt 3 gt Note that external oscillator use overrides the GPIO functions on GP4 and GPS 5 2 TRIS Register This register controls the data direction for GPIO A 1 from a TRIS Register bit puts the corresponding output driver in a hi impedance mode A 0 puts the contents of the output data latch on the selected pins enabling the output buffer The exceptions are GP3 which is input only and its TRIS bit will always read as 1 while GP6 and GP7 TRIS bits will read as 0 Note A read of the ports reads the pins not the output data
40. guidance only and are not tested Note 1 When A D is off it will not consume any current other than minor leakage current The power down current spec includes any such leakage from the A D module 2 VREF current is from GP1 pin or VDD pin whichever is selected as reference input 3 The A D conversion result never decreases with an increase in the Input Voltage and has no missing codes 1999 Microchip Technology Inc DS30561B page 105 PIC12C67X FIGURE 12 9 A D CONVERSION TIMING BSF ADCONO GOX Q4 A D DATA ADRES ADIF GO SAMPLE 134 lt Tosc 2 A D CLK 4 132 re age ae OLD DATA Y NEW DATA SAMPLING STOPPED DONE Note 1 lf the A D clock source is selected as RC a time of TCY is added before the A D clock starts This allows the SLEEP instruction to be executed TABLE 12 8 A D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 130 TAD A D clock period PIC12C67X 1 6 us Tosc based VREF gt 3 0V PIC12LC67X 2 0 us Tosc based VREF full range PIC12C67X 2 0 4 0 6 0 us A D RC Mode PIC12LC67X 3 0 6 0 9 0 us A D RC Mode 131 TCNV Conversion time not including S H 11 11 TAD time Note 1 132 TACQ Acquisition
41. in software 9 6 Context Saving During Interrupts During an interrupt only the return PC value is saved on the stack Typically users may wish to save key reg isters during an interrupt i e W register and STATUS register This will have to be implemented in software Example 9 1 shows the storing and restoring of the STATUS and W registers The register W TEMP must be defined in both banks and must be defined at the same offset from the bank base address i e if W_TEMP is defined at 0x20 in bank 0 it must also be defined at 0xA0 in bank 1 Example 9 2 shows the saving and restoring of STA TUS and W using RAM locations 0x70 Ox7F W_TEMP is defined at 0x70 and STATUS_TEMP is defined at 0x71 The example a Stores the W register b Stores the STATUS register in bank 0 c Executes the ISR code d Restores the STATUS register and bank select bit e Restores the W register f Returns from interrupt EXAMPLE 9 1 SAVING STATUS AND W REGISTERS USING GENERAL PURPOSE RAM 0x20 Ox6F MOVWE W_TEMP Copy W to TEMP register could be bank one or zero SWAPF STATUS W Swap status to be saved into W BCF STATUS RPO Change to bank zero regardless of current bank MOVWE STATUS_TEMP Save status to bank zero STATUS_TEMP register ISR SWAPE STATUS TEMP W Swap STATUS TEMP register into W sets bank to original state MOVWE STATUS Move W
42. in the device number 1 C as in PIC12C671 These devices have EPROM type memory and operate over the standard voltage range 2 LC as in PIC12LC671 These devices have EPROM type memory and operate over an extended voltage range 3 CE as in PIC12CE674 These devices have EPROM type memory EEPROM data memory and operate over the standard voltage range 4 LCE as in PIC12LCE674 These devices have EPROM type memory EEPROM data memory and operate over an extended voltage range 2 1 UV Erasable Devices The UV erasable version offered in windowed pack age is optimal for prototype development and pilot pro grams The UV erasable version can be erased and repro grammed to any of the configuration modes Microchip s PICSTART Plus and PRO MATE pro grammers both support the PIC12C67X Third party programmers also are available refer to the Microchip Third Party Guide for a list of sources Note Please note that erasing the device will also erase the pre programmed internal calibration value for the internal oscillator The calibration value must be saved prior to erasing the part 2 2 One Time Programmable OTP Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications The OTP devices packaged in plastic packages per mit the user to program them once In addition to the program memory the co
43. nominal time out period of 18 ms with no prescaler The time out periods vary with tempera ture VDD and process variations from part to part see DC specs If longer time out periods are desired a prescaler with a division ratio of up to 1 128 can be assigned to the WDT under software control by writing to the OPTION register Thus time out periods up to 2 3 seconds can be realized The CLRWDT and SLEEP instructions clear the WDT and the postscaler if assigned to the WDT and prevent it from timing out early and generating a premature device RESET condition The TO bit in the STATUS register will be cleared upon a Watchdog Timer time out 9 7 2 WDT PROGRAMMING CONSIDERATIONS It should also be taken into account that under worst case conditions VDD Min Temperature Max and max WDT prescaler it may take several seconds before a WDT time out occurs Note When the prescaler is assigned to the WDT always execute a CLRWDT instruction before changing the prescale value other wise a WDT reset may occur See Example 7 1 and Example 7 2 for changing pres caler between WDT and Timer0 FIGURE 9 15 WATCHDOG TIMER BLOCK DIAGRAM From TMRO Clock Source Figure 7 5 Lo 11 M re Postscaler WDT Timer e U X 8 Y A 8 to 1MUX PS lt 2 0 gt WDT PSA Enable Bit To TMRO Figure 7 5
44. pro gram data are then supplied to or from the device Note Microchip does not recommend code pro depending if the command was a load or a read For tecting windowed devices complete details of serial programming please refer to the PIC12C67X Programming Specifications bs in FIGURE TYPICAL IN CIRCUIT S Four memory locations 2000h 2003h are designated M SC PROGRAMMING S FRIAL as ID locations where the user can store checksum or If the code protection bit s have not been pro grammed the on chip program memory can be read out for verification purposes other code identification numbers These locations are CONNECTION not accessible during normal execution but are read able and writable during program verify It is recom i To Normal mended that only the 4 least significant bits of the ID External Connections location are used Connector PIC12C67X Signals i 9 11 In Circuit Serial Programming 5V VoD PIC12C67X microcontrollers can be serially pro OV l Vss grammed while in the end application circuit This is VPP e MGLR VPP simply done with two lines for clock and data and three i other lines for power ground and the programming volt CLK I GP1 age This allows customers to manufacture boards with unprogrammed devices and then program the micro Data VO GPO controller just before shipping the product This also allows the most
45. read as 0 Note 1 When the wake up is due to an interrupt and the GIE bit is set the PC is loaded with the interrupt vector 0004h TABLE 9 7 INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Power on Reset MCLR Resets Wake up via WDT Reset WDT or Interrupt w XXXX XXXX uuuu uuuu uuuu uuuu INDF 0000 0000 0000 0000 0000 0000 TMRO XXXX XXXX uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 pc 10 STATUS 0001 1xxx 000q quuu 9 uuuq quuu FSR XXXX XXXX uuuu uuuu uuuu uuuu GPIO 11xx xxxx 11uu uuuu 11uu uuuu PIC12CE67X GPIO XX XXXX uu uuuu uu uuuu PIC12C67X PCLATH 0 0000 0 0000 u uuuu INTCON 0000 000x 0000 000u uuuu uqqa l PIR1 aom e 0 q ADCONO 0000 0000 0000 0000 uuuu uquu OPTION 1111 1111 1111 1111 uuuu uuuu TRIS 11 1111 11 1111 uu uuuu PIE sos Sas u PCON 0 BERUS AE onus OSCCAL 0111 00 uuuu uu uuuu uu ADCON 1 000 000 uuu Legend u unchanged x unknown unimplemented bit read as 0 q value depends on condition Note 1 One or more bits in INTCON and PIR1 will be affected to cause wake up 2 When the wake up is due to an interrupt and the GIE bit is set the PC is loaded with the interrupt vector 0004h See Table 9 5 for reset value for specific condition If wake up was due to A D completing then bit 6 1 all other interrupts generating a wake up will cause b
46. recent firmware or a custom firmware i to be programmed i vog The device is placed into a program verify mode by ereman holding the GP1 and GPO pins low while raising the MCLR VPP pin from VIL to VIHH see programming specification GP1 clock becomes the programming clock and GPO data becomes the programming data Both GPO and GP1 are Schmitt Trigger inputs in this mode 1999 Microchip Technology Inc DS30561B page 67 PIC12C67X NOTES ae DS30561B page 68 1999 Microchip Technology Inc PIC12C67X 10 0 INSTRUCTION SET SUMMARY Each PIC12C67X instruction is a 14 bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction The PIC12C67X instruc tion set summary in Table 10 2 lists byte oriented bit oriented and literal and control operations Table 10 1 shows the opcode field descriptions For byte oriented instructions f represents a file reg ister designator and d represents a destination desig nator The file register designator specifies which file register is to be used by the instruction The destination designator specifies where the result of the operation is to be placed If d is zero the result is placed in the W register If d is one the result is placed in the file register specified in the instruction For bit oriented instructions b represents a bit field designator which sel
47. sheet and recommended workarounds As device documentation issues become known to us we will publish an errata sheet The errata will specify the revi sion of silicon and revision of document to which it applies To determine if an errata sheet exists for a particular device please check with one of the following Microchip s Worldwide Web site http www microchip com Your local Microchip sales office see last page The Microchip Corporate Literature Center U S FAX 480 786 7277 When contacting a sales office or the literature center please specify which device revision of silicon and data sheet include liter ature number you are using Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation We have spent a great deal of time to ensure that this document is correct However we realize that we may have missed a few things If you find any information that is missing or appears in error please Fill out and mail in the reader response form in the back of this data sheet E mail us at webmaster microchip com We appreciate your assistance in making this a better document DS30561B page 2 1999 Microchip Technology Inc PIC12C67X 1 0 GENERAL DESCRIPTION The PIC12C67X devices are low cost high perfor mance CMOS fully static 8 bit microcontrollers with integrated analog to digital A D converter and EEPROM data memory EEPROM on PIC1
48. skip if result 0 None 00 1011 dfff ffff The contents of register f are decremented If d is 0 the result is placed in the W register If d is 1 the result is placed back in reg ister f If the result is O the next instruc tion which is already fetched is discarded A NOP is executed instead making it a two cycle instruction 1 1 2 HERE DECFSZ CNT 1 GOTO LOOP CONTINUE Before Instruction PC address HERE After Instruction OCNT 1 ifCNT 0 PC address CONTINUE if CNT 0 PC address HERE 1 1999 Microchip Technology Inc DS30561B page 75 PIC12C67X GOTO Syntax Operands Operation Status Affected Encoding Description Words Cycles Example INCF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example DS30561B page 76 Unconditional Branch label GOTO k 0 lt k lt 2047 k gt PC lt 10 0 gt PCLATH lt 4 3 gt PC lt 12 11 gt None 10 lkkk kkkk kkkk GOTO is an unconditional branch The eleven bit immediate value is loaded into PC bits lt 10 0 gt The upper bits of PC are loaded from PCLATH lt 4 3 gt GOTO is a two cycle instruction 1 2 GOTO THERE After Instruction C Address THERE Increment f label INCF fd O lt f lt 127 de 0 1 f 1 gt dest Z 00 1010 dfff ELLE The contents of register f are incremented If
49. structure and subject 5 What deletions from the data sheet could be made without affecting the overall usefulness 6 Isthere any incorrect or misleading information what and where 7 How would you improve this document 8 How would you improve our software systems and silicon products DS30561B page 126 1999 Microchip Technology Inc PIC12C67X PIC12C67X PRODUCT IDENTIFICATION SYSTEM PART NO XX X XX XXX Examples E Pattern Special Requirements a PIC12CE673 04 P Commercial Temp Package P 300 mil PDIP PDIP Package 4 MHz JW 300 mil Windowed Ceramic Side Brazed normal VDD limits SM a A b PIC12CE673 04 P Temperature EA Se Industrial Temp PDIP Range 20 to 125 C package 4 MHz normal VDD limits Frequency e is re 200 Kile c PIC12CE673 101 P Range e Z F Industrial Temp PDIP package 10 MHz normal VDD limits Device PIC12CE673 d PIC12C671 04 P PIC12CE674 ial Temp PIC12LCE673 PDIP Package 4 MHz PIC12LCE674 I PIC12C671 normal VDD limits PIC12C672 e PIC12C671 04VSM Aa as amp ru 3818 on hait reel for only PIC12LC671 package 4 MHz normal PIC12LC672 Vpp limits PIC12LC671T Tape amp reel for SOIC only f PIC12C671 041 P PIC12LC672T Tape amp reel for SOIC only Industrial Temp PDIP package 4 MHz normal VDD limits JW Devices are UV erasable and can be programmed to any device configuration JW Devices meet the electrical reguir
50. the previous eight bits of data sending data 6 2 Device Addressing FIGURE 6 5 CONTROL BYTE FORMAT After generating a START condition the processor Read Write Bit transmits a control byte consisting of a EEPROM address and a Read Write bit that indicates what type Device Select Don t Care of operation is to be performed The EEPROM address Bits Bits consists of a 4 bit device code 1010 followed by three don t care bits s 1 0 1 0 X X X TE The last bit of the control byte determines the operation to be performed When set to a one a read operation EEPROM Address is selected and when set to a zero a write operation is selected Figure 6 5 The bus is monitored for its cor Start Condition Acknowledge Condition responding EEPROM address all the time lt generates an acknowledge bit if the EEPROM address was true and it is not in a programming mode 1999 Microchip Technology Inc DS30561B page 35 PIC12C67X 6 3 Write Operations 6 3 1 BYTE WRITE Following the start signal from the processor the device code 4 bits the don t care bits 3 bits and the R W bit which is a logic low are placed onto the bus by the processor This indicates to the addressed EEPROM that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle Therefore the next byte transmitted by the processor is the word address and will be written into the address pointer Only the l
51. time Note 2 20 us 5 us The minimum time is the amplifier setting time This may be used if the new input voltage has not changed by more than 1 LSb i e 20 0 mV 5 12V from the last sampled voltage as stated on CHOLD 134 Teo Q4 to A D clock start Tosc 2 8 lf the A D clock source is selected as RC a time of Tcy is added before the A D clock starts This allows the SLEEP instruction to be exe cuted 135 Tswc Switching from convert gt sample time 1 58 TAD These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested This specification ensured by design Note 1 ADRES register may be read on the following Tcy cycle 2 See Section 8 1 for min conditions DS30561B page 106 1999 Microchip Technology Inc PIC12C67X TABLE 12 9 EEPROM MEMORY BUS TIMING REQUIREMENTS PIC12CE673 674 ONLY AC Characteristics Standard Operating Conditions unless otherwise specified Operating Temperature 0 C lt TA lt 70 C Vcc 3 0V to 5 5V commercial 40 C lt TA lt 85 C Vcc 3 0V to 5 5V industrial 40 C lt TA 125 C Vcc 4 5V to 5 5V extended Operating Voltage VDD range is described in Section 12 1 Parameter Symbol Min Max Units Conditions Clock frequency
52. 0 gt to select one of these seven modes e LP Low Power Crystal HS High Speed Crystal Resonator XT Crystal Resonator INTRC Internal 4 MHz Oscillator EXTRC External Resistor Capacitor Can be configured to support CLKOUT 9 2 2 CRYSTAL OSCILLATOR CERAMIC RESONATORS In XT HS or LP modes a crystal or ceramic resonator is connected to the GP5 OSC1 CLKIN and GP4 OSC2 pins to establish oscillation Figure 9 1 The PIC12C67X oscillator design requires the use of a parallel cut crystal Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications When in XT HS or LP modes the device can have an external clock source drive the GP5 OSC1 CLKIN pin Figure 9 2 FIGURE 9 1 CRYSTAL OPERATION OR CERAMIC RESONATOR XT HS OR LP OSC CONFIGURATION c1 OSC PIC12C67X ch ds d C XTAL REO To internal logic H ns Note 1 See Capacitor Selection tables for recommended values of C1 and C2 2 A series resistor RS may be required for AT strip cut crystals 3 RF varies with the oscillator mode selected approx value 10 MO FIGURE 9 2 EXTERNAL CLOCK INPUT OPERATION XT HS OR LP OSC CONFIGURATION Clock from gt OSC1 ext system PIC12C67X Open OSC2 TABLE 9 1 CAPACITOR SELECTION FOR CERAMIC RESONATORS PIC12C67X Osc Resonator Cap Range Cap Sek
53. 100 ns Note 1 14 TckL2ioV CLKOUT 1 to Port out valid 0 5Tcy 20 ns Note 1 15 TioV2ckH Port in valid before CLKOUT T Tosc 200 ns Note 1 16 TckH2iol Port in hold after CLKOUT T 0 ns Note 1 17 TosH2ioV OSC1T Q1 cycle to Port out valid 50 150 ns 18 TosH2iol OSC1T Q2 cycle to Port PIC12C67X 100 ns 18A input invalid I O in hold PIC12LC67X 200 E ns time 19 TioV2osH Port input valid to OSC1T VO in setup 0 ns time 205 TioR Port output rise time PIC12C67X 10 40 ns 20A PIC12LC67X 80 ns 21 TioF Port output fall time PIC12C67X 10 40 ns 21A PIC12LC67X sm 80 ns 22tt Tinp GP2 INT pin high or low time TCY ns 23tt Trop GP0 GP1 GP3 change INT high or low TCY ns time Note 1 These parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested These parameters are asynchronous events not related to any internal clock edge Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x Tosc DS30561B page 102 1999 Microchip Technology Inc PIC12C67X FIGURE 12 7 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER TIMING V i 2 VDD AT i o E 2 MCLR mm
54. 1B page 16 1999 Microchip Technology Inc PIC12C67X 4 2 2 3 The INTCON Register is a readable and writable regis ter which contains various enable and flag bits for the TMRO Register overflow GPIO port change and exter INTCON REGISTER Note Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit GIE INTCON lt 7 gt nal GP2 INT pin interrupts REGISTER 4 3 INTCON REGISTER ADDRESS OBh 8Bh R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W x GIE PEIE TOIE INTE GPIE TOIF INTF GPIF Readable bit bit7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O GIE Global Interrupt Enable bit 1 Enables all un masked interrupts 0 Disables all interrupts PEIE Peripheral Interrupt Enable bit 1 Enables all un masked peripheral interrupts 0 Disables all peripheral interrupts TOIE TMRO Overflow Interrupt Enable bit 1 Enables the TMRO interrupt 0 Disables the TMRO interrupt INTE INT External Interrupt Enable bit 1 Enables the external interrupt on GP2 INT TOCKI AN2 pin 0 Disables the external interrupt on GP2 INT TOCKI AN2 pin GPIE GPIO Interrupt on Change Enable bit 1 Enables the GPIO Interrupt on Change 0 Disables the GPIO Interrupt on Change TOIF TMRO Overflow Interrupt Flag bit 1 TMRO register has overflo
55. 2 BTFSC f b Bit Test f Skip if Clear 1 2 01 Obb bfff ffff 3 BTFSS f b Bit Test f Skip if Set 1 2 0 bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 1x kkkk kkkk C DC Z ANDLW k AND literal with W 1 11 001 kkkk kkkk Z CALL k Call subroutine 2 0 Okkk kkkk kkkk CLRWDT Clear Watchdog Timer 1 00 0000 0110 0100 TOPD GOTO k Go to address 2 0 kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 000 kkkk kkkk Z MOVLW k Move literal to W 1 O0xx kkkk kkkk RETFIE Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in w 2 11 Olxx kkkk kkkk RETURN Return from Subroutine 2 00 0000 0000 1000 SLEEP Go into standby mode 1 00 0000 0110 0011 TOPD SUBLW k Subtract W from literal 1 110x kkkk kkkk C DC Z XORLW k Exclusive OR literal with W 1 1010 kkkk kkkk Z Note 1 When an UO register is modified as a function of itself i e MOVF PORTB 1 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a 0 2 If this instruction is executed on the TMRO register and where applicable d 1 the prescaler will be cleared if assigned to the TimerO Module 3 If Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as
56. 250 ns HS osc mode PIC12CE67X 10 5 us LP osc mode 2 Tcv Instruction Cycle Time Note 1 400 DC ns Tcy 4 Fosc 3 TosL External Clock in OSC1 High 50 ns XT oscillator TosH or Low Time 25 us LP oscillator 10 ns HS oscillator 4 TOSR External Clock in OSC1 Rise 25 ns XT oscillator TosF or Fall Time 50 ns LP oscillator 15 ns HSoscillator T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 Instruction cycle period TCY equals four times the input oscillator time base period All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device exe cuting code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current consumption All devices are tested to operate at min values with an external clock applied to the OSC1 CLKIN pin When an external clock input is used the Max cycle time limit is DC no clock for all devices OSC2 is discon nected has no loading for the PIC12C67X DS30561B page 100 1999 Microchip Technology Inc PIC12C67X TABLE 12 2 CALIBRATED INTERNAL RC FREQUENCIES PIC12C671 PIC12C672 PIC12CE673 PIC12CE674 PIC12LC671 PIC12LC672 PIC12LCE673 PIC12LCE674 AC Character
57. 2CE67X versions only All PlCmicro microcontrollers employ an advanced RISC architecture The PIC12C67X microcontrollers have enhanced core features eight level deep stack and multiple internal and external interrupt sources The separate instruction and data buses of the Harvard architecture allow a 14 bit wide instruction word with the separate 8 bit wide data The two stage instruction pipeline allows all instructions to execute in a single cycle except for program branches which require two cycles A total of 35 instructions reduced instruction set are available Additionally a large register set gives some of the architectural innovations used to achieve a very high performance PIC12C67X microcontrollers typically achieve a 2 1 code compression and a 4 1 speed improvement over other 8 bit microcontrollers in their class The PIC12C67X devices have 128 bytes of RAM 16 bytes of EEPROM data memory PIC12CE67X only 5 VO pins and 1 input pin In addition a timer counter is available Also a 4 channel high speed 8 bit A D is provided The 8 bit resolution is ideally suited for appli cations requiring low cost analog interface i e thermostat control pressure sensing etc The PIC12C67X devices have special features to reduce external components thus reducing cost enhancing system reliability and reducing power con sumption The Power On Reset POR Power up Timer PWRT and Oscillator Start up Timer OST elimina
58. 55 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480 792 7277 Technical Support 480 792 7627 Web Address http www microchip com Rocky Mountain 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7966 Fax 480 792 7456 Atlanta 500 Sugar Mill Road Suite 200B Atlanta GA 30350 Tel 770 640 0034 Fax 770 640 0307 Boston 2 Lan Drive Suite 120 Westford MA 01886 Tel 978 692 3848 Fax 978 692 3821 Chicago 333 Pierce Road Suite 180 Itasca IL 60143 Tel 630 285 0071 Fax 630 285 0075 Dallas 4570 Westgrove Drive Suite 160 Addison TX 75001 Tel 972 818 7423 Fax 972 818 2924 Detroit Tri Atria Office Building 32255 Northwestern Highway Suite 190 Farmington Hills MI 48334 Tel 248 538 2250 Fax 248 538 2260 Kokomo 2767 S Albright Road Kokomo Indiana 46902 Tel 765 864 8360 Fax 765 864 8387 Los Angeles 18201 Von Karman Suite 1090 Irvine CA 92612 Tel 949 263 1888 Fax 949 263 1338 New York 150 Motor Parkway Suite 202 Hauppauge NY 11788 Tel 631 273 5305 Fax 631 273 5335 San Jose Microchip Technology Inc 2107 North First Street Suite 590 San Jose CA 95131 Tel 408 436 7950 Fax 408 436 7955 Toronto 6285 Northam Drive Suite 108 Mississauga Ontario L4V 1X5 Canada Tel 905 673 0699 Fax 905 673 6509 ASIA PACIFIC Australia Microchip Technology Australia Pty Ltd Suite 22 41 Rawson Street Epping 2121 NSW Australia Tel 61 2 9868 6733
59. 61 and DO61A 5 This spec applies to GP3 MCLR configured as external MCLR and GP3 MCLR configured as input with internal pull up enabled 6 This spec applies when GP3 MCLR is configured as an input with pull up disabled The leakage current of the MCLR circuit is higher than the standard I O logic EEE DS30561B page 96 1999 Microchip Technology Inc PIC12C67X 12 4 DC CHARACTERISTICS PIC12LC671 672 Commercial Industrial PIC12LCE673 674 Commercial Industrial Standard Operating Conditions unless otherwise specified Operating temperature 0 C lt TA lt 70 C commercial DC CHARACTERISTICS 40 C lt TA 85 C industrial Operating voltage VDD range as described in DC spec Section 12 1 and Section 12 2 Param Characteristic Sym Min TypT Max Units Conditions No Input Low Voltage VO ports VIL D030 with TTL buffer Vss 0 8V V For 4 5V lt VDD 5 5V Vss O 15VDD V otherwise D031 with Schmitt Trigger buffer Vss 0 2VDD V D032 MCLR GP2 TOCKI AN2 INT Vss 0 2VDD V in EXTRC mode D033 OSC1 in EXTRC mode Vss 0 2VDD V Note 1 D033 OSC1 in XT HS and LP Vss 0 3VDD V Note 1 Input High Voltage I O ports VIH D040 with TTL buffer 2 0V VDD V 4 5V lt VDD lt 5 5V D040A 0 25VDD 0 8V VDD V otherwise D041 with Schmitt Trigger buffer 0 8VDD VDD V For entire VDD range D042 MCLR GP2 TOCKI AN2 INT
60. 62 Japan Microchip Technology Japan K K Benex S 1 6F 3 18 20 Shinyokohama Kohoku Ku Yokohama shi Kanagawa 222 0033 Japan Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Microchip Technology Korea 168 1 Youngbo Bldg 3 Floor Samsung Dong Kangnam Ku Seoul Korea 135 882 Tel 82 2 554 7200 Fax 82 2 558 5934 Singapore Microchip Technology Singapore Pte Ltd 200 Middle Road 3107 02 Prime Centre Singapore 188980 Tel 65 334 8870 Fax 65 334 8850 Taiwan Microchip Technology Taiwan 11F 3 No 207 Tung Hua North Road Taipei 105 Taiwan Tel 886 2 2717 7175 Fax 886 2 2545 0139 EUROPE Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1 3 Ballerup DK 2750 Denmark Tel 45 4420 9895 Fax 45 4420 9910 France Microchip Technology SARL Parc d Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A ler Etage 91300 Massy France Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Microchip Technology GmbH Gustav Heinemann Ring 125 D 81739 Munich Germany Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V Le Colleoni 1 20041 Agrate Brianza Milan Italy Tel 39 039 65791 1 Fax 39 039 6899883 United Kingdom Arizona Microchip Technology Ltd 505 Eskdale Road Winnersh Triangle Wokingham Berkshire England RG41 5TU Tel 44 118 921 5869 Fax 44 118 921 5820 01 18 02 2002 Mi
61. 72 and the PIC12CE674 the first 2K x 14 0000h 07FFh is implemented Accessing a loca tion above the physically implemented address will cause a wraparound The reset vector is at 0000h and the interrupt vector is at 0004h FIGURE 4 1 PIC12C67X PROGRAM MEMORY MAP AND STACK PC lt 12 0 gt CALL RETURN 13 RETFIE RETLW Stack Level 1 Stack Level 8 Reset Vector 0000h X Peripheral Interrupt Vector 0004h 0005h On Chip Program Memory _ 03FFh 0400h PIC12C672 and PIC12CE674 only 07FFh nn gg 1FFFh 4 2 Data Memory Organization The data memory is partitioned into two banks which contain the General Purpose Registers and the Special Function Registers Bit RPO is the bank select bit RPO STATUS lt 5 gt 1 Bank 1 RPO STATUS lt 5 gt 0 Bank 0 Each Bank extends up to 7Fh 128 bytes The lower locations of each Bank are reserved for the Special Function Registers Above the Special Function Regis ters are General Purpose Registers implemented as static RAM Both Bank 0 and Bank 1 contain Special Function Registers Some high use Special Function Registers from Bank 0 are mirrored in Bank 1 for code reduction and quicker access Also note that FOh through FFh on the PIC12C67X is mapped into Bank 0 registers 70h 7Fh as common RAM 4 2 1 GENERAL PURPOSE REGISTER FILE The register file can be accesse
62. CE Real Time In Circuit Emulator PICMASTER PICMASTER CE In Circuit Emulator ICEPIC e In Circuit Debugger MPLAB ICD for PIC16F877 Device Programmers PRO MATE II Universal Programmer PICSTART Plus Entry Level Prototype Programmer Low Cost Demonstration Boards SIMICE PICDEM 1 PICDEM 2 PICDEM 3 PICDEM 17 SEEVAL KEELOQ 11 1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8 bit microcon troller market MPLAB is a Windows based applica tion which contains Multiple functionality editor simulator programmer sold separately emulator sold separately Afull featured editor A project manager Customizable tool bar and key mapping Astatus bar On line help MPLAB allows you to Edit your source files either assembly or C One touch assemble or compile and download to PICmicro tools automatically updates all project information Debug using source files absolute listing file object code The ability to use MPLAB with Microchip s simulator MPLAB SIM allows a consistent platform and the abil ity to easily switch from the cost effective simulator to the full featured emulator with minimal retraining 11 2 MPASM Assembler MPASM is a full featured universal macro assembler for all PlCmicro MCU s It can produce absolute code directly in the
63. CKI Low Pulse Width No Prescaler 0 5TCY 20 ns Must also meet With Prescaler 10 ns parameter 42 42 TtOP TOCKI Period No Prescaler Tcy 40 ns With Prescaler Greater of ns N prescale 20 or Tcv 40 value 2 4 N 256 48 TCKE2tmr1 Delay from external clock edge to timer 2Tosc 7Tos increment c These parameters are characterized but not tested T Datain Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested TABLE 12 6 GPIO PULL UP RESISTOR RANGES Vpp Volts Temperature C Min Typ Max Units GPO GP1 2 5 40 38K 42K 63K Q 25 42K 48K 63K Q 85 42K 49K 63K Q 125 50K 55K 63K Q 5 5 40 15K 17K 20K Q 25 18K 20K 23K Q 85 19K 22K 25K Q 125 22K 24K 28K Q GP3 2 5 40 285K 346K 417K Q 25 343K 414K 532K Q 85 368K 457K 532K Q 125 431K 504K 593K Q 5 5 40 247K 292K 360K Q 25 288K 341K 437K Q 85 306K 371K 448K Q 125 351K 407K 500K Q These parameters are characterized but not tested DS30561B page 104 1999 Microchip Technology Inc PIC12C67X TABLE 12 7 A D CONVERTER CHARACTERISTICS PIC12C671 672 04 PIC12CE673 674 04 COMMERCIAL INDUSTRIAL EXTENDED PIC12C671 672 10 PIC12CE673 674 10 COMMERCIAL INDUSTRIAL EXTENDED PIC12LC671 672 04 PIC12LCE673 674 04 COMMERCIAL INDUSTRIAL
64. DD 5 5V HS mode D010A 19 29 HA Fosc 32kHz VDD 3 0V WDT disabled LP mode Commercial Temperature 19 37 uA Fosc 32kHz VDD 3 0V WDT disabled LP mode Industrial Temperature 32 60 HA Fosc 32kHz VDD 3 0V WDT disabled LP mode Extended Temperature D020 Power down Current IPD 0 25 6 pA VoD 3 0V Commercial WDT disabled D021 025 7 pA VoD 3 0V Industrial WDT disabled D021B 2 14 pA Vpp 3 0V Extended WDT disabled 0 5 8 HA VDD 5 5V Commercial WDT disabled 0 8 9 HA VDD 5 5V Industrial WDT disabled 3 16 HA VDD 5 5V Extended WDT disabled D022 Watchdog Timer Current AIWDT 2 2 5 HA VDD 3 0V Commercial 2 2 6 HA VDD 3 0V Industrial 4 11 HA Vpp 3 0V Extended D028 Supply Current AIEE 0 1 0 2 mA Fosc 4MHz VDD 5 5V SCL 400kHz During read write to For PIC12CE673 674 only EEPROM peripheral These parameters are characterized but not tested Note 1 Data in Typical Typ column is based on characterization results at 25 C This data is for design guidance only and is not tested 2 This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data 3 The supply current is mainly a function of the operating voltage and freguency Other factors such as bus loading oscillator type bus rate internal code execution pattern and temperature also have
65. EF VO TTL ST Bi directional VO port serial programming clock analog input 1 voltage reference Can be software programmed for internal weak pull up and interrupt on pin change This buffer is a Schmitt Trigger input when used in serial programming mode GP2 TOCKI AN2 INT ST Bi directional VO port analog input 2 Can be configured as TOCKI or external interrupt GP3 MCLR VPP TTL ST Input port master clear reset input programming voltage input When configured as MCLR this pin is an active low reset to the device Voltage on MCLR VPP must not exceed VDD during normal device operation Can be software pro grammed for internal weak pull up and interrupt on pin change Weak pull up always on if configured as MCLR This buffer is Schmitt Trigger when in MCLR mode GP4 0SC2 AN3 CLKOUT VO TTL Bi directional VO port oscillator crystal output analog input 3 Connections to crystal or resonator in crystal oscillator mode HS XT and LP modes only GPIO in other modes In EXTRC and INTRC modes the pin output can be configured to CLK OUT which has 1 4 the frequency of OSC1 and denotes the instruction cycle rate GP5 OSC1 CLKIN VO TTL ST Bi directional IO port oscillator crystal input external clock source input GPIO in INTRC mode only OSC1 in all other oscillator modes Schmitt trigger input for EXTRC oscillator mode VDD 1 Positive supply for logic and UO pins Vss
66. GP3 AMCLR VPP M 4 99 5 GP2 TOCK AN2 1 Na INT PDIP Windowed CERDIP VC Vpp 1 UU 8 Vss GPS OSCVCLKIN IS 99 7 j GPO ANO PROC 3 OO 6 GPUANIVREF EE ie mm GP2 TOCKI AN2 GP3 MCLR VPP 14 S 3 5 INT Special Microcontroller Features In Circuit Serial Programming ICSP Internal 4 MHz oscillator with programmable calibration Selectable clockout Power on Reset POR Power up Timer PWRT and Oscillator Start up Timer OST Watchdog Timer WDT with its own on chip RC oscillator for reliable operation Programmable code protection Power saving SLEEP mode Interrupt on pin change GPO GP1 GP3 Internal pull ups on I O pins GPO GP1 GP3 Internal pull up on MCLR pin Selectable oscillator options INTRC Precision internal 4 MHz oscillator EXTRC External low cost RC oscillator XT Standard crystal resonator HS High speed crystal resonator LP Power saving low frequency crystal CMOS Technology Low power high speed CMOS EPROM EEPROM technology Fully static design Wide operating voltage range 2 5V to 5 5V Commercial Industrial and Extended temperature ranges Low power consumption lt 2 mA 5V 4 MHz 15 uA typical 3V 32 kHz lt 1 uA typical standby current 1999 Microchip Technology Inc DS30561B page 1 PIC12C67X Table of Contents 1 0 CEET Le TEE 3 2 0 PIC12C67X Device Varieties ss ohne rented re de eben eee nin e ch a 5 3 0 4 0
67. ICMASTER PICMASTER CE The PICMASTER system from Microchip Technology is a full featured professional quality emulator system This flexible in circuit emulator provides a high quality universal platform for emulating Microchip 8 bit PICmicro microcontrollers MCUS PICMASTER sys tems are sold worldwide with a CE compliant model available for European Union EU countries 11 8 ICEPIC ICEPIC is a low cost in circuit emulation solution for the Microchip Technology PIC16C5X PIC16C6X PIC16C7X and PIC16CXXX families of 8 bit one time programmable OTP microcontrollers The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules or daughter boards The emulator is capable of emulating without target application circuitry being present 11 9 MPLAB ICD In Circuit Debugger Microchip s In Circuit Debugger MPLAB ICD is a pow erful low cost run time development tool This tool is based on the flash PIC16F877 and can be used to develop for this and other PICmicro microcontrollers from the PIC16CXXX family MPLAB ICD utilizes the In Circuit Debugging capability built into the PIC16F87X This feature along with Microchip s In Cir cuit Serial Programming protocol offers cost effective in circuit flash programming and debugging from the graphical user interface of the MPLAB Integrated Development Environment This enables a designer to develop and deb
68. IGH to enable the processor to generate the STOP condition Figure 6 4 FIGURE 6 1 BLOCK DIAGRAM OF GPIO6 SDA LINE Note Acknowledge bits are not generated if an internal programming cycle is in progress VDD Reset To EEPROM SDA Pad D mm E D ke Data Bus Output Latch Y la D CK d Schmitt Trigger Input Latch Read Itchpin GPIO FIGURE 6 2 BLOCK DIAGRAM OF GPIO7 SCL LINE VDD P To EEPROM SCL Pad x Write c lt Q a PI Data Bus SRO Output Latch Q omc CK Schmitt Trigger Read Itchpin GPIO DS30561B page 34 1999 Microchip Technology Inc PIC12C67X FIGURE 6 3 DATA TRANSFER SEQUENCE ON THE SERIAL BUS seu A 6 ae Ie D SDA x X N f f 64d Se EE START ADDRESS OR DATA STOP CONDITION ACKNOWLEDGE ALLOWED CONDITION VALID TO CHANGE FIGURE 6 4 ACKNOWLEDGE TIMING Acknowledge Bit set Jr Jo fol a s foy J7 fep ek f el al SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point 4 A Receiver must release the SDA line at this allowing the Receiver to pull the SDA line low to point so the Transmitter can continue acknowledge
69. KA Internal RC 4 MHz 400 HA 900 HA XT 4 MHz 400 HA 900 HA LP 32 KHz 15 HA 60 HA Does not include current through external R amp C FIGURE 13 3 WDT TIMER TIME OUT FIGURE 13 4 10H vs VOH VDD 2 5 V PERIOD vs VDD 55 0 1 50 2 45 3 40 4 A E E 5 35 X D e 2 Max 125 C n 8 6 30 2 Max 85 C 7 25 8 20 gi Typ 25 C Max 40 C 15 10 5 75 1 0 1 25 1 5 1 75 2 0 2 25 2 5 Mim 40C 10 VOH Volts 0 2 5 3 5 4 5 5 5 6 5 VDD Volts DS30561B page 110 1999 Microchip Technology Inc PIC12C67X FIGURE 13 5 lou vs Vor VDD 3 5 V FIGURE 13 7 lo vs VoL VDD 2 5 V 0 35 30 5 Max 40 C T Min 41250 25 E 10 6 gt in 20 t Typ 25 C 15 s 9 15 on Max 40 C Min 85 C 10 Min 125 C 25 1 5 2 0 2 5 3 0 3 5 5 VOH Volts 0 FIGURE 13 6 10H vs VoH VDD 5 5 V 0 0 25 0 5 0 75 1 0 VoL Volts FIGURE 13 8 lor vs VoL VDD 3 5 V 45 Max 40 C 40 35 30 Typ 25 C gt E ER 9 20 40 15 3 5 4 0 4 5 5 0 5 5 Min 85 C Von volts Min 125 C 10 0 0 0 25 0 5 0 75 1 0 VOL Volts 1999 Microchip Technology Inc DS30561B page 111 PIC12C67X
70. LAB ICE emulator and download the firmware to the emulator for testing Additional proto type area is available for the user to build some addi tional hardware and connect it to the microcontroller socket s Some of the features include an RS 232 interface a potentiometer for simulated analog input push button switches and eight LEDs connected to PORTB 11 14 PICDEM 2 Low Cost PIC16CXX Demonstration Board The PICDEM 2 is a simple demonstration board that supports the PIC16C62 PIC16C64 PIC16C65 PIC16C73 and PIC16C74 microcontrollers All the necessary hardware and software is included to run the basic demonstration programs The user can program the sample microcontrollers provided with the PICDEM 2 board on a PRO MATE II pro grammer or PICSTART Plus and easily test firmware The MPLAB ICE emulator may also be used with the PICDEM 2 board to test firmware Additional prototype area has been provided to the user for adding addi tional hardware and connecting it to the microcontroller socket s Some of the features include a RS 232 inter face push button switches a potentiometer for simu lated analog input a Serial EEPROM to demonstrate usage of the 12C bus and separate headers for connec tion to an LCD module and a keypad 11 15 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package It will also support future
71. LTAGE FREQUENCY GRAPH 40 C lt TA lt 85 C 6 0 5 5 5 0 VDD Volts 2 0 0 4 10 20 25 Frequency MHz Note 1 The shaded region indicates the permissible combinations of voltage and frequency 2 The maximum rated speed of the part limits the permissible combinations of voltage and frequency Please reference the Product Identification System section for the maximum rated speed of the parts 1999 Microchip Technology Inc DS30561B page 91 PIC12C67X 12 1 DC Characteristics PIC12C671 672 Commercial Industrial Extended PIC12CE673 674 Commercial Industrial Extended Standard Operating Conditions unless otherwise specified BG CHARACTERISTICS Operating Temperature 0 C lt TA lt 70 C commercial 40 C lt TA lt 85 C industrial 40 C lt TA lt 125 C extended Parm Characteristic Sym Min Typ Max Units Conditions No D001 Supply Voltage VDD 3 0 5 5 V D002 RAM Data Retention VDR 1 5 V Device in SLEEP mode Voltage D003 VDD Start Voltage to ensure VPOR Vss V See section on Power on Reset for details Power on Reset D004 VDD Rise Rate to ensure SVDD 0 05 V ms See section on Power on Reset for details Power on Reset D010 Supply Current IDD 12 25 mA Fosc 4MHz VDD 3 0V XT and EXTRC mode Note 4 D010C 12 25 mA Fosc 4MHz VDD 3 0V INTRC mode Note 6 2 2 8 mA Fosc 10MHz V
72. MICROCHIP PIC12C67X 8 Pin 8 Bit CMOS Microcontroller with A D Converter and EEPROM Data Memory Devices Included in this Data Sheet PIC12C671 PIC12C672 PIC12CE673 PIC12CE674 Note Throughout this data sheet PIC12C67X refers to the PIC12C671 PIC12C672 PIC12CE673 and PIC12CE674 PIC12CE67X refers to PIC12CE673 and PIC12CE674 High Performance RISC CPU Only 35 single word instructions to learn All instructions are single cycle 400 ns except for program branches which are two cycle Operating speed DC 10 MHz clock input DC 400 ns instruction cycle Memory Device Piedra Data Data RAM EEPROM PIC12C671 1024 x 14 128 x 8 PIC12C672 2048 x 14 128x8 PIC12CE673 1024 x 14 128x8 16x8 PIC12CE674 2048 x 14 128x8 16x8 14 bit wide instructions 8 bit wide data path Interrupt capability Special function hardware registers 8 level deep hardware stack Direct indirect and relative addressing modes for data and instructions Peripheral Features Four channel 8 bit A D converter 8 bit real time clock counter TMRO with 8 bit programmable prescaler 1 000 000 erase write cycle EEPROM data memory EEPROM data retention gt 40 years Pin Diagrams PDIP SOIC Windowed CERDIP EA s VpD 1 uu 8 vss GP5 OSC1 CLKIN 112 9 9 7 1 lt GP0 AN0 GP4 OSC2 AN3 J cLKourT 113 S S 6 gt GP1 AN1 VREF
73. NE ACTIVITY A A AS Xp N C C C DATA n Oo K K K A C X Don t Care Bit K FIGURE 6 10 SEQUENTIAL READ s T SC DATA n DATA n 1 DATA n 2 DATA n X 0 P SDA LINE i M P ACTIVITY sea A A A A N C C C C Oo K K K K amp C K 1999 Microchip Technology Inc DS30561B page 37 PIC12C67X NOTES ie SE EE EE EE EE EE g 0 TIIOOKIEOKTC lt K X7KGDGIOei aa DS30561B page 38 1999 Microchip Technology Inc PIC12C67X 7 0 TIMERO MODULE The TimerO module timer counter has the following fea tures 8 bit timer counter Readable and writable 8 bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Figure 7 1 is a simplified block diagram of the TimerO module Timer mode is selected by clearing bit TOCS OPTION lt 5 gt In timer mode the TimerO module will increment every instruction cycle without prescaler If the TMRO register is written the increment is inhibited for the following two instruction cycles Figure 7 2 and Figure 7 3 The user can work around this by writing an adjusted value to the TMRO register Counter mode is selected by setting bit TOCS OPTION lt 5 gt In counter mode Timer0 will increment either on every rising or falling edge of pin RA4 TOCKI The incrementing edge is determined by the bit TOSE OPTION lt 4 gt Clearing bit TOSE selects the rising e
74. NOM MAX Number of Pins n 8 8 Pitch p 100 2 54 Top to Seating Plane A 140 155 170 3 56 3 94 4 32 Molded Package Thickness A2 115 130 145 2 92 3 30 3 68 Base to Seating Plane Al 015 0 38 Shoulder to Shoulder Width E 200 313 325 7 62 7 94 8 26 Molded Package Width E1 240 250 260 6 10 6 35 6 60 Overall Length D 360 373 385 9 14 9 46 9 78 Tip to Seating Plane L 125 130 135 3 18 3 30 3 43 Lead Thickness c 008 012 015 0 20 0 29 0 38 Upper Lead Width B1 045 058 070 1 14 1 46 1 78 Lower Lead Width B 014 018 022 0 36 0 46 0 56 Overall Row Spacing eB 310 370 430 7 87 9 40 10 92 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15 Controlling Parameter Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 001 Drawing No C04 018 DS30561B page 116 1999 Microchip Technology Inc PIC12C67X 8 Lead Plastic Small Outline SM Medium 208 mil SOIC Laag E um GE on A2 Ba I L Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p 050 1 27 Overall Height A 070 075 080 1 78 1 97 2 03 Molded Package Th
75. ON GIE PEIE TOIE INTE GPIE TOIF INTF GPIF 0000 000x 0000 000u DCH PIR1 ADIF Q 0 BCh PIE1 ADIE Q 0 1Eh ADRES A D Result Register XXXX XXXX uuuu uuuu 1Fh ADCONO ADCS1 ADCSO reserved CHS1 CHSO GO DONE reserved ADON 0000 0000 0000 0000 9Fh ADCON1 PCFG2 PCFG1 PCFGO 000 000 05h GPIO SCU SDA GP5 GP4 GP3 GP2 GP1 GPO 11xx xxxx lluu uuuu 85h TRIS TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRISO 11 1111 11 1111 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used for A D conversion Note 1 These registers can be addressed from either bank 2 The SCL GP7 and SDA GP6 bits are unimplemented on the PIC12C671 672 and read as 0 kYax xz gt x s e s v vr 1999 Microchip Technology Inc DS30561B page 52 PIC12C67X 9 0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other proces sors are special circuits to deal with the needs of real time applications The PIC12C67X family has a host of such features intended to maximize system reliability minimize cost through elimination of external compo nents provide power saving operating modes and offer code protection These are e Oscillator selection Reset Power on Reset POR Power up Timer PWRT Oscillator Start up Timer OST Inte
76. P2 TOCKI M SYNC AN2 INT a al H I 2 H TMROreg X Cycles TOSE i TOCS PSA Set flag bit TOIF on Overflow 0 M E 8 bit Prescaler U Watchdog 1 x 8 Timer 8 to 1MUX PS lt 2 0 gt PSA e a 0 1 WDT Enable bit MUX Ja PSA Y WDT Time out Note TOCS TOSE PSA PS lt 2 0 gt are OPTION lt 5 0 gt DS30561B page 42 1999 Microchip Technology Inc PIC12C67X 7 3 1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the TimerO mod ule use the sequence shown in Example 7 2 The prescaler assignment is fully under software con trol Le it can be changed on the fly during program EXAMPLE 7 2 CHANGING PRESCALER execution WDT TIMERO Note To avoid an unintended device RESET the a d CLRWDT Clear WDT and following instruction sequence shown in pe Example 7 1 must be executed when B STATUS RPO EE 1 changing the prescaler assignment from MOVLW b xxxx0xxx Select TMRO new TimerO to the WDT This sequence must prescale value and be followed even if the WDT is disabled MOVWF OPTION REG clock source BCF STATUS RPO Bank 0 EXAMPLE 7 1 CHANGING PRESCALER TIMERO WDT BCF STATUS RPO Bank 0 CLRF TMRO Clear TMRO amp Prescaler BSF STATUS RPO Bank 1 CLRWDT Clears WDT MOVLW b xxxx1xxx Select new prescale MOVWF OPTION REG value amp WDT BCF STATUS RPO Bank O TABLE 7 1 REGISTERS ASSOCIATED WITH TIMERO
77. PMENT TOOLS FROM MICROCHIP TABLE 11 1 S89IA8P 198 s UO e qejreA e SI 100 luauidoleAsg 1 epp AuIOEIEAE 10 ou KBojouuoe diuo0J9IIN 1901002 LL 91 YL EL ZL S9 v9 9 z909LOld UUM L009 LAG 1e66ngeq Wou OOI GE WI SU gen ol MOY uo uomreuuojut 10 WOd d YOOJOILW MMM IE eis qem Jul Bojouuoe diuooJorN eui 19e31002 2 Vy Aedoleaad NVO OLSZdOIN 104 SAedolaaaa QIo4521u UOISIJJOINUY ZHIN 9G L 104 SAedolaaaa 1O491U UOISIIO9NUY ZH SZL VA S 4adojanag dou ZH ST Wy SA UUUBIGOAG wni Glow Wy 4epuodsueil 001333 1134 uonenje 3 6007133 ZVi W3Q9ld Vri INaaold N3QOld 1 1 Cc NAQOld 1 I NaaDId 3oIWIS xx JeuiueJBo4d Iesiaalun II 33 1 VIN Oid xx Wy Ae IESISAIUN 1502 01 SNidgLYVLSOld 1966nqsq MNOAIO UI dor Avid AO1EINW3 11n2412 U 1509 M0O1 moIdAOI 30 HALSVINOId HALSVWNOId xx 39rg8V Id AR AE AE AR SE AE AR AE AE AR SE sg AR AE AE AR AE AE AR AE AE AR AE AE ANIIdW NSVdWN 4ejduio2 819 AVI1dW A llduuo9 LO AVI1dW OLSZd N O D lul gt gt gt XXXSOH ZXX 8L ld XXLOZLLOld ZE d XX6O9LOId XX849LOld X899LOld XXLO9LOId X4991L91d XZ949LOld XXX99LOld X9O9LOId XSO9LOId 000t L ld KOCH ld 1ueuiuoJiAu3 1lu uido
78. START PICMASTER PRO MATE and MPLAB are registered trademarks of Microchip Technology Incorpo rated in the U S A and other countries FlexROM and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U S A All other trademarks mentioned herein are the property of their respective companies 1999 Microchip Technology Inc DS30561B page 125 PIC12C67X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod uct If you wish to provide your comments on organization clarity subject matter and ways in which our documentation can better serve you please FAX your comments to the Technical Publications Manager at 480 786 7578 Please list the following information and use this outline to provide us with your comments about this Data Sheet To Technical Publications Manager Total Pages Sent RE Reader Response From Name Company Address City State ZIP Country Telephone FAX Application optional Would you like a reply Y N Device PIC12C67X Literature Number DS30561B Questions 1 What are the best features of this document 2 How does this document meet your hardware and software development needs 3 Do you find the organization of this data sheet easy to follow If not why 4 What additions to the data sheet do you think would enhance the
79. Sub TMRO Interrupt eee Timing Diagrams A D Conversion CLKOUT and I O External Clock Timing Time out Sequence Timer0 E TimerO Interrupt Timing TimerO with External Clock Wake up from Sleep via Interrupt TRIS Instruction TRIS Register eorr heredes Two s Complement sss U UV Erasable Devices 5 W W Register Wake up from SLEEP Watchdog Timer WDT 53 56 59 65 WDT EE HE tatin nt S eto pee OND Block Diagram E Period RE ene remets Programming Considerations 65 Timeout u WWW On Line Support 2 X XORLW Instruction 81 XORWE Instruction 81 1999 Microchip Technology Inc DS30561B page 123 PIC12C67X NOTES wc DS30561B page 124 1999 Microchip Technology Inc PIC12C67X ON LINE SUPPORT Microchip provides on line support on the Microchip World Wide Web WWW site The web site is used by Microchip as a means to make files and information easily available to customers To view the site the user must have access to the Internet and a web browser such as Netscape or Microsoft Explorer Files are also available for FTP download from our FTP site Connecting to the Microchip Internet Web Site The Microchip web site is availab
80. TA lt 70 C commercial 40 C lt TA lt 85 C industrial 40 C lt TA lt 125 C extended Operating voltage Vpp range as described in DC spec Section 12 1 and Section 12 2 Param Characteristic Sym Min Typt Max Units Conditions No Input Low Voltage VO ports VIL DO30 with TTL buffer Vss 0 8V V For 4 5V lt VDD 5 5V Vss O0 15VDD V lotherwise D031 with Schmitt Trigger buffer Vss 0 2VDD V D032 MCLR GP2 TOCKI AN2 INT Vss 0 2VDD V in EXTRC mode DO33 OSC1 in EXTRC mode Vss 0 2VDD Note 1 D033 OSC1 in XT HS and LP Vss 0 3VDD V Note Input High Voltage VO ports VIH D040 with TTL buffer 2 0V VDD V 4 5V lt VDD 5 5V D040A 0 25VDD 0 8V VDD V otherwise D041 with Schmitt Trigger buffer 0 8VDD VDD V For entire VDD range D042 MCLR GP2 TOCKI AN2 INT 0 8VDD VDD V D042A OSC1 XT HS and LP 0 7VDD VDD V Note D043 OSC1 in EXTRC mode 0 9VDD VDD V Input Leakage Current Notes 2 3 D060 VO ports liL 1 uA Vss lt VPIN lt VDD Pin at hi impedance D061 GP3 MCLR Note 5 30 uA Vss lt VPIN lt VDD D061A GP3 Note 6 5 uA Vss lt VPIN lt VDD D062 GP2 TOCKI 5 uA Vss lt VPIN lt VDD D063 OSC1 5 HA Vss lt VPIN VDD XT HS and LP osc configuration D070 GPIO weak pull up current Note 4 IPUR 50 250 400 HA VDD DN VPIN VSS MCLR pull up
81. The exact latency depends on when the interrupt event occurs Figure 9 14 The latency is the same for one or two cycle instructions Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit ADIF PEE aoe Wake up If in SLEEP mode D to CPU DS30561B page 62 1999 Microchip Technology Inc PIC12C67X FIGURE 9 14 INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 G2 Q3 Q4 Q1 Q2 Q3 04 Q1 02 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 FX NS xw NE NL NT NE NEN EL NL NB ONE NL NL NPAT NA NLA NS CLKOUT me Ze Ee i INT pi EE Sa o i pin i T Ee i i INTF flag EA Jo Interrupt Latency 2 i INTCON lt 1 gt is d GIEbit INTCON 7 INSTRUCTION ELOW PC lt PC X POHI X PC 1 X 0004h X OO05A s a Int PC wette Inst O004n inst 0005h Mhn Inst PC 1 Inst PC Dummy Cycle Dummy Cycle Inst 0004h Note 1 INTE flag is sampled here every Q1 2 Interrupt latency 3 4 TCY where TCY instruction cycle time Latency is the same whether Inst PC is a single cycle or a 2 cycle instruction 3 CLKOUT is available only in INTRC and EXTRC oscillator modes 4 For minimum width of INT pulse refer to AC specs 5 INTF is enabled to be set anytime during the Q4 Q1 cycles 1999 Microchip Tech
82. a NOP 1999 Microchip Technology Inc DS30561B page 71 PIC12C67X 10 2 Instruction Descriptions ADDLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example ADDWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Add Literal and W label ADDIW k 0 lt k lt 255 W k gt W C DC Z El 111x kkkk kkkk The contents of the W register are added to the eight bit literal k and the result is placed in the W regis ter 1 1 ADDLW 0x15 Before Instruction W 0x10 After Instruction W 0x25 Add W and f label ADDWF fd 0 lt f lt 127 de 0 1 W f dest C DC Z 00 0111 dfff ffff Add the contents of the W register with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in reg ister f 1 1 ADDWF FSR 0 Before Instruction W 0x17 FSR OxC2 After Instruction W OxD9 FSR 0xC2 ANDLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example ANDWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example And Literal with W label ANDIW k O lt k lt 255 W AND k gt W 7 11 1001 kkkk kkkk The contents of W register are AND ed wit
83. a wide operating range and better stability A well designed crystal oscillator will provide good performance with TTL gates Two types of crystal oscillator circuits can be used one with parallel resonance or one with series resonance Figure 9 3 shows implementation of a parallel resonant oscillator circuit The circuit is designed to use the fundamental frequency of the crystal The 74AS04 inverter performs the 180 degree phase shift that a parallel oscillator requires The 4 7 kQ resistor provides the negative feedback for stability The 10 kQ potentiometers bias the 74AS04 in the linear region This circuit could be used for external oscillator designs FIGURE 9 3 EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT 5V To Other Devices 310k 4 7k 74AS04 PIC12C67X 74AS04 to Ak CLKIN e I 20 pF Figure 9 4 shows a series resonant oscillator circuit This circuit is also designed to use the fundamental freguency of the crystal The inverter performs a 180 degree phase shift in a series resonant oscillator circuit The 330 Q resistors provide the negative feedback to bias the inverters in their linear region FIGURE 9 4 EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT To Other 330 330 Devices AW AN 74AS04 74AS04 En SE 74AS04 PIC12C67X CLKIN 9 2 4 EXTERNAL RC OSCILLATOR For timing insen
84. ag bit TOIF on overflow FIGURE 7 2 TIMERO TIMING INTERNAL CLOCK NO PRESCALE PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 o2 oa Q4 Q1 Q2 o3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 o3 Q4 Q1 Q2 o3 64 Q1 Q2 Q3 Q4 rogram i i i i SEN PCT PC X PCI Y PC Y PC 3 Y PC Y PC 5 Y POUSE Instruction i MOVWF TMR0 MOVF TMR0 WMOVF TMR0 WMOVF TMRO WMOVF TMRO WMOVF TMRO W TMRO TU X TOT X TOZ X NU NIU X NII Y NIL X NIUZ e Instruction A i A A i I Executed i i i Write TMRO Read TMRO Read TMRO Read TMRO Read TMRO Read TMRO executed reads NTO reads NTO reads NTO reads NTO 1 reads NTO 2 1999 Microchip Technology Inc DS30561B page 39 PIC12C67X FIGURE 7 3 TIMERO TIMING INTERNAL CLOCK PRESCALE 1 2 Q1 Q2 Q3 Q4 Q1 Q2 aa a4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 aa Q4 o1 aa Q3 Q4 Q1 Q2 a3 Q4 Q1 Q2 Q3 04 Program ounter POT Y PC X PC I Y PC 2 X PC 3 X PC 4 i PC 5 Y PC 6 5 Instruction MOVWF TMRO MOVF TMRO WMOVF TMRO MOVE TMRO WMOVE TMRO WMOVF TMRO W Fetch TMR0 TO X TUE Xa HIT i NET Instruction I I I i I i Execute Write TMRO Read TMRO Read TMRO Read TMRO Read TMRO Read TMPO executed reads NTO reads NTO reads NTO reads NTO reads NTO 1 FIGURE 7 4 TIMERO INTERRUPT TIMING ai ce as os ai ce as aa ai a2 as aa Q1 o2 a3 aa ai a
85. alue on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on all other Reset Resets Bank 1 80h 1 INDF Addressing this location uses contents of FSR to address data memory not a physical register 0000 0000 0000 0000 81h OPTION GPPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 1111 LITE 1311 1111 82h PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 83n STATUS IRP 9 RP10 RPO TO PD 7 DC C 0001 1xxx 000q quuu 84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRIS GPIO Data Direction Register emi TILL pee p 86h Unimplemented 87h Unimplemented 88h Unimplemented 89h Unimplemented 8Ah 2 PCLATH Write Buffer for the upper 5 bits of the PC 0 0000 0 0000 8Bh 1 INTCON GIE PEIE TOIE INTE GPIE TOIF INTF GPIF 0000 000x 0000 000u 8Ch PIE1 ADIE 0 0 8Dh Unimplemented 8Eh PCON POR 0 u 8Fh OSCCAL CAL3 CAL2 CAL1 CALO CALFST CALSLW 0111 00 uuuu uu 90h Unimplemented 91h Unimplemented 92h Unimplemented 93h Unimplemented 94h Unimplemented 95h Unimplemented 96h Unimplemented 97h Unimplemented 98h Unimplemented 99h Unimplemented 9Ah Unimplemented 9Bh Unimplemented 9Ch Unimplemented 9Dh Unimplemented
86. and the IRP bit STATUS lt 7 gt as shown in Figure 4 4 However IRP is not used in the PIC12C67X A simple program to clear RAM locations 20h 2Fh using indirect addressing is shown in Example 4 1 FIGURE 4 4 DIRECT INDIRECT ADDRESSING EX AMPLE 4 1 INDI movlw 0x20 movwf FSR NEXT CLIPE INDF incf FSR F btfss FSR 4 goto NEXT CONTINUE RECT ADDRESSING jinitialize pointer to RAM clear INDF register inc pointer all done no clear next yes continue Direct Addressing RP1 RPO 6 from opcode 0 er gt N V J bank select location select 00 01 10 Indirect Addressing IRPO 7 FSR register 0 id A bank select 11 id 00h Data Memory 7Fh not u 180h lt V location select sed 1FFh Bank 0 Bank 1 For register file map detail see Figure 4 2 Bank 2 Bank 3 Note 1 The RP1 and IRP bits are reserved always maintain these bits clear 1999 Microchip Technology Inc DS30561B page 23 PIC12C67X NOTES Eech DS30561B page 24 1999 Microchip Technology Inc PIC12C67X 5 0 I O PORT As with any other register the VO register can be written and read under program control However read instructions e MOVF GPIO W always read the VO pins independent of the pin s input output modes On RESET all VO ports are
87. be noted that a WDT Reset does not drive MCLR pin low When MCLR is asserted the state of the OSC1 CLKIN and CLKOUT OSC2 pins are as follows TABLE 9 3 CLKIN CLKOUT PIN STATES WHEN MCLR ASSERTED 9 2 6 CLKOUT The PIC12C67X can be configured to provide a clock out signal CLKOUT on pin 3 when the configuration word address 2007h is programmed with Fosc2 Fosc1 and FOSCO equal to 101 for INTRC or 111 for EXTRC The oscillator frequency divided by 4 can be used for test purposes or to synchronize other logic Oscillator Mode OSC1 CLKIN Pin OSC2 CLKout Pin EXTRC CLKOUT on OSC2 OSC1 pin is tristated and driven by external circuit OSC2 pin is driven low EXTRC OSC2 is VO OSC1 pin is tristated and driven by external Circuit OSC2 pin is tristate input INTRC CLKOUT OSC1 pin is OSC2 pin is driven on OSC2 tristate input low INTRC OSC2 is OSC1 pin is OSC2 pin is VO tristate input tristate input 1999 Microchip Technology Inc DS30561B page 56 FIGURE 9 6 SIMPLIFIED BLOCK DIAGRAM OF ON CHIP RESET CIRCUIT Weak ia Pull up Le Ee GP3 MCLR VPP Pin MCLRE INTERNAL MCLR WDT ISLEEE Module WDT Time out VDD rise 325 detect power on Reset VDD S OST PWRT OST J 10 bit Ripple counter j D OSC1 CLKIN Pin PWRT
88. c debugging using MPLAB C17 and MPLAB C18 and MPASM The Soft ware Simulator offers the flexibility to develop and debug code outside of the laboratory environment mak ing it an excellent multi project software development tool 11 6 MPLAB ICE High Performance Universal In Circuit Emulator with MPLAB IDE The MPLAB ICE Universal In Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers MCUS Software control of MPLAB ICE is provided by the MPLAB Integrated Development Environment IDE which allows editing make and download and source debugging from a single environment Interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro cessors The universal architecture of the MPLAB ICE allows expansion to support new PlCmicro microcon trollers The MPLAB ICE Emulator System has been designed as a real time emulation system with advanced fea tures that are generally found on more expensive devel opment tools The PC platform and Microsoft Windows 3 x 95 98 environment were chosen to best make these features available to you the end user MPLAB ICE 2000 is a full featured emulator system with enhanced trace trigger and data monitoring fea tures Both systems use the same processor modules and will operate across the full operating speed range of the PICmicro MCU 11 7 P
89. can link relocatable objects from assembly or C source files along with pre compiled libraries using directives from a linker script MPLIB is a librarian for pre compiled code to be used with MPLINK When a routine from a library is called from another source file only the modules that contains that routine will be linked in with the application This allows large libraries to be used efficiently in many dif ferent applications MPLIB manages the creation and modification of library files MPLINK features include e MPLINK works with MPASM and MPLAB C17 and MPLAB C18 MPLINK allows all memory areas to be defined as sections to provide link time flexibility MPLIB features include MPLIB makes linking easier because single librar ies can be included instead of many smaller files MPLIB helps keep code maintainable by grouping related modules together MPLIB commands allow libraries to be created and modules to be added listed replaced deleted or extracted 11 5 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC host environment by simulating the PICmicro series microcontrollers on an instruction level On any given instruction the data areas can be examined or modified and stimuli can be applied from a file or user defined key press to any of the pins The execution can be performed in single step execute until break or trace mode MPLAB SIM fully supports symboli
90. ch are sup plied on a 3 5 inch disk programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE Il or PICSTART Plus device programmers and easily debug and test the sample code In addition PICDEM 17 sup ports down loading of programs to and executing out of external FLASH memory on board The PICDEM 17 is also usable with the MPLAB ICE or PICMASTER emu lator and all of the sample programs can be run and modified using either emulator Additionally a gener ous prototype area is available for user hardware 11 17 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designers Kit supports all Microchip 2 wire and 3 wire Serial EEPROMS The kit includes everything necessary to read write erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials The Total Endurance Disk is included to aid in trade off analysis and reliability calculations The total kit can significantly reduce time to market and result in an optimized system 11 18 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products The HCS eval uation kit includes an LCD display to show changing codes a decoder to decode transmissions and a pro gramming interface to program test transmitters DS30561B page 86 1999 Microchip Technology Inc PIC12C67X DEVELO
91. chip Technology Inc PIC12C67X ACc uracV Error aa ss agan dede 51 ADCONO Register ee 45 ADIF RR RE RE EE Er EE 47 Analog Input Model Block Diagram 48 Analog to Digital Converter 45 Configuring Analog Port Pins Configuring the Interrupt Configuring the Module Connection Considerations Conversion Clock SMU a uu U 0 COnVer lOfl REED RR RD datent Converter Characteristics Equations Flowchart of A D Operation GOIDONE bIt SE EE EE tra hea PPM Internal Sampling Switch Rss Impedence Operation During Sleep 0 0 0 ee ee Sampling Requirements Sampling Time Source Impedence ss Time Delays usun a EAR Transfer Function Absolute Maximum Ratings ADDLW Instruction ADDWF Instruction ADIE bit 5 een ires rn C EHE E it Seaton A IF Bits ce Tot e e RO NE Rte ADRES Register ACU vas ANDLW Instruction ANDWE Instruction eese Application Notes Architecture Harvardo iudi tamis aasma RR SR gil kh hati 7 ed EE EE dE ee Seeche 7 eN ELE OR OE N OE EE Pe e pe tea ass 7 Assembler MPASM Assembler 83 B BCE Instruction l L L eee denied 73 Bit Manipulation sese Block Diagrams Analog Input Model On Chip Reset Circuit Timer0 iue
92. clock speed Set CALFST 1 for greater increase in fre quency or set CALSLW 1 for greater decrease in fre quency Note that bits 1 and O of OSCCAL are unimplemented and should be written as 0 when mod ifying OSCCAL for compatibility with future devices Note Please note that erasing the device will also erase the pre programmed internal calibration value for the internal oscillator The calibration value must be saved prior to erasing the part 9 3 Reset The PIC12C67X differentiates between various kinds of reset Power on Reset POR MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset normal operation Some registers are not affected in any reset condition their status is unknown on POR and unchanged in any other reset Most other registers are reset to a reset state on Power on Reset POR MCLR Reset WDT Reset and MCLR Reset during SLEEP They are not affected by a WDT Wake up which is viewed as the resumption of normal operation The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 9 5 These bits are used in software to determine the nature of the reset See Table 9 6 for a full description of reset states of all registers A simplified block diagram of the on chip reset circuit is shown in Figure 9 6 The PIC12C67X has a MCLR noise filter in the MCLR reset path The filter will detect and ignore small pulses It should
93. coming out of the pin 4 Does not include GP3 For GP3 see parameters D061 and DO61A ma 5 This spec applies to GP3 MCLR configured as external MCLR and GP3 MCLR configured as input with internal pull up enabled 6 This spec applies when GP3 MCLH is configured as an input with pull up disabled The leakage current of the MCLR circuit is higher than the standard l O logic 1999 Microchip Technology Inc DS30561B page 97 PIC12C67X Standard Operating Conditions unless otherwise specified Operating temperature 0 C lt TA lt 70 C commercial DC CHARACTERISTICS 40 C lt TA lt 85 C industrial Operating voltage VDD range as described in DC spec Section 12 1 and Section 12 2 Param Characteristic Sym Min Typt Max Units Conditions No Output High Voltage D090 VO ports Note 3 VOH VDD 0 7 V loH 3 0 mA VDD 4 5V 40 C to 85 C D090A VDD 0 7 V loH 2 5 mA VDD 4 5V 40 C to 125 C D092 OSC2 CLKOUT VDD 0 7 V loH TBD VDD 4 5V 40 C to 85 C D092A VDD 0 7 V loH TBD VDD 4 5V 40 C to 125 C Capacitive Loading Specs on Output Pins D100 OSC2 pin Cosc2 15 pF in XT and LP modes when external clock is used to drive OSC1 D101 All VO pins Clo 50 pF T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not teste
94. crochip Technology Inc
95. ctual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our product If you have any further questions about this matter please contact the local sales office nearest to you Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information or infringement of patents or other intellectual property rights arising from such use or otherwise Use of Microchip s products as critical com ponents in life support systems is not authorized except with express written approval by Microchip No licenses are con veyed implicitly or otherwise under any intellectual property rights DNV Certification Inc DNV MSC The Netherlands Accredited by the RvA Z DIN V ISO 9001 QS 9000 REGISTERED FIRM Trademarks The Microchip name an
96. d Note 1 In EXTRC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC12C67X be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent nor mal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin 4 Does not include GP3 For GP3 see parameters D061 and DO61A 5 This spec applies to GP3 MCLR configured as external MCLR and GP3 MCLR configured as input with internal pull up enabled 6 This spec applies when GP3 MCLR is configured as an input with pull up disabled The leakage current of the MCLR circuit is higher than the standard I O logic DS30561B page 98 1999 Microchip Technology Inc PIC12C67X 12 5 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats 1 TppS2ppS 3 Tcc st I2C specifications only 2 TppS 4 Ts I2C specifications only T F Frequency T Time Lowercase letters pp and their meanings pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI SC SCK do SDO ss ss dt Data in tO TOCKI io VO port ti T1CKI me MCLR wr WR Uppercase letters and their meanings S F Fall P Period H High R Rise Invalid Hi impedance V Valid L Low Z Hi impedance DC only AA output access
97. d either directly or indi rectly through the File Select Register FSR Section 4 5 1999 Microchip Technology Inc DS30561B page 11 PIC12C67X FIGURE 4 2 PIC12C67X REGISTER FILE 42 2 SPECIAL FUNCTION REGISTERS MAP The Special Function Registers are registers used by File File the CPU and Peripheral Modules for controlling the Address Address desired operation of the device These registers are implemented as static RAM 00h INDF INDF 1 80h f TA Oth TMRO OPTION 81h The Special Function Registers can be classified into 02h PCL PCL 82h two sets core and peripheral Those registers associ ated with the core functions are described in this sec 03h STATUS STATUS 83h tion and those related to the operation of the peripheral 04h FSR FSR 84h features are described in the section of that peripheral 05h GPIO TRIS 85h feature 06h 86h 07h 87h 08h 88h 09h 89h OAh PCLATH PCLATH 8Ah OBh INTCON INTCON 8Bh OCh PIR1 PIE1 8Ch ODh 8Dh OEh PCON BEh OFh OSCCAL 8Fh 10h 90h 11h 91h 12h 92h 13h 93h 14h 94h 15h 95h 16h 96h 17h 97h 18h 98h 19h 99h 1Ah 9Ah 1Bh 9Bh 1Ch 9Ch 1Dh 9Dh 1Eh ADRES 9Eh 1Fh ADCONO ADCON1 9Fh 20h AOh General Purpose Register General JCS BFh Purpose COh Register EFh 70h Mapped FOh in Bank 0 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations read as 0 Note 1
98. d logo the Microchip logo FilterLab KEELOG microlD MPLAB PIC PlCmicro PICMASTER PICSTART PRO MATE SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Tech nology Incorporated in the U S A and other countries dsPIC ECONOMONITOR FanSense FlexROM fuzzyLAB In Circuit Serial Programming ICSP ICEPIC microPort Migratable Memory MPASM MPLIB MPLINK MPSIM MXDEV PICC PICDEM PICDEM net rfPIC Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U S A Serialized Quick Turn Programming SQTP is a service mark of Microchip Technology Incorporated in the U S A All other trademarks mentioned herein are property of their respective companies 2002 Microchip Technology Incorporated Printed in the U S A All Rights Reserved D Printed on recycled paper Microchip received QS 9000 quality system certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona in July 1999 The Company s quality system processes and procedures are QS 9000 compliant for its PICmicro 8 bit MCUs KEELOQ code hopping devices Serial EEPROMS and microperipheral products In addition Microchip s quality system for the design and manufacture of development systems is ISO 9001 certified 2002 Microchip Technology Inc MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 23
99. d not be driven from external devices at the same time in order to change the level on this pin wired or wired and The resulting high output currents may damage the chip 1999 Microchip Technology Inc DS30561B page 31 PIC12C67X NOTES ae DS30561B page 32 1999 Microchip Technology Inc PIC12C67X 6 0 EEPROM PERIPHERAL OPERATION The PIC12CE673 and PIC12CE674 each have 16 bytes of EEPROM data memory The EEPROM mem ory has an endurance of 1 000 000 erase write cycles and a data retention of greater than 40 years The EEPROM data memory supports a bi directional 2 wire bus and data transmission protocol These two wires are serial data SDA and serial clock SCL that are mapped to bit6 and bit7 respectively of the GPIO reg ister SFR 06h Unlike the GPO GP5 that are con nected to the I O pins SDA and SCL are only connected to the internal EEPROM peripheral For most applications all that is required is calls to the following functions Byte Write Byte write routine Inputs EEPROM Address EEADDR EEPROM Data EEDATA Outputs Return 01 in W if OK else return 00 in W Read Current Read EEPROM at address currently held by EE device Inputs NONE Outputs EEPROM Data EEDATA k Return 01 in W if OK else return 00 in W Read Random Read EEPROM byte at supplied address Inputs EEPROM Address EEADDR Outputs EEPROM Data EEDATA Return 01 in W if OK els
100. ded and executed during the Q2 Q3 and Q4 cycles Data memory is read during Q2 operand read and written during Q4 destination write FIGURE 3 2 CLOCK INSTRUCTION CYCLE Qi Q2 93 a4 Qi Q2 Q3 Q4 Qi Q2 Q3 a4 osci VO K Oy NE A N VS WS SN Qi en Q2 ZA IE iX Internal Q3 fe FR Ta Do Q4 N PC PC PC 1 H PC 2 OSC2 CLKOUT A HA OER EXTRC and Fetch INST PC TAS modes Execute INST PC 1 Fetch INST PC 1 Execute INST PC Fetch INST PC 2 Execute INST PC 1 EXAMPLE 3 1 INSTRUCTION PIPELINE FLOW TCY0 Tcy1 Tcv2 TCY3 Tcv4 Tcy5 1 MOVLW 55h Fetch 1 Execute 1 2 MOVWF GPIO Fetch 2 Execute 2 3 CALL SUB 1 Fetch 3 Execute 3 4 BSF GPIO BIT3 Forced NOP Fetch 4 Flush 5 Instruction address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle except for any program branches These take two cycles since the fetched instruction is flushed from the pipeline while the new instruction is being fetched and then executed DS30561B page 10 1999 Microchip Technology Inc PIC12C67X 4 0 MEMORY ORGANIZATION 4 1 Program Memory Organization The PIC12C67X has a 13 bit program counter capable of addressing an 8K x 14 program memory space For the PIC12C671 and the PIC12CE673 the first 1K x 14 0000h 03FFh is implemented For the PIC12C6
101. dge Restrictions on the external clock input are dis cussed in detail in Section 7 2 The prescaler is mutually exclusively shared between the TimerO module and the Watchdog Timer The pres caler assignment is controlled in software by control bit PSA OPTION lt 3 gt Clearing bit PSA will assign the prescaler to the TimerO module The prescaler is not readable or writable When the prescaler is assigned to the TimerO module prescale values of 1 2 1 4 1 256 are selectable Section 7 3 details the operation of the prescaler 7 1 Timer0 Interrupt The TMRO interrupt is generated when the TMRO reg ister overflows from FFh to 00h This overflow sets bit TOIF INTCON lt 2 gt The interrupt can be masked by clearing bit TOIE INTCON lt 5 gt Bit TOIF must be cleared in software by the TimerO module interrupt ser vice routine before re enabling this interrupt The TMRO interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP See Figure 7 4 for TimerO interrupt timing PSA FIGURE 7 1 TIMERO BLOCK DIAGRAM Fosc 4 0 X mem GP2 TOCKI E Programmable AN2 INT Prescaler TOSE l PS lt 2 0 gt TOCS Note 1 TOCS TOSE PSA PS lt 2 0 gt OPTION lt 5 0 gt 2 The prescaler is shared with Watchdog Timer refer to Figure 7 6 for detailed block diagram Data Bus 8 Sync with Internal TMR0 clocks 2 TcY delay Set interrupt fl
102. e the error in measuring the interval between two edges on Timer0 input 4TOSC max 2 External clock if no prescaler selected prescaler output otherwise 3 The arrows indicate the points in time where sampling occurs 1999 Microchip Technology Inc DS30561B page 41 PIC12C67X 7 3 An 8 bit counter is available as a prescaler for the TimerO module or as a postscaler for the Watchdog Timer respectively Figure 7 6 For simplicity this counter is being referred to as prescaler throughout this data sheet Note that there is only one prescaler available which is mutually exclusively shared between Prescaler The PSA and PS lt 2 0 gt bits OPTION lt 3 0 gt determine the prescaler assignment and prescale ratio When assigned to the Timer0 module all instructions writing to the TMRO register e CLRF 1 MOVWF 1 BSF 1 x etc will clear the prescaler When assigned to WDT a CLRWDT instruction will clear the prescaler along with the Watchdog Timer The pres the Timer0 module and the Watchdog Timer Thus a caler is not readable or writable prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer and vice versa FIGURE 7 6 BLOCK DIAGRAM OF THE TIMERO WDT PRESCALER CLKOUT Fosc 4 Data Bus 8 d G
103. e PC The upper example in the figure shows how the PC is loaded on a write to PCL PCLATH 4 0 PCH The lower exam ple in the figure shows how the PC is loaded during a CALL or GOTO instruction PCLATH lt 4 3 gt PCH FIGURE 4 3 LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 12 8 7 O Instruction with PC PCL as Destination PCLATH lt 4 0 gt 8 5 ALU result PCLATH PCH PCL 12 11 10 8 7 0 PC i GOTO CALL 2 PCLATH lt 4 3 gt 11 Opcode 10 0 PCLATH 4 3 1 COMPUTED GOTO A Computed GOTO is accomplished by adding an off set to the program counter ADDWF PCL When doing a table read using a computed GOTO method care should be exercised if the table location crosses a PCL memory boundary each 256 byte block Refer to the application note Implementing a Table Read AN556 4 3 2 STACK The PIC12C67X family has an 8 level deep x 13 bit wide hardware stack The stack space is not part of either program or data space and the stack pointer is not readable or writable The PC is PUSHed onto the stack when a CALL instruction is executed or an inter rupt causes a branch The stack is POPed in the event ofa RETURN RETLW Or a RETFIE instruction execu tion PCLATH is not affected by a PUSH or POP oper ation The stack operates as
104. e parameters are characterized but not tested Note 1 Data in Typical Typ column is based on characterization results at 25 C This data is for design guidance only and is not tested 2 This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data 3 The supply current is mainly a function of the operating voltage and frequency Other factors such as bus loading oscillator type bus rate internal code execution pattern and temperature also have an impact on the current consumption a The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all VO pins tristated pulled to Vss TOCKI VDD MCLR VDD WDT disabled b For standby current measurements the conditions are the same except that the device is in SLEEP mode 4 For EXTRC osc configuration current through REXT is not included The current through the resistor can be estimated by the formula Ir VDD 2REXT mA with REXT in kOhm 5 The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VDD or Vss 6 INTRC calibration value is for 4MHz nominal at 5V 25 C 1999 Microchip Technology Inc DS30561B page 93 PIC12C67X 12 2 DC Characteristics PIC12LC671 672 Commercial Industrial PIC12LCE673 674 Commercial Industrial Standard Operating Conditions
105. e return 00 in W The code for these functions is available on our web site www microchip com The code will be accessed by either including the source code FL67XINC ASM or by linking FLASH67X ASM FLASH67X INC provides external definition to the calling program 6 0 1 SERIAL DATA SDA is a bi directional pin used to transfer addresses and data into and data out of the device For normal data transfer SDA is allowed to change only during SCL low Changes during SCL high are reserved for indicating the START and STOP condi tions 6 0 2 SERIAL CLOCK This SCL signal is used to synchronize the data trans fer from and to the EEPROM 6 1 Bus Characteristics The following bus protocol is to be used with the EEPROM data memory In this section the term proces sor is used to denote the portion of the PIC12C67X that interfaces to the EEPROM via software Data transfer may be initiated only when the bus is not busy During data transfer the data line must remain stable whenever the clock line is HIGH Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition Accordingly the following bus conditions have been defined Figure 6 3 6 1 1 BUS NOT BUSY A Both data and clock lines remain HIGH 6 1 2 START DATA TRANSFER B A HIGH to LOW transition of the SDA line while the clock SCL is HIGH determines a START condition All commands must be preceded by a START condition
106. e the minimum and should be lt 8 us for preferred operation This is because TAD when derived from Tosc is kept away from on chip phase clock transitions This reduces to a large extent the effects of digital switching noise This is not possible with the RC derived clock The loss of accuracy due to digital switching noise can be significant if many I O pins are active In systems where the device will enter SLEEP mode after the start of the A D conversion the RC clock source selection is required In this mode the digital noise from the modules in SLEEP are stopped This method gives high accuracy 8 7 Effects of a Reset A device reset forces all registers to their reset state This forces the A D module to be turned off and any conversion is aborted The value that is in the ADRES register is not modified for a Reset The ADRES regis ter will contain unknown data after a Power on Reset 8 8 Connection Considerations If the input voltage exceeds the rail values VSS or VDD by greater than 0 2V then the accuracy of the conver sion is out of specification Note For the PIC12C67X care must be taken when using the GP4 pin in A D conversions due to its proximity to the OSC1 pin An external RC filter is sometimes added for anti aliasing of the input signal The R component should be selected to ensure that the total source impedance is kept under the 10 kQ recommended specification Any external compone
107. eared by hardware when the A D conversion 0 A D converter module is shut off and consumes no operating current bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset 1999 Microchip Technology Inc DS30561B page 45 PIC12C67X REGISTER 8 2 ADCON1 REGISTER ADDRESS 9Fh U 0 U 0 U 0 U 0 U 0 R W 0 R W 0 R W 0 PCFG2 PCFG1 PCFGO R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 2 Unimplemented Read as 0 bit 1 0 PCFG lt 2 0 gt A D Port Configuration Control bits PCFG lt 2 0 gt GP4 GP2 GP1 GPO VREF 0000 A A A A VDD 001 A A VREF A GP1 010 D A A A VDD 011 D A VREF A GP1 100 D D A A VDD 101 D D VREF A GP1 110 D D D A VDD 111 D D D D VDD A Analog input D Digital VO Note 1 Value on reset 2 Any instruction that reads a pin configured as an analog input will read a O DS30561B page 46 1999 Microchip Technology Inc PIC12C67X The ADRES Register contains the result of the A D conversion When the A D conversion is complete the result is loaded into the ADRES register the GO DONE bit ADCONO 2 is cleared and A D interrupt flag bit ADIF PIE1 lt 6 gt is set The block diagrams of the A D module are shown in Figure 8 1 After the A D module has been con
108. ecification of the desired device When a prescaler is used the external clock input is divided by the asynchronous ripple counter type pres caler so that the prescaler output is symmetrical For the external clock to meet the sampling requirement the ripple counter must be taken into account There fore it is necessary for TOCKI to have a period of at least 4Tosc and a small RC delay of 40 ns divided by the prescaler value The only requirement on TOCKI high and low time is that they do not violate the mini mum pulse width requirement of 10 ns Refer to param eters 40 41 and 42 in the electrical specification of the desired device 7 2 2 TMRO INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks there is a small delay from the time the external clock edge occurs to the time the Timer0 mod ule is actually incremented Figure 7 5 shows the delay from the external clock edge to the timer incrementing FIGURE 7 5 TIMERO TIMING WITH EXTERNAL CLOCK iot G21 Q31 Q4 ail Q2l Q31 Q4 ail a2 Q3 Q4 fail Q21 asl Q4 i i i i Small pulse i External Clock Input or i Prescaler output SY V N i i ues samping hi External Clock Prescaler EL 1 i i d Output after sampling I Increment Timer0 Q4 Timer0 i TO X TO 1 X TO 2 Note 1 Delay from clock input change to Timer0 increment is 3Tosc to 7 Tosc Duration of Q Tosc Therefor
109. ects the number of the bit affected by the operation while f represents the number of the file in which the bit is located For literal and control operations K represents an eight or eleven bit constant or literal value TABLE 10 1 OPCODE FIELD DESCRIPTIONS Field Description Register file address 0x00 to Ox7F Working register accumulator Bit address within an 8 bit file register Literal field constant data or label x iIm oj z Don t care location 0 or 1 The assembler will generate code with x O It is the recommended form of use for compatibility with all Microchip software tools d Destination select d 0 store result in W d 1 store result in file register f Default is d 1 label Label name TOS Top of Stack PC Program Counter PCLATH Program Counter High Latch GIE Global Interrupt Enable bit WDT Watchdog Timer Counter TO Time out bit PD Power down bit dest Destination either the W register or the specified register file location Options Contents Assigned to lt gt Register bit field e Inthe set of italics User defined term font is courier The instruction set is highly orthogonal and is grouped into three basic categories Byte oriented operations Bit oriented operations Literal and control operations All instructions are executed within
110. ed 14h Unimplemented iam MEN 15h Unimplemented 16h Unimplemented 17h Unimplemented 18h Unimplemented 19h Unimplemented 1Ah Unimplemented E 1Bh Unimplemented Ge SC 1Ch Unimplemented 1Dh Unimplemented m 1Eh ADRES A D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 reserved CHS1 CHSO GO DONE reserved ADON 0000 0000 0000 0000 Legend x unknown u unchanged q value depends on condition unimplemented read as 0 Shaded locations are unimplemented read as 0 These registers can be addressed from either bank The upper byte of the program counter is not directly accessible PCLATH is a holding register for the PC lt 12 8 gt whose con tents are transferred to the upper byte of the program counter Other non power up resets include external reset through MCLR and Watchdog Timer Reset The IRP and RP1 bits are reserved on the PIC12C67X always maintain these bits clear The SCL GP7 and SDA GP6 bits are unimplemented on the PIC12C671 672 and read as 0 DS30561B page 13 1999 Microchip Technology Inc PIC12C67X TABLE 4 1 PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY CONT Value on V
111. ee Register 4 6 for register Bit1 is POR Power on Reset It is cleared on a Power on Reset and is unaffected otherwise The user sets this bit following a Power on Reset On subsequent resets if POR is 0 it will indicate that a Power on Reset must have occurred TABLE 9 4 TIME OUT IN VARIOUS SITUATIONS Oscillator Configuration Power up Wake up from SLEEP PWRTE 0 PWRTE 1 XT HS LP 72 ms 1024Tosc 1024Tosc 1024Tosc INTRC EXTRC 72 ms TABLE 9 5 STATUS PCON BITS AND THEIR SIGNIFICANCE POR TO PD 0 1 1 Power on Reset 0 0 x llegal TO is set on POR 0 x 0 Illegal PD is set on POR 1 0 u WDT Reset 1 0 0 WDT Wake up 1 u u MCLR Reset during normal operation 1 1 0 MCLR Reset during SLEEP or interrupt wake up from SLEEP Legend u unchanged x unknown DS30561B page 58 1999 Microchip Technology Inc PIC12C67X TABLE 9 6 RESET CONDITION FOR SPECIAL REGISTERS Condition Program STATUS PCON Counter Register Register Power on Reset 000h 0001 1xxx nens us MCLR Reset during normal operation 000h 000u uuuu u MCLR Reset during SLEEP 000h 0001 Ouuu u WDT Reset during normal operation 000h 0000 uuuu u WDT Wake up from SLEEP PC 1 uuu0 Ouuu u Interrupt wake up from SLEEP PC 1 uuul Ouuu u Legend u unchanged x unknown unimplemented bit
112. ement of each oscillator type including LC devices Sales and Support Data Sheets 1 Your local Microchip sales office 2 The Microchip Corporate Literature Center U S FAX 480 786 7277 3 The Microchip Worldwide Site www microchip com Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom mended workarounds To determine if an errata sheet exists for a particular device please contact one of the following Please specify which device revision of silicon and Data Sheet include Literature you are using New Customer Notification System Register on our web site www microchip com cn to receive the most current information on our products 1999 Microchip Technology Inc DS30561B page 127 Note the following details of the code protection feature on PICmicro MCUs The PICmicro family meets the specifications contained in the Microchip Data Sheet Microchip believes that its family of PlCmicro microcontrollers is one of the most secure products of its kind on the market today when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowl edge require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet The person doing so may be engaged in theft of intelle
113. er series perfect for applications with space limitations Low cost low power high perfor mance ease of use and UO flexibility make the PIC12C67X series very versatile even in areas where no microcontroller use has been considered before i e timer functions replacement of glue logic and PLD s in larger systems coprocessor applications 1 2 Family and Upward Compatibility The PIC12C67X products are compatible with other members of the 14 bit PIC16CXXX families 1 3 Development Support The PIC12C67X devices are supported by a full featured macro assembler a software simulator an in circuit emulator a low cost development programmer and a full featured programmer A C compiler and fuzzy logic support tools are also available 1999 Microchip Technology Inc DS30561B page 3 PIC12C67X TABLE 1 1 PIC12C67X amp PIC12CE67X FAMILY OF DEVICES PIC12C671 PIC12LC671 PIC12C672 PIC12LC672 PIC12CE673 PIC12LCE673 PIC12CE674 PIC12LCE674 Maximum 10 10 10 10 10 10 10 10 Frequency of Operation MHz EPROM 1024 x 14 1024 x 14 2048 x 14 2048 x 14 1024 x 14 1024 x 14 2048 x 14 2048 x 14 Program Memory Memor y RAM Data 128 128 128 128 128 128 128 128 Memory bytes EEPROM es 16 16 16 16 Data Memory bytes Timer TMRO TMRO TMRO TMRO TMRO TMRO TMRO TMRO Peripherals Module s A D Con 4 4 4 4 4 4 4 4 verter 8 bit Channels Wa
114. es using separate buses This improves bandwidth over traditional von Neumann architecture in which pro gram and data are fetched from the same memory using the same bus Separating program and data buses also allow instructions to be sized differently than the 8 bit wide data word Instruction opcodes are 14 bits wide making it possible to have all single word instructions 14 bit wide program memory access bus fetches a 14 bit instruction in a single instruction cycle A two stage pipeline overlaps fetch and execu tion of instructions Example 3 1 Conseguently all instructions 35 execute in a single cycle 400 ns 10 MHz except for program branches The table below lists program memory EPROM data memory RAM and non volatile memory EEPROM for each PIC12C67X device EEPROM Device Program RAM Data Data Memory Memory Memory PIC12C671 1K x 14 128 x 8 PIC12C672 2K x 14 128x8 PIC12CE673 1K x 14 128x8 16x8 PIC12CE674 2K x 14 128x8 16x8 The PIC12C67X can directly or indirectly address its register files or data memory All special function regis ters including the program counter are mapped in the data memory The PIC12C67X has an orthogonal symmetrical instruction set that makes it possible to carry out any operation on any register using any addressing mode This symmetrical nature and lack of special optimal situations make programming with the PIC12C67X simple yet ef
115. eset Status bit 1 No Power on Reset occurred 0 A Power on Reset occurred must be set in software after a Power on Reset occurs bit 0 Unimplemented Read as 0 DS30561B page 20 1999 Microchip Technology Inc PIC12C67X 4 2 2 7 OSCCAL REGISTER The Oscillator Calibration OSCCAL Register is used to calibrate the internal 4 MHz oscillator It contains four bits for fine calibration and two other bits to either increase or decrease frequency REGISTER 4 7 OSCCAL REGISTER ADDRESS 8Fh R W 0 R W 1 R W 1 R W 1 R W 0 R W 0 U 0 U 0 CAL3 CAL2 CAL1 CALO CALFST CALSLW R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 4 CAL lt 3 0 gt Fine Calibration bit 3 CALFST Calibration Fast 1 Increase frequency 0 No change bit 2 CALSLW Calibration Slow 1 Decrease frequency 0 No change bit 1 0 Unimplemented Read as 0 Note If CALFST 1 and CALSLW 1 CALFST has precedence 1999 Microchip Technology Inc DS30561B page 21 PIC12C67X 4 3 PCL and PCLATH The Program Counter PC is 13 bits wide The low byte comes from the PCL Register which is a readable and writable register The high byte PC lt 12 8 gt is not directly readable or writable and comes from PCLATH On any reset the PC is cleared Figure 4 3 shows the two situations for the loading of th
116. eset as long as the PWRT is active The PWRT s time delay allows VDD to rise to an acceptable level A configuration bit is provided to enable disable the PWRT The power up time delay will vary from chip to chip due to VDD temperature and process variation See Table 11 4 9 4 3 OSCILLATOR START UP TIMER OST The Oscillator Start up Timer OST provides 1024 oscillator cycle from OSC1 input delay after the PWRT delay is over This ensures that the crystal oscil lator or resonator has started and stabilized The OST time out is invoked only for XT LP and HS modes and only on Power on Reset or wake up from SLEEP 9 4 4 TIME OUT SEQUENCE On power up the Time out Sequence is as follows first PWRT time out is invoked after the POR time delay has expired then OST is activated The total time out will vary based on oscillator configuration and the status of the PWRT For example in RC mode with the PWRT disabled there will be no time out at all Figure 9 7 Figure 9 8 and Figure 9 9 depict time out sequences on power up Since the time outs occur from the POR pulse if MCLR is Kept low long enough the time outs will expire Then bringing MCLR high will begin execution immediately Figure 9 9 This is useful for testing purposes or to synchronize more than one PIC12C67X device operat ing in parallel 9 4 5 POWER CONTROL PCON STATUS REGISTER The Power Control Status Register PCON address 8Eh has one bit S
117. esult back read modify write The user should keep this in mind when operating on special function registers such as ports DS30561B page 70 1999 Microchip Technology Inc PIC12C67X TABLE 10 2 INSTRUCTION SET SUMMARY Mnemonic Description Cycles 14 Bit Opcode Status Notes Operands MSb LSb Affected BYTE ORIENTED FILE REGISTER OPERATIONS ADDWF f d Add W and f 1 00 0111 afff ffff C DC Z 1 2 ANDWF f d ANDW with f 1 00 0101 dfff ffff Z 1 2 CLRF f Clear f 1 00 0001 1fff ffff Z 2 CLRW Clear W 1 00 0001 0000 0011 Z COMF f d Complement f 1 00 001 dfff ffff Z 1 2 DECF Ld Decrementf 1 00 0011 dfff ffff 2Z 1 2 DECFSZ f d Decrement f Skip if 0 1 2 00 011 dfff ffff 1 2 3 INCF fd Increment f 1 00 010 dfff free Z 1 2 INCFSZ fd Increment f Skip if 0 1 2 00 111 dfff ffff 1 2 3 IORWF fd Inclusive OR W with f 1 00 0100 dfff ffff Z 1 2 MOVF fd Move f 1 00 000 afff ffff Z 1 2 MOVWF f Move W to f 1 00 0000 1fff ffff NOP No Operation 1 00 0000 OxxO 0000 RLF f d Rotate Left f through Carry 1 00 01 dfff ffff C 1 2 RRF f d Rotate Right f through Carry 1 00 00 dfff ffff C 1 2 SUBWF f d Subtract W from f 1 00 0010 afff ffff C DC Z 1 2 SWAPF f d Swap nibbles in f 1 00 10 dfff ffff 1 2 XORWF f d Exclusive OR W with f 1 00 0110 afff ffff Z 1 2 BIT ORIENTED FILE REGISTER OPERATIONS BCF fb Bit Clear f 1 0 OObb bfff ffff 1 2 BSF f b BitSetf 1 0 Olbb bfff ffff 1
118. ficient In addition the learn ing curve is reduced significantly PIC12C67X devices contain an 8 bit ALU and working register The ALU is a general purpose arithmetic unit It performs arithmetic and Boolean functions between the data in the working register and any register file The ALU is 8 bits wide and capable of addition sub traction shift and logical operations Unless otherwise mentioned arithmetic operations are two s comple ment in nature In two operand instructions typically one operand is the working register W register The other operand is a file register or an immediate con stant In single operand instructions the operand is either the W register or a file register The W register is an 8 bit working register used for ALU operations It is not an addressable register Depending on the instruction executed the ALU may affect the values of the Carry C Digit Carry DC and Zero Z bits in the STATUS register The C and DC bits operate as a borrow bit and a digit borrow out bit respectively in subtraction See the SUBLW and SUBWF instructions for examples 1999 Microchip Technology Inc DS30561B page 7 PIC12C67X FIGURE 3 1 PIC12C67X BLOCK DIAGRAM
119. figured as desired the selected channel must be acquired before the con version is started The analog input channels must have their corresponding TRIS bits selected as an input To determine sample time see Section 8 1 After this acquisition time has elapsed the A D conversion can be started The following steps should be followed for doing an A D conversion 1 Configure the A D module Configure analog pins voltage reference and digital VO ADCON1 and TRIS Select A D input channel ADCONO Select A D conversion clock ADCONO Turn on A D module ADCONO FIGURE 8 1 A D BLOCK DIAGRAM Configure A D interrupt if desired Clear ADIF bit Set ADIE bit Set GIE bit Wait the required acquisition time Start conversion Set GO DONE bit ADCONO Wait for A D conversion to complete by either Polling for the GO DONE bit to be cleared OR Waiting for the A D interrupt Read A D Result Register ADRES clear bit ADIF if required For the next conversion go to step 1 step 2 or step 3 as required The A D conversion time per bit is defined as TAD A minimum wait of 2TAD is required before next acquisition starts VIN CHS lt 1 0 gt 11 S DI GP4 AN3 Input voltage A D Converter VREF Reference i o TE qua x GP2 AN2 i E O N x GP1 AN1 VREF 00 aos x GPO ANO voltage Are PCFG lt 2 0 gt 1999
120. form of HEX files for device program mers or it can generate relocatable objects for MPLINK MPASM has a command line interface and a Windows shell and can be used as a standalone application on a Windows 3 x or greater system MPASM generates relocatable object files Intel standard HEX files MAP files to detail memory usage and symbol reference an absolute LST file which contains source lines and gen erated machine code and a COD file for MPLAB debugging MPASM features include MPASM and MPLINK are integrated into MPLAB projects MPASM allows user defined macros to be created for streamlined assembly MPASM allows conditional assembly for multi pur pose source files MPASM directives allow complete control over the assembly process 11 3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers and inte grated development environments for Microchip s PIC17CXXX and PIC18CXXX family of microcontrol lers respectively These compilers provide powerful integration capabilities and ease of use not found with other compilers For easier source level debugging the compilers pro vide symbol information that is compatible with the MPLAB IDE memory display 1999 Microchip Technology Inc DS30561B page 83 PIC12C67X 11 4 MPLINK MPLIB Linker Librarian MPLINK is a relocatable linker for MPASM and MPLAB C17 and MPLAB C18 It
121. h INTRC TTL Input Buffer RD TRIS Q D EN RD PORT Ke DS30561B page 30 1999 Microchip Technology Inc PIC12C67X TABLE 5 1 SUMMARY OF PORT REGISTERS Value on Value on Power on all other Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Resets 85h TRIS GPIO Data Direction Register S511 1111 oe bet celia eta 81h OPTION GPPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 03h STATUS IRPU RP10 RPO TO PD Z DC C 0001 1xxx 0004 quuu 05h GPIO scL spat GP5 GP4 GP3 GP2 GP1 GPO 11xx xxxx 11uu uuuu Legend Shaded cells not used by Port Registers read as 0 unimplemented read as 0 x unknown u unchanged q see tables in Section 9 4 for possible values Note 1 The IRP and RP1 bits are reserved on the PIC12C67X always maintain these bits clear 2 The SCL and SDA bits are unimplemented on the PIC12C671 and PIC12C672 5 4 VO Programming Considerations 5 4 1 BI DIRECTIONAL VO PORTS Any instruction which writes operates internally as a read followed by a write operation The BCF and BSF instructions for example read the register into the CPU execute the bit operation and write the result back to the register Caution must be used when these instructions are applied to a port with both inputs and outputs defined For example a BSF operation on bit5 of GPIO will cause all eight bi
122. h the eight bit literal K The result is placed in the W reg ister 1 1 ANDLW Ox5F Before Instruction W OxA3 After Instruction W 0x03 AND W with f label ANDWF fd 0 lt f lt 127 de 0 1 W AND f dest Z 00 0101 dfff ffff AND the W register with register f If d is O the result is stored in the W register If d is 1 the result is stored back in register f 1 1 ANDWF FSR 1 Before Instruction W 0x17 FSR OxC2 After Instruction W 0x17 FSR 0x02 DS30561B page 72 1999 Microchip Technology Inc PIC12C67X BCF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example BSF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Bit Clear f label BCF fb O lt f lt 127 O lt b lt 7 0 gt f lt b gt None 01 00bb bfff ffff Bit b in register f is cleared 1 1 BCF FLAG REG 7 Before Instruction FLAG REG 0xC7 After Instruction FLAG REG 0x47 Bit Set f label BSF f O lt f lt 127 O lt b lt 7 1 gt f lt b gt None 01 01bb bfff ffff Bit b in register T is set 1 1 BSF FLAG REG 7 Before Instruction FLAG REG 0x0A After Instruction FLAG REG 0x8A BTFSC Syntax Operands Operation Status Affected Encoding Description Words Cycles Example
123. ickness A2 069 074 078 1 75 1 88 1 98 Standoff Al 002 005 010 0 05 0 13 0 25 Overall Width E 300 313 325 7 62 7 95 8 26 Molded Package Width E1 201 208 212 5 11 5 28 5 38 Overall Length D 202 205 210 5 13 5 21 5 33 Foot Length L 020 025 030 0 51 0 64 0 76 Foot Angle 0 4 8 0 4 8 Lead Thickness c 008 009 010 0 20 0 23 0 25 Lead Width B 014 017 020 0 36 0 43 0 51 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom B 0 12 15 0 12 15 Controlling Parameter Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side Drawing No C04 056 1999 Microchip Technology Inc DS30561B page 117 PIC12C67X 8 Lead Ceramic Side Brazed Dual In line with Window JW 300 mil qT T n 1 U 1 M i ea beir L A1 i C B1 _ A D Leg eB B ke Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p 100 2 54 Top to Seating Plane A 145 165 185 3 68 4 19 4 70 Top of Body to Seating Plane A2 103 123 143 2 62 3 12 3 63 Standoff A1 025 035 045 0 64 0 89 1 14 Package Width E1 280 290 300 7 11 7 37 7 62 Overall Length D 510 520 530 12 95 13 21 13 46 Tip to Seati
124. iguration memory space 2000h 3FFFh which can be accessed only during programming REGISTER 9 1 CONFIGURATION WORD CP1 CPO CP1 CPO CP1 CPO MCLRE CP1 CPO PWRTE WDTE FOSC2 FOSC1 FOSCO Register CONFIG bit13 bi Address 2007h bit 13 8 CP lt 1 0 gt Code Protection bit pairs 6 5 11 Code protection off 00 All memory is code protected MCLRE Master Clear Reset Enable bit 1 Master Clear Enabled 0 Master Clear Disabled PWRTE Power up Timer Enable bit 1 PWRT disabled 0 PWRT enabled WDTE Watchdog Timer Enable bit 1 WDT enabled 0 WDT disabled FOSC lt 2 0 gt Oscillator Selection bits 111 EXTRC Clockout on OSC2 110 EXTRC OSC2 is VO 101 INTRC Clockout on OSC2 100 INTRC OSC2 is VO 011 Invalid Selection 010 HS Oscillator 001 XT Oscillator 000 LP Oscillator bit 7 bit 4 bit 3 bit 2 0 Note 1 10 Locations 400h through 7FEh code protected do not use for PIC12C671 and PIC12CE673 01 Locations 200h through 7FEh code protected All of the CP lt 1 0 gt pairs have to be given the same value to enable the code protection scheme listed 1999 Microchip Technology Inc DS30561B page 53 PIC12C67X 9 2 Oscillator Configurations 9 2 1 OSCILLATOR TYPES The PIC12C67X can be operated in seven different oscillator modes The user can program three configuration bits FOSC lt 2
125. ime out status bit TO is set Watchdog Timer and its prescaler are cleared The processor is put into SLEEP mode with the oscillator stopped 1 1 SLEEP 1999 Microchip Technology Inc DS30561B page 79 PIC12C67X SUBLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example 1 Example 2 Example 3 Subtract W from Literal label SUBLW k 0 lt k lt 255 k W gt W C DC Z 11 110x kkkk kkkk The W register is subtracted 2 s complement method from the eight bit literal k The result is placed in the W register 1 1 SUBLW 0x02 Before Instruction W 1 C After Instruction W 1 C 1 resultis positive Before Instruction W 2 C After Instruction W 0 C 1 result is zero Before Instruction W 3 C After Instruction W OxFF C O resultis nega tive SUBWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example 1 Example 2 Example 3 Subtract W from f label SUBWF fd O lt f lt 127 de 0 1 f W gt dest C DC Z 00 0010 dfff TEET Subtract 2 s complement method W register from register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in regis ter f 1 1 SUBWE REG1 1 Before Instruction REG1 3 W 2
126. in the event of MCLR VPP pin breakdown due to Electrostatic Discharge ESD or Electrical Overstress EOS FIGURE 9 11 EXTERNAL BROWN OUT PROTECTION CIRCUIT 1 MCLR PIC12C67X Note 1 This circuit will activate reset when VDD goes below Vz 0 7V where Vz Zener voltage 2 Resistors should be adjusted for the character istics of the transistor FIGURE 9 12 EXTERNAL BROWN OUT PROTECTION CIRCUIT 2 VDD MCLR PIC12C67X Note 1 This brown out circuit is less expensive albeit less accurate Transistor Q1 turns off when VDD is below a certain level such that R1 VDD 0 7V R1 R2 2 Resistors should be adjusted for the charac teristics of the transistor 1999 Microchip Technology Inc DS30561B page 61 PIC12C67X 9 5 Interrupts There are four sources of interrupt Interrupt Sources TMRO Overflow Interrupt External Interrupt GP2 INT pin GPIO Port Change Interrupts pins GPO GP1 GP3 A D Interrupt The Interrupt Control Register INTCON records indi vidual interrupt requests in flag bits It also has individ ual and global interrupt enable bits Note Individual interrupt flag bits are set regard less of the status of their corresponding mask bit or the GIE bit A global interrupt enable bit GIE INTCON lt 7 gt enables if set all un masked interrupts or disables if cleared all interru
127. initiated in the same way as write operations with the exception that the R W bit of the EEPROM address is set to one There are three basic types of read operations current address read random read and sequential read Read Operations 6 5 1 CURRENT ADDRESS READ The EEPROM contains an address counter that main tains the address of the last word accessed internally incremented by one Therefore if the previous read access was to address n the next current address read operation would access data from address n 1 Upon receipt of the EEPROM address with the R W bit set to one the EEPROM issues an acknowledge and trans mits the 8 bit data word The processor will not acknowledge the transfer but does generate a stop condition and the EEPROM discontinues transmission Figure 6 8 6 5 2 RANDOM READ Random read operations allow the processor to access any memory location in a random manner To perform this type of read operation first the word address must be set This is done by sending the word address to the EEPROM as part of a write operation After the word address is sent the processor generates a start condi tion following the acknowledge This terminates the write operation but not before the internal address pointer is set Then the processor issues the control byte again but with the R W bit set to a one The EEPROM will then issue an acknowledge and trans mits the 8 bit data word The processor will not ackn
128. into STATUS register SWAPF W_TEMP E Swap W TEMP SWAPE W_TEMP W Swap W_TEMP into W RETFIE Return from interrupt EXAMPLE 9 2 SAVING STATUS AND W REGISTERS USING SHARED RAM 0x70 0x7F MOVWE W_TEMP Copy W to TEMP register bank independent MOVE STATUS W Move STATUS register into W MOVWE STATUS TEMP Save contents of STATUS register ISR MOVE STATUS TEMP W Retrieve copy of STATUS register MOVWE STATUS Restore pre isr STATUS register contents SWAPF W TEMP F SWAPE W TEMP W Restore pre isr W register contents RETFIE Return from interrupt DS30561B page 64 1999 Microchip Technology Inc PIC12C67X 9 7 Watchdog Timer WDT The Watchdog Timer is a free running on chip RC oscillator which does not require any external compo nents This RC oscillator is separate from the RC oscil lator of the OSC1 CLKIN pin That means that the WDT will run even if the clock on the OSC1 CLKIN and OSC2 CLKOUT pins of the device has been stopped for example by execution of a SLEEP instruction Dur ing normal operation a WDT time out generates a device RESET Watchdog Timer Reset If the device is in SLEEP mode a WDT time out causes the device to wake up and continue with normal operation Watch dog Timer Wake up The WDT can be permanently disabled by clearing configuration bit WDTE Section 9 1 9 7 1 WDT PERIOD The WDT has a
129. ion 2 RETURN After Interrupt PC TOS Rotate Left f through Carry label RLF fd O lt f lt 127 de 0 1 See description below C 00 1101 dfff ffff The contents of register f are rotated one bit to the left through the Carry Flag If d is 0 the result is placed in the W register If d is 1 the result is stored back in reg ister f MEE EG Register f w RLF REGI 0 Before Instruction REGI 1110 0110 C 0 After Instruction REGI 1110 0110 W 1100 1100 C 1 RRF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example SLEEP Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Rotate Right f through Carry label RRF fd O lt f lt 127 de 0 1 See description below C 00 1100 dfff ffff The contents of register f are rotated one bit to the right through the Carry Flag If d is 0 the result is placed in the W register If d is 1 the result is placed back in reg ister f gt C Register f m 1 1 RRF REG1 0 Before Instruction REGI 1110 0110 C 0 After Instruction REGI 1110 0110 W 0111 0011 C 0 label SLEEP None 00h WDT 0 gt WDT prescaler 1 TO 0 PD TO PD 00 0000 0110 0011 The power down status bit PD is cleared T
130. ion results at 25 C This data is for design guidance only and is not tested 2 This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data 3 The supply current is mainly a function of the operating voltage and frequency Other factors such as bus loading oscillator type bus rate internal code execution pattern and temperature also have an impact on the current consumption a The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all VO pins tristated pulled to Vss TOCKI VDD MCLR VDD WDT disabled b For standby current measurements the conditions are the same except that the device is in SLEEP mode 4 For EXTRC osc configuration current through REXT is not included The current through the resistor can be estimated by the formula Ir VDD 2REXT mA with REXT in kOhm 5 The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all VO pins in hi impedance state and tied to VDD or Vss 6 INTRC calibration value is for 4MHz nominal at 5V 25 C DS30561B page 94 1999 Microchip Technology Inc PIC12C67X 12 3 DC CHARACTERISTICS PIC12C671 672 Commercial Industrial Extended PIC12CE673 674 Commercial Industrial Extended DC CHARACTERISTICS Standard Operating Conditions unless otherwise specified Operating temperature 0 C lt
131. istics Standard Operating Conditions unless otherwise specified Operating Temperature 0 C lt TA 70 C commercial 40 C lt TA lt 85 C industrial 40 C lt TA 125 C extended Operating Voltage VDD range is described in Section 10 1 ae Sym Characteristic Min Typ Max Units Conditions Internal Calibrated RC Frequency 3 65 4 00 4 28 MHz VDD 5 0V Internal Calibrated RC Frequency 3 55 4 00 4 31 MHz VDD 2 5V These parameters are characterized but not tested Note 1 Data in the Typical Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1999 Microchip Technology Inc DS30561B page 101 PIC12C67X FIGURE 12 6 CLKOUT AND VO TIMING O4 Q1 Q2 i Q3 OSC1 CLKOUT a fa ie alme de ts ie de cem NER VO Pin input LR 2 EE KE T 15 z gt I ier old value i ne i new value i 20 21 Note Refer to Figure 12 4 for load conditions TABLE 12 3 CLKOUT AND VO TIMING REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 10 TosH2ckL OSC1T to CLKOUTJ 75 200 ns Note 1 11 TosH2ckH OSC1T to CLKOUTT 75 200 ns Note 1 12 TckR CLKOUT rise time 35 100 ns Note 1 13 TckF CLKOUT fall time gem 35
132. it 6 u If wake up was due to A D completing then bit 3 O all other interrupts generating a wake up will cause bit 3 u meo 1999 Microchip Technology Inc DS30561B page 59 PIC12C67X FIGURE 9 7 TIME OUT SEGUENCE ON POWER UP MCLR NOT TIED TO VDD CASE 1 VDD mm MCLR INTERNAL POR TPWRF PWRT TIME OUT Tosr OST TIME OUT INTERNAL RESET FIGURE 9 8 TIME OUT SEQUENCE ON POWER UP MCLR NOT TIED TO Vpp CASE 2 VDD EE l MCLR INTERNAL POR we TPWRF gt PWRT TIME OUT OST TIME OUT INTERNAL RESET FIGURE 9 9 TIME OUT SEGUENCE ON POWER UP MCLR TIED TO VDD VDD mm MCLR INTERNAL POR ia TPWRT PWRT TIME OUT 14 TOSTe OST TIME OUT INTERNAL RESET DS30561B page 60 1999 Microchip Technology Inc PIC12C67X FIGURE 9 10 EXTERNAL POWER ON RESET CIRCUIT FOR SLOW VDD POWER UP VDD AD R A MCLR c PIC12C67X Note 1 External Power on Reset circuit is required only if VDD power up slope is too slow The diode D helps discharge the capacitor quickly when VDD powers down 2 R lt 40kQ is recommended to make sure that voltage drop across R does not violate the device s electrical specification 3 R121000 to 1 KQ will limit any current flowing into MCLR from external capacitor C
133. itera EE TimerO WDT Prescaler 42 Watchdog Timer BSF Instruction is i dci roh nee a e iaiia BIESG InStruetOR sie se EN rrt ede Ge eb de ass BESS INSttuctiOn EE CAL2 bit 85 CALS Dit du arce AN At eat eens AE EAM END ATI CALFST teer EE CALL Instruction SO GALSLWBIE ta Garry DR hearra san Clocking Scheme Loi CERF INStruCtiOn EE EER Ge o nene tte tte etn 74 CLRW Instruction 74 CLRWDT Instruction 75 Code Examples Changing Prescaler Timer0 to WDT Changing Prescaler WDT to Timer0 E Indirect Addressing esee Code Protection COMF Instruction Computed GOTO is Configuration Bits eee ee ee ke RA ee D DC Characteristics PIC12C671 672 PIC12CE673 674 PIC12LC671 672 PIC12LCE673 674 DECF Instruction Sat DECESZ lristructionizl ease a N GESE eerte Development Support sese Digit Carry bit Direct Addressing ss E EEPROM Peripheral Operation Electrical Characteristics PIC12C67X F Family of Devices ss 4 Fet aer d i aud deh ee US 1 ESR RegIsters Lines ee pres ee hend ems nas 13 14 23 G General Description 3 GIE bibu EE EE OUE IE OG 62 GOTO Instruction 1999 Microchip Technology Inc DS30561B page 121 PIC12C67X VON ehm 25 eh di RE RA EE ra es 25 VO Programming Consideratio
134. ke up Yes Yes Yes Yes Yes Yes Yes Yes from SLEEP on pin change nterrupt 4 4 4 4 4 4 4 4 Sources O Pins 5 5 5 5 5 5 5 5 nput Pins 1 1 1 1 1 1 1 1 nternal Yes Yes Yes Yes Yes Yes Yes Yes Pull ups n Circuit Yes Yes Yes Yes Yes Yes Yes Yes Serial Programming Number of 35 35 35 35 35 35 35 35 nstructions Voltage 3 0V 5 5V 2 5V 5 5V 3 0V 5 5V 2 5V 5 5V 3 0V 5 5V 2 5V 5 5V 3 0V 5 5V 2 5V 5 5V Range Volts Packages 8 pin DIP 8 pin DIP 8 pin DIP 8 pin DIP 8 pin DIP 8 pin DIP 8 pin DIP 8 pin DIP JW SOIC JW SOIC JW SOIC JW SOIC JW JW JW JW All PIC12C67X devices have Power on Reset selectable Watchdog Timer selectable code protect and high I O current capability All PIC12C67X devices use serial programming with data pin GPO and clock pin GP1 HEESE EE EE ll __ _ gt K_ lt X_ es DS30561B page 4 1999 Microchip Technology Inc PIC12C67X 2 0 PIC12C67X DEVICE VARIETIES A variety of frequency ranges and packaging options are available Depending on application and production requirements the proper device option can be selected using the information in the PIC12C67X Product Iden tification System section at the end of this data sheet When placing orders please use that page of the data sheet to specify the correct part number For example the PIC12C67X device type is indicated
135. l A dq papau e8V1dW soo a1eMYOS TT ET SAM PAZ pue Spie0g ouiag DS30561B page 87 1999 Microchip Technology Inc PIC12C67X NOTES DS30561B page 88 1999 Microchip Technology Inc PIC12C67X 12 0 ELECTRICAL SPECIFICATIONS FOR PIC12C67X Absolute Maximum Ratings T Ambient temperature under Dlas i etie e a Hee eed Eee iter 40 to 125 C Storage ul 65 C to 150 C Voltage on any pin with respect to Vss except VDD and MCL 0 3V to VDD 0 3V Voltage on VDD With tespect to VSS ua y Ati i en as 0 to 7 0V Voltage on MCLR with respect to VSS Note 2 0 to 14V Total power dissipation Note EE 700 mW Maximum current out Of VSS TEE 200 mA Maximumrc rrentinto VDD PIM eebe rece a a ik EE ee Ge NT docte dde ated ne eh le sea EE ee 150 mA Input clamp current IK VI lt 0 or VI gt VDD se se see Ge SR Sea ee GR See ee Ge Ge ee Gee ee SA Ge AR SA i ent ee SA ee SA Ge Ge ee SA Gee SA ee 20 mA Output clamp current lok VO lt 0 or VO gt MDDI 20 mA Maximum output current sunk by any VO pin is 25 mA Maximum output current sourced by any VO pin sisi 25 mA Maximum current sunk by GPIO pins combined sis 100 mA Maximum current sourced by GPIO pins combined iii 100 mA Note 1 Power dissipation is calculated as follows Pdis VDD x IDD Y 10H gt VDD VOH x IOH X Vol x IOL NOTICE Stresses above those listed under Absolute Maximum Ratings may cau
136. latches That is if an output driver on a pin is enabled and driven high but the external system is holding it low a read of the port will indicate that the pin is low Upon reset the TRIS Register is all 1 s making all pins inputs TRIS for pins GP4 and GPS is forced to a 1 where appropriate Writes to TRIS lt 5 4 gt will have an effect in EXTRC and INTRC oscillator modes only When GP4 is configured as CLKOUT changes to TRIS lt 4 gt will have no effect 5 3 VO Interfacing The equivalent circuit for an I O port pin is shown in Figure 5 1 through Figure 5 5 All port pins except GP3 which is input only may be used for both input and output operations For input operations these ports are non latching Any input must be present until read by an input instruction e MOVF GPIO W The outputs are latched and remain unchanged until the output latch is rewritten To use a port pin as output the corresponding direction control bit in TRIS must be cleared 0 For use as an input the corresponding TRIS bit must be set Any I O pin except GP3 can be programmed individually as input or output Port pins GP6 SDA and GP7 SCL are used for the serial EEPROM interface on the PIC12CE673 674 These port pins are not available externally on the package Users should avoid writing to pins GP6 SDA and GP7 SCL when not communicating with the serial EEPROM memory Please see Section 6 0 EEPROM Peripheral Operation f
137. le by using your favorite Internet browser to attach to www microchip com The file transfer site is available by using an FTP ser vice to connect to ftp ftp microchip com The web site and file transfer site provide a variety of services Users may download files for the latest Development Tools Data Sheets Application Notes User s Guides Articles and Sample Programs A vari ety of Microchip specific business information is also available including listings of Microchip sales offices distributors and factory representatives Other data available for consideration is Latest Microchip Press Releases Technical Support Section with Frequently Asked Questions Design Tips Device Errata Job Postings Microchip Consultant Program Member Listing Links to other useful web sites related to Microchip Products Conferences for products Development Sys tems technical information and more Listing of seminars and events Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides System users a listing of the latest versions of all of Microchip s development systems software products Plus this line provides information on how customers can receive any currently available upgrade kits The Hot Line Numbers are 1 800 755 2345 for U S and most of Canada and 1 480 786 7302 for the rest of the world 981103 Trademarks The Microchip name logo PIC PICmicro PIC
138. lt 70 C commercial 40 C lt TA lt 85 C industrial 40 C lt TA lt 125 C extended Operating voltage VDD range as described in DC spec Section 12 1 and DC CHARACTERISTICS Section 12 2 Param Characteristic Sym Min Typt Max Units Conditions No Output High Voltage D090 UO ports Note 3 VOH VDD 0 7 V loH 3 0 mA VDD 4 5V 40 C to 85 C D090A VDD 0 7 V loH 2 5 mA VDD 4 5V 40 C to 125 C D092 OSC2 CLKOUT VDD 0 7 V loH 1 3 mA VDD 4 5V 40 C to 85 C D092A VDD 0 7 V loH 1 0 mA VDD 4 5V 40 C to 125 C Capacitive Loading Specs on Output Pins D100 OSC2 pin Cosc2 15 pF in XT and LP modes when external clock is used to drive OSC1 D101 All VO pins Clo 50 pF T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In EXTRC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC12C67X be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin 4 Does not include GP3 For GP3 see parameters D0
139. lt k lt 2047 PC 1 TOS k gt PC lt 10 0 gt PCLATH lt 4 3 gt PC lt 12 11 gt None 10 Okkk kkkk kkkk Call Subroutine First return address PC 1 is pushed onto the stack The eleven bit immedi ate address is loaded into PC bits lt 10 0 gt The upper bits of the PC are loaded from PCLATH CALLis a two cycle instruction HERE CALL THER E Before Instruction C Address HERE After Instruction PC Address THERE TOS Address HERE 1 CLRF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example CLRW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Clear f label CLRF f 0 lt f lt 127 00h f 12Z Z 00 0001 LEEF DID The contents of register f are cleared and the Z bit is set 1 1 CLRF FLAG REG Before Instruction FLAG REG After Instruction FLAG REG Z Il o x a gt Clear W label CLRW None 00h W 1 7 Z 00 0001 0000 0011 W register is cleared Zero bit Z is set 1 1 CLRW Before Instruction W 0x5A After Instruction W 0x00 Z 1 DS30561B page 74 1999 Microchip Technology Inc PIC12C67X CLRWDT Syntax Operands Operation Status Affected Encoding Description Words Cycles Example COMF Syntax Operands Operation Status Affected Encodi
140. n TABLE 8 1 TAD vs DEVICE OPERATING FREQUENCIES AD Clock Source TAD Device Frequency Operation ADCS lt 1 0 gt 4 MHz 1 25 MHz 333 33 kHz 2Tosc 00 500 ns 1 6 us Gus BTOSC 01 2 0 us 6 4 us 24 us 9 32Tosc 10 8 0 us 25 6 us 96 us Internal ADC RC Oscillator 11 2 6 us 1 4 2 6 ys 2 6 ys Note 1 The RC source has a typical TAD time of 4 us 2 These values violate the minimum required TAD time mio For faster conversion times the selection of another clock source is recommended While in RC mode with device frequency above 1 MHz conversion accuracy is out of specification For extended voltage devices LC please refer to Electrical Specifications section 1999 Microchip Technology Inc DS30561B page 49 PIC12C67X 8 4 A D Conversions Clearing the GO DONE bit during a conversion will abort the current conversion The ADRES register will NOT be updated with the partially completed A D con version sample That is the ADRES register will con tinue to contain the value of the last completed conversion or the last value written to the ADRES reg ister After the A D conversion is aborted a 2TAD wait The GO DONE bit should NOT be set in is required before the next acquisition is started After this 2TAD wait an acquisition is automatically started on the selected channel Example 8 2 shows how to perform an A D conversion The GPIO pins are configured as analog i
141. n intended For example CLRF STATUS will clear the upper three bits and set the Z bit This leaves the STATUS Register as 000u uluu where u unchanged REGISTER 4 1 It is recommended therefore that only BCF BSF SWAPF and MOVWF instructions are used to alter the STATUS Register because these instructions do not affect the Z C or DC bits from the STATUS Register For other instructions not affecting any status bits see the Instruction Set Summary Note 1 Bits IRP and RP1 STATUS lt 7 6 gt are not used by the PIC12C67X and should be maintained clear Use of these bits as general purpose R W bits is NOT recom mended since this may affect upward compatibility with future products 2 The C and DC bits operate as a borrow and digit borrow bit respectively in sub traction See the SUBLW and SUBWF instructions for examples STATUS REGISTER ADDRESS 03h 83h Reserved Reserved R W 0 R 1 R 1 R W x R W x R W x IRP RP1 RPO TO PD Z DC C Readable bit bit7 bit 7 1 Bank 2 3 100h 1FFh 0 Bank 0 1 00h FFh bit 6 5 11 Bank 3 180h 1FFh 10 Bank 2 100h 17Fh 01 Bank 1 80h FFh 00 Bank 0 00h 7Fh bit 4 TO Time out bit 0 A WDT time out occurred bit 3 PD Power down bit 0 By execution of the SLEEP instruction Z Zero bit bit 2 bit 1 bit 0 Note the source register 1
142. nfiguration bits must also be programmed 2 3 Quick Turn Programming QTP Devices Microchip offers a QTP Programming Service for fac tory production orders This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi lized The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory Certain code and prototype verification procedures apply before produc tion shipments are available Please contact your local Microchip Technology sales office for more details 2 4 Serialized Quick Turn Programming_ SOTPSM Devices Microchip offers a unique programming service where a few user defined locations in each device are pro grammed with different serial numbers The serial num bers may be random pseudo random or sequential Serial programming allows each device to have a unique number which can serve as an entry code password or ID number 1999 Microchip Technology Inc DS30561B page 5 PIC12C67X NOTES EEE DS30561B page 6 1999 Microchip Technology Inc PIC12C67X 3 0 ARCHITECTURAL OVERVIEW The high performance of the PIC12C67X family can be attributed to a number of architectural features com monly found in RISC microprocessors To begin with the PIC12C67X uses a Harvard architecture in which program and data are accessed from separate memo ri
143. ng Description Words Cycles Example Clear Watchdog Timer label CLRWDT None 00h WDT 0 gt WDT prescaler 1 TO 1 PD TO PD 00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer It also resets the prescaler of the WDT Status bits TO and PD are set 1 1 CLRWDT Before Instruction WDT counter After Instruction WDT counter 0x00 WDT prescaler 0 TO 1 PD 1 Complement f label COMF fd 0 lt f lt 127 de 0 1 f dest Z 00 1001 dfff ffff The contents of register f are complemented If d is 0 the result is stored in W If d is 1 the result is stored back in register f 1 1 COMF REG1 0 Before Instruction REG1 0x13 After Instruction REG1 0x13 W OxEC DECF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example DECFSZ Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Decrement f label DECF fd O lt f lt 127 de 0 1 f 1 gt dest Z 00 0011 dfff ftf Decrement register f If d is 0 the result is stored in the W regis ter If d is 1 the result is stored back in register f 1 1 DECF CNT 1 Before Instruction 0x01 Z 0 After Instruction 0x00 Z Decrement f Skip if 0 label DECFSZ f d O lt f lt 127 de 0 1 f 1 dest
144. ng Plane L 130 140 150 3 30 3 56 3 81 Lead Thickness c 008 010 012 0 20 0 25 0 30 Upper Lead Width B1 050 055 060 1 27 1 40 1 52 Lower Lead Width B 016 018 020 0 41 0 46 0 51 Overall Row Spacing eB 296 310 324 7 52 7 87 8 23 Window Diameter W 161 166 171 4 09 4 22 4 34 Lid Length T 440 450 460 11 18 11 43 11 68 Lid Width U 260 270 280 6 60 6 86 7 11 Controlling Parameter JEDC Equivalent MS 015 Drawing No C04 083 DS30561B page 118 1999 Microchip Technology Inc PIC12C67X APPENDIX A COMPATIBILITY APPENDIX B CODE FOR To convert code written for PIC16C5X to PIC12C67X ACCESSING EEPROM the user should take the following steps DATA MEMORY 1 Remove any program memory page select Please refer to our web site at www microchip com for operations PA2 PA1 PAO bits for CALL GOTO code availability 2 Revisit any computed jump operations write to PC or add to PC etc to make sure page bits are set properly under the new scheme 3 Eliminate any data memory page switching Redefine data variables to reallocate them 4 Verify all writes to STATUS OPTION and FSR registers since these have changed 5 Change reset vector to 0000h E _ z lt amp E amp _ _ gt _ a sr 1999 Microchip Technology Inc DS30561B page 119 PIC12C67X NOTES Eech DS30561B page 120 1999 Micro
145. nology Inc DS30561B page 63 PIC12C67X 9 5 1 TMRO INTERRUPT An overflow FFh 00h in the TMRO register will set flag bit TOIF INTCON lt 2 gt The interrupt can be enabled disabled by setting clearing enable bit TOIE INTCON lt 5 gt Section 7 0 The flag bit TOIF INTCON lt 2 gt will be set regardless of the state of the enable bits If used this flag must be cleared in software 9 5 2 INT INTERRUPT External interrupt on GP2 INT pin is edge triggered either rising if bit INTEDG OPTION 6 is set or fall ing if the INTEDG bit is clear When a valid edge appears on the GP2 INT pin flag bit INTF INTCON lt 1 gt is set This interrupt can be disabled by clearing enable bit INTE INTCON lt 4 gt Flag bit INTF must be cleared in software in the interrupt service rou tine before re enabling this interrupt The INT interrupt can wake up the processor from SLEEP if bit INTE was set prior to going into SLEEP The status of global inter rupt enable bit GIE decides whether or not the proces sor branches to the interrupt vector following wake up See Section 9 8 for details on SLEEP mode 9 5 8 GPIO INTCON CHANGE An input change on GP3 GP1 or GPO sets flag bit GPIF INTCON lt 0 gt The interrupt can be enabled disabled by setting clearing enable bit GPIE INTCON lt 3 gt Section 5 1 This flag bit GPIF INTCON 0 will be set regardless of the state of the enable bits If used this flag must be cleared
146. nputs The analog reference VREF is the device VDD The A D interrupt is enabled and the A D conversion clock is FRC The conversion is performed on the GPO channel Note the same instruction that turns on the A D EXAMPLE 8 2 DOING AN A D CONVERSION BSF STATUS RPO Select Page 1 CLRF ADCON1 Configure A D inputs BSF PIEL ADIE Enable A D interrupts BCF STATUS RPO Select Page 0 MOVLW OxC1 RC Clock A D is on Channel 0 is selected MOVWF ADCONO H BCF PIRI ADIF Clear A D interrupt flag bit BSF INTCON PEIE Enable peripheral interrupts BSF INTCON GIE Enable all interrupts Ensure that the required sampling time for the selected input channel has elapsed Then the conversion may be started BSF ADCONO GO Start A D Conversion The ADIF bit will be set and the GO DONE bit is cleared upon completion of the A D Conversion Eech DS30561B page 50 1999 Microchip Technology Inc PIC12C67X 8 5 A D Operation During Sleep The A D module can operate during SLEEP mode This reguires that the A D clock source be set to RC ADCS lt 1 0 gt 11 When the RC clock source is selected the A D module waits one instruction cycle before starting the conversion This allows the SLEEP instruction to be executed which eliminates all digital switching noise from the conversion When the conver sion is completed the GO DONE bit will be cleared and the result loaded into the ADRES Registe
147. ns 31 ID Locations fa INCF Instruction ee ek ee ee a INGFSZ INStUGUG EE In Circuit Serial Programming INDF Register rre rne tes Indirect Addressing ee ee ee Initialization Conditions for All Registers gs Instruction Cycla oreet ee treten retra 10 Instruction Flow Pipelining a 10 Instruction Format 69 Instruction Set INCFSZ IORLW OPTION d RE tr INTCON Register INTEDG Dil roten 16 Internal Sampling Switch Rss Impedence 48 ue 4 08 A D 62 GP2 INT 62 GPIO Port DS30561B page 122 K KeeLoq Evaluation and Programming Tools 86 L Loading of PO ieget eoe cx Po deas 22 M MOLRE mE 56 59 Memory Data Memory eege kee ge eg danses Program Memory ees ee ee ee ek ee ee ee ee Register File Map PIC12CE67X d leke itr eerte ees MOVLW Instruction aa MOVWE Instruction esses MPLAB Integrated Development Environment Software 83 N NOP INStrUCTION RE EE su Ga OE ER das 78 Oo OPEOdE Sas er kaha isma ahus MPa RE IE 69 OPTION Instruction ee ee ua ee ee 78 OPTION Register ern nene eren nt 16 OMNOGOMA RE EE EE ERR 7 OSC selection 53 OSCCAL Register ss 21 Oscillator EXTRC
148. nts connected via hi impedance to an analog input pin capacitor zener diode etc should have very little leakage current at the pin 8 9 Transfer Function The ideal transfer function of the A D converter is as fol lows the first transition occurs when the analog input voltage VAIN is 1 LSb or Analog VREF 256 Figure 8 3 FIGURE 8 3 A D TRANSFER FUNCTION L FFh 2 amp FEh 2 1 o 1 o Weg ke 1 1 z caro sl KU N ean Ge 03h EET EET EET 02h a sn ORE a gt A s M 00h facte A rod 00 20 2 o ov OU 4 409 0 NO Nw zl cio d 2d Dr NOM os A NS gt Ke Analog input voltage 1999 Microchip Technology Inc DS30561B page 51 PIC12C67X FIGURE 8 4 FLOWCHART OF A D OPERATION ADON 0 y Conversion Delayed 1 Instruction Cycle Start of A D Finish Conversion GO 0 ADIF 1 ice Abort Conversion Finish Conversion Wake up Yes D ee n Kx ED 60 0 From Sleep Wait2TAD amp Y Y RN BEES PS Wait 2 TAD R Stay in Slee ADIF 1 Wait 2 TAD e TABLE 8 2 SUMMARY OF A D REGISTERS Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Power on all other Reset Resets OBh 8Bh INTC
149. on GPIO should be considered The MCLR pin if enabled must be at a logic high level VIHMC 9 8 1 WAKE UP FROM SLEEP The device can wake up from SLEEP through one of the following events 1 External reset input on MCLR pin 2 Watchdog Timer Wake up if WDT was enabled 3 GP2 INT interrupt interrupt GPIO port change or some Peripheral Interrupts External MCLR Reset will cause a device reset All other events are considered a continuation of program execution and cause a wake up The TO and PD bits in the STATUS register can be used to determine the cause of device reset The PD bit which is set on power up is cleared when SLEEP is invoked The TO bit is cleared if a WDT time out occurred and caused wake up The following peripheral interrupt can wake the device from SLEEP 1 A D conversion when A D clock source is RC Other peripherals can not generate interrupts since during SLEEP no on chip Q clocks are present When the SLEEP instruction is being executed the next instruction PC 1 is pre fetched For the device to wake up through an interrupt event the corresponding interrupt enable bit must be set enabled Wake up is regardless of the state of the GIE bit If the GIE bit is clear disabled the device continues execution at the instruction after the SLEEP instruction If the GIE bit is set enabled the device executes the instruction after the SLEEP instruction and then branche
150. one single instruc tion cycle unless a conditional test is true or the pro gram counter is changed as a result of an instruction In this case the execution takes two instruction cycles with the second cycle executed as a NOP One instruc tion cycle consists of four oscillator periods Thus for an oscillator frequency of 4 MHz the normal instruction execution time is 1 us If a conditional test is true or the program counter is changed as a result of an instruc tion the instruction execution time is 2 us Table 10 2 lists the instructions recognized by the MPASM assembler Figure 10 1 shows the three general formats that the instructions can have Note To maintain upward compatibility with future PIC12C67X products do not use the OPTION and TRIS instructions All examples use the following format to represent a hexadecimal number Oxhh where h signifies a hexadecimal digit FIGURE 10 1 GENERAL FORMAT FOR INSTRUCTIONS Byte oriented file register operations 13 8 7 6 0 OPCODE d f FILE d 0 for destination W d 1 for destination f f 7 bit file register address Bit oriented file register operations 13 109 7 6 0 OPCODE b BIT f FILE b 3 bit bit address f 7 bit file register address Literal and control operations General 13 8 7 0 OPCODE k literal k 8 bit immediate value CALL and GOTO instructions only 13 11 10 0 OPCODE k lite
151. or information on serial EEPROM communication Note On a Power on Reset GPO GP1 GP2 and GP4 are configured as analog inputs and read as 0 1999 Microchip Technology Inc DS30561B page 25 PIC12C67X FIGURE 5 1 BLOCK DIAGRAM OF GPO ANO AND GP1 AN1 VREF PIN Data Bus D Q von ZB Voo WR PORT 2 a i M gt P HP ZS VO Pin Data Latch i A id DY D a Y WR TRIS CON D TRIS Latch SZ Analog Input TTL Mode Input Buffer RD TRIS Q D T e EN RD PORT p GPO INT and GP1 INT To A D Converter Note 1 Wake up on pin change interrupts for GPO and GP1 DS30561B page 26 1999 Microchip Technology Inc PIC12C67X FIGURE 5 2 BLOCK DIAGRAM OF GP2 TOCKI AN2 INT PIN Data Bus T D Q Von Von WR PORT CK K 6 1 P ZN VO Pin Data Latch A EE 7 gt CHE a 8 Y T Vss Vss WR TRIS CON G s E TRIS Latch Analog Input 2 Schmitt Trigger d Mode Input Buffer RD TRIS Q D EN RD PORT gt TMR0 Clock Input GP2 INT To A D Converter A aa 1999 Microchip Technology Inc DS30561B page 27 PIC12C67X FIGURE 5 3 BLOCK DIAGRAM OF GP3 MCLR VPP PIN
152. ore a new transmis 4700 3 0V lt Vcc lt 4 5V sion can start 1300 4 5V lt Vcc lt 5 5V Output fall time from VIH TOF 20 0 1 250 ns Note 1 CB lt 100 pF minimum to VIL maximum CB Input filter spike suppression TSP 50 ns Notes 1 3 SDA and SCL pins Write cycle time TWC 4 ms Endurance 1M cycles 25 C Vcc 5 0V Block Mode Note 4 Note 1 Not 100 tested CB total capacitance of one bus line in pF 2 As a transmitter the device must provide an internal minimum delay time to bridge the undefined region min imum 300 ns of the falling edge of SCL and avoid unintended generation of START or STOP conditions 3 The combined TsP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression This eliminates the need for a TI specification for standard operation 4 This parameter is not tested but ensured by characterization For endurance estimates in a specific applica tion please consult the Total Endurance Model which can be obtained on Microchip s website 1999 Microchip Technology Inc DS30561B page 107 PIC12C67X NOTES EEE DS30561B page 108 1999 Microchip Technology Inc PIC12C67X 13 0 DC AND AC CHARACTERISTICS PIC12C671 PIC12C672 PIC12LC671 PIC12LC672 PIC12CE673 PIC12CE674 PIC12LCE673 PIC12LCE674 The graphs and tables provided in this section are for design guidance and are not tested In some graphs or tables the da
153. ower four address bits are used by the device and the upper four bits are don t cares If the address byte is acknowledged the processor will then transmit the data word to be written into the addressed memory location The memory acknowledges again and the processor generates a stop condition This initiates the internal write cycle and during this time will not generate acknowledge sig nals After a byte write command the internal address counter will not be incremented and will point to the same address location that was just written If a stop bit sequence is transmitted to the device at any point in the write command seduence before the entire seguence is complete then the command will abort and no data will be written If more than 8 data bits are transmitted before the stop bit sequence is sent then the device will clear the previously loaded byte and begin loading the data buffer again If more than one data byte is trans mitted to the device and a stop bit is sent before a full eight data bits have been transmitted then the write command will abort and no data will be written The EEPROM memory employs a Vcc threshold detector circuit which disables the internal erase write logic if the Vcc is below minimum VDD Byte write operations must be preceded and immediately followed by a bus not busy bus cycle where both SDA and SCL are held high See Figure 6 7 for Byte Write operation 6 4 Since the EEPROM will not acknowledge du
154. owledge the transfer but does generate a stop condition and the EEPROM discontinues transmission Figure 6 9 After this command the internal address counter will point to the address location following the one that was just read 6 5 3 SEQUENTIAL READ Seguential reads are initiated in the same way as a ran dom read except that after the device transmits the first data byte the processor issues an acknowledge as opposed to a stop condition in a random read This directs the EEPROM to transmit the next seguentially addressed 8 bit word Figure 6 10 To provide sequential reads the EEPROM contains an internal address pointer which is incremented by one at the completion of each read operation This address pointer allows the entire memory contents to be serially read during one operation FIGURE 6 8 CURRENT ADDRESS READ s T s A CONTROL T R BYTE ei Tig ENE P SDA LINE ACTIVITY S 1 1 0 X X X 1 E A N C DATA Oo K A e C X Don t Care Bit K FIGURE 6 9 RANDOM READ s s T s A CONTROL WORD A CONTROL T R BYTE ADDRESS n R BYTE 0 T T P S 1 0 1 0 xx xo IX Xxx S 1 0 10 X X 1 P SDA LI
155. prescaler to the Watchdog Timer by setting bit PSA OPTION lt 3 gt The OPTION Register is a readable and writable regis ter which contains various control bits to configure the TMRO WDT prescaler the External INT Interrupt TMRO and the weak pull ups on GPIO REGISTER 4 2 OPTION REGISTER ADDRESS 81h R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 GPPU INTEDG TOCS TOSE PSA PS2 PS1 PSO R Readable bit W Writable bit bit7 bitO i i U Unimplemented bit read as 0 n Value at POR reset bit 7 GPPU Weak Pull up Enable 1 Weak pull ups disabled 0 Weak pull ups enabled GPO GP1 GP3 bit 6 INTEDG Interrupt Edge 1 Interrupt on rising edge of GP2 TOCKI AN2 INT pin 0 Interrupt on falling edge of GP2 TOCKI AN2 INT pin bit5 TOCS TMRO Clock Source Select bit 1 Transition on GP2 TOCKI AN2 INT pin 0 Internal instruction cycle clock CLKOUT bit4 TOSE TMRO Source Edge Select bit 1 Increment on high to low transition on GP2 TOCKI AN2 INT pin 0 Increment on low to high transition on GP2 TOCKI AN2 INT pin bit 3 PSA Prescaler Assignment bit 1 Prescaler is assigned to the WDT 0 Prescaler is assigned to the Timer0 module bit 2 0 PS lt 2 0 gt Prescaler Rate Select bits Bit Value TMRO Rate WDT Rate 000 1 2 1 1 001 1 4 1 2 010 1 8 1 4 011 1 16 1 8 100 1 32 1 16 101 1 64 1 32 110 1 128 1 64 111 1 256 1 128 ae DS3056
156. pts When bit GIE is enabled and an interrupt s flag bit and mask bit are set the interrupt will vector immediately Individual interrupts can be dis abled through their corresponding enable bits in vari ous registers Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit The GIE bit is cleared on reset FIGURE 9 13 INTERRUPT LOGIC The return from interrupt instruction RETFIE exits the interrupt routine as well as sets the GIE bit which re enables interrupts The GP2 INT GPIO port change interrupt and the TMRO overflow interrupt flags are contained in the INTCON register The peripheral interrupt flag ADIF is contained in the Special Function Register PIR1 The corresponding interrupt enable bit is contained in Special Function Register PIE1 and the peripheral interrupt enable bit is contained in Special Function Register INTCON When an interrupt is responded to the GIE bit is cleared to disable any further interrupt the return address is pushed onto the stack and the PC is loaded with 0004h Once in the interrupt service routine the source s of the interrupt can be determined by polling the interrupt flag bits The interrupt flag bit s must be cleared in software before re enabling interrupts to avoid repeated interrupts For external interrupt events such as GPIO change interrupt the interrupt latency will be three or four instruction cycles
157. r If the A D interrupt is enabled the device will wake up from SLEEP If the A D interrupt is not enabled the A D mod ule will then be turned off although the ADON bit will remain set When the A D clock source is another clock option not RC a SLEEP instruction will cause the present conver sion to be aborted and the A D module to be turned off though the ADON bit will remain set Turning off the A D places the A D module in its lowest current consumption state Note For the A D module to operate in SLEEP the A D clock source must be set to RC ADCS lt 1 0 gt 11 To perform an A D conversion in SLEEP the GO DONE bit must be set followed by the SLEEP instruction 8 6 A D Accuracy Error The overall accuracy of the A D is less than 1 LSb for VDD 5V 10 and the analog VREF VDD This over all accuracy includes offset error full scale error and integral error The A D converter is monotonic over the full VDD range The resolution and accuracy may be less when either the analog reference VDD is less than 5 0V or when the analog reference VREF is less than VDD The maximum pin leakage current is specified in the Device Data Sheet electrical specification parameter D060 In systems where the device frequency is low use of the A D RC clock is preferred At moderate to high fre quencies TAD should be derived from the device oscil lator TAD must not violat
158. ral k 11 bit immediate value 1999 Microchip Technology Inc DS30561B page 69 PIC12C67X 10 1 Special Function Registers as Source Destination The PIC12C67X s orthogonal instruction set allows read and write of all file registers including special function registers There are some special situations the user should be aware of 10 1 1 STATUS AS DESTINATION If an instruction writes to STATUS the Z C and DC bits may be set or cleared as a result of the instruction and overwrite the original data bits written For example executing CLRF STATUS will clear register STATUS and then set the Z bit leaving 0000 0100b in the reg ister 10 1 2 TRIS AS DESTINATION Bit 3 of the TRIS register always reads as a 1 since GP3 is an input only pin This fact can affect some read modify write operations on the TRIS register 10 1 3 PCL AS SOURCE OR DESTINATION Read write or read modify write on PCL may have the following results Read PC Write PCL PCL dest PCLATH PCH 8 bit destination value gt PCL Read Modify Write PCL ALU operand PCLATH PCH 8 bit result PCL Where PCH program counter high byte not an addressable register PCLATH Program counter high holding latch dest destination WREG or f 10 1 4 BIT MANIPULATION All bit manipulation instructions are done by first read ing the entire register operating on the selected bit and writing the r
159. ring a write cycle this can be used to determine when the cycle is complete this feature can be used to maximize bus throughput Once the stop condition for a write com mand has been issued from the processor the device initiates the internally timed write cycle ACK polling can be initiated immediately This involves the proces sor sending a start condition followed by the control byte for a write command R W 0 If the device is still busy with the write cycle then no ACK will be returned If no ACK is returned then the start bit and control byte must be re sent If the cycle is complete then the device will return the ACK and the processor can then proceed with the next read or write command See Figure 6 6 for flow diagram Acknowledge Polling FIGURE 6 6 ACKNOWLEDGE POLLING FLOW Send Write Command i Send Stop Condition to Initiate Write Cycle i Send Start Y Send Control Byte with R W 0 Did EEPROM Acknowledge ACK 0 YES Next Operation FIGURE 6 7 BYTE WRITE S S T CONTROL WORD T BYTE ADDRESS DATA o 7 ES Eas A S SDA LINE P ROTEN sliloltlolxixixlo X X X X A A A C C C K K K X Don t Care Bit DS30561B page 36 1999 Microchip Technology Inc PIC12C67X 6 5 Read operations are
160. rrupts Watchdog Timer WDT SLEEP Code protection D locations In circuit serial programming The PIC12C67X has a Watchdog Timer which can be shut off only through configuration bits It runs off its own RC oscillator for added reliability There are two timers that offer necessary delays on power up One is the Oscillator Start up Timer OST intended to keep the chip in reset until the crystal oscillator is stable The other is the Power up Timer PWRT which provides a fixed delay of 72 ms nominal on power up only designed to keep the part in reset while the power sup ply stabilizes With these two timers on chip most applications need no external reset circuitry SLEEP mode is designed to offer a very low current power down mode The user can wake up from SLEEP through external reset Watchdog Timer Wake up or through an interrupt Several oscillator options are also made available to allow the part to fit the application The INTRC EXTRC oscillator option saves system cost while the LP crystal option saves power A set of configuration bits are used to select various options 9 1 The configuration bits can be programmed read as 0 or left unprogrammed read as 1 to select various device configurations These bits are mapped in pro gram memory location 2007h Configuration Bits The user will note that address 2007h is beyond the user program memory space In fact it belongs to the special test conf
161. ruction DS30561B page 66 1999 Microchip Technology Inc PIC12C67X FIGURE 9 16 WAKE UP FROM SLEEP THROUGH INTERRUPT at a2 aslaa ai aal asl 04 ol ol ol oalou ail aal 03104 ol aal as 04 ail aal aal Q4 osci UV AV A A V A SLY AN VV ODE CLKOUT 4 EE I A Tost 2 EE sr GPIO pin Y AT lt 0 gt i f Interrupt Latency i h 1 1 Note 3 1 Sieg i i i se l i i i j Processor in 1 1 f INTCON lt 7 gt i M SLEEP i j INSTRUCTION FLOW I I pc Y PC X PC X PC 2 X PCr2 A PC 2 OM O0004h A 00055 Instruetion J inst PC SLEEP Inst PC 1 Ins PC 2 Inst 0004h insiO005h ec Inst PC 1 SLEEP Inst PC 1 Dummy cycle Dummy cycle Inst 0004h Note 1 XT HS or LP oscillator mode assumed 2 Tosr 1024Tosc drawing not to scale This delay will not be there for INTRC and EXTRC osc mode 3 GIE 1 assumed In this case after wake up the processor jumps to the interrupt routine If GIE 0 execution will continue in line 4 CLKOUT is not available in XT HS or LP osc modes but shown here for timing reference 9 9 Program Verification Code Protection After reset and if the device is placed into program ming verify mode the program counter PC is at loca tion OOh A 6 bit command is then supplied to the device Depending on the command 14 bits of
162. s os ee Oe RO RAA tg CLKOUT Timer0 TOIF bit INTCON lt 2 gt L Interrupt Latency2 GIE bit INTCON lt 7 gt INSTRUCTION FLOW Inst PC Inst PC 1 Inst 0004h Inst 0005h Instruction fetched Inst PC 1 Inst PC Dummy cycle Dummy cycle Inst 0004h PC 4 PC X PC 1 X PC 1 X 0004h X 0005h executed Instruction i Note 1 interrupt flag bit TOIF is Sampled here every at 2 Interrupt latency 3TCY where TCY instruction cycle time 3 CLKOUT is available only in the INTRC and EXTRC oscillator modes DS30561B page 40 1999 Microchip Technology Inc PIC12C67X 7 2 Using Timer0 with an External Clock When an external clock input is used for Timer0 it must meet certain reguirements The reguirements ensure the external clock can be synchronized with the internal phase clock Tosc Also there is a delay in the actual incrementing of Timer0 after synchronization 7 2 1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used the external clock input is used as the clock source The synchronization of TOCKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks Figure 7 5 There fore it is necessary for TOCKI to be high for at least 2Tosc and a small RC delay of 20 ns and low for at least 2Tosc and a small RC delay of 20 ns Refer to the electrical sp
163. s to the inter rupt address 0004h In cases where the execution of the instruction following SLEEP is not desirable the user should have a NoP after the SLEEP instruction 9 8 2 WAKE UP USING INTERRUPTS When global interrupts are disabled GIE cleared and any interrupt source has both its interrupt enable bit and interrupt flag bit set one of the following will occur If the interrupt occurs before the the execution of a SLEEP instruction the SLEEP instruction will complete as a NOP Therefore the WDT and WDT postscaler will not be cleared the TO bit will not be set and PD bits will not be cleared f the interrupt occurs during or after the execu tion of a SLEEP instruction the device will imme diately wake up from sleep The SLEEP instruction will be completely executed before the wake up Therefore the WDT and WDT postscaler will be cleared the TO bit will be set and the PD bit will be cleared Even if the flag bits were checked before executing a SLEEP instruction it may be possible for flag bits to become set before the SLEEP instruction completes To determine whether a SLEEP instruction executed test the PD bit If the PD bit is set the SLEEP instruction was executed as a NOP To ensure that the WDT is cleared a CLRWDT instruc tion should be executed before a SLEEP inst
164. se permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 1999 Microchip Technology Inc DS30561B page 89 PIC12C67X FIGURE 12 1 PIC12C67X VOLTAGE FREQUENCY GRAPH 40 C lt TA lt 0 C 70 C TA lt 125 C 6 0 5 5 5 0 4 5 VDD Volts 4 0 3 5 0 4 10 20 25 Frequency MHz Note 1 The shaded region indicates the permissible combinations of voltage and frequency 2 The maximum rated speed of the part limits the permissible combinations of voltage and frequency Please reference the Product Identification System section for the maximum rated speed of the parts FIGURE 12 2 PIC12C67X VOLTAGE FREGUENCY GRAPH 0 C lt TA lt 70 C 6 0 5 5 5 0 VDD 4 5 Volts l 4 0 3 5 3 0 2 5 0 4 10 20 25 Frequency MHz Note 1 The shaded region indicates the permissible combinations of voltage and frequency 2 The maximum rated speed of the part limits the permissible combinations of voltage and frequency Please reference the Product Identification System section for the maximum rated speed of the parts DS30561B page 90 1999 Microchip Technology Inc PIC12C67X FIGURE 12 3 PIC12LC67X VO
165. sitive applications the RC device option offers additional cost savings The RC oscillator frequency is a function of the supply voltage the resistor REXT and capacitor CEXT values and the operating temperature In addition to this the oscillator frequency will vary from unit to unit due to normal process parameter variation Furthermore the difference in lead frame capacitance between package types will also affect the oscillation frequency especially for low CEXT values The user also needs to take into account variation due to tolerance of external R and C components used Figure 9 5 shows how the R C combination is connected to the PIC12C67X For REXT values below 2 2 KO the oscillator operation may become unstable or stop completely For very high REXT values i e 1 MQ the oscillator becomes sensitive to noise humidity and leakage Thus we recommend keeping REXT between 3 KO and 100 ko Although the oscillator will operate with no external capacitor CEXT 0 pF we recommend using values above 20 pF for noise and stability reasons With no or small external capacitance the oscillation frequency can vary dramatically due to changes in external capacitances such as PCB trace capacitance or package lead frame capacitance The variation is larger for larger R since leakage current variation will affect RC frequency more for large R and for smaller C since variation of input capacitance will affect RC frequency more
166. status flag Z is affected 1 1 MOVF FSR 0 After Instruction W value in FSR register Z 1 Move W to f label MOVWF f O lt f lt 127 W f None 00 0000 TEEL fff Move data from W register to reg ister f 1 1 MOVWE OPTION Before Instruction OPTION OxFF W Ox4F After Instruction OPTION Ox4F W 0x4F 1999 Microchip Technology Inc DS30561B page 77 PIC12C67X NOP No Operation Syntax label NOP Operands None Operation No operation Status Affected None Encoding 00 0000 OxxO 0000 Description No operation Words 1 Cycles 1 Example NOP OPTION Load Option Register Syntax label OPTION Operands None Operation W gt OPTION Status Affected None Encoding 00 0000 0110 0010 Description The contents of the W register are loaded in the OPTION register This instruction is supported for code compatibility with PIC16C5X products Since OPTION is a read able writable register the user can directly address it Words 1 Cycles 1 Example To maintain upward compatibility with future PIC12C67X products do not use this instruction RETFIE Syntax Operands Operation Status Affected Encoding Description Words Cycles Example RETLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Example TABLI II
167. ta presented are outside specified operating range i e outside specified VDD range This is for information only and devices will operate properly only within the specified range The data presented in this section is a statistical summary of data collected on units from different lots over a period of time Typical represents the mean of the distribution while max or min represents mean 3o and mean 36 respectively where o is standard deviation FIGURE 13 1 CALIBRATED INTERNAL RC FIGURE 13 2 CALIBRATED INTERNAL RC FREQUENCY RANGE VS FREQUENCY RANGE VS TEMPERATURE VDD 5 0V TEMPERATURE VDD 2 5V INTERNAL RC IS INTERNAL RC IS CALIBRATED TO 25 C 5 0V CALIBRATED TO 25 C 5 0V 4 50 4 50 4 40 4 40 4 30 4 30 mass Max 4 20 Vex 4 20 ta H 4 10 410 3 gt 4 00 400 pe o 7 3 90 2 3 90 3 80 3 80 3 70 Min 3 70 3 60 3 60 Min 3 50 3 50 40 0 25 85 125 40 o 25 85 125 Temperature Deg C Temperature Deg C 1999 Microchip Technology Inc DS30561B page 109 PIC12C67X TABLE 13 1 DYNAMIC IDD TYPICAL WDT ENABLED 25 C Oscillator Frequency VDD 2 5V VDD 5 5V External RC 4 MHz 400 HA 900
168. te the need for external reset circuitry There are five oscillator configurations to choose from including INTRC precision internal oscillator mode and the power saving LP Low Power oscillator mode Power saving SLEEP mode Watchdog Timer and code protection features improve system cost power and reliability The SLEEP power down feature provides a power saving mode The user can wake up the chip from SLEEP through several external and internal interrupts and resets A highly reliable Watchdog Timer with its own on chip RC oscillator provides protection against software lock up A UV erasable windowed package version is ideal for code development while the cost effective One Time Programmable OTP version is suitable for production in any volume The customer can take full advantage of Microchip s price leadership in OTP microcontrollers while benefiting from the OTP s flexibility 1 1 Applications The PIC12C67X series fits perfectly in applications ranging from personal care appliances and security Systems to low power remote transmitters receivers The EPROM technology makes customizing applica tion programs transmitter codes appliance settings receiver frequencies etc extremely fast and conve nient while the EEPROM data memory PIC12CE67X only technology allows for the changing of calibration factors and security codes The small footprint pack ages for through hole or surface mounting make this microcontroll
169. ted Encoding Description Words Cycles Example XORWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Example Exclusive OR Literal with W label XORLW k 0 lt k lt 255 W XOR k gt W 7 11 1010 kkkk kkkk The contents of the W register are XOR ed with the eight bit lit eral K The result is placed in the W register 1 1 XORLW OxAF Before Instruction W OxB5 After Instruction W OxlA Exclusive OR W with f label XORWF fd 0 lt f lt 127 de 0 1 W XOR f dest 7 00 0110 dfff EES Exclusive OR the contents of the W register with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f 1 1 XORWF REG 1 Before Instruction REG OxAF W OxB5 After Instruction REG 0x1A W OxB5 1999 Microchip Technology Inc DS30561B page 81 PIC12C67X NOTES Eech DS30561B page 82 1999 Microchip Technology Inc PIC12C67X 11 0 DEVELOPMENT SUPPORT The PICmicro microcontrollers are supported with a full range of hardware and software development tools Integrated Development Environment MPLAB IDE Software Assemblers Compilers Linkers MPASM Assembler MPLAB C17 and MPLAB C18 C Compilers MPLINK MPLIB Linker Librarian Simulators MPLAB SIM Software Simulator Emulators MPLAB I
170. time per bit is defined as TAD The A D conversion requires 9 5 TAD per 8 bit conversion The source of the A D conversion clock is software selected The four possible options for TAD are e 2TOSC e 8TOSC e 32Tosc Internal ADC RC oscillator For correct A D conversions the A D conversion clock TAD must be selected to ensure a minimum TAD time of 1 6 us If the minimum TAD time of 1 6 us can not be obtained TAD should be x8 us for preferred operation Table 8 1 shows the resultant TAD times derived from the device operating frequencies and the A D clock Source selected 8 3 Configuring Analog Port Pins The ADCON and TRIS Registers control the opera tion of the A D port pins The port pins that are desired as analog inputs must have their corresponding TRIS bits set input If the TRIS bit is cleared output the digital output level VoH or VOL will be converted The A D operation is independent of the state of the CHS lt 2 0 gt bits and the TRIS bits Note 1 When reading the port register all pins configured as analog input channel will read as cleared a low level Pins config ured as digital inputs will convert an ana log input Analog levels on a digitally configured input will not affect the conver sion accuracy 2 Analog levels on any pin that is defined as a digital input including the AN lt 3 0 gt pins may cause the input buffer to con sume current that is out of the devices specificatio
171. ts of GPIO to be read into the CPU Then the BSF operation takes place on bit5 and GPIO is written to the output latches If another bit of GPIO is used as a bi directional UO pin i e bit0 and it is defined as an input at this time the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin overwrit ing the previous content As long as the pin stays in the input mode no problem occurs However if bitO is switched to an output the content of the data latch may now be unknown Reading the port register reads the values of the port pins Writing to the port register writes the value to the port latch When using read modify write instructions i e BCF BSF etc on a port the value of the port pins is read the desired operation is done to this value and this value is then written to the port latch Example 5 1 shows the effect of two sequential read modify write instructions on an I O port EXAMPLE 5 1 READ MODIFY WRITE INSTRUCTIONS ON AN 1 0 PORT lnitial GPIO Settings GPIO lt 5 3 gt Inputs GPIO lt 2 0 gt Outputs GPIO latch GPIO pins ee Os EE TEE BCF GPIO 5 1 01 ppp 11 pppp BCF GPIO 4 10 ppp 11 pppp MOVLW 007h H TRIS GPIO 10 ppp 10 pppp Note that the user may have expected the pin values to be 00 pppp The 2nd BCF caused 7GP5 to be latched as the pin value High A pin actively outputting a Low or High shoul
172. ug source code by watching variables single stepping and setting break points Running at full speed enables testing hardware in real time The MPLAB ICD is also a programmer for the flash PIC16F87X family DS30561B page 84 1999 Microchip Technology Inc PIC12C67X 11 10 PRO MATE II Universal Programmer The PRO MATE II Universal Programmer is a full fea tured programmer capable of operating in stand alone mode as well as PC hosted mode PRO MATE Il is CE compliant The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability It has an LCD display for instructions and error messages keys to enter commands and a modular detachable socket assembly to support various package types In stand alone mode the PRO MATE II can read verify or program PICmicro devices It can also set code protect bits in this mode 11 11 PICSTART Plus Entry Level Development System The PICSTART programmer is an easy to use low cost prototype programmer It connects to the PC via one of the COM RS 232 ports MPLAB Integrated Development Environment software makes using the programmer simple and efficient PICSTART Plus supports all PICmicro devices with up to 40 pins Larger pin count devices such as the PIC16C92X and PIC17C76X may be supported with an adapter socket PICSTART Plus is CE compliant 11 12 SIMICE Entry Level Hardware Simulator
173. wed must be cleared in software 0 TMRO register did not overflow INTF INT External Interrupt Flag bit 1 The external interrupt on GP2 INT TOCKI AN2 pin occurred must be cleared in software 0 The external interrupt on GP2 INT TOCKVAN 2 pin did not occur GPIF GPIO Interrupt on Change Flag bit 1 GPO GP1 or GP3 pins changed state must be cleared in software 0 Neither GPO GP1 nor GP3 pins have changed state Writable bit Unimplemented bit read as 0 Value at POR reset bitO c M H IH 2 II 1999 Microchip Technology Inc DS30561B page 17 PIC12C67X 4 2 2 4 PIE1 REGISTER This register contains the individual enable bits for the Note Bit PEIE INTCON lt 6 gt must be set to Peripheral interrupts enable any peripheral interrupt REGISTER 4 4 PIE1 REGISTER ADDRESS 8Ch U 0 R W 0 U 0 U 0 U 0 U 0 U 0 U 0 ADIE R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 Unimplemented Read as 0 bit 6 ADIE A D Converter Interrupt Enable bit 1 Enables the A D interrupt 0 Disables the A D interrupt bit 5 0 Unimplemented Read as 0 zz ____ 7X lt _ _ _ _ gt _ lt _ E L__ r n DS30561B page 18 1999 Microchip Technology Inc PIC12C67X

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