FAIRCHILD HUF75617D3 HUF75617D3S handbook
Contents
1. Ves tp ov gt tav he FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15 UNCLAMPED ENERGY WAVEFORMS RL Voo agron Vas Vpp DUT Ig REF FIGURE 16 GATE CHARGE TEST CIRCUIT FIGURE 17 GATE CHARGE WAVEFORMS Vps RL Vas Ll DUT 90 Ves 50 PULSE WIDTH gt Vas 0 FIGURE 18 SWITCHING TIME TEST CIRCUIT FIGURE 19 SWITCHING TIME WAVEFORM 2001 Fairchild Semiconductor Corporation HUF75617D3 Rev HUF75617D3 PSPICE Electrical Model SSUBCKT HUF75617d3 2 1 3 CA 128 9 9 10 CB 15 14 1 0e 9 CIN 68 5 4e 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 117 8 EDS 14 8 5 81 EGS 13 8 6 81 ESG 6 1068 1 EVTHRES 6 21 198 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1 0e 9 LGATE 1 9 5 24e 9 LSOURCE 3 7 4 25e 9 GATE 10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3 9e 2 RGATE 9 202 45 rev 24May 2000 LDRAIN RLDRAIN DPLCAP 5 DRAIN o2 51 DBREAK RSLC2 ESLC 11 50 RDRAIN 1 ESI me TO EVTHRES DBODY LGATE EVTEMP 9 20 RLGATE LSOURCE 8 SOURCE 3 RSOURCE RLSOURCE RBREAK RLDRAIN 2 5 10 RLGATE 1 9 52 4 8 RLSOURCE 3 7 42 5 RSLC1 5 51 RSLCMOD 1 6 RSLC2 5 50 1e3 CA RSOURCE 8 7 RSOURCEMOD 3 2e 2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 17 18 RVTEMP2. TS H HUF75617D3 HUF75617D3S SEMICONDUCTOR Data Sheet December 2001 16A 100V 0 090 Ohm UltraFET amp Power MOSFETs ae Packaging 251 252 Features SOURCE Ultra Low On Resistance DRAIN DRAIN _ FLANGE TDS ON 0 0900 Vas 10V gt Simulation Models A GATE Temperature Compensated PSPICE and SABER DRAIN SOURCE j Electrical Models FLANGE Spice and SABER Thermal Impedance Models HUF75617D3 HUF75617D3S gt www fairchildsemi com Peak Current vs Pulse Width Curve UIS Rating Curve Symbol D Ordering Information PART NUMBER PACKAGE BRAND HUF75617D3 TO 251AA 75617D i HUF75617D3S TO 252AA 75617D S NOTE When ordering use the entire part number Add the suffix T to obtain the variant in tape and reel e g HUF75617D3ST Absolute Maximum Ratings 25 C Unless Otherwise Specified HUF75617D3 HUF75617D3S UNITS Drain to Source Voltage Note 1 Vpss 100 V Drain to Gate Voltage Ras 20kQ Note 1 VDGR 100 V Gate to Source Voltage scis ser RR eee et Rx RR E REOR Vas 20 V Drain Current Continuous 25 C Vas 10V Figure 2 Ip 16 A Continuous Tc 100 C Vas 10V Figure 2 Ip 11 A Pulsed Drain
3. OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss 250 Vas OV Figure 11 100 V Zero Gate Voltage Drain Current Ipss Vps 95V Ves OV 5 1 Vps 90V Vag OV 150 C 250 Gate to Source Leakage Current lass Vas 20V 100 ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH Vas Vps Ip 250pA Figure 10 2 4 V Drain to Source On Resistance 11 16A Vas 10V Figure 9 0 080 0 090 94 THERMAL SPECIFICATIONS Thermal Resistance Junction to Case 251 252 2 34 96 W Thermal Resistance Junction to RoJA 100 96 W Ambient SWITCHING SPECIFICATIONS Vcs 10V Turn On Time ton Vpp 50V Ip 16A 60 ns Turn On Delay Time ta ON Voc P 6 ns Rise Time tr Figures 18 19 35 ns Turn Off Delay Time td OFF 44 ns Fall Time tf 28 ns Turn Off Time 108 ns GATE CHARGE SPECIFICATIONS Total Gate Charge Qg ror Vas OV to 20V Vpp 50V 31 39 nC Gate Charge at 10V Qgi10 Vas OV to 10V ee 5 18 22 nC Threshold Gate Charge QgTH Vas OV to 2V Figures 13 16 17 1 3 1 6 nC Gate to Source Gate Charge Qgs 2 7 nC Gate to Drain Miller Charge 6 4 nC CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Vas OV 570 pF Output Capacitance Coss
4. CYCLE 0 5 MAX 25 Vpp 15V lt E 20 5 Q 15 z amp 10 Ty 175 C Tj 55 C___ a S 5 25 C 0 2 3 4 5 6 Vas GATE TO SOURCE VOLTAGE V FIGURE 7 TRANSFER CHARACTERISTICS 3 0 PULSE DURATION 80us DUTY CYCLE 0 5 25 o 52 20 za lt x ag Qc 1 5 NZ 5 10 lt Vas 10 Ip 16 0 5 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE RESISTANCE vs JUNCTION TEMPERATURE 100 If Rz 0 tav L Iqg 1 3 RATED BVpss Vpp lfR 0 tav L R In Ias R 1 3 RATED BVpss 1 lt E 2 tc tc 2 10 STARTING Ty 25 C 2 lt a STARTING Ty 150 C lt 1 0 001 0 01 0 1 1 10 tay TIME AVALANCHE ms NOTE Refer to Fairchild Application Notes AN9321 and AN9322 FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 30 Vos 10V 25 Vas 6V Vas 25V 77 Ip DRAIN CURRENT A a 10 5 PULSE DURATION 8006 DUTY CYCLE 0 5 25 0 1 0 1 2 3 4 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 8 SATURATION CHARACTERISTICS 1 2 Ves Vps Ip 250A E o NORMALIZED GATE THRESHOLD VOLTAGE
5. Current ass dme Ro RE Reb dd eR E IRAE Esa in Figure 4 Pulsed Avalanche Rating UIS Figures 6 14 15 POWER DISSIPAUOMN D em Pp 64 Der te Above 2500 aS Mar en 0 43 W C Operating and Storage Ty TsrG 55 to 175 C Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case for 106 TL 300 C Package Body for 10s See Techbrief 34 Tpkg 260 C NOTE Ty 25 C to 150 C CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Product reliability information can be found at http www fairchildsemi com products discrete reliability index html For severe environments see our Automotive HUFA series All Fairchild semiconductor products are manufactured assembled and tested under ISO9000 and QS9000 quality systems certification 2001 Fairchild Semiconductor Corporation HUF75617D3 Rev B HUF75617D3 Electrical Specifications T 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
6. Mee 2 125 pF Reverse Transfer Capacitance Crss 5 20 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 16A 1 25 V Isp 7A 1 00 V Reverse Recovery Time trr Isp 16A dlgp dt 100A us 80 ns Reverse Recovered Charge QRR Isp 16A dlsp dt 100A us 5 170 nC 2001 Fairchild Semiconductor Corporation HUF75617D3 Rev HUF75617D3 Typical Performance Curves 1 2 18 d 1 0 15 E lt 2 08 12 10 2 2 06 2 9 a z 2 4 o a 0 4 6 4 02 3 a 0 0 0 25 50 75 100 125 175 25 50 75 100 125 150 Tc CASE TEMPERATURE 9 FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE CASE TEMPERATURE C 175 FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE
7. TEMPERATURE 2 at r DUTY CYCLE DESCENDING ORDER 1 E02 0 1 0 05 2 0 02 a F 0 01 ul 5 DM 9 z 0 1 E a gt to NOT DUTY FACTOR D 1 2 SINGLE PULSE PEAK Ty X Zouc X Tc 0 01 LLLI 105 104 10 107 100 10 t RECTANGULAR PULSE DURATION s FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 300 T TTTTLITT 250 TIIT 200 FOR TEMPERATURES a 4 ABOVE 259 DERATE PEAK 4 CURRENT AS FOLLOWS g 100 tc DES l l25 175 5 Y 150 o x ui Vas 10V a 2 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 1 1 1 LLLLLIL 105 1074 10 10 10 t PULSE WIDTH s FIGURE 4 PEAK CURRENT CAPABILITY 10 2001 Fairchild Semiconductor Corporation HUF75617D3 Rev HUF75617D3 Typical Performance Curves continued 200 100 10 Ip DRAIN CURRENT A 0 1 SINGLE PULSE MAX RATED XC 25 RJ 100us 1ms OPERATION IN THIS AREA MAY 10ms LIMITED BY DS ON 1 10 Vps DRAIN TO SOURCE VOLTAGE V 100 200 FIGURE 5 FORWARD BIAS SAFE OPERATING AREA 30 PULSE DURATION 80us DUTY
8. 19 S1A 6 12 13 8 S1TAMOD S1B 13 12 13 8 S1BMOD 52 6 15 14 13 S2AMOD S2B 13 15 14 18 S2BMOD RVTHRES VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PNR V 5 51 16 6 32 3 5 MODEL DBODYMOD D IS 6 0e 13 RS 11 0 3 XTI 4 5 TRS1 1 1e 3 TRS2 7 1e 6 6 5e 10 TT 4 1e 8 M 0 54 MODEL DBREAKMOD D RS 5 6e 1TRS1 8 0e 4 52 3 0e 6 MODEL DPLCAPMOD D 7 0e 1 015 1e 3 0 89 10 MODEL MMEDMOD NMOS VTO 3 10 KP 3 IS 1e 30 N 10 TOX 1L 1 W 1 RG 245 MODEL MSTROMOD NMOS 3 64 KP 42 IS 1 30 N 10 TOX 1L 1u W 1u MODEL MWEAKMOD NMOS VTO 2 68 KP 0 02 IS 1e 30 N 10 TOX 1L 1u W 1 RG 24 5 MODEL RBREAKMOD RES TC1 1 05e 3TC2 5 0e 7 MODEL RDRAINMOD RES 1 1 20e 2 TC2 3 00e 5 MODEL RSLCMOD RES TC1 3 2e 3 TC2 1 0e 6 MODEL RSOURCEMOD RES TC1 1e 3 TC2 1e 6 MODEL RVTHRESMOD RES TC1 2 2e 3 TC2 9 0e 6 MODEL RVTEMPMOD RES TC1 2 4e 3TC2 1 8e 6 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH MODEL S2AMOD VSWITCH MODEL S2BMOD VSWITCH RON 1e 5 ROFF 2 0 1 VON 5 9 VOFF 3 1 RON 1e 5 ROFF 2 0 1 VON 3 1 VOFF 5 9 RON 1e 5 ROFF 2 0 1 VON 0 6 VOFF 0 5 RON 1e 5 ROFF 2 0 1 VON 0 5 VOFF 0 6 ENDS NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronic
9. C PowerTrench EcoSPARK ISOPLANAR QFET E CMOS LittleFET QS EnSigna MicroFET QT Optoelectronics FACT MicroPak Quiet Series FACT Quiet Series MICROWIRE SILENT SWITCHER 9 STAR POWER is used under license DISCLAIMER SMART START STAR POWER Stealth SuperSOT 3 SuperSOT 6 SuperSOT 8 SyncFET TinyLogic TruTranslation UHC UltraFET 9 VCX FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant into the body or b support or sustain life or c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or sys
10. ductor Corporation HUF75617D3 Rev B HUF75617D3 SPICE Thermal Model REV 24 May 2000 th JUNCTION HUF75617D CTHERM th 6 1 00e 3 2 6 5 4 00e 3 CTHERMS 5 4 4 00e 3 CTHERMA 4 3 3 60e 3 CTHERM5 3 2 7 00e 3 CTHERM6 2 tl 5 00e 2 CTHERM1 RTHERM1 th 6 1 59e 2 2 6 5 3 96e 2 RTHERMS 5 4 1 12 1 RTHERM4 4 3 4 27 1 RTHERM2 RTHERMS 3 2 6 45e 1 RTHERM6 2 tl 7 00e 1 2 SABER Thermal Model SABER thermal model HUF75617D RTHERM3 template thermal_model th tl thermal_c th tl ctherm ctherm1 th 6 1 00e 3 ctherm ctherm2 6 5 4 00e 3 ctherm ctherm3 5 4 4 00e 3 RTHERM4 ctherm ctherm4 4 3 3 60e 3 ctherm ctherm5 2 7 00e 3 ctherm ctherm6 2 tl 5 00 2 CTHERM4 rtherm rtherm1 th 6 1 59e 2 rtherm rtherm2 6 5 3 96e 2 rtherm rtherm3 5 4 1 12e 1 5 rtherm rtherm4 4 3 4 27e 1 rtherm rtherm5 3 2 6 45e 1 rtherm rtherm6 2 tl 7 00e 1 5 RTHERM6 CTHERM6 2001 Fairchild Semiconductor Corporation HUF75617D3 Rev TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks ACEx FAST OPTOLOGIC Bottomless FASTr OPTOPLANAR CoolFET FRFET PACMAN CROSSVOLT GlobalOptoisolator POP DenseTrench GTO Power247 DOME HiSe
11. in n2 n5 1 0 9 10 DE I4 MMED EBREAK ligate n1 n9 5 24 9 20 MSTRO l lsource n3 n7 4 25 9 RLGATE 5 e CIN i LSOURCE SOURCE m mmed n16 n6 n8 n8 model mmedmod I21u w 1u 8 7 o3 m mstrong n16 n6 n8 n8 model mstrongmod I 1u w 1u RSOURCE m mweak n16 n21 n8 n8 model mweakmod I 1u w 1u RLSOURCE res rbreak n17 n18 1 1 1 1 05e 3 tc2 5 0 7 PA So us RBREAK res rdrain n50 n16 3 9e 2 1 20e 2 tc2 3 00e 5 13 13 17 18 9 20 2 45 res rldrain n2 n5 10 S1B o o S2B RVTEMP res rlgate n1 n9 52 4 13 CB 19 res rlsource n3 n7 42 5 CA 14 4 T n5 n51 1e 6 3 2e 3 tc2 1 0 6 2 res rslc2 n5 n50 163 EGS 8 5 res rsource n8 n7 3 2e 2 1e 3 tc2 1e 6 S res rvtemp n18 n19 1 tcl 2 4e 3 tc2 1 8e 6 8 22 res rvthres n22 n8 1 tcl 2 2e 3 tc2 9 0e 6 RVTHRES spe ebreak n11 n7 n17 n18 2 117 8 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n10 n8 1 n20 n6 n18 n22 1 spe evthres n6 n21 n19 n8 1 Sw vcsp s a n6 n12 n13 n8 model s1amod sw vcsp sib n13 n12 n13 n8 model s1bmod vcsp s2a n6 n15 n14 n13 model s2amod Sw vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 166 32 3 5 2001 Fairchild Semicon
12. o 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2001 Fairchild Semiconductor Corporation HUF75617D3 Rev HUF75617D3 Typical Performance Curves continued 1 2 2000 Ip 250uA 1600 Vas OV f 1 2 Ciss Cas 1 1 Coss 100 1 0 Crss NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 0 9 10 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C 0 1 1 0 10 100 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE VOLTAGE vs JUNCTION TEMPERATURE 10 Vpp 50V WAVEFORMS IN XA DESCENDING ORDER Ip 16A Ip 10 4 1 Vas GATE TO SOURCE VOLTAGE V 0 5 10 15 20 Qg GATE CHARGE nC NOTE Refer to Fairchild Application Notes AN7254 and 7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 2001 Fairchild Semiconductor Corporation HUF75617D3 Rev B HUF75617D3 Test Circuits and Waveforms Vps BVpss VARY tp TO OBTAIN REQUIRED PEAK las
13. s Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 2001 Fairchild Semiconductor Corporation HUF75617D3 Rev B HUF75617D3 SABER Electrical Model REV 24 May 2000 template huf75617d3 n2 n1 n3 electrical n2 n1 n3 var i iscl dp model dbodymod isl 6 0e 13 rs 11 0 3 xti 4 5 trs1 1 1e 3 trs2 7 1 6 cjo 6 5e 10 tt 4 1 8 m 0 54 dp model dbreakmod rs 5 6e 1 trs1 8 0e 4 trs2 3 0e 6 dp model dplcapmod cjo 7 0e 10 isl 10 30 0 89 10 m model mmedmod type _n vto 3 10 kp 3 is 1e 30 tox 1 m model mstrongmod type _n vto 3 64 kp 42 is 1e 30 tox 1 1 m model mweakmod type n vto 2 68 kp 0 02 is 1e 30 tox 1 LDRAIN Sw vcsp model 1 1 5 roff 0 1 von 5 9 voff 3 1 DPLCAP 5 DRAIN sw vcsp model s1bmod ron 1 5 0 1 von 3 1 voff 5 9 2 Sw vcsp model s2amod 1 5 roff 0 1 von 0 6 voff 0 5 10 Sw vcsp model s2bmod 1 5 0 1 von 0 5 voff 0 6 RSLC1 RLDRAIN 51 c ca n12 n8 9 9e 10 RSLC2 c cb n15 n14 1 0e 9 c cin n6 n8 5 4e 10 eet 50 DBREAK dp dbody n7 n5 model dbodymod dp dbreak n5 n11 model dbreakmod ESG 8 RDRAIN 11 dp dplcap n10 n5 model dplcapmod EVTHRES iit n8 n17 2 1 14 LGATE EVTEMP RGATE ls DBODY l ldra
14. tem or to affect its safety or effectiveness reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms Advance Information Formative or In Design This datasheet contains the design specifications for product development Specifications may change in any manner without notice Preliminary First Production This datasheet contains preliminary data and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design No Identification Needed Full Production This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only
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