intersil HUF75545P3 HUF75545S3S handbook
Contents
1. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss 250 Vas OV Figure 11 80 V Zero Gate Voltage Drain Current Ipss Vps 75V Vas 0V 1 uA Vps 70V Vas OV 150 C 250 pA Gate to Source Leakage Current lass Vas 20V F 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH Vas Vps 250pA Figure 10 2 4 Drain to Source On Resistance TDS ON 75A Vas 10V Figure 9 0 0082 0 010 THERMAL SPECIFICATIONS Thermal Resistance Junction to Case ReJc TO 220 and TO 263 0 55 9C W Thermal Resistance Junction to RaJA 62 Ambient SWITCHING SPECIFICATIONS Vcs 10V Turn On Time Vpp 40V lp 75 210 ns Vas 10V Turn On Delay Time Ras 2 50 14 ns Rise Time t Eigures 19 19 125 ns Turn Off Delay Time td OFF 40 ns Fall Time tf 90 ns Turn Off Time torr 195 ns GATE CHARGE SPECIFICATIONS Total Gate Charge Qg rOT Vas 0V to 20V Vpp 40V 195 235 nC Gate Charge at 10V Qg 10 Vas 0V to 10V 1 0mA 105 125 nC Threshold Gate Charge Vas 0V to 2V Figures 13 16 1 68 82 nC Gate to Source Gate Charge Qgs 15 nC Reverse Transfer Capacitance 43 nC CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Vas 3750 Output Capacitance Co2. HUF75545P3 HUF75545S3S CA 1999 File Number 4738 1 75A 80V 0 010 Ohm N Channel UltraFET Power MOSFET Packaging Features i EARE TAERAA Ultra Low On Resistance SOURCE DRAIN TDS ON 0 0100 Vas 10V FLANGE Simulation Models Temperature Compensated and SABER Electrical Models GATE Spice and SABER Thermal Impedance Models SOURCE www semi Intersil com FLANGE Peak Current vs Pulse Width Curve HUF75545P3 HUF75545S3S UIS Rating Curve Ordering Information Symbol g D PART NUMBER PACKAGE BRAND HUF75545P3 TO 220AB 75545P HUF75545S3S TO 263AB 755455 NOTE When ordering use the entire part number Add the suffix T to obtain the TO 263AB variant in tape and reel e g HUF75545S3ST Absolute Maximum Ratings 25 Unless Otherwise Specified HUF75545P3 HUF75545S3S UNITS Drain to Source Voltage Note 1 Vpss 80 V Drain to Gate Voltage Ras 20 Note 1 VpGR 80 V Gate to So rce Voltage sss gt lt Ree i ara RH S a UR tuns Vas 20 V Drain Current Continuous 25 Vas 10V Figure 2 Ip 75 A Continuous 100 C Vas 10V Figure 2 Ip 73 A Pulsed Drain Gurrent iisssisek ee a e ues e koe rk eder ean pes Figure 4 Pulsed Aval
3. 175 150 Ibm PEAK CURRENT 100 TRANSCONDUCTANCE C MAY LIMIT CURRENT IN THIS REGION L pa 1075 104 t PULSE WIDTH s FIGURE 4 PEAK CURRENT CAPABILITY 3 intersil HUF75545P3 HUF75545S3S Typical Performance Curves Continued 600 600 I L las 1 3 RATED BVpss Vpp 5 d 100 ul 5 100 2 o gt OPERATION IN THIS 2 lt 10 L AREA MAY BE 5 LIMITED BY TDS ON E sina S lt INGLE PULSE RATED 5 1 10 1 10 100 200 0 001 0 01 0 1 1 10 Vps DRAIN TO SOURCE VOLTAGE V tay TIME IN AVALANCHE ms NOTE Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 5 FORWARD BIAS SAFE OPERATING AREA FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 150 i 150 PULSE DURATION 80us LZ T ves 7 DUTY 0 5 Vas 6V lt 120 L DDF 120 E E 5 5 90 90 2 2 o o z z 60 lt 60 rtc rc a a S E 30 30 PULSE DURATION 80us DUTY CYCLE 0 5 MAX Tc 25 0 0 2 3 4 5 6 0 1 2 3 4 Vas TO SOURCE VOLTAGE V Vps DRAIN TO SOURCE VOLTAGE V FIGURE 7 TRANSFER CHARACTE
4. S1B 13 12 13 8 S1BMOD 52 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 LGATE RLGATE CA DPLCAP 5 10 RSLC1 51 RSLC2 ESLC 50 RDRAIN so EVTHRES 14 EVTEMP Mie d _ 9 20 MSTRO IN E 8 S1A 9 9 52 12 13 14 15 8 13 S1B o o S2B 13 CB 14 s es 1 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 320 3 MMED DBREAK 11 MWEAK RSOURCE RBREAK 17 RVTHRES MODEL DBODYMOD D IS 3 6e 12 RS 2 1e 3 TRS1 1 5e 3 TRS2 5 1e 6 CJO 4 6e 9 TT 3 3e 8 M 0 55 MODEL DBREAKMOD D RS 2 3e 1 TRS1 0 TRS2 1 8 5 MODEL DPLCAPMOD D 4 8 9 IS 1 30 N 10 VJ 1M 0 8 MODEL MMEDMOD NMOS VTO 3 04 KP 2618 1e 30N 10 1L 21 MODEL MSTROMOD NMOS 3 5 KP 105 IS 1e 30 N 10 1L MODEL MWEAKMOD NMOS VTO 2 65 KP 0 12 IS 1 30 N 10 TOX 1 MODEL RBREAKMOD RES TC1 1 3e 3 TC2 1 6 MODEL RDRAINMOD RES TC1 9e 3 TC2 2 8e 5 MODEL RSLCMOD RES TC1 1 53e 3 TC2 2e 5 MODEL RSOURCEMOD RES TC1 1e 3 TC2 1 6 MODEL RVTHRESMOD RES TC1 2 3e 3 TC2 1 2e 5 MODEL RVTEMPMOD RES TC1 2 9e 3 TC2 5e 7 1 W 1 MODEL S1AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 5 VOFF 3 MODEL S1BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 3 VOFF 5 MODEL S2AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 1 5 VOFF 0 5 M
5. n8 model s1amod sw vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 16e6 320 3 8 intersil HUF75545P3 HUF75545S3S SPICE Thermal Model REV 21 May 1999 th JUNCTION HUF75545T th 6 6 4e 3 CTHERM 6 5 3 0e 2 CTHERM3 5 4 1 4e 2 RTHERM1 CTHERM1 CTHERMA 4 3 1 6e 2 CTHERMB 3 2 5 5e 2 6 2 tl 1 5 RTHERM th 6 3 2e 3 RTHERM 6 5 8 1e 3 RTHERM2 CTHERM2 5 4 2 3e 2 RTHERMA 4 3 1 3e 1 5 2 1 8e 1 6 2 tl 3 8e 2 5 Thermal Model RTHERM3 SABER thermal model HUF75545T template thermal model th tl thermal c th tl ctherm ctherm1 th 6 6 4e 3 ctherm ctherm2 6 5 3 0e 2 4 4 ctherm ctherm3 5 4 1 4 2 ctherm ctherm4 4 3 1 6e 2 ctherm ctherm5 3 2 5 5e 2 ctherm ctherm6 2 tl 1 5 rtherm rtherm1 th 6 3 2e 3 rtherm rtherm2 6 5 8 1e 3 5 5 rtherm rtherm3 5 4 2 3e 2 rtherm rtherm4 4 3 1 3e 1 rtherm rthermb 2 1 8e 1 rtherm rtherm6 2 t 3 8e 2 6 CTHERM6 All Intersil semiconductor products are manufactured assembled and tested under 1509000 quality systems certification Intersil semiconductor products are sold by description only Inter
6. 0 DBREAK d dbody n7 n71 model dbodymod RDRAIN 7 d dbreak n72 n11 modelzdbreakmod ESG 11 d dplcap n10 n5 model dplcapmod EVTHRES 21 76 i it nB n17 1 LGATE EVTEMP a MWEAK RGATE 6 10 l ldrain n2 n5 1e 9 9 20 l gate n1 n9 5 1e 9 RLGATE K MSTRO 7 11 n3 n7 4 4e 9 LSOURCE 8 SOURCE m mmed n16 n8 n8 model mmedmod I 1u w 1u E o 3 m mstrong n16 n6 n8 n8 model2mstrongmod 1 w 1u RSOURCE m mweak n16 n21 n8 n8 model mweakmod 1 w 1u RLSOURCE S1A 9 992A res rbreak n17 n18 1 tc1 1 3e 3 tc2 1 6 129 144 34 15 RBREAK res rdbody n71 n5 2 1 3 tc1 1 5 3 tc2 5 1e 6 8 13 17 18 res rdbreak n72 n5 2 3 1 tc1 0 tc2 1 8e 5 res rdrain n50 n16 4 8e 3 c1 9e 3 1 2 2 8e 5 S1B 81 5 res rgate n9 n20 0 87 CA B 19 res rldrain n2 n5 10 m 14 IT 4 res rlgate n1 n9 51 res rlsource n3 n7 44 EGS EDS res rslc1 n5 n51 1e 6 1 53e 3 tc2 2e 5 8 51 2 n5 n50 1e3 22 res rsource n8 n7 1 6 3 tc1 1e 3 tc2 1e 6 RVTHRES res rvtemp n18 n19 1 tc1 2 9e 3 tc2 5e 7 res rvthres n22 n8 1 tc1 2 3 3 tc2 1 2e 5 n11 n7 n17 n18 87 4 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 Spe evtemp n20 n6 n18 n22 1 Spe evthres n6 n21 n19 n8 1 Sw vcsp s1la n6 n12 n13
7. ODEL S2BMOD VSWITCH RON 1e 5 ROFF 2 0 1 VON 2 0 5 VOFF 1 5 ENDS W 1 0 87 L 1uW tuRG 87 LDRAIN RLDRAIN DBODY LSOURCE RLSOURCE 18 RVTEMP 19 22 DRAIN SOURCE 3 NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 7 intersil HUF75545P3 HUF75545S3S SABER Electrical Model REV 21 may 1999 template huf75545 n2 n1 n3 electrical n2 n1 n3 var i iscl d model dbodymod is 3 6e 12 cjo 4 6e 9 tt 3 3e 8 m 0 55 d model dbreakmod d model dplcapmod cjo 4 8e 9 is 1e 30 vj21 0 m 0 8 m model mmedmod type n vto 3 04 kp 6 is 1e 30 tox 1 m model mstrongmod type n vto 3 5 kp 105 is 1e 30 tox 1 m model mweakmod type n vto 2 65 kp 0 12 is 1e 30 tox 1 LDRAIN sw vcsp model s1amod ron 16 5 0 1 von 5 voff 3 DPLCAP 5 DRAIN Sw vcsp model s1bmod ron 1 5 roff 0 1 von 3 voff 5 10 SE o 2 Sw vcsp model s2amod ron 1e 5 roff 0 1 von 1 5 voff 0 5 RLDRAIN 1e 0 0 1 RSLC1 Sw vcsp model s2bmod ron 1e 5 roff 0 1 von 0 5 voff 1 5 17 RDBREAK c ca n12 n8 5 4e 9 RSLC2 c cb n15 n14 5 3e 9 is RDBODY c cin n6 n8 3 4e 9 5
8. RISTICS FIGURE 8 SATURATION CHARACTERISTICS 2 5 1 2 Ves Vps lp 2504A PULSE DURATION 8005 Ves 10V 75A DUTY CYCLE 0 5 MAX NORMALIZED GATE THRESHOLD VOLTAGE o NORMALIZED DRAIN TO SOURCE ON RESISTANCE 9 o 0 4 80 40 0 40 80 120 160 200 80 40 0 40 80 120 160 200 TJ JUNCTION TEMPERATURE C Tj JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs RESISTANCE vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 4 intersil HUF75545P3 HUF75545S3S Typical Performance Curves Continued 10000 w Ip 2504A Ciss Ces 53 5 5 Coss Cps Cap z9 lt E 1000 82 5 lt gm Cnss Cap 2 Vas OV f 1MHz 100 SEPA 80 40 0 40 80 120 160 200 0 1 1 10 80 TJ JUNCTION TEMPERATURE C DRAIN TO SOURCE VOLTAGE V FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE VOLTAGE vs JUNCTION TEMPERATURE 10 8 9 6 tc 2 4 WAVEFORMS IN 2 2 DESCENDING ORDER 9 lp 75 lp 35A gt 0 0 30 60 90 120 Qg GATE CHARGE nC NOTE Refer to Intersil Application Notes 7254 7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURREN
9. T Test Circuits and Waveforms Vps BVpss Vps VARY tp TO OBTAIN las Pri REQUIRED PEAK lAs VoD d Vas i ov gems tAV FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15 UNCLAMPED ENERGY WAVEFORMS 5 intersil HUF75545P3 HUF75545S3S Test Circuits and Waveforms Continued lg REF FIGURE 16 GATE CHARGE TEST CIRCUIT DUT FIGURE 18 SWITCHING TIME TEST CIRCUIT Vas 20V agn gt lg REF 0 FIGURE 17 GATE CHARGE WAVEFORMS 50 lt PULSE WIDTH FIGURE 19 SWITCHING TIME WAVEFORM 6 intersil HUF75545P3 HUF75545S3S PSPICE Electrical Model SUBCKT HUF75545213 rev 21 May 1999 CA 12 8 5 4e 9 CB 15 14 5 3e 9 CIN 6 8 3 4e 9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 1887 4 EDS 14 8 5 81 EGS 138681 ESG 610681 EVTHRES 6 21 198 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1 0e 9 LGATE 1 9 5 1e 9 GATE LSOURCE 3 7 4 4e 9 10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 4 80e 3 RGATE 9 200 87 RLDRAIN 2 5 10 RLGATE 1 9 51 RLSOURCE 3 7 44 RSLC1 5 51 RSLCMOD 1 6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1 6e 3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 STAMOD
10. anche Rating UIS Figures 6 14 15 Power DISSIDatlOl uei eoa ose cesare rere PR S UN RR RO RU nunc cac Pp 270 Derate ADoVe 259 C acest 1 8 W C Operating and Storage Tj TsrG 55 to 175 Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case for 106 TL 300 Package Body for 10s See Techbrief 34 Tpkg 260 oc NOTES 1 TJ 25 to 150 C CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied 1 CAUTION These devices are sensitive to electrostatic discharge Follow proper ESD Handling Procedures UltraFET is a trademark of Intersil Corporation PSPICE is a registered trademark of MicroSim Corporation SABER is a Copyright of Analogy Inc http www intersil com or 407 727 9207 Copyright Intersil Corporation 1999 HUF75545P3 HUF75545S3S Electrical Specifications 25 Unless Otherwise Specified
11. sil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site http www intersil com 9 intersil
12. ss 1 2 1100 Reverse Transfer Capacitance Cnss 350 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 75A 1 25 V Isp 35A 1 00 V Reverse Recovery Time trr Isp 75 dlsp dt 100A us 100 ns Reverse Recovered Charge QRR Isp 75A dlsp dt 100A us 300 nC 2 intersil HUF75545P3 HUF75545S3S Typical Performance Curves 1 2 1 0 POWER DISSIPATION MULTIPLIER o 0 25 50 75 100 125 150 175 CASE TEMPERATURE FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE Ip DRAIN CURRENT A 80 60 Vas 10V 40 20 0 25 50 75 100 125 150 175 CASE TEMPERATURE C FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE 2 DUTY CYCLE DESCENDING ORDER 0 5 1502 0 1 0 05 4 0 02 z B 0 01 4 gt 5 2 2 5 0 1 J 1 n eu 1 cod to SINGLE PULSE NOTES 1 DUTY FACTOR D t4 t2 1 0 01 PEAK Tj Ppy X Zojc X Rgjc Tc 1075 104 103 10 1071 100 10 t RECTANGULAR PULSE DURATION s FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 2000 1000 FOR TEMPERATURES ABOVE 259C DERATE PEAK CURRENT AS FOLLOWS 1
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