FAIRCHILD HUF75531SK8 handbook
Contents
1. E TL ee ee _ maim HM pf ene HE Mix cd WIL PEAK Ty Pou Zoya x Roua Ta 105 10 4 10 10 107 100 10 102 103 t RECTANGULAR PULSE DURATION s FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 500 ma ee E E E E AE E esp WRIST er cea 25 C HELL Bu FOR TEMPERATURES 509C W um eL LL Ll ABOVE 259 DERATE PEAK 100 NH CURRENT AS FOLLOWS 10 TRANSCONDUCTANCE nmm ao MAY LIMIT CURRENT IN THIS REGION EHE HERE EE BE ERE EE 10 104 103 1072 1071 100 10 102 103 t PULSE WIDTH s Ibm PEAK CURRENT FIGURE 4 PEAK CURRENT CAPABILITY 2001 Fairchild Semiconductor Corporation HUF75531SK8 Rev B 755315 8 Typical Performance Curves Continued 200 200 P 0 100 lt 100 tav L lAs 1 3 RATED BVpss Vpp 0 a z R tav L R In Ias R 1 3 RATED BVpss VDD 110 10 HS d 5 S gt OPERATION IN THIS J 2 10 STARTING T 250C as lt 4 T 1 2 J ail TT TTT 2 SN F SINGLE PULSE lt ib 1 LLL Rcx 0 1 i 1 NON 0 01 0 1 1 10 100 Vps DRAIN SOURCE VOLTAGE V tA TIME AVALANCHE NOTE Refer to Fairchild Application Notes 9321 and AN9322 FIGURE 5 FORWARD BIAS SAFE2. 4 a lg REF 0 FIGURE 17 GATE CHARGE WAVEFORMS ton s gt torr ta OFF 10 90 Ves 50 50 PULSE WIDTH FIGURE 19 SWITCHING TIME WAVEFORM dissipation ratings Precise determination of Ppp is complex and influenced by many factors 1 Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board The number of copper layers and the thickness of the board The use of external heat sinks The use of thermal vias Air flow and board orientation For non steady state applications the pulse width the duty cycle and the transient thermal response of the part the board and the environment they are in of CO P Fairchild provides thermal information to assist the designer s preliminary application evaluation Figure 20 HUF75531SK8 Rev B 755315 8 defines the for the device as a function of the top graph Spice and SABER thermal models are provided for copper component side area This is for a horizontally each of the listed pad areas positioned FR 4 board with 102 copper after 1000 seconds of steady state power with no air flow This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation Pulse applications can be evaluated using the Fairchild device Spice thermal model o
3. PAI rie HUF75531SK8 2 SEMICONDUCTOR Data Sheet December 2001 6A 80V 0 030 Ohm N Channel UltraFET Power MOSFET Packaging JEDEC MS 012AA Features BRANDING DASH Ultra Low On Resistance DS ON 0 0300 Ves 10V 5 e Simulation Models Temperature Compensated PSPICE and SABER Electrical Models Spice and SABER Thermal Impedance Models www fairchildsemi com Peak Current vs Pulse Width Curve UIS Rating Curve Symbol SOURCE 1 DRAIN 8 Ordering Information SOUCI PART NUMBER PACKAGE BRAND SOURCE 3 DRAIN 6 HUF75531SK8 MS 012AA 75531SK8 GATE 4 DRAIN 5 NOTE When ordering use the entire part number Add the suffix T to obtain the variant in tape and reel e g HUF75531SK8T Absolute Maximum Ratings T4 25 C Unless Otherwise Specified HUF75531SK8 UNITS Drain to Source Voltage Note 1 Vpss 80 V Drain to Gate Voltage Ras 20kQ Note 1 VDGR 80 V Gale Source VOlA0S ri o bee VGS 20 V Drain Current Continuous 25 C Vas 10V Figure 2 ID 6 A Continuous 100 C Vas 10V Figure 2 Ip 4 A Pulsed Drain IDM Figure 4 Pulsed Avalanche sex RERO noe b
4. 10 RLGATE 7 LSOURCE m mmed n16 n6 n8 n8 model mmedmod I 1u w 1u 8 7 wie ae m mstrong 116 n6 n8 n8 model mstrongmod l 1u 1 RSOURCE m mweak n16 121 n8 n8 model mweakmod l 1u w 1u RLSOURCE res rbreak n17 n18 1 tcl 1 21e 3 tc2 0 Nu 15 res rdrain 50 16 9 30e 3 tc1 1 32e 2 tc2 3 21e 5 13 14 17 18 res rgate n9 n20 1 70 res rldrain n2 n5 10 S1B 9 S2B RVTEMP res rlgate n1 n9 11 2 13 CB 19 res rlsource n3 n7 1 29 CA 14 IT Q res rsic1 n5 n51 1e 6 tc1 4 00e 3 tc2 0 y VBAT res rslc2 n5 n50 1e3 EGS EDS n8 n7 11 35 3 1 00e 3 tc2 0 s res rvtemp n18 n19 1 tc1 2 44e 3 tc2 0 8 22 res rvthres n22 n8 1 tc1 2 56e 3 tc2 9 91e 6 spe ebreak n11 n7 n17 n18 86 60 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 spe evtemp n20 n6 n18 n22 1 spe evthres n6 n21 n19 n8 1 sw vcsp s1a n6 n12 n13 n8 model s1amod sw vcsp s b n13 n12 n13 n8 model s1bmod sw vcsp s2a n6 n15 n14 n13 model s2amod sw vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i 151 gt 50 RVTHRES iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 125 2 HUF75531SK8 Rev B 2001 Fairchild Semiconductor Corporation 755315 8 SPICE Thermal Model REV 12 Feb 2000 th 9 JUNCTION HUF75531SK8 Copper
5. OPERATING AREA FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY PULSE DURATION 80us DUTY CYCLE 0 5 MAX lt z 2 2 cc cc D O O z z cc cc a a PULSE DURATION 80us DUTY CYCLE 0 5 MAX Ta 25 C 0 0 5 1 0 1 5 2 0 VGs GATE TO SOURCE VOLTAGE V Vps DRAIN TO SOURCE VOLTAGE V FIGURE 7 TRANSFER CHARACTERISTICS FIGURE 8 SATURATION CHARACTERISTICS 2 5 PULSE DURATION 80us DUTY CYCLE 0 5 MAX N ON RESISTANCE in NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE 0 5 80 40 0 40 80 120 160 80 40 0 40 80 120 160 Ty JUNCTION TEMPERATURE C Ty JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs RESISTANCE vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 2001 Fairchild Semiconductor Corporation HUF75531SK8 Rev B 755315 8 Typical Performance Curves Continued 3000 LL EE O 5 p 1000 T N lt a a OF a lt _ 32 5 o O Qa lt ux 15 o 100 tc 9 BRI a 50 80 40 0 40 80 120 160 0 1 1 0 10 80 JUNCTION TEMPERATURE 9C Vps DRAIN TO SOURCE VOLTAGE V FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE VOLTAGE vs JUNCTION TEMPERATURE 10 gt O aq 8 ar gt LU 6 tcc 9 4 WAVEFORMS 2 DESCENDING ORDER o
6. Qg rOT Vas OV to 20V Vpp 40V 68 82 nC Gate Charge at 10V Vas 0Vtoi0V 0 shan 37 45 nC Threshold Gate Charge Qg TH Ves OV to 2V E 13 16 17 2 4 2 9 nC Gate to Source Gate Charge Qgs 4 8 nC Gate to Drain Miller Charge 14 nC CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Ves OV 1210 Output Capacitance Coss 2 385 Reverse Transfer Capacitance Crss 115 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 6A 1 25 V Isp 4A 1 00 V Reverse Recovery Time trr Isp 6A dlsp dt 100A us 105 ns Reverse Recovered Charge Isp dlsp dt 100A us 325 nC 2001 Fairchild Semiconductor Corporation HUF75531SK8 Rev B 755315 8 Typical Performance Curves 1 2 T 1 0 AR 2 lt 0 8 2 0 6 2 z lt 2 oa E oc amp 5 0 2 0 0 25 50 75 100 125 150 Ta AMBIENT TEMPERATURE C Ta AMBIENT TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE CASE TEMPERATURE 3 1 OS O OA OR te ae IM ES ft u g mani lt 0 1 m IEEE c pf a m 1 11 z Ss aii HIIS HH co E lt
7. 2 Ip 6A Ip z 1A S 0 10 20 30 40 Qg GATE CHARGE nC NOTE Refer to Fairchild Application Notes AN7254 and AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms Vps BVpss tp Vps VARY tp TO OBTAIN las REQUIRED PEAK lAs CUTS VDD Ves yee 2 E E oV eere a gt tav FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15 UNCLAMPED ENERGY WAVEFORMS 2001 Fairchild Semiconductor Corporation HUF75531SK8 Rev 755315 8 Test Circuits Waveforms Continued lg REF FIGURE 16 GATE CHARGE TEST CIRCUIT Vas FIGURE 18 SWITCHING TIME TEST CIRCUIT Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature T jy and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation Pp in an application Therefore the applications ambient temperature C and thermal resistance Rg C W must be reviewed to ensure that T is never exceeded Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part Cau Ta EQ 1 ou 2 In using surface mount devices such as the SOP 8 package the environment in which it is applied will have a significant influence on the part s current and maximum power 2001 Fairchild Semiconductor Corporation Voo
8. Area 0 04 2 CTHERM th 8 2 0e 3 2 8 7 5 0 3 1 CTHERM1 CTHERMS 7 6 1 0e 2 CTHERM4 6 5 4 0e 2 CTHERM5 5 4 9 0e 2 CTHERM6 4 3 1 2e 1 CTHERM7 2 0 5 RTHERM2 CTHERM2 8 2 tl 1 3 RTHERM th 8 0 1 RTHERM2 8 7 0 5 RTHERM3 7 6 1 0 RTHERM3 CTHERM3 RTHERM4 6 5 5 0 RTHERM5 5 4 8 0 6 RTHERM6 4 3 26 RTHERM7 2 39 RTHERM8 2 tl 55 SABER Thermal Model Copper Area 0 04 in RTHERM4 CTHERM4 template thermal_model th tl BIER thermal c th tl 4 ctherm ctherm1 th 8 2 0e 3 ctherm ctherm3 7 6 1 0 2 ctherm ctherm4 6 5 4 0e 2 ctherm ctherm5 5 4 9 0e 2 ctherm ctherm6 4 3 1 2e 1 ctherm ctherm7 3 2 0 5 RTHERM7 CTHERM7 ctherm ctherm8 2 tl 1 3 rtherm rtherm1 th 8 0 1 rtherm rtherm2 8 7 2 0 5 rtherm rtherm3 7 6 1 0 RTHERM8 CTHERMS8 rtherm rtherm4 6 5 5 0 rtherm rtherm5 5 4 8 0 rtherm rtherm6 4 3 26 rtherm rtherm7 3 2 39 t CASE rtherm rtherm8 2 tl 2 55 TABLE 1 THERMAL MODELS component 2001 Fairchild Semiconductor Corporation HUF75531SK8 Rev B
9. ERMAL RESISTANCE vs MOUNTING PAD AREA 150 COPPER BOARD AREA DESCENDING ORDER E E ee 0281 me 90 gs TTT M L e EN 0 ern 60 ZoJA THERMAL IMPEDANCE 9C W 30 t RECTANGULAR PULSE DURATION s FIGURE 21 THERMAL IMPEDANCE vs MOUNTING PAD AREA 2001 Fairchild Semiconductor Corporation HUF75531SK8 Rev B 755315 8 PSPICE Electrical Model SUBCKT HUF75531SK8 213 rev 22 Feb 2000 CA 128 2 00e 9 CB 15 14 2 00e 9 CIN 6 8 1 09e 9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD LDRAIN DPLCAP 10 5 DPLCAPMOD ee S DRAIN 42 10 RLDRAIN EBREAK 11 7 17 18 86 60 RSLC1 EDS 14 8 5 81 51 EGS 13 8 6 81 RSLC2 ESG 6 106 8 1 ESLC 44 EVTHRES 6 21198 1 EVTEMP 20 6 18 22 1 50 EVTHRES a LDRAIN 2 5 1 0e 9 LGATE EVTEMP LGATE 1 9 1 12e 9 GATE RGATE LSOURCE 3 7 1 29e 10 E 4 16 9 20 DBREAK DBODY IT 8 17 1 MWEAK MMED 16 6 8 8 MMEDMOD RLGATE MSTRO 16688 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 LSOURCE SOURCE 7 gt 3 RSOURCE RDRAIN 50 16 RDRAINMOD 9 30e 3 RLSOURCE RGATE 9 20 1 70 SIA 9 992A RLDRAIN 2 5 10 29 42 RBREAK E RLGATE 1 9 11 2 8 13 RLSOURCE 3 7 1 29 RSLC1 551 RSLCMOD 1 6 RVTEMP RSLC2 5 50 1e3 CA Us CB 19 RSOURCE 8 7 RSOURCEMOD 11 35e 3 14 4 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD 5s S1B 13 12 13 8 S1B
10. MOD 52 6 15 14 13 S2AMOD RVTHRES S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 125 2 MODEL DBODYMOD D IS 1 06e 12 RS 5 86e 3 TRS1 4 97e 5 TRS2 2 11e 6 1 51 9 TT 1 05e 7 0 53 MODEL DBREAKMOD D RS 4 45e 1TRS1 1 02e 3TRS2 0 MODEL DPLCAPMOD D 1 48e 915 1e 3 0 78 MODEL MMEDMOD NMOS 3 18 KP 2 55 IS 1e 30 N 10 TOX 1 L 1u W 1 RG 1 70 MODEL MSTROMOD NMOS VTO 3 67 KP 5515 1 30 N 10 TOX 1 L 1u W 1 MODEL MWEAKMOD NMOS VTO 2 83 0 1 IS 1 30 N 10 TOX 1 L 1u W 1 RG 17 0 Rs 0 10 MODEL RBREAKMOD RES TC1 1 21e 3TC2 0 MODEL RDRAINMOD RES TC1 1 32e 2 TC2 3 21 5 MODEL RSLCMOD RES TC1 4 00e 3 TC2 0 MODEL RSOURCEMOD RES TC1 1 00e 3 TC2 0 MODEL RVTHRESMOD RES TC1 2 56e 3 TC2 9 91e 6 MODEL RVTEMPMOD RES TC1 2 44e 3TC2 0 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH MODEL S2AMOD VSWITCH MODEL S2BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 6 0 VOFF 4 0 RON 1e 5 ROFF 0 1 VON 4 0 VOFF 6 0 RON 1e 5 ROFF 0 1 VON 3 0 VOFF 0 0 RON 1e 5 ROFF 20 1 VON 0 0 VOFF 3 0 ENDS NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by
11. William J Hepp and C Frank Wheatley 2001 Fairchild Semiconductor Corporation HUF75531SK8 Rev B 755315 8 SABER Electrical Model REV 22 feb 2000 template huf75531sk8 n2 n1 n3 electrical n2 n1 n3 var i iscl dp model dbodymod is 1 06 12 rs 5 86e 3 trs1 4 97e 5 trs2 2 11e 6 dp model dbreakmod rs24 45e 1 trs1 1 02e 3 trs2 0 dp model dplcapmod cjo 1 48e 9 is 1e 30 m 0 78 m model mmedmod type _n vto 3 18 kp 2 55 is 1e 30 tox 1 m model mstrongmod type _n vto 3 67 kp 55 is 1e 30 tox 1 m model mweakmod type _n vto 2 83 kp 0 1 is 1e 30 tox 1 cjo 1 51e 9 tt 1 05e 7 m 0 53 LDRAIN sw_vcsp model s1amod ron 1e 5 roff 0 1 von 6 0 voff 4 0 DPLCAP 5 DRAIN sw vcsp model sibmod ron 1 5 0 1 von 4 0 voff 6 0 we 22 Sw vcsp model s2amod ron 16 5 roff 0 1 von 3 0 voff 0 0 10 Sw vcsp model s2bmod ron 16 5 roff 0 1 von 0 0 voff 3 0 RSLC1 RLDRAIN 1 c ca n12 n8 2 00e 9 RSLC2 i c cb n15 n14 2 00e 9 n6 n8 1 09 9 50 DBREAK dp dbody n7 n5 model dbodymod F dp dbreak n5 n11 model dbreakmod 8 RDRAIN ESG 11 dp dplcap n10 n5 model dplcapmod EVTHRES 21 i it n8 n17 1 I MWEAK LGATE EVTEMP a DBODY GATE RGATE l6 idrain n2 n5 1 00 9 16 E e EBREAK l gate n1 n9 1 12e 9 20 MSTR l source n3 n7 1 29
12. on 2001 Fairchild Semiconductor Corporation HUF75531SK8 Rev B 755315 8 Electrical Specifications T 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip 250uA Ves OV Figure 11 80 V Zero Gate Voltage Drain Current Ipss Vps 75V Ves OV 1 Vps 70V Vas OV Ta 150 C 250 Gate to Source Leakage Current lass Vas 20 100 ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH Vas Vps Ip 250pA Figure 10 2 4 V Drain to Source On Resistance DS ON Ip 6A Vas 10V Figure 9 2 0 025 0 030 Q THERMAL SPECIFICATIONS Thermal Resistance Junction to Roya Pad Area 0 76 in 490 3 mm Note 2 50 C W Ambient Pad Area 0 054 in 34 8 mm Note 3 i 152 C W Pad Area 0 0115 2 7 42 mm Note 4 189 C W SWITCHING SPECIFICATIONS Ves 10V Turn On Time ton Vpp 40V Ip 6A 55 ns Turn On Delay Time B E 10 5 ns Rise Time ty Figures 18 19 25 ns Turn Off Delay Time td OFF 49 ns Fall Time tf 29 s ns Turn Off Time loFF 115 ns GATE CHARGE SPECIFICATIONS Total Gate Charge
13. r manually utilizing the normalized maximum transient thermal impedance curve Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms For pulse widths less than 100ms the transient thermal impedance is determined by the die and package Therefore CTHERM through CTHERMS5 RTHERM1 through RTHERM5 remain constant for each of the thermal models listing of the model component values is available in Table 1 Displayed on the curve are Rg values listed in the Electrical Specifications table The points were chosen to depict the 240 compromise between the copper board area the thermal resistance and ultimately the power dissipation Roya 83 2 23 6 1N AREA 200 189 C W 0 0115in Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2 Rega Is defined as the natural log of the area times a coefficient added to a constant The area in square inches is the top copper area including the gate and source pads Rosa C W o e Roja 83 2 23 6 x In Area EQ 2 The transient thermal impedance Zg a is also effected by 0 1 1 0 varied top copper board area Figure 21 shows the effect of AREA TOP COPPER AREA in copper pad area on single pulse transient thermal impedance Each trace represents a copper pad area in square inches corresponding to the descending list in the FIGURE 20 TH
14. x dbo UIS Figures 6 14 15 Power DISSIDAUON i9 air d rio d a deiecta ex ao A dU wol i nh descr Pp 2 5 W Derate Above 259 20 mW 9C Operating and Storage Ty 55 to 150 C Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case for 105 TL 300 Package Body for 10s See Techbrief 70 Tpkg 260 NOTES 1 TJ 25 C to 125 C 2 509C W measured using FR 4 board with 0 76 2 490 3 mm copper pad at 10 second 3 1529C W measured using FR 4 board with 0 054 2 34 8 mm copper pad at 1000 seconds 4 1899C W measured using FR 4 board with 0 0115 2 7 42 mm copper pad at 1000 seconds CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Product reliability information can be found at http www fairchildsemi com products discrete reliability index html For severe environments see our Automotive HUFA series All Fairchild semiconductor products are manufactured assembled and tested under 1509000 and QS9000 quality systems certificati
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