MICROCHIP PIC12C67X AND PIC12CE67X EPROM Memory Programming Specification handbook
Contents
1. Legend Input O Output P Power 1998 Microchip Technology Inc DS40175A page 1 PIC12C67X and PIC12CE67X 2 0 PROGRAM MODE ENTRY In the configuration memory space 0x2000 0x20FF are utilized When in configuration memory as in the 2 1 User Program Memory Map user memory the 0x2000 0x2XFF segment is repeat edly accessed as the PC exceeds 0x2XFF see The user memory space extends from 0x0000 to Figure 2 1 Ox1FFF 8K Table 2 1 shows actual implementation of program memory in the PIC12C67X family A user may store identification information ID in four ID locations The ID locations are mapped in 0x2000 TABLE 2 1 IMPLEMENTATION OF 0x2003 PROGRAM MEMORY IN THE Note 1 All other locations in PIC configuration PIC12C67X memory are reserved and should not be programmed Device Program Memory Size Note 2 Due to the secure nature of the on board PIC12C671 0x000 Ox3FF 1K EEPROM memory in the PIC12CE673 PIC12CE673 674 it can be accessed only PIC12C672 0x000 Ox7FF 2K by the user program PIC12CE674 When the PC reaches the last location of the imple mented program memory it will wrap around and address a location within the physically implemented memory see Figure 2 1 In programming mode the program memory space extends from 0x0000 to Ox3FFF with the first half 0x0000 0x1FFF being user program memory and the second half 0x2000 0x3FFF being configuration memory The2. Read Unscrambled Write Enabled Read Unscrambled Write Enabled ID Locations 0x2000 0x2003 Read Unscrambled Write Enabled Read Unscrambled Write Enabled INTRC Calibration Word 0X7FF Read Unscrambled Write Enabled Read Unscrambled Write Enabled 1998 Microchip Technology Inc DS40175A page 9 PIC12C67X and PIC12CE67X 3 2 Checksum 3 2 1 CHECKSUM CALCULATIONS Checksum is calculated by reading the contents of the PIC12C67X and PIC12CE67X memory locations and adding the opcodes up to the maximum user address able location excluding the oscillator calibration loca tion in the last address e g Ox3FE for the PIC12C671 CE673 Any carry bits exceeding 16 bits are neglected Finally the configuration word appropri ately masked is added to the checksum Checksum computation for each member of the PIC12C67X and PIC12CE67X devices is shown in Table 3 2 The checksum is calculated by summing the following The contents of all program memory locations e The configuration word appropriately masked e Masked ID locations when applicable The least significant 16 bits of this sum is the check sum The following table describes how to calculate the checksum for each device Note that the checksum cal culation differs depending on the code protect setting Since the program memory locations read out differ ently depending on the code protect setting the table describes how to manipulate
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4. N N 1 N of Program Cycles No Yes ID Configuration Error PROGRAM FLOW CHART PIC12C67X AND PIC12CE67X CONFIGURATION WORD Read Data Command No Data Correct Yes v Apply 3N Program Cycles l Increment Address Command DS40175A page 6 Program Cycle 100 Cycles v Report Program ID Config Error No Data Correct Data Correct Set Vpp Vppmax Read Data Command Set Vpp ViHH2 Read Data Command Data Correct Set VpD Vppmin Read Data Command Set Vpp ViHH2 1998 Microchip Technology Inc EPROM Memory Programming Specification 1 0 1 2 LOAD DATA After receiving this command the chip will load in a 14 bit data word when 16 cycles are applied as described previously A timing diagram for the load data command is shown in Figure 4 1 1 0 1 3 READ DATA After receiving this command the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input The GPO pin will go into output mode on the second rising clock edge and it will revert back to input mode hi imped ance after the 16th rising edge A timing diagram of this command is shown in Figure 4 2 1 0 1 4 INCREMENT ADDRESS The PC is incremented when this command is received timing diagram of this command is shown in
5. PC will increment from 0x0000 to Ox1FFF and wrap to 0x000 or 0x2000 to Ox3FFF and wrap around to 0x2000 not to 0x0000 Once in con figuration memory the highest bit of the PC stays a 1 thus always pointing to the configuration memory The only way to point to user program memory is to reset the part and reenter program verify mode as described in Section 2 2 The last location of the program memory space holds the factory programmed oscillator calibration value This location should not be programmed except when blank a non blank value should not cause the device to fail a blank check If blank the programmer should program it to a RETLW XX statement where XX is the calibration value DS40175A page 2 1998 Microchip Technology Inc EPROM Memory Programming Specification FIGURE 2 1 PROGRAM MEMORY MAPPING ID Location IRW PRW Implemented Implemented ID Location Implemented ID Location ID Location Reserved Reserved Reserved Reserved Reserved Configuration Word Reserved Reserved Reserved Reserved a E EE a s 1998 Microchip Technology Inc DS40175A page 3 PIC12C67X and PIC12CE67X 2 2 Program Verify Mode The program verify mode is entered by holding pins GP1 and GPO low while raising MCLR pin from VIL to VIHH high voltage VDD is then raised from VIL to VIH Once in this mode the user program memory and the configuration m
6. ok Note Any programmer not meeting these requirements may only be classified as prototype or development programmer but not a production quality programmer 1998 Microchip Technology Inc DS40175A page 7 PIC12C67X and PIC12CE67X 2 0 CONFIGURATION WORD The PIC12C67X and PIC12CE67X family members have several configuration bits These bits can be pro grammed reads 0 or left unprogrammed reads 1 to select various device configurations Figure 2 1 pro vides an overview of configuration bits FIGURE 2 1 CONFIGURATION WORD Bit Number 13 12 11 10 2 1 0 Register CONFIG CP1 lcro cP CPO CP1 CPO IMCLRE m CP0 Pware FOSC2 FOSC1 FOSC0 ddress 2007h bit 13 8 6 5 CP1 CP0 Code Protection bits 1 2 11 Code protection off 10 0400h 07FFh code protected 01 0200h 07FFh code protected 00 0000h 07FFh code protected MCLRE GP3 MCLR pin function select 1 GP3 MCLR pin function is MCLR 0 GP3 MCLR pin function is digital 1 0 MCLR internally tied to Vdd PWRTE Power up Timer Enable bit 1 1 PWRT disabled 0 PWRT enabled WDTE Watchdog Timer Enable bit 1 WDT enabled 0 WDT disabled FOSC2 FOSC0 Oscillator Selection bits 111 EXTRC oscillator CLKOUT function on GP4 OSC2 CLKOUT pin 110 EXTRC oscillator GP4 function on GP4 OSC2 CLKOUT pin 101 INTRC oscillator CLKOUT function on GP4 OSC2 CLKOUT pin 100 INT
7. the actual program mem ory values to simulate the values that would be read from a protected device When calculating a checksum by reading a device the entire program memory can simply be read and summed The configuration word and ID locations can always be read Note that some older devices have an additional value added in the checksum This is to maintain compatibil ity with older device programmer checksums TABLE 3 2 CHECKSUM COMPUTATION Ox25E6 at Device Bs sA Checksum See 0 and max address PIC12C671 OFF SUM 0x000 0x3FE CFGW amp Ox3FFF 3B3F 070D PIC12CE673 1 2 SUM 0x000 0x1FF CFGW 8 Ox3FFF SUM ID 4E5E 0013 ALL CFGW amp 0x3FFF SUM ID 3B4E 071C PIC12C672 OFF SUM 0x000 0x7FE CFGW amp Ox3FFF 373F 030D PIC12CE674 1 2 SUM 0x000 0x3FF CFGW amp Ox3FFF SUM ID 5D6E 0F23 3 4 SUM 0x000 0x1FF CFGW 8 Ox3FFF SUM ID 4A5E FC13 ALL CFGW 8 0x3FFF SUM ID 374E 031C Legend CFGW Configuration Word SUM a b Sum of locations a through b inclusive SUM ID ID locations masked by OxF then made into a 16 bit value with IDO as the most significant nibble For example IDO 0x12 ID1 0x37 ID2 0x4 ID3 0x26 then SUM ID 0x2746 Checksum Sum of all the individual expressions MODULO 0xFFFF Addition amp Bitwise AND DS40175A page 10 1998 Microchip Technology Inc EPROM Memory Programming Specification 4 0 PROGRAM VERIFY MODE ELECTRICAL CHARACTERIS
8. this information may be provided Microchip Technology Inc feels strongly that this feature is important for the benefit of the end customer TABLE 3 1 PIC12C671 PIC12CE673 To code protect e Protect all memory e Protect 0200h 07FFh e No code protection CONFIGURATION WORD 00 0000 X00X XXXX 01 0101 X01X XXXX 11 1111 X11X XXXX Program Memory Segment R W in Protected Mode R W in Unprotected Mode Configuration Word 0x2007 Read Unscrambled Write Enabled Read Unscrambled Write Enabled Unprotected memory segment Read Unscrambled Write Enabled Read Unscrambled Write Enabled Protected memory segment Read All 0 s Write Disabled Read Unscrambled Write Enabled ID Locations 0x2000 0x2003 INTRC Calibration Word OX3FF Read Unscrambled Write Enabled Read Unscrambled Write Enabled Read Unscrambled Write Enabled Read Unscrambled Write Enabled PIC12C672 PIC12CE674 To code protect e Protect all memory e Protect 0200h 07FFh e Protect 0400h 07FFh e No code protection 00 0000 X00X XXXX 01 0101 X01X XXXX 10 1010 X10X XXXX 11 1111 X11X XXXX Program Memory Segment R W in Protected Mode R W in Unprotected Mode Configuration Word 0x2007 Read Unscrambled Write Enabled Read Unscrambled Write Enabled Unprotected memory segment Protected memory segment Read Unscrambled Write Enabled Read All 0 s Write Disabled
9. 75A page 14 1998 Microchip Technology Inc Copyright Each Manufacturing Company All Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 100 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
10. 8 ThidO Hold time after VppT 2 us P9 TPPDP Hold time after VPP T 5 us Note 1 Program must be verified at the minimum and maximum VDD limits for the part Note 2 VIHH must be greater than VDD 4 5V to stay in programming verify mode 1998 Microchip Technology Inc DS40175A page 11 EPROM Memory Programming Specification FIGURE 4 1 LOAD DATA COMMAND PROGRAM VERIFY lt us min Program Verify Mode FIGURE 4 2 READ DATA COMMAND PROGRAM VERIFY P6 GPI CLOCK SA GPO cr lt us min us mint 1 i RB7 output Program Verify Mode FIGURE 4 3 INCREMENT ADDRESS COMMAND PROGRAM VERIFY VDD VIHH MCLR VPP fi P3 P4 us min 100ns min Program Verify Mode 1998 Microchip Technology Inc DS40175A page 12 EPROM Memory Programming Specification NOTES 1998 Microchip Technology Inc DS40175A page 13 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office Microchip Technology Inc 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 602 786 7200 Fax 602 786 7277 Technical Support 602 786 7627 Web http www microchip com Atlanta Microchip Technology Inc 500 Sugar Mill Road Suite 200B Atlanta GA 30350 Tel 770 640
11. Address 0 0 0 1 1 0 Begin programming 0 0 1 0 0 0 End Programming 0 0 1 1 1 0 DS40175A page 4 1998 Microchip Technology Inc EPROM Memory Programming Specification FIGURE 1 1 PROGRAM FLOW CHART PIC12C67X AND PIC12CE67X PROGRAM MEMORY No Yes Report Programming Read Data Command N N 1 N of Program Cycles E Data Correct Yes Apply 3N Additional Program Cycles Load Data Command Program Cycle Command All Locations Done s Begin Programming Yes Verify all Locations Vpp mn Vpp VinH2 Report Verify Data Correct Vpp un Error End Programming Command Wait 1 Verify all Locations VDD max Vpp VinH2 Report Verif Data Correct van ise Eror Yes Vppp Vpp range for programming typically 4 75V 5 25V Vpp mn Minimum Vpp for device operation Vpp max Maximum Vpp for device operation 1998 Microchip Technology Inc DS40175A page 5 PIC12C67X and PIC12CE67X FIGURE 1 2 amp ID LOCATIONS Set Vpp Vinut Load Configuration Command No Increment Address Command Address 2004 Yes Increment Address Command I Increment Address Command Program ID Loc Program Cycle
12. Figure 4 3 1 0 1 5 BEGIN PROGRAMMING A load command load configuration or load data must be given before every begin programming command Programming of the appropriate memory test program memory or user program memory will begin after this command is received and decoded Programming should be performed with a series of 100us programming pulses A programming pulse is defined as the time between the begin programming command and the end programming commandl 1 0 1 6 END PROGRAMMING After receiving this command the chip stops program ming the memory configuration program memory or user program memory that it was programming at the time 1 1 Programming Algorithm Requires Variable VDD The PIC12C67X and PIC12CE67X uses an intelligent algorithm The algorithm calls for program verification at Vppmin as well as VDDmax Verification at VDDMIN guarantees good erase margin Verification at VDDmax guarantees good program margin The actual programming must be done with VDD in the VDDP range 4 75 5 25V VDDP Vec range required during programming VDD min minimum operating VDD spec for the part VDD max maximum operating VDD spec for the part Programmers must verify the PIC12C67X and PIC12CE67X at its specified VDDmax and Vppmin lev els Since Microchip may introduce future versions of the PIC12C67X and PIC12CE67X with a broader VDD range it is best that these levels are user selectable defaults are
13. RC oscillator GP4 function on GP4 OSC2 CLKOUT pin 011 invalid selection 010 HS oscillator 001 XT oscillator 000 LP oscillator Note 3 All of the CP1 CPO pairs have to be given the same value to enable the code protection scheme listed 4 07FFh is always uncodeprotected on the 12C672 and 03FFh is always uncodeprotected on the 120671 This location contains the RETLW xx calibration instruction for the INTRC LE te i a nr Vr rrcrr rr rt DS40175A page 8 1998 Microchip Technology Inc EPROM Memory Programming Specification 3 0 CODE PROTECTION The program code written into the EPROM can be pro tected by writing to the CPO 8 CP1 bits of the configu ration word For PIC12C67X and PIC12CE67X devices once code protection is enabled all protected segments read 0 s or garbage values and are prevented from further programming All unprotected segments including ID and configuration word locations and calibration word location read normally and can be programmed 3 1 Embedding Configuration Word and ID Information in the Hex File To allow portability of code the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file If configuration word information was not present in the hex file then a simple warning message may be issued Similarly while saving a hex file configuration word and ID information must be included An option to not include
14. S PIC 12C 671T 101 SM fH Av Fi Micnochp PIC12C67X AND PIC12CE67X EPROM Memory Programming Specification This document includes the programming Pin Diagram specifications for the following devices e PIC12C671 e PIC12C672 VDD lt VSS e PIC12CE673 GP5 OSC1 CLKIN 29 GPO ANO PIC12CE674 SPORE A 99 lt gt GP1 AN1 VREF GP3 MCLR Vep O lt GP2 TOCKI x AN2 INT 1 0 PROGRAMMING THE PIC12C67X AND PIC12CE67X The PIC12C67X and PIC12CE67X can be pro grammed using a serial method In serial mode the PIC12C67X and PIC12CE67X can be programmed while in the users system This allows for increased design flexibility 1 1 Hardware Requirements The PIC12C67X and PIC12CE67X requires two pro grammable power supplies one for VDD 2 0V to 6 0V recommended and one for VPP 12V to 14V Both supplies should have a minimum resolution of 0 25V 1 2 Programming Mode The programming mode for the PIC12C67X and PIC12CE67X allows programming of user program memory special locations used for ID and the configu ration word for the PIC12C67X and PIC12CE67X PIN DESCRIPTIONS DURING PROGRAMMING PIC12C671 672 and PIC12CE673 674 During Programming Pin Name Pin Name Pin Type Pin Description GP1 CLOCK Clock input GPO DATA O Data input output GP3 MCLR VPP VPP P Programming Power VDD VDD P Power Supply Vss Vss P Ground
15. TICS TABLE 4 1 AC DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM VERIFY TEST MODE Standard Operating Conditions Operating Temperature 10 C lt TA lt 40 C unless otherwise stated 25 C is recommended Operating Voltage 4 5V lt VDD lt 5 5V unless otherwise stated nee Sym Characteristic Min Typ Max Units Conditions General PD1 VDDP Supply voltage during programming 4 75 5 0 5 25 V PD2 IDDP Supply current from VDD 20 mA during programming PD3 Voov Supply voltage during verify Vopmin VpDmax V Note 1 PD4 VIHH1 Voltage on MCLR VPP during 12 75 13 25 V Note 2 programming PD5 VIHH2 Voltage on MCLR VPP during verify VDD 4 0 13 5 PD6 IPP Programming supply current from 50 mA VPP PD9 VIH1 GPO GP1 input high level 0 8 VDD V Schmitt Trigger input PD8 VIL1 GPO GP1 input low level 0 2 VDD V Schmitt Trigger input Serial Program Verify P1 TR MCLR VPP rise time Vss to VIHH 8 0 us for test mode entry P2 T MCLR Fall time 8 0 us P3 Tseti Data in setup time before clock 100 ns P4 Thld1 Data in hold time after clock 100 ns P5 Tdly1 Data input not driven to next clock 1 0 us input delay required between com mand data or command command P6 Tdly2 Delay between clock J to clock T of 1 0 us next command or data P7 Tdly3 Clock T to data out valid 200 ns during read data P
16. emory can be accessed and pro grammed in serial fashion The mode of operation is serial and the memory that is accessed is the user pro gram memory GP1 is a Schmitt Trigger input in this mode The sequence that enters the device into the program ming verify mode places all other logic into the reset state the MCLR pin was initially at VIL This means that all O are in the reset state High impedance inputs Note 1 The MCLR pin must be raised from VIL to VIHH before VDD is applied This is to ensure that the device does not have the PC incremented while in valid operation range Note 2 Do not power GP2 GP4 or GP5 before VDD is applied 1 0 1 PROGRAM VERIFY OPERATION The GP1 pin is used as a clock input pin and the GPO pin is used for entering command bits and data input output during serial operation To input a com mand the clock pin GP1 is cycled six times Each command bit is latched on the falling edge of the clock with the least significant bit LSB of the command being input first The data on pin GPO is required to have a minimum setup and hold time see AC DC specs with respect to the falling edge of the clock Commands that have data associated with them read and load are specified to have a minimum delay of ips between the command and the data After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit Data is also input and ou
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18. onale Colleoni Palazzo Taurus 1 V Le Colleoni 1 20041 Agrate Brianza Milan Italy Tel 39 39 6899939 Fax 39 39 6899883 1 13 98 Microchip received ISO 9001 Quality System certification for its worldwide fabrication facilities in January 1997 Our field programmable PICmicro 8 bit MCUs Serial EEPROMs related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization ISO All rights reserved 1998 Microchip Technology Incorporated USA 2 98 d Printed on recycled paper RE PE ES Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information or infringement of patents or other intellectual property rights arising from such use or otherwise Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip No licenses are conveyed implicitly or otherwise under any intellectual property rights The Microchip logo and name are registered trademarks of Microchip Technology Inc in the U S A and other countries All rights reserved All other trademarks mentioned herein are the property of their respective companies DS401
19. tput LSB first Therefore during a read operation the LSB will be transmitted onto pin GPO on the rising edge of the second cycle and during a load operation the LSB will be latched on the falling edge of the second cycle A minimum 1us delay is also specified between consecutive commands All commands are transmitted LSB first Data words are also transmitted LSB first The data is transmitted on the rising edge and latched on the falling edge of the clock To allow for decoding of commands and reversal of data pin configuration a time separation of at least Tus is required between a command and a data word or another command The commands that are available are listed in Table 1 1 1 0 1 1 LOAD CONFIGURATION After receiving this command the program counter PC will be set to 0x2000 By then applying 16 cycles to the clock pin the chip will load 14 bits a data word as described above to be programmed into the config uration memory A description of the memory mapping schemes for normal operation and configuration mode operation is shown in Figure 2 1 After the configuration memory is entered the only way to get back to the user pro gram memory is to exit the program verify test mode by taking MCLR low VIL TABLE 1 1 COMMAND MAPPING Command Mapping MSB LSB Data Load Configuration 0 0 0 0 0 0 0 data 14 0 Load Data 0 0 0 0 1 0 0 data 14 0 Read Data 0 0 0 1 0 0 0 data 14 0 Increment
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