intersil HUF75339G3 HUF75339P3 HUF75339S3S handbook
Contents
1. Turn On Time ton Vpp 30V Ip 75A 110 ns RI 0 40 Vas 10V Turn On Delay Time Reg 5 10 15 ns Rise Time tr 60 ns Turn Off Delay Time td OFF 20 ns Fall Time tf i 25 ns Turn Off Time toFF 2 70 ns GATE CHARGE SPECIFICATIONS Total Gate Charge 20 Vpp 30V 110 130 nc Gate Charge at 10V Qg 10 Ves OV to 10V He 60 75 nC Threshold Gate Charge Vas OV to 2V 4 37 45 nC Gate to Source Gate Charge Qgs 9 nC Reverse Transfer Capacitance gt 23 nc 122 intersil HUF75339G3 HUF75339P3 HUF75339S3S Electrical Specifications 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Ves OV 2000 i pF f 1MHz Output Capacitance Coss Figure 12 700 pF Reverse Transfer Capacitance Crss 160 Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 75A 1 25 V Reverse Recovery Time trr Isp 75 dlsp dt 100A us gt 85 ns Reverse Recovered Charge QRR Isp 75A digp dt 100A us 160 nC Typical Performance Curves 1 2 80 a 1 02. i it n8 n17 1 LSOURCE CIN 8 SOURCE l Idrain n2 n5 1 0e 9 o 3 l lgate n1 n9 2 0 9 RSOURCE l lsource n3 n7 4 7e 10 RLSOURCE i I lgate i I lsource I I lgate 5 0 0302 952 RBREAK Pis 14 is 17 18 del dmod 1 1 1 m mmed n16 n6 n8 n8 model mmedmod 1u w 1u m mstrong n16 n6 n8 n8 model mstrongmod 1u w 1u SIB S2B RVTEMP m mweak n16 n21 n8 n8 modelamweakmod 1 1 13 19 14 4 res rbreak n17 n18 1 tc1 1 08e 3 tc2 2 5e 7 VBAT res rdbody n71 n5 3 02e 3 3 0 3 tc2 4 0e 6 EGS 5 EDS res rdbreak n72 n5 8 5e 2 tc1 8 0e 4 tc2 1 0e 7 8 res rdrain n50 n16 1 95e 3 tc1 2 05e 2 tc2 1 6e 5 22 res rgate n9 n20 0 34 RVTHRES res rldrain n2 n5 10 res rlgate n1 n9 20 res rlsource n3 n7 4 7 res rslc1 n5 n51 1e 6 tc1 6 0e 3 tc2 2 8e 6 res rslc2 n5 n50 1e3 res rsource n8 n7 6e 3 tc1 5 5e 4 tc2 1 75e 5 res rvtemp n18 n19 1 tc1 2 3e 3 tc2 4 0 6 res rvthres n22 n8 1 tc1 3 65 3 tc2 6 0e 6 n11 n7 n17 18 59 2 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n8 1 spe esg n10 n8 1 spe evtemp 20 18 22 1 spe evthres 21 19 8 1 sw_vcsp s1a n6 n12 n13 n8 model s1amod sw vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n15 n14 n13 model s2amod Sw vcsp s2b n13 n15 n1
3. ED F Data Sheet HUF75339G3 HUF75339P3 HUF75339S3S June 1999 File Number 4363 5 75A 55V 0 012 Ohm N Channel UltraFET Power MOSFETs These N Channel power MOSFETs manufactured using the EN innovative UltraFET process This advanced process technology achieves the lowest possible on resistance per silicon area resulting in outstanding performance This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge It was designed for use in applications where power efficiency is important such as switching regulators switching converters motor drivers relay drivers low voltage bus switches and power management in portable and battery operated products Features 75A 55V Simulation Models Temperature Compensated PSPICE and SABER Models SPICE and SABER Thermal Impedance Models Available on the WEB at www Intersil com families models htm Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature TB334 Guidelines for Soldering Surface Mount Components to PC Boards Formerly developmental type TA75339 Symbol Ordering Information D PART NUMBER PACKAGE BRAND HUF75339G3 TO 247 75339G G HUF75339P3 TO 220AB 75339P HUF75339S3S TO 263AB 75339S 5 NOTE When ordering use the entire part number Add the suffix T to obtain the TO 2
4. RATED 25 C 100us x 1 5 5 10 5 LIMITED BY rps oN Vpss MAX 55V LII 10 100 200 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 5 FORWARD BIAS SAFE OPERATING AREA 150 120 90 60 30 1 2 PULSE DURATION 80us DUTY CYCLE 0 5 MAX 25 C 3 4 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 7 SATURATION CHARACTERISTICS 500 If R 0 L las 1 3 RATED BVpss Vpp IfRzO L R In las R 1 3 RATED BVpss 1 100 las AVALANCHE CURRENT A H STARTING Ty 150 C uil srme ee 0 001 0 01 0 1 1 10 tay TIME IN AVALANCHE ms NOTE Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 150 PULSE DURATION 80 5 DUTY CYCLE 0 5 MAX Vpp 15V 120 Ip DRAIN CURRENT e eo 0 1 5 3 0 4 5 6 0 7 5 Vas GATE SOURCE VOLTAGE V FIGURE 8 TRANSFER CHARACTERISTICS 124 intersil HUF75339G3 HUF75339P3 HUF75339S3S Typical Performance Curves continued 2 5 PULSE DURATION 80us DUTY CYCLE 0 5 Vos 10V Ip 75 NORMALIZED DRAIN TO SOURCE ON RESISTANCE amp 80 40 0 40 80 120 160 200 Ty JUN
5. Vas DUT IG REF Ig REF 0 FIGURE 16 GATE CHARGE TEST CIRCUIT FIGURE 17 GATE CHARGE WAVEFORM Vps RL bio Vpp DUT 50 L PULSE WIDTH 0 Vas FIGURE 18 SWITCHING TIME TEST CIRCUIT FIGURE 19 RESISTIVE SWITCHING WAVEFORMS 126 intersil HUF75339G3 HUF75339P3 HUF75339S3S PSPICE Electrical Model HUF75339 2 1 3 CA 12 82 80e 9 15 14 2 80e 9 CIN 6 8 1 77 9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 59 2 EDS 14 8 5 81 EGS 13 8 6 81 ESG6 10681 EVTHRES 6 21 198 1 20 6 18 22 1 GATE IT 8 17 1 LDRAIN 2 5 1 0e 9 LGATE 1 9 2 0 9 LSOURCE 7 4 7 10 K1 LSOURCE 0 0302 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1 95e 3 RGATE 9 200 34 RLDRAIN 2 5 10 RLGATE 1 9 20 RLSOURCE 3 7 4 7 RSLC1 5 51 RSLCMOD 1 0e 6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 6 0e 3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD 52 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 rev 23 February 1999 DPLCAP 5 10 RSLC1 51 RSLC2 ESLC _ 50 RDRAIN gt EVTHRES AN LGATE EVTEMP 2 9 20 amp 5 IN 8 1 952 12 9 3 m dE 8 13 518 2 13
6. 14 2 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 230 4 LDRAIN DRAIN were RLDRAIN DBREAK 11 DBODY EBREAK MWEAK LSOURCE SOURCE A ETE RSOURCE RLSOURCE RBREAK 17 18 RVTEMP 19 4 22 RVTHRES MODEL DBODYMOD D IS 3 5e 12 RS 3 02 3 1 02 5 5 TRS1 8 0e 3 TRS2 4 0 6 2 9e 9 TT 4 35 8 0 5 MODEL DBREAKMOD D RS 8 5 2 TRS1 8 0 4 TRS2 1 0e 7 MODEL DPLCAPMOD D 2 25 9 IS 1 30 0 8 MODEL MMEDMOD NMOS VTO 3 1 KP 1 5 IS 1 30 10 TOX 1L 1u W 1u RG 0 34 MODEL MSTROMOD NMOS VTO 3 73 KP 86 5 IS 1 30 10 TOX 1 lu W lu MODEL MWEAKMOD NMOS VTO 2 7 0 01 IS 1e 30 10 TOX 1L 1 W 1 RG 3 4 MODEL RBREAKMOD RES TC1 1 08 3 TC2 2 5e 7 MODEL RDRAINMOD RES TC1 2 05e 2 TC2 1 6 5 MODEL RSLCMOD RES TC1 6 0e 3 TC2 2 8e 6 MODEL RSOURCEMOD RES TC1 5 5 4 1 75e 5 MODEL RVTHRESMOD RES TC1 3 65 3 TC2 6 0e 6 MODEL RVTEMPMOD RES TC1 2 3e 3 TC2 4 0e 6 MODEL S1AMOD VSWITCH RON 1 5 ROFF 0 1 VON 9 VOFF 5 5 MODEL S1BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 5 5 VOFF 9 MODEL S2AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 VOFF 2 1 MODEL S2BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 2 1 VOFF 0 ENDS NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit
7. Ty TstG 55 to 175 oc Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case for 106 TL 300 oc Package Body for 10s See 334 Tpkg 260 C CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 Ty 25 C to 150 C Electrical Specifications Tc 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip 250uA Veg OV Figure 11 55 V Zero Gate Voltage Drain Current Ipss Vps 50V Ves OV i 1 Vps 45V Vag OV 150 C 250 Gate to Source Leakage Current lass Vas 20 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH Vos Vps 250 Figure 10 2 4 Drain to Source On Resistance 10 75 Veas 10V Figure 9 0 010 0 012 Q THERMAL SPECIFICATIONS Thermal Resistance Junction to Case ReJc Figure 3 0 74 C W Thermal Resistance Junction to Ambient 247 30 C W TO 220 TO 263 x 62 C W SWITCHING SPECIFICATIONS Vcs 10V
8. for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 127 intersil HUF75339G3 HUF75339P3 HUF75339S3S SABER Electrical Model REV 23 February 1999 template huf75339 n2 n1 n3 electrical n2 n1 n3 var i iscl d model dbodymod is 3 5e 12 n 1 02 xti 5 5 cjo 2 9e 9 tt 4 35e 8 m 0 5 d model dbreakmod LDRAIN d model dplcapmod cjo 2 25e 9 is 1 30 10 m 2 0 8 5 DRAIN m model mmedmod type _n vto 3 1 1 5 is 1 30 tox 1 10 2 m model mstrongmod n vto 3 73 kp 86 5 is 1e 30 tox 1 RLDRAIN m model mweakmod type _n vto 2 7 kp 0 01 is 1e 30 tox 1 RSLC1 Sw vcsp model 1 1 5 0 1 von 9 voff 5 5 51 RDBREAK sw vcsp model s1bmod ron 1 5 0 1 von 5 5 voff 9 RSLC2 T sw_vesp model s2amod ron 1 5 0 1 von 0 voff 2 1 V RDBODY sw_vcsp model s2bmod ron 1 5 0 1 von 2 1 voff 0 _ 50 DBREAK c ca n12 n8 2 8e 9 71 c cb n15 n14 2 8e 9 ESG 3 ORAN 11 n6 n8 1 77 9 EVTHRES 18 MWEAK d dbody n7 n71 model dbodymod LGATE EVTEMP DBODY d dbreak 72 n11 model dbreakmod GATE RGATE 6 EBREAK d dplcap n10 n5 model dplcapmod wee 9 20 RLGATE
9. lt 60 lt 08 2 5 0 6 5 40 z 9 lt o a 0 4 M 6 0 2 a 0 0 0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 CASE TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE Tc CASE TEMPERATURE C FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE 2 DUTY CYCLE DESCENDING ORDER 1405 0 2 0 1 o gL oo i lt H 0 02 C a u 0 01 DM 0 1 N to NOTES DUTY FACTOR D t4 t2 SINGLE PULSE PEAK Ty X Zouc Tc 0 01 L l titi 105 10 4 10 3 10 2 1071 100 t RECTANGULAR PULSE DURATION FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 10 123 intersil HUF75339G3 HUF75339P3 HUF75339S3S Typical Performance Curves continued Ip DRAIN CURRENT A Ip DRAIN CURRENT A PEAK CURRENT 500 100 10 FOR TEMPERATURES ABOVE 25 C DERATE PEAK CURRENT AS FOLLOWS TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION pa s 150 t PULSE WIDTH FIGURE 4 PEAK CURRENT CAPABILITY Ty
10. 4 13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 230 4 0 128 _imtersil HUF75339G3 HUF75339P3 HUF75339S3S SPICE Thermal Model REV 11 February 1999 th JUNCTION HUF75339 CTHERM1 th 6 5 00 3 CTHERM2 6 5 1 90 2 CTHERNG 5 4 7 95e 3 CTHERMA 4 3 9 00e 3 CTHERMS 3 2 2 95e 2 6 2 tl 12 55 RTHERM1 CTHERM1 RTHERM1 th 6 5 04e 3 2 6 5 1 25 2 RTHERM2 RTHERMS 5 4 3 54e 2 RTHERM4 4 3 1 98e 1 RTHERMS 3 2 2 99e 1 RTHERM6 2 tl 3 97e 2 CTHERM2 SABER Thermal Model RTHERM3 SABER thermal model HUF75339 template thermal_model th tl thermal_c th tl ctherm ctherm1 th 6 5 00e 3 ctherm ctherm2 6 5 1 90e 2 RTHERM4 ctherm ctherm3 5 4 7 95e 3 ctherm ctherm4 4 3 9 00e 3 ctherm ctherm5 3 2 2 95e 2 ctherm ctherm6 2 tl 12 55 CTHERM3 CTHERM4 rtherm rtherm1 th 6 5 04e 3 rtherm rtherm2 6 5 1 25e 2 RTHERM5 rtherm rtherm3 5 4 3 54e 2 rtherm rtherm4 4 3 1 98e 1 rtherm rtherm5 3 2 2 99e 1 rtherm rtherm6 2 tl 3 97e 2 5 6 CTHERM6 All Intersil semiconductor products are manufactured assembled and tested under ISO9000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at a
11. 63AB variant in tape and reel e g HUF75339S3ST Packaging JEDEC STYLE 247 JEDEC TO 220AB SOURCE DRAIN FLANGE JEDEC TO 263AB DRAIN FLANGE GATE SOURCE 121 CAUTION These devices are sensitive to electrostatic discharge follow proper ESD Handling Procedures UltraFET is a trademark of Intersil Corporation PSPICEG is a registered trademark of MicroSim Corporation SABERO is a Copyright of Analogy Inc http www intersil com or 407 727 9207 Copyright Intersil Corporation 1999 HUF75339G3 HUF75339P3 HUF75339S3S Absolute Maximum Ratings 255 Unless Otherwise Specified UNITS Drain to Source Voltage Note 1 Vpss 55 V Drain to Gate Voltage Ras 20kQ Note 1 VpGR 55 V Gate to Source Voltage sedere sr hasa d Da ex RE uh Ed ea ba edu va Vas 20 Drain Current Gontinuous Figure 23 E DRE Sid 75 Pulsed Drain Current us ee Ret Figure 4 Pulsed Avalanche 0 1 Eas Figures 6 14 15 Power Dissipation sso ead queque b na seas Pp 200 w Derate Above 259C idest ea REOR pees ha Fa bs 1 35 wc Operating and Storage
12. CTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1 2 Ip 250uA _ NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 5 0 9 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 10 1 2 Ves Ip 250 1 0 0 8 NORMALIZED GATE THRESHOLD VOLTAGE 0 6 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 3750 Ves OV f 1MHz 3000 Rss Coss Cps 2250 1500 C CAPACITANCE pF 750 0 10 20 30 40 50 60 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE WAVEFORMS IN GATE TO SOURCE VOLTAGE V 0 10 20 Qg GATE CHARGE nC DESCENDING ORDER lp 75A lp 56A 4 Ip 37 5A Ip 18A 40 50 60 NOTE Refer to Intersil Application Notes AN7254 and AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 125 intersil HUF75339G3 HUF75339P3 HUF75339S3S Test Circuits and Waveforms Vps VARY tp TO OBTAIN REQUIRED PEAK lAs Vas lt tp 0v FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15 UNCLAMPED ENERGY WAVEFORMS Vps RL Vpp lt V Qg TOT Lo
13. ny time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site http www intersil com 129 intersil
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