intersil HUF75333G3 HUF75333P3 HUF75333S3S handbook
Contents
1. TL Package Body for 10s See Techbrief 334 Tpkg 55 55 20 66 Figure 4 Figures 6 14 15 150 1 55 to 175 300 260 UNITS CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 Ty 25 C to 150 C Electrical Specifications Tc 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip 250uA Veg OV Figure 11 55 V Zero Gate Voltage Drain Current Ipss Vps 50V Vas OV 2 1 Vps 45V Vag OV 150 C 250 Gate to Source Leakage Current less Ves 20V 5 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas rTH Vas Vos 25 Figure 10 2 2 4 Drain to Source On Resistance 10 66A Vag 10V Figure 9 0 013 0 016 Q THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Figure 3 1 C W Thermal Resistance Junction to Ambient TO 247 30 90 W TO 220 TO 263 62 C W SWITCHING SPECIFICATIONS Vas 10V Turn On Time ton Vp2. 0 1 5 3 0 4 5 6 0 7 5 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 7 SATURATION CHARACTERISTICS 0 L las 1 3 RATED BVpss Vpp 0 tav L R In Ias R 1 3 RATED BVpss 1 las AVALANCHE CURRENT A 0 001 0 01 tay TIME IN AVALANCHE ms NOTE Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 150 PULSE DURATION 80us DUTY CYCLE 0 5 MAX 15 559 Ip DRAIN CURRENT e 0 1 5 3 0 Vas GATE TO SOURCE VOLTAGE V 4 5 6 0 7 5 FIGURE 8 TRANSFER CHARACTERISTICS 106 intersil HUF75333G3 HUF75333P3 HUF75333S3S Typical Performance Curves continued 2 5 T T T PULSE DURATION 80us DUTY CYCLE 0 5 MAX Ves 10V Ip 66A 2 0 1 5 ON RESISTANCE 1 0 NORMALIZED DRAIN TO SOURCE 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1 2 Ip 250uA 14 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 10 Ves Ip 250A NORMALIZED
3. 75553 CA Data Sheet HUF75333G3 HUF75333P3 HUF 75333S3S June 1999 File Number 4362 5 66A 55V 0 016 Ohm N Channel UltraFET Power MOSFETs These N Channel power MOSFETs manufactured using the EN innovative UltraFET process This advanced process technology achieves the lowest possible on resistance per silicon area resulting in outstanding performance This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge It was designed for use in applications where power efficiency is important such as switching regulators switching convertors motor drivers relay drivers low voltage bus switches and power management in portable and battery operated products Features 66A 55V Simulation Models Temperature Compensated PSPICE and SABER Models SPICE and SABER Thermal Impedance Models Available on the WEB at www Intersil com families models htm Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature TB334 Guidelines for Soldering Surface Mount Components to PC Boards Formerly developmental type TA75333 Symbol Ordering Information D PART NUMBER PACKAGE BRAND HUF75333G3 TO 247 75333G G HUF75333P3 TO 220AB 75333P HUF75333S3S TO 263AB 75333S 5 NOTE When ordering use the entire part number Add the suffix to obtain the T
4. 4e 4 tc2 1 55e 5 CA 13 CB 19 res rdrain n50 n16 4 5e 3 tc1 1 16e 2 tc2 1 7e 5 n 14 4 res rgate 9 20 1 res rldrain n2 n5 10 EGS EDS res rlgate n1 n9 10 8 res rlsource n3 n7 10 22 res rsic1 n5 n51 1e 6 3 96e 3 tc2 2 7e 6 RVTHRES res rsic2 n5 n50 1e3 res rsource n8 n7 5 95e 3 1e 3 tc2 1e 5 res rvtemp n18 n19 1 tcl 2 75 3 tc2 0 5e 6 res rvthres n22 n8 1 tc1 2 8e 3 tc2 1e 6 spe ebreak n11 n7 n17 n18 58 85 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 Spe evtemp n20 n6 n18 n22 1 Spe evthres n6 n21 n19 n8 1 Sw 5 51 n12 n13 n8 model s1amod sw vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n15 n14 n13 model s2amod vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 180 4 110 intersil HUF75333G3 HUF75333P3 HUF75333S3S SPICE Thermal Model REV January 1999 th JUNCTION HUF75333 CTHERM th 6 4 9e 4 CTHERM2 6 5 4 5e 3 CTHERNG 5 4 6 0e 3 RTHERM1 CTHERM4 4 3 8 5e 3 CTHERMS 3 2 1 0 2 CTHERM6 2 tl 5 0e 2 CTHERM1 RTHERM1 th 6 6 0e 4 2 6 5 6 8e 3 RTHERM2 5 4 3 3e 2 RTHERM4 4 3 9 7e 2 5 2 3 3e 1 RTHERM6 2 tl 3 6e 1 CTHERM2 SABER Thermal Model RTHERM
5. 0 9 vj 1 45 MODEL MMEDMOD NMOS VTO 3 183 KP 2 IS 1e 30 10 TOX 1L tuW RG 1 MODEL MSTROMOD NMOS VTO 3 66 KP 51 5 IS 1e 30 N 10 TOX 1 1u W 1u MODEL MWEAKMOD NMOS VTO 2 703 KP 0 008 IS 1 30 N 10 1L 1uW RG 10 MODEL RBREAKMOD RES TC1 1 05e 3 TC2 4 5e 7 MODEL RDRAINMOD RES TC1 1 16e 2 TC2 1 7e 5 MODEL RSLCMOD RES TC1 3 96e 3 TC2 2 7e 6 MODEL RSOURCEMOD RES TC1 1e 3 TC2 1 5 MODEL RVTHRESMOD RES TC 2 8e 3 TC2 1 0e 6 MODEL RVTEMPMOD RES TC1 2 75e 3 2 0 5e 6 MODEL S1AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 8 VOFF 3 MODEL S1BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 3 VOFF 8 MODEL S2AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 VOFF 0 5 MODEL S2BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 5 VOFF 0 ENDS NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 109 intersil HUF75333G3 HUF75333P3 HUF75333S3S SABER Electrical Model REV August 1997 template huf75333 n2 n1 n3 electrical n2 n1 n3 var i iscl d model dbodymod is 1 3e 12 xti 6 cjo 1 7e 9 tt 40e 8 n 1 m 0 45 vj 0 75 d model dbreakmod d model cjo 1 8 9 is 18 30 1 m
6. GATE THRESHOLD VOLTAGE 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2000 Ves OV f 1MHz Ciss Cas Cap Cnss Cap Coss Cps Cap a e 1000 CAPACITANCE pF 500 0 10 20 30 40 50 60 Vps DRAIN TO SOURCE VOLTAGE FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE WAVEFORMS IN DESCENDING ORDER Ip 66A Ip 50A Vas GATE TO SOURCE VOLTAGE Ip Ip 16A 0 10 30 40 Qg GATE CHARGE nC NOTE Refer to Intersil Application Notes AN7254 and AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 107 intersil HUF75333G3 HUF75333P3 HUF75333S3S Test Circuits and Waveforms Vps VARY tp TO OBTAIN REQUIRED PEAK lAs Vas ov FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT IG REF FIGURE 16 GATE CHARGE TEST CIRCUIT 5 Mop DUT FIGURE 18 SWITCHING TIME TEST CIRCUIT i L Vas Vpp Qg ToT oo let FIGURE 15 UNCLAMPED ENERGY WAVEFORMS Vas 20V Qgs a gt REF 0 FIGURE 17 GATE CHARGE WAVEFORM 50 PULSE WIDTH FIGURE 19 RESISTIVE SWITCHING WAVEFORMS 108 intersil HUF75333G3 HUF75333P3 HUF75333S3S PSPICE Electrical Model HUF75333 213
7. 0 125 150 175 Tc CASE TEMPERATURE C Tc CASE TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE DUTY CYCLE DESCENDING ORDER 0 5 NORMALIZED THERMAL IMPEDANCE NOTES DUTY FACTOR D 1 42 PEAK Ty X Zeuc Tc LLLI 1 105 104 103 10 10 10 10 t RECTANGULAR PULSE DURATION s FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 105 intersil HUF75333G3 HUF75333P3 HUF75333S3S Typical Performance Curves continued Ibm PEAK CURRENT A Ip DRAIN CURRENT A Ip DRAIN CURRENT A 1000 100 50 500 100 10 LIN THIS REGION 105 TRANSCONDUCTANCE L MAY LIMIT CURRENT FOR TEMPERATURES ABOVE 259C DERATE PEAK CURRENT AS FOLLOWS l 155 A t PULSE WIDTH s FIGURE 4 PEAK CURRENT CAPABILITY Ty MAX RATED AREA MAY BE OPERATION IN THIS LIMITED BY rps oN Vpss MAX 55V 10 100 200 Vps DRAIN TO SOURCE VOLTAGE FIGURE 5 FORWARD BIAS SAFE OPERATING AREA 150 120 90 60 30 PULSE DURATION 80us DUTY CYCLE 0 5 MAX Tc 25 C
8. 0 9 vj 1 45 fcz0 5 m model mmedmod type n vto 3 183 kp 2 is 1e 30 tox 1 LDRAIN m model mstrongmod type n vto 3 66 kp 51 5 is 1e 30 tox 1 DPLCAP 5 DRAIN m model mweakmod type n vto 2 703 kp 8e 3 is 1e 30 tox 1 2 Sw vcsp model 1 1e 5 0 1 von 8 voff 3 10 Sw vcsp model s1bmod ron 1e 5 roff 0 1 von 3 voff 8 RSLC1 RLDRAIN Sw vcsp model s2amod 1e 5 0 1 von 0 voff 5 51 RDBREAK Sw vcsp model s2bmod 16 5 0 1 von 5 voff 0 RSLC2 ISCL 12 RDBODY c ca n12 n8 1 8e 9 c cb n15 n14 1 73e 9 50 DBREAK c cin n6 n8 1 19e 9 p ESG RDRAIN 14 71 d dbody n7 n71 model dbodymod EVTHRES d dbreak n72 n11 model dbreakmod lor 6 d dplcap n10 n5 model dplcapmod LGATE EVTEMP a MWEAK DBODY GATE RGATE 6 iit n8 n17 1 16 Dee 5 18 EBREAK 3 20 I 4MSTRO n2 n5 1 9 RLGATE aD CE I gate n1 n9 1e 9 CIN 8 Soun SOURCE l lsource n7 1e 9 wie o 3 RSOURCE m mmed n16 n8 n8 model mmedmod 1u w 1u RLSOURCE m mstrong n16 n8 n8 model mstrongmod 1u w 10 SiA S2A m mweak n16 n21 n8 n8 model mweakmod 1u w 1u 12 45 15 RBREAK res rbreak n17 n18 1 tcl 1 07e 3 tc2 4 5e 7 B res rdbody n71 n5 3e 3 2 7 3 tc2 7 7 5189 52 RVTEMP res rdbreak n72 n5 1 1e 1 tc1
9. 02 24 99 CA 12 8 1 8e 9 CB 15 14 1 73e 9 LDRAIN CIN 6 8 1 19e 9 DPLCAP 5 dr DRAIN 2 10 DBODY 7 5 DBODYMOD RSLC1 DBREAK 5 11 DBREAKMOD Ei DBREAK DPLCAP 10 5 DPLCAPMOD RSLC2 ESLC T EBREAK 11 7 17 18 58 85 50 a EDS 14 8 5 81 EGS 13 8 6 81 RDRAIN DBODY ESG6 10681 ESG 4 EBREAK EVTHRES 6 21 198 1 EVTHRES P E EVTEMP 20 6 18221 ae MWEAK LGATE EVTEMP GATE RGATE 6 IT 8 17 1 1 0 oats 8 MSTRO LDRAIN 2 5 1e 9 LSOURCE LGATE 1 9 1e 9 CIN 8 SOURCE LSOURCE 7 1 9 7 wie 5 4 K1 LSOURCE LGATE 0 0085 RSOURCE RLSOURCE MMED 16 6 8 8 MMEDMOD 1A 9 spn MSTRO 16 6 8 8 MSTROMOD 12 RBREAK MWEAK 16 21 8 8 MWEAKMOD 13 17 18 RBREAK 17 18 RBREAKMOD 1 5 oS2B RVTEMP RDRAIN 50 16 RDRAINMOD 4 50e 3 13 i RGATE 9 20 1 CA RLDRAIN 2 5 10 RLGATE 37 10 EGS EDS RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e 6 8 RSLC2 5 50 163 22 RSOURCE 8 7 RSOURCEMOD 5 95e 3 RVTHRES RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD 52 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 180 4 MODEL DBODYMOD D IS 1 3e 12 RS 20 003 TRS1 2 7e 3 TRS2 7 7 1 7 9 TT 40e 8 M 0 45 IKF 20 6 MODEL DBREAKMOD D RS 0 1e 1 TRS1 4 4 TRS2 1 55 5 IKF 16 5 MODEL DPLCAPMOD D 1 8 9 IS 16 30 N 1M
10. 3 SABER thermal model HUF75333 CTHERM3 template thermal_model th tl thermal_c th tl ctherm ctherm1 th 6 4 9e 4 ctherm ctherm2 6 5 4 5e 3 RTHERM4 ctherm ctherm3 5 4 6 0e 3 ctherm ctherm4 4 3 8 5e 3 ctherm ctherm5 3 2 1 0e 2 ctherm ctherm6 2 tl 5 0e 2 CTHERM4 rtherm rtherm1 th 6 6 0e 4 rtherm rtherm2 6 5 6 8e 3 RTHERM5 rtherm rtherm3 5 4 3 3e 2 rtherm rtherm4 4 3 9 7e 2 rtherm rtherm5 2 3 3e 1 rtherm rtherm6 2 tl 3 6e 1 5 RTHERM6 CTHERM6 All Intersil semiconductor products are manufactured assembled and tested under ISO9000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site http www intersil com 111 intersil
11. O 263AB variant in tape and reel e g HUF75333S3ST Packaging JEDEC STYLE TO 247 JEDEC TO 220AB SOURCE DRAIN FLANGE JEDEC TO 263AB DRAIN FLANGE GATE SOURCE 103 CAUTION These devices are sensitive to electrostatic discharge follow proper ESD Handling Procedures UltraFET is a trademark of Intersil Corporation PSPICEG is a registered trademark of MicroSim Corporation SABERO is a Copyright of Analogy Inc http www intersil com or 407 727 9207 Copyright Intersil Corporation 1999 HUF75333G3 HUF75333P3 HUF75333S3S Absolute Maximum Ratings Tc 25 C Unless Otherwise Specified Drain to Source Voltage Note 1 Vpss Drain to Gate Voltage Ras 20kQ Note 1 VDGR Gate to Source Voltage sss ee eser d ee kane bea CE ex Ree SUR dre Vas Drain Current Goritinuous Figure 2 err Rer DRE Penh DEN Ip Pulsed Drain IDM Pulsed Avalanche Eas Power Dissipation 2 oa Brea renee aad Pa Papa eed ped d due done Sans Pp Derate Above 25 C iuis estes eno ER pees eke eed qu DT RO e dub ret Operating and Storage Ty TerG Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case for 105
12. p 30V Ip 66A 100 ns Turn On Delay Time td ON a TENUES 12 ns Rise Time tr gt 55 E ns Turn Off Delay Time td OFF p 11 ns Fall Time tf 25 ns Turn Off Time 8 55 ns GATE CHARGE SPECIFICATIONS Total Gate Charge Qg ror 0 20 Vpp 30V 70 85 nC Gate Charge at 10V Vag OV to 10V E im 40 50 nc Threshold Gate Charge QgrH Vas OV to 2V ad us 2 5 3 0 nC Gate to Source Gate Charge Qgs 6 2 nC Reverse Transfer Capacitance 16 nC 104 intersil HUF75333G3 HUF75333P3 HUF75333S3S Electrical Specifications T 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Ves OV 1300 f 1MHz Output Capacitance Coss Figure 12 480 pF Reverse Transfer Capacitance Crss 115 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Reverse Recovery Time ter Isp 66A dlsgp dt 100A us gt 75 ns Reverse Recovered Charge QRR Isp 66A disp dt 100A us 140 nC Typical Performance Curves 12 70 a 1 0 x 60 E E 50 2 os 6 ac 5 0 6 5 _ amp rtc a 0 4 a 20 B 02 10 a 0 0 0 25 50 75 100 125 150 175 25 50 75 10
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