intersil HUF75332G3 HUF75332P3 HUF75332S3S handbook
Contents
1. e 1000 Tc 25 C FOR TEMPERATURES lt ABOVE 25 C DERATE z CURRENT AS FOLLOWS E E zia ps Tc e 150 3 x x Vas 10V ul a 100 B TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 105 104 103 10 107 100 101 t PULSE WIDTH s FIGURE 4 PEAK CURRENT CAPABILITY 500 0 TTTT 500 _ tav L Iag 1 3 RATED BVpss Vpp lt IERzO E tav L R In las R 1 3 RATED BVpss Vpp 1 lt 100 tc 100 E u STARTING TJ 259C g z lt P IN THIS lt _ 1590 AREA MAY STARTING TJ 1509C L LIMITED BY TDS ON VDSS MAX 55V 1 0 001 0 01 0 1 1 10 1 10 100 200 tay TIME IN AVALANCHE ms Vps DRAIN TO SOURCE VOLTAGE V NOTE Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 5 FORWARD BIAS SAFE OPERATING AREA FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 150 150 7 PULSE DURATION 25 C DUTY 0 5 ge 120 E E z 2 90 90 s 175 o o z z 4 60 lt 60 5 5 2 Tc 25 C 0 1 5 3 0 4 5 6 0 7 5 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 7 SATURATION CHARACTERISTICS 27 5 6 0 7 5 Vee GATE TO SOURCE VOLTAGE V FIGURE 8 TRANSFER CHARACTERISTICS 97 intersil HUF75332G3 HUF75332P3 HUF75332S3S Typical Performance Curves continued 2 5 PULSE DURATION 80us DUTY CYCLE 0 5 MAX Ves 10V 62. Turn On Time ton Vpp 30V Ip 60A 100 ns Turn On Delay Time ta ON EE gt 12 ns Rise Time tr 55 ns Turn Off Delay Time td OFF 11 ns Fall Time tr 25 ns Turn Off Time toFF 55 ns GATE CHARGE SPECIFICATIONS Total Gate Charge QgToT Ves 0Vto20V 30 70 85 nG Gate Charge at 10V Vas OV to 10V pis Ein 40 50 nc Threshold Gate Charge QgtH Vas OV to 2V Pd 2 5 3 0 nC Gate to Source Gate Charge Qgs 6 nG Reverse Transfer Capacitance 15 nG 95 intersil HUF75332G3 HUF75332P3 HUF75332S3S Electrical Specifications 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Ves OV 1300 f 1MHz Output Capacitance Coss Figure 12 480 pF Reverse Transfer Capacitance Crss 115 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 60A 1 25 V Reverse Recovery Time trr Isp 60A dlsp dt 100A us gt 75 ns Reverse Recovered Charge Isp 60A dlsp dt 100A us 140 nG Typical Performance Curves 1 2 80 d 10 E lt 60 H 2 08 2 E 0 6 gt 40 2 2 lt o a 0 4 E m 6 8 02 0 0 0 25
3. FIGURE 17 GATE CHARGE WAVEFORM 50 lt PULSE WIDTH FIGURE 19 RESISTIVE SWITCHING WAVEFORMS 99 intersil HUF75332G3 HUF75332P3 HUF75332S3S PSPICE Electrical Model SUBCKT HUF75332 213 rev 17 February 1999 CA 12 8 1 8e 9 CB 15 14 1 73e 9 LDRAIN CIN 6 8 1 19 9 DPLCAP 5 ifr DRAIN o 2 10 DBODY 7 5 DBODYMOD RSLC1 REDRAIN DBREAK 5 11 DBREAKMOD i DBREAK DPLCAP 10 5 DPLCAPMOD RSLC2 ESLC 11 EBREAK 11 7 17 1858 85 50 M EDS 14 8 5 81 EGS 138 6 81 RDRAIN DBODY ESG 61068 1 ESG o EBREAK 1 EVTHRES 621198 1 EVTHRES a EVTEMP 20 6 18 22 1 I MWEAK LGATE EVTEMP care ROME IT 8 17 1 1e 8 FC MSTRO LDRAIN 2 5 1e 9 LSOURCE LGATE 1 9 1e 9 CIN 8 OURCE LSOURCE 3 7 1e 9 7 3 K1 LSOURCE LGATE 0 0085 RSOURCE RLSOURCE MMED 16 6 8 8 MMEDMOD iude desk MSTRO 16 6 8 8 MSTROMOD an RBREAK MWEAK 16 21 8 8 MWEAKMOD u 17 18 RBREAK 17 18 RBREAKMOD 1 S1B q o S2B RVTEMP RDRAIN 50 16 RDRAINMOD 4 5e 3 13 19 RGATE 9 201 3 CA 14 RLDRAIN 2 5 10 A RLGATE 1 9 10 EDS ESAN RLSOURCE 37 10 RSLC1 5 51 RSLCMOD 1e 6 5 8 RSLC2 5 50 1e3 22 RSOURCE 8 7 RSOURCEMOD 5 95 3 RVTHRES RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 SIAMOD S1B 13 12 13 8 S1BMOD 52 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 180 4 6 MODEL DB
4. Simulation Models Temperature Compensated PSPICE and SABER Models SPICE and SABER Thermal Impedance Models Available on the WEB at www intersil com Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature TB334 Guidelines for Soldering Surface Mount Components to PC Boards Symbol D G S JEDEC TO 220AB SOURCE DRAIN GATE DRAIN FLANGE JEDEC TO 263AB GATE SOURCE DRAIN FLANGE 94 CAUTION These devices are sensitive to electrostatic discharge follow proper ESD Handling Procedures UltraFET is a trademark of Intersil Corporation PSPICE is a registered trademark of MicroSim Corporation SABERO is a Copyright of Analogy Inc http www intersil com or 407 727 9207 Copyright Intersil Corporation 1999 HUF75332G3 HUF75332P3 HUF75332S3S Absolute Maximum Ratings 25 C Unless Otherwise Specified UNITS Drain to Source Voltage Note 1 Vpss 55 V Drain to Gate Voltage Ras 20kQ Note 1 VpGR 55 V Gate to Source Voltage sss ee eser d ayasa CE qasaq Vas 20 V Drain Current Goritinuous Figure 2 err Rer DRE Penh DEN PER EE Ip 60 A Pulsed Drain IDM Figure 4 Pulsed Avalanche 0 1 EAS Figures 6 14 15 Power Dissipation e o
5. n51 2n50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 180 4 6 101 intersil HUF75332G3 HUF75332P3 HUF75332S3S SPICE Thermal Model REV 11February 1999 th JUNCTION HUF75332 CTHERM1 th 6 4 00e 3 CTHERM2 6 5 7 00e 3 CTHERNG 5 4 7 50e 3 RTHERM1 CTHERM4 4 3 8 00e 3 CTHERMS 3 2 1 85e 2 CTHERM6 2 tl 12 55 CTHERM1 RTHERM1 th 6 7 09e 3 2 6 5 1 77e 2 RTHERM2 RTHERMS 5 4 4 97 2 RTHERMA 4 3 2 79e 1 5 3 2 4 21e 1 RTHERM6 2 tl 5 58e 2 CTHERM2 SABER Thermal Model RTHERM3 SABER thermal model HUF75332 CTHERM3 template thermal_model th tl thermal_c th tl ctherm ctherm1 th 6 4 00e 3 ctherm ctherm2 6 5 7 00e 3 RTHERM4 ctherm ctherm3 5 4 7 50e 3 ctherm ctherm4 4 3 8 00e 3 ctherm ctherm5 3 2 1 85e 2 ctherm ctherm6 2 tl 12 55 CTHERM4 rtherm rtherm1 th 6 7 09e 3 rtherm rtherm2 6 5 1 77e 2 RTHERM5 rtherm rtherm3 5 4 4 97e 2 rtherm rtherm4 4 3 2 79e 1 rtherm rtherm5 2 4 21e 1 rtherm rtherm6 2 tl 5 58e 2 5 RTHERM6 CTHERM6 All Intersil semiconductor products are manufactured assembled and tested under 1509000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify
6. 1 LSOURCE CIN 8 a SOURCE L ldrain n2 n5 1 0 9 SE o 3 l lgate n1 n9 1 0e 9 RSOURCE l source n3 n7 1 0e 9 RLSOURCE k Kl i I lgate i I lsource I I lgate 1 1 0 0085 S1A 952 12 RBREAK i3 14 is 17 18 m mmed n16 n6 n8 n8 model mmedmod 1u w lu 8 13 m mstrong n16 n6 n8 n8 model mstrongmod 1u 1 m mweak n16 n21 n8 n8 model mweakmod lu 1 S1B o 18 952 CB 1 A 19 res rbreak n17 n18 1 tcl 1 05e 3 tc2 4 5e 7 14 4 res rdbody n71 n5 3 0e 3 tc1 2 7e 3 tc2 7 0e 7 VBAT res rdbreak n72 n5 1 71e 2 tc1 4 0e 4 tc2 1 55e 5 EGS EDS res rdrain n50 n16 4 5e 3 tc1 1 16e 2 tc2 1 7e 5 8 res rgate n9 n20 1 3 22 res rldrain n2 n5 10 RVTHRES res rlgate n1 n9 10 res rlsource n3 n7 10 res rsic1 n5 n51 1 6 3 96e 3 tc2 2 7e 6 res rsic2 n5 n50 1e3 res rsource n8 n7 5 95e 3 tc1 1e 3 tc2 1e 5 res rvtemp n18 n19 1 tcl 2 75 3 tc2 5 0e 7 res rvthres n22 n8 1 tc1 2 8e 3 tc2 1 0e 5 Spe ebreak n11 n7 n17 n18 58 85 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 Spe evtemp n20 n6 n18 n22 1 Spe evthres n6 n21 n19 n8 1 Sw vcsp s1a n6 n12 n13 n8 model s1amod sw vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod Sw vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i
7. 1u w lu 8 13 m mstrong n16 n6 n8 n8 model mstrongmod 1u 1 m mweak n16 n21 n8 n8 model mweakmod lu 1 S1B o 18 952 CB 1 A 19 res rbreak n17 n18 1 tcl 1 05e 3 tc2 4 5e 7 14 4 res rdbody n71 n5 3 0e 3 tc1 2 7e 3 tc2 7 0e 7 VBAT res rdbreak n72 n5 1 71e 2 tc1 4 0e 4 tc2 1 55e 5 EGS EDS res rdrain n50 n16 4 5e 3 tc1 1 16e 2 tc2 1 7e 5 8 res rgate n9 n20 1 3 22 res rldrain n2 n5 10 RVTHRES res rlgate n1 n9 10 res rlsource n3 n7 10 res rsic1 n5 n51 1 6 3 96e 3 tc2 2 7e 6 res rsic2 n5 n50 1e3 res rsource n8 n7 5 95e 3 tc1 1e 3 tc2 1e 5 res rvtemp n18 n19 1 tcl 2 75 3 tc2 5 0e 7 res rvthres n22 n8 1 tc1 2 8e 3 tc2 1 0e 5 Spe ebreak n11 n7 n17 n18 58 85 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 Spe evtemp n20 n6 n18 n22 1 Spe evthres n6 n21 n19 n8 1 Sw vcsp s1a n6 n12 n13 n8 model s1amod sw vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod Sw vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 180 4 6 101 intersil HUF75332G3 HUF75332P3 HUF75332S3S SPICE Thermal Model REV 11February 1999 th JUNCTION HUF75332 CTHERM1 th 6 4 00e 3 CTHERM2 6 5
8. 50 75 100 125 150 175 25 50 75 100 125 150 175 Tc CASE TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE Tc CASE TEMPERATURE C FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE 2 DUTY CYCLE DESCENDING ORDER 1L 0 E 0 2 0 1 Qo 2L Foo i 1 Ng L 0 02 1 a ul 0 01 2 401 J ti 1 ui t NOTES DUTY FACTOR D ty to SINGLE PULSE PEAK Ty X Zouc Tc 0 01 1075 1074 103 10 107 100 10 t RECTANGULAR PULSE DURATION s FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 96 intersil HUF75332G3 HUF75332P3 HUF75332S3S Typical Performance Curves continued PULSE DURATION 80us DUTY CYCLE 0 5 MAX e 1000 Tc 25 C FOR TEMPERATURES lt ABOVE 25 C DERATE z CURRENT AS FOLLOWS E E zia ps Tc e 150 3 x x Vas 10V ul a 100 B TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 105 104 103 10
9. 7 00e 3 CTHERNG 5 4 7 50e 3 RTHERM1 CTHERM4 4 3 8 00e 3 CTHERMS 3 2 1 85e 2 CTHERM6 2 tl 12 55 CTHERM1 RTHERM1 th 6 7 09e 3 2 6 5 1 77e 2 RTHERM2 RTHERMS 5 4 4 97 2 RTHERMA 4 3 2 79e 1 5 3 2 4 21e 1 RTHERM6 2 tl 5 58e 2 CTHERM2 SABER Thermal Model RTHERM3 SABER thermal model HUF75332 CTHERM3 template thermal_model th tl thermal_c th tl ctherm ctherm1 th 6 4 00e 3 ctherm ctherm2 6 5 7 00e 3 RTHERM4 ctherm ctherm3 5 4 7 50e 3 ctherm ctherm4 4 3 8 00e 3 ctherm ctherm5 3 2 1 85e 2 ctherm ctherm6 2 tl 12 55 CTHERM4 rtherm rtherm1 th 6 7 09e 3 rtherm rtherm2 6 5 1 77e 2 RTHERM5 rtherm rtherm3 5 4 4 97e 2 rtherm rtherm4 4 3 2 79e 1 rtherm rtherm5 2 4 21e 1 rtherm rtherm6 2 tl 5 58e 2 5 RTHERM6 CTHERM6 All Intersil semiconductor products are manufactured assembled and tested under 1509000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which
10. Recovery Time trr Isp 60A dlsp dt 100A us gt 75 ns Reverse Recovered Charge Isp 60A dlsp dt 100A us 140 nG Typical Performance Curves 1 2 80 d 10 E lt 60 H 2 08 2 E 0 6 gt 40 2 2 lt o a 0 4 E m 6 8 02 0 0 0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 Tc CASE TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE Tc CASE TEMPERATURE C FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE 2 DUTY CYCLE DESCENDING ORDER 1L 0 E 0 2 0 1 Qo 2L Foo i 1 Ng L 0 02 1 a ul 0 01 2 401 J ti 1 ui t NOTES DUTY FACTOR D ty to SINGLE PULSE PEAK Ty X Zouc Tc 0 01 1075 1074 103 10 107 100 10 t RECTANGULAR PULSE DURATION s FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 96 intersil HUF75332G3 HUF75332P3 HUF75332S3S Typical Performance Curves continued PULSE DURATION 80us DUTY CYCLE 0 5 MAX
11. may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site http www intersil com 102 intersil intersil Data Sheet HUF75332G3 HUF75332P3 HUF 75332S3S June 1999 File Number 4489 3 60A 55V 0 019 Ohm N Channel UltraFET Power MOSFETs These N Channel power MOSFETs are manufactured using the EN innovative UltraFET process This advanced process technology achieves the lowest possible on resistance per silicon area resulting in outstanding performance This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge It was designed for use in applications where power efficiency is important such as switching regulators switching converters motor drivers relay drivers low voltage bus switches and power management in portable and battery operated products Formerly developmental type TA75332 Ordering Information PART NUMBER PACKAGE BRAND HUF75332G3 TO 247 75332G HUF75332P3 TO 220AB 75332P HUF7533283S TO 263AB 753328 NOTE When ordering use the entire part number Add the suffix T to obtain the TO 263AB variant in tape and reel e g HUF75332S3ST Packaging JEDEC STYLE TO 247 SOURCE Features 60A 55V
12. 0A NORMALIZED DRAIN SOURCE ON RESISTANCE 5 amp 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1 2 Ip 250 A NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE 0 9 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 1 2 T T Ves Vps 2504A NORMALIZED GATE THRESHOLD VOLTAGE 80 40 0 40 80 120 160 200 TJ JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2000 T T Ves OV f 1MHz Ciss CGs CGp Cnss Coss Cps Cap 4 a e 1000 C CAPACITANCE pF 500 0 10 20 30 40 50 60 DRAIN TO SOURCE VOLTAGE V FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 WAVEFORMS IN DESCENDING ORDER Ip 60A Vas GATE TO SOURCE VOLTAGE V 0 10 20 lp 45A Ip 30A Ip 15A 40 50 60 Qg GATE nC NOTE Refer to Intersil Application Notes AN7254 and AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 98 intersil HUF75332G3 HUF75332P3 HUF75332S3S Test Circuits and Waveforms Vps VARY tp TO OBTAIN REQUIRED PEAK lAs
13. 107 100 101 t PULSE WIDTH s FIGURE 4 PEAK CURRENT CAPABILITY 500 0 TTTT 500 _ tav L Iag 1 3 RATED BVpss Vpp lt IERzO E tav L R In las R 1 3 RATED BVpss Vpp 1 lt 100 tc 100 E u STARTING TJ 259C g z lt P IN THIS lt _ 1590 AREA MAY STARTING TJ 1509C L LIMITED BY TDS ON VDSS MAX 55V 1 0 001 0 01 0 1 1 10 1 10 100 200 tay TIME IN AVALANCHE ms Vps DRAIN TO SOURCE VOLTAGE V NOTE Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 5 FORWARD BIAS SAFE OPERATING AREA FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 150 150 7 PULSE DURATION 25 C DUTY 0 5 ge 120 E E z 2 90 90 s 175 o o z z 4 60 lt 60 5 5 2 Tc 25 C 0 1 5 3 0 4 5 6 0 7 5 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 7 SATURATION CHARACTERISTICS 27 5 6 0 7 5 Vee GATE TO SOURCE VOLTAGE V FIGURE 8 TRANSFER CHARACTERISTICS 97 intersil HUF75332G3 HUF75332P3 HUF75332S3S Typical Performance Curves continued 2 5 PULSE DURATION 80us DUTY CYCLE 0 5 MAX Ves 10V 60A NORMALIZED DRAIN SOURCE ON RESISTANCE 5 amp 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1 2 Ip 250 A
14. 8 7 RSOURCEMOD 5 95 3 RVTHRES RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 SIAMOD S1B 13 12 13 8 S1BMOD 52 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 180 4 6 MODEL DBODYMOD D IS 1 3e 12 RS 3 0e 3 IKF 20 XTI 2 6 TRS1 2 7e 3 TRS2 7 0 7 1 7e 9 TT 4 0 8 M 0 45 vj 0 75 MODEL DBREAKMOD D RS 1 71e 2 IKF 1 0e 5 TRS1 4 0e 4 TRS2 1 55e 5 MODEL DPLCAPMOD D CJO 1 8e 9 IS 1e 30 N 1M 0 9 vj 1 45 MODEL MMEDMOD NMOS VTO 3 183 KP 2 IS 1 30 N 10 TOX 1L 10 W 1u RG 1 3 MODEL MSTROMOD NMOS VTO 3 66 KP 51 5 IS 1e 30 N 10 TOX 1 L 1u W lu MODEL MWEAKMOD NMOS VTO 2 703 KP 0 008 IS 1e 30 N 10 TOX 1 L 1u W lu RG 13 MODEL RBREAKMOD RES TC1 1 05e 3 TC2 4 5e 7 MODEL RDRAINMOD RES TC1 1 16e 2 TC2 1 7e 5 MODEL RSLCMOD RES TC1 3 96e 3 2 2 7e 6 MODEL RSOURCEMOD RES TC1 1e 3 TC2 1 5 MODEL RVTHRESMOD RES TC1 2 8e 3 TC2 1 0e 5 MODEL RVTEMPMOD RES TC1 2 75e 3 2 5 0e 7 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH MODEL S2AMOD VSWITCH MODEL S2BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 8 VOFF 3 RON 1e 5 ROFF 0 1 VON 3 VOFF 8 RON 1e 5 ROFF 0 1 VON 0 VOFF 0 5 RON 1e 5 ROFF 0 1 VON 0 5 VOFF 0 ENDS NOTE For further discussion of the PSPICE model consult A New PSPICE Sub
15. 99 template huf75332 n2 n1 n3 electrical n2 n1 n3 var i iscl d model dbodymod is 1 3e 12 xti 6 cjo 1 7e 9 tt 4 0e 8 m 0 45 vj 0 75 d model dbreakmod LDRAIN d model dplcapmod cjo 1 8e 9 is 1e 30 m 0 9 vj 1 45 DPLCAP 5 DRAIN m model mmedmod type n vto 3 183 kp 2 is 1e 30 tox 1 10 W 2 m model mstrongmod type n vto 3 66 kp 51 5 is 1e 30 tox 1 RLDRAIN m model mweakmod type n vto 2 703 kp 8 0e 3 is 1e 30 tox 1 RSLC1 sw_vcsp model 1 ron 1e 5 roff 0 1 von 8 voff 3 51 RDBREAK sw_vcsp model s1bmod ron 1e 5 roff 0 1 von 3 voff 8 RSLC2 sw_vcsp model s2amod ron 1e 5 roff 0 1 von 0 voff 0 5 RDBODY sw_vcsp model s2bmod ron 1e 5 roff 0 1 von 0 5 voff 0 I 50 DBREAK c ca n12 n8 1 8e 9 71 c cb n15 n14 1 73e 9 ESG RRRA 11 c cin n6 n8 1 19e 9 EVTHRES 21 76 MWEAK d dbody n7 n71 model dbodymod LGATE EVTEMP DBODY d dbreak n72 n11 model dbreakmod GATE RGATE 6 MED EBREAK d dplcap n10 n5 model dplcapmod I 9 20 3 lM n RLGATE HCIMSTRO i it n8 n17 1 LSOURCE CIN 8 a SOURCE L ldrain n2 n5 1 0 9 SE o 3 l lgate n1 n9 1 0e 9 RSOURCE l source n3 n7 1 0e 9 RLSOURCE k Kl i I lgate i I lsource I I lgate 1 1 0 0085 S1A 952 12 RBREAK i3 14 is 17 18 m mmed n16 n6 n8 n8 model mmedmod
16. ATi KU HSS E ES Data Sheet HUF75332G3 HUF75332P3 HUF 75332S3S June 1999 File Number 4489 3 60A 55V 0 019 Ohm N Channel UltraFET Power MOSFETs These N Channel power MOSFETs are manufactured using the EN innovative UltraFET process This advanced process technology achieves the lowest possible on resistance per silicon area resulting in outstanding performance This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge It was designed for use in applications where power efficiency is important such as switching regulators switching converters motor drivers relay drivers low voltage bus switches and power management in portable and battery operated products Features 60A 55V Simulation Models Temperature Compensated PSPICE and SABER Models SPICE and SABER Thermal Impedance Models Available on the WEB at www intersil com Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature TB334 Guidelines for Soldering Surface Mount Components to PC Boards Symbol Formerly developmental type TA75332 D Ordering Information PART NUMBER PACKAGE BRAND G HUF75332G3 TO 247 75332G HUF75332P3 TO 220AB 75332P S HUF753328S3S TO 263AB 753328 NOTE When ordering use the entire part number Add the suffix T to obtain the TO 263AB variant in tape and re
17. Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 100 intersil HUF75332G3 HUF75332P3 HUF75332S3S SABER Electrical Model REV 17 February 1999 template huf75332 n2 n1 n3 electrical n2 n1 n3 var i iscl d model dbodymod is 1 3e 12 xti 6 cjo 1 7e 9 tt 4 0e 8 m 0 45 vj 0 75 d model dbreakmod LDRAIN d model dplcapmod cjo 1 8e 9 is 1e 30 m 0 9 vj 1 45 DPLCAP 5 DRAIN m model mmedmod type n vto 3 183 kp 2 is 1e 30 tox 1 10 W 2 m model mstrongmod type n vto 3 66 kp 51 5 is 1e 30 tox 1 RLDRAIN m model mweakmod type n vto 2 703 kp 8 0e 3 is 1e 30 tox 1 RSLC1 sw_vcsp model 1 ron 1e 5 roff 0 1 von 8 voff 3 51 RDBREAK sw_vcsp model s1bmod ron 1e 5 roff 0 1 von 3 voff 8 RSLC2 sw_vcsp model s2amod ron 1e 5 roff 0 1 von 0 voff 0 5 RDBODY sw_vcsp model s2bmod ron 1e 5 roff 0 1 von 0 5 voff 0 I 50 DBREAK c ca n12 n8 1 8e 9 71 c cb n15 n14 1 73e 9 ESG RRRA 11 c cin n6 n8 1 19e 9 EVTHRES 21 76 MWEAK d dbody n7 n71 model dbodymod LGATE EVTEMP DBODY d dbreak n72 n11 model dbreakmod GATE RGATE 6 MED EBREAK d dplcap n10 n5 model dplcapmod I 9 20 3 lM n RLGATE HCIMSTRO i it n8 n17
18. NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE 0 9 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 1 2 T T Ves Vps 2504A NORMALIZED GATE THRESHOLD VOLTAGE 80 40 0 40 80 120 160 200 TJ JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2000 T T Ves OV f 1MHz Ciss CGs CGp Cnss Coss Cps Cap 4 a e 1000 C CAPACITANCE pF 500 0 10 20 30 40 50 60 DRAIN TO SOURCE VOLTAGE V FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 WAVEFORMS IN DESCENDING ORDER Ip 60A Vas GATE TO SOURCE VOLTAGE V 0 10 20 lp 45A Ip 30A Ip 15A 40 50 60 Qg GATE nC NOTE Refer to Intersil Application Notes AN7254 and AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 98 intersil HUF75332G3 HUF75332P3 HUF75332S3S Test Circuits and Waveforms Vps VARY tp TO OBTAIN REQUIRED PEAK lAs Vas ov FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT DUT IG REF FIGURE 16 GATE CHARGE TEST CIRCUIT an FIGURE 18 SWITCHING TIME TEST CIRCUIT FIGURE 15 UNCLAMPED ENERGY WAVEFORMS 12 Ig REF 0
19. ODYMOD D IS 1 3e 12 RS 3 0e 3 IKF 20 XTI 2 6 TRS1 2 7e 3 TRS2 7 0 7 1 7e 9 TT 4 0 8 M 0 45 vj 0 75 MODEL DBREAKMOD D RS 1 71e 2 IKF 1 0e 5 TRS1 4 0e 4 TRS2 1 55e 5 MODEL DPLCAPMOD D CJO 1 8e 9 IS 1e 30 N 1M 0 9 vj 1 45 MODEL MMEDMOD NMOS VTO 3 183 KP 2 IS 1 30 N 10 TOX 1L 10 W 1u RG 1 3 MODEL MSTROMOD NMOS VTO 3 66 KP 51 5 IS 1e 30 N 10 TOX 1 L 1u W lu MODEL MWEAKMOD NMOS VTO 2 703 KP 0 008 IS 1e 30 N 10 TOX 1 L 1u W lu RG 13 MODEL RBREAKMOD RES TC1 1 05e 3 TC2 4 5e 7 MODEL RDRAINMOD RES TC1 1 16e 2 TC2 1 7e 5 MODEL RSLCMOD RES TC1 3 96e 3 2 2 7e 6 MODEL RSOURCEMOD RES TC1 1e 3 TC2 1 5 MODEL RVTHRESMOD RES TC1 2 8e 3 TC2 1 0e 5 MODEL RVTEMPMOD RES TC1 2 75e 3 2 5 0e 7 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH MODEL S2AMOD VSWITCH MODEL S2BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 8 VOFF 3 RON 1e 5 ROFF 0 1 VON 3 VOFF 8 RON 1e 5 ROFF 0 1 VON 0 VOFF 0 5 RON 1e 5 ROFF 0 1 VON 0 5 VOFF 0 ENDS NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 100 intersil HUF75332G3 HUF75332P3 HUF75332S3S SABER Electrical Model REV 17 February 19
20. Vas ov FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT DUT IG REF FIGURE 16 GATE CHARGE TEST CIRCUIT an FIGURE 18 SWITCHING TIME TEST CIRCUIT FIGURE 15 UNCLAMPED ENERGY WAVEFORMS 12 Ig REF 0 FIGURE 17 GATE CHARGE WAVEFORM 50 lt PULSE WIDTH FIGURE 19 RESISTIVE SWITCHING WAVEFORMS 99 intersil HUF75332G3 HUF75332P3 HUF75332S3S PSPICE Electrical Model SUBCKT HUF75332 213 rev 17 February 1999 CA 12 8 1 8e 9 CB 15 14 1 73e 9 LDRAIN CIN 6 8 1 19 9 DPLCAP 5 ifr DRAIN o 2 10 DBODY 7 5 DBODYMOD RSLC1 REDRAIN DBREAK 5 11 DBREAKMOD i DBREAK DPLCAP 10 5 DPLCAPMOD RSLC2 ESLC 11 EBREAK 11 7 17 1858 85 50 M EDS 14 8 5 81 EGS 138 6 81 RDRAIN DBODY ESG 61068 1 ESG o EBREAK 1 EVTHRES 621198 1 EVTHRES a EVTEMP 20 6 18 22 1 I MWEAK LGATE EVTEMP care ROME IT 8 17 1 1e 8 FC MSTRO LDRAIN 2 5 1e 9 LSOURCE LGATE 1 9 1e 9 CIN 8 OURCE LSOURCE 3 7 1e 9 7 3 K1 LSOURCE LGATE 0 0085 RSOURCE RLSOURCE MMED 16 6 8 8 MMEDMOD iude desk MSTRO 16 6 8 8 MSTROMOD an RBREAK MWEAK 16 21 8 8 MWEAKMOD u 17 18 RBREAK 17 18 RBREAKMOD 1 S1B q o S2B RVTEMP RDRAIN 50 16 RDRAINMOD 4 5e 3 13 19 RGATE 9 201 3 CA 14 RLDRAIN 2 5 10 A RLGATE 1 9 10 EDS ESAN RLSOURCE 37 10 RSLC1 5 51 RSLCMOD 1e 6 5 8 RSLC2 5 50 1e3 22 RSOURCE
21. a d Pa Papa eed ped d due done Pp 145 w Derate Above 25 C iwc estes erase pees eke kausa e dub ret edd c ar 0 97 wc Operating and Storage Temperature Ty TstG 55 to 175 oc Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case for 106 TL 300 9c Package Body for 10s See Techbrief 334 Tpkg 260 96 CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 Ty 259C to 150 C Electrical Specifications 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip 250 Vag Figure 11 55 V Zero Gate Voltage Drain Current Ipss Vps 50V Ves OV 1 Vps 45V Vag OV Tc 150 C 250 Gate to Source Leakage Current lass Vas 20V 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH Vas Vos Ip 250HA Figure 10 2 2 4 Drain to Source On Resistance 10 60A Vag 10V Figure 9 0 016 0 019 THERMAL SPECIFICATIONS The
22. el e g HUF75332S3ST Packaging JEDEC STYLE TO 247 JEDEC TO 220AB SOURCE SOURCE _ DRAIN GATE DRAIN FLANGE JEDEC TO 263AB DRAIN FLANGE GATE SOURCE 94 CAUTION These devices are sensitive to electrostatic discharge follow proper ESD Handling Procedures UltraFETTM is a trademark of Intersil Corporation PSPICE is a registered trademark of MicroSim Corporation SABERO is a Copyright of Analogy Inc http www intersil com or 407 727 9207 Copyright Intersil Corporation 1999 HUF75332G3 HUF75332P3 HUF75332S3S Absolute Maximum Ratings 25 C Unless Otherwise Specified UNITS Drain to Source Voltage Note 1 Vpss 55 V Drain to Gate Voltage Ras 20kQ Note 1 VpGR 55 V Gate to Source Voltage sss ee eser d ayasa CE qasaq Vas 20 V Drain Current Goritinuous Figure 2 err Rer DRE Penh DEN PER EE Ip 60 A Pulsed Drain IDM Figure 4 Pulsed Avalanche 0 1 EAS Figures 6 14 15 Power Dissipation e oa d Pa Papa eed ped d due done Pp 145 w Derate Above 25 C iwc estes erase pees eke kausa e dub ret edd c ar 0 97 wc Operating and Storage Temperature Ty TstG 55 to 175 oc Maximum Temperature f
23. or Soldering Leads at 0 063in 1 6mm from Case for 106 TL 300 9c Package Body for 10s See Techbrief 334 Tpkg 260 96 CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 Ty 259C to 150 C Electrical Specifications 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip 250 Vag Figure 11 55 V Zero Gate Voltage Drain Current Ipss Vps 50V Ves OV 1 Vps 45V Vag OV Tc 150 C 250 Gate to Source Leakage Current lass Vas 20V 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH Vas Vos Ip 250HA Figure 10 2 2 4 Drain to Source On Resistance 10 60A Vag 10V Figure 9 0 016 0 019 THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Figure 3 1 03 Thermal Resistance Junction to Ambient RoJA TO 247 30 90 W TO 220 TO 263 62 C W SWITCHING SPECIFICATIONS Vcs 10V
24. rmal Resistance Junction to Case Figure 3 1 03 Thermal Resistance Junction to Ambient RoJA TO 247 30 90 W TO 220 TO 263 62 C W SWITCHING SPECIFICATIONS Vcs 10V Turn On Time ton Vpp 30V Ip 60A 100 ns Turn On Delay Time ta ON EE gt 12 ns Rise Time tr 55 ns Turn Off Delay Time td OFF 11 ns Fall Time tr 25 ns Turn Off Time toFF 55 ns GATE CHARGE SPECIFICATIONS Total Gate Charge QgToT Ves 0Vto20V 30 70 85 nG Gate Charge at 10V Vas OV to 10V pis Ein 40 50 nc Threshold Gate Charge QgtH Vas OV to 2V Pd 2 5 3 0 nC Gate to Source Gate Charge Qgs 6 nG Reverse Transfer Capacitance 15 nG 95 intersil HUF75332G3 HUF75332P3 HUF75332S3S Electrical Specifications 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Ves OV 1300 f 1MHz Output Capacitance Coss Figure 12 480 pF Reverse Transfer Capacitance Crss 115 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 60A 1 25 V Reverse
25. that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site http www intersil com 102 intersil
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