intersil HUF75329D3 HUF75329D3S handbook
Contents
1. Tpkg 55 55 20 20 Figure 4 Figures 6 14 15 128 0 86 55 to 175 300 260 UNITS CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 Ty 25 C to 150 C Electrical Specifications 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip 250A Vas OV Figure 11 55 V Zero Gate Voltage Drain Current Ipss Vps 50V Vas OV z 1 Vps 45V Vas OV 150 C 250 Gate to Source Leakage Current lass Vas 20V gt 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH Vas Vps Ip 250 Figure 10 2 x 4 Drain to Source On Resistance 10 20A Vag 10V Figure 9 s 0 022 0 026 Q THERMAL SPECIFICATIONS Thermal Resistance Junction to Case ReJc Figure 3 1 17 C W Thermal Resistance Junction to Ambient ReJA TO 251 TO 252 100 C W SWITCHING SPECIFICATIONS Vcs 10V Turn On Time ton Vpp 30V Ip 20A 60 ns Turn On Del2. 1e 3 tc1 8 04e 2 tc2 1 37e 4 8 res rgate 9 20 1 52 22 res ridrain n2 n5 10 RVTHRES res rlgate n1 n9 26 9 res rlsource n3 n7 28 6 res rsic1 n5 n51 1 6 4 83e 3 tc2 1 16e 6 res rsic2 n5 n50 1e3 res rsource n8 n7 13 85e 3 tc1 0 tc2 2 0 res rvtemp n18 n19 1 tcl 1 35 3 tc2 1 16e 6 res rvthres n22 n8 1 tc1 3 43e 3 tc2 1 63e 5 Spe ebreak n11 n7 n17 n18 58 13 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 Spe evtemp n20 n6 n18 n22 1 Spe evthres n6 n21 n19 n8 1 Sw vcsp s1a n6 n12 n13 n8 model s1amod sw vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 135 3 5 83 intersil HUF75329D3 HUF75329D3S SPICE Thermal Model REV 23 February 1999 th JUNCTION HUF75329D CTHERM1 th 6 2 80e 3 CTHERM2 6 5 1 00 2 CTHERNG 5 4 6 80e 3 RTHERM1 CTHERM4 4 3 7 00e 3 CTHERMS 3 2 1 60e 2 CTHERM6 2 tl 15 55 CTHERM1 RTHERM1 th 6 7 94 3 2 6 5 1 98e 2 RTHERM2 RTHERMS 5 4 5 57 2 RTHERMA 4 3 3 13e 1 5 3 2 4 71e 1 RTHERM6 2 tl 6 26e 2 CTHERM2 SABER Thermal Model RTHERM3 SABER thermal model HUF75329D template thermal_model th tl thermal_c th tl ctherm ctherm1 th
3. 0 6 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 1500 Ves OV f 1MHz Ciss Cap 1200 Crss Coss Cps Cap 900 600 C CAPACITANCE pF 300 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE WAVEFORMS IN DESCENDING ORDER Vas GATE TO SOURCE VOLTAGE V 0 5 10 Ip 20 7 Ip 12 5A Ip 5A 20 25 30 35 Qg GATE CHARGE nC NOTE Refer to Intersil Application Notes AN7254 and AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 80 intersil HUF75329D3 HUF75329D3S Test Circuits and Waveforms Vps VARY tp TO OBTAIN REQUIRED PEAK lAs Vas ov FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT DUT IG REF FIGURE 16 GATE CHARGE TEST CIRCUIT DUT FIGURE 18 SWITCHING TIME TEST CIRCUIT FIGURE 15 UNCLAMPED ENERGY WAVEFORMS 24 E ak Ig REF 0 FIGURE 17 GATE CHARGE WAVEFORM 50 PULSE WIDTH FIGURE 19 RESISTIVE SWITCHING WAVEFORMS 81 intersil HUF75329D3 HUF75329D3S PSPICE Electrical Model SUBCKT HUF75329D 213 rev 6 19 97 12 8 1 72e 9 CB 15 14 1 52e 9 LDRAIN CIN 6 89 61e 10 DPLCAP 5 p DRAIN o2 10 DBODY 7 5 DBODYMOD RSLC1 P DRAIN DBR
4. Vpp 1 2 100 c 5 o STARTING Ty 25 C 9 10 10 3 STARTING Ty 150 C OPERATION IN THIS 5 AREA MAY LIMITED BY rps oN 5 55 1 1 0 01 0 1 1 10 100 tay TIME IN AVALANCHE ms DRAIN TO SOURCE VOLTAGE V NOTE Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 5 FORWARD BIAS SAFE OPERATING AREA FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 100 100 PULSE DURATION 80us DUTY CYCLE 0 5 MAX 80 80 z 60 60 tc 2 7 tc a 20 PULSE DURATION 80us B 20 9p DUTY CYCLE 0 5 MAX Tc 25 C 0 l 0 0 1 2 3 4 5 0 1 5 3 0 4 5 6 0 7 5 Vps DRAIN SOURCE VOLTAGE V Vas GATE TO SOURCE VOLTAGE V FIGURE 7 SATURATION CHARACTERISTICS FIGURE 8 TRANSFER CHARACTERISTICS 79 intersil HUF75329D3 HUF75329D3S Typical Performance Curves continued PULSE DURATION 80 6 DUTY CYCLE 0 5 MAX Vas 10V Ip 20A ON RESISTANCE NORMALIZED DRAIN TO SOURCE 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1 2 Ip 250A 1 1 1 0 0 9 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 10 1 2 T T T Ves Vps lp 2504A 1 0 0 8 NORMALIZED GATE THRESHOLD VOLTAGE
5. 0 175 CASE TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE Tc CASE TEMPERATURE C CASE TEMPERATURE T TTTTT T T T DUTY CYCLE DESCENDIN 0 5 ORDER Zogc NORMALIZED THERMAL IMPEDANCE t RECTANGULAR PULSE DURATION s FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE DUTY FACTOR D ty to PEAK Ty X Zeuc Tc FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs 10 78 intersil HUF75329D3 HUF75329D3S Typical Performance Curves continued Ip DRAIN CURRENT A Ip DRAIN CURRENT A 1000 I L I I FOR TEMPERATURES 1 ABOVE 25 C DERATE 2 CURRENT AS FOLLOWS 1 2 ac a 3 100 lt a L B TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 I 1075 1074 101 t PULSE WIDTH FIGURE 4 PEAK CURRENT CAPABILITY 2 500 rr 0020 Ty MAX RATED tav L Iag 1 3 RATED BVpss Vpp 100 0 ha tav L R In Ias R 1 3 RATED BVpss
6. 0 IS 1e 30 N 10 TOX 2 1 L 1u W 1u MODEL MWEAKMOD NMOS VTO 2 91 KP 0 06 IS 1e 30 N 10 TOX 1L 1u W 1u RG 15 2 RS 0 1 MODEL RBREAKMOD RES TC1 1 05e 3 TC2 1 94e 7 MODEL RDRAINMOD RES TC1 8 04e 2 TC2 1 37e 4 MODEL RSLCMOD RES TC1 4 83e 3 TC2 1 16 6 MODEL RSOURCEMOD RES TC1 0 TC2 0 MODEL RVTHRESMOD RES TC 3 43e 3 TC2 1 63e 5 MODEL RVTEMPMOD RES TC1 1 35e 3 2 1 16 6 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH MODEL S2AMOD VSWITCH MODEL S2BMOD VSWITCH RON 1e 5 ROFF 2 0 1 VON 7 90 VOFF 4 90 RON 1e 5 ROFF 2 0 1 VON 4 90 VOFF 7 90 RON 1e 5 ROFF 2 0 1 VON 0 50 VOFF 2 50 RON 1e 5 ROFF 2 0 1 VON 2 50 VOFF 0 50 ENDS NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 82 intersil HUF75329D3 HUF75329D3S SABER Electrical Model REV June 1997 template huf75329d n2 n1 n3 electrical n2 n1 n3 var i iscl d model dbodymod is 7 50 13 cjo 1 51 9 tt 4 05e 8 m 0 5 d model dbreakmod LDRAIN d model dplcapmod cjo 13 5e 10 is 1 30 n 10 0 85 DPLCAP 5 DRAIN m model mmedmod type _n vto 3 25 kp 2 50 is 1e 30 tox 1 10 o2 m model mstrongmod type _n vto 3 80 k
7. 6 2 80e 3 ctherm ctherm2 6 5 1 00e 2 RTHERM4 ctherm ctherm3 5 4 6 80e 3 ctherm ctherm4 4 3 7 00e 3 5 3 2 1 60e 2 ctherm ctherm6 2 tl 15 55 CTHERM3 CTHERM4 rtherm rtherm1 th 6 7 94e 3 rtherm rtherm2 6 5 1 98e 2 RTHERM5 rtherm rtherm3 5 4 5 57e 2 rtherm rtherm4 4 3 3 13e 1 rtherm rtherm5 2 4 71e 1 rtherm rtherm6 2 tl 6 26e 2 5 RTHERM6 CTHERM6 All Intersil semiconductor products are manufactured assembled and tested under ISO9000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site http www intersil com 84 intersil
8. AKHU CAN Data Sheet HUF75329D3 HUF75329D3S June 1999 File Number 4426 4 20A 55V 0 026 Ohm N Channel UltraFET Power MOSFETs These N Channel power MOSFETs manufactured using the ol innovative UltraFET process This advanced process technology achieves the lowest possible on resistance per silicon area resulting in outstanding performance This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge It was designed for use in applications where power efficiency is important such as switching regulators switching converters motor drivers relay drivers low voltage bus switches and power management in portable and battery operated products Features 20A 55V Simulation Models Temperature Compensated PSPICE and SABER Models SPICE and SABER Thermal Impedance Models Available on the WEB at www semi Intersil com families models htm Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature TB334 Guidelines for Soldering Surface Mount Components to PC Boards Formerly developmental type TA75329 Symbol Ordering Information D PART NUMBER PACKAGE BRAND HUF75329D3 TO 251AA 75329D G HUF75329D3S TO 252AA 75329D NOTE When ordering use the entire part number Add the suffix T to 5 obtain the TO 252AA variant tape and reel e g
9. EAK 5 11 DBREAKMOD E DBREAK DPLCAP 10 5 DPLCAPMOD RSLC2 ESLC 11 EBREAK 11 7 17 18 58 13 750 EDS 148581 EGS 138681 RDRAIN DBODY ESG6 10681 ESG o9 EBREAK EVTHRES 6 21 198 1 h EVTHRES 21 76 EVTEMP 20 6 18221 MWEAK LGATE EVTEMP GATE RGATE 6 8 9 20 IT 8 17 1 7 6 4 5 LDRAIN 2 5 1e 9 RLGATE LSOURCE LGATE 1 9 2 86e 9 CIN SOURCE LSOURCE 3 7 2 69e 9 8 7 o 3 RSOURCE MMED 16 6 8 8 MMEDMOD RLSOURCE MSTRO 16 6 8 8 MSTROMOD siad gd MWEAK 16 21 8 8 MWEAKMOD RP ou RBREAK uA 45 17 18 RBREAK 17 18 RBREAKMOD 1 8 B RDRAIN 50 16 RDRAINMOD 1e 3 SIBo 52 RVTEMP RGATE 9 20 1 52 1 RLDRAIN 2 5 10 CA BB 14 19 RLGATE 1 9 26 9 RLSOURCE 3 7 28 6 EGS EDS RSLC1 551 RSLCMOD 1e 6 RSLC2 5 50 1e3 8 RSOURCE 8 7 RSOURCEMOD 13 85e 3 22 RVTHRES 22 8 RVTHRESMOD 1 RVTHRES RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 135 3 5 MODEL DBODYMOD D IS 7 50e 13 RS 5 05e 3 TRS1 2 21e 3 TRS2 1 02e 6 1 51 9 TT 4 05 8 M 0 5 MODEL DBREAKMOD D RS 2 14e 1 TRS1 9 62e 4 TRS2 1 23e 6 MODEL DPLCAPMOD D 13 5 10 IS 16 30 N 10 0 85 MODEL MMEDMOD NMOS VTO 3 25 KP 2 50 IS 1e 30 N 10 TOX 1L 1u W 1 RG 1 52 MODEL MSTROMOD NMOS VTO 3 80 KP 70
10. HUF75329D3ST Packaging JEDEC TO 251AA JEDEC TO 252AA SOURCE DRAIN DRAIN DRAIN FLANGE GATE FLANGE GATE SOURCE 76 CAUTION These devices are sensitive to electrostatic discharge follow proper ESD Handling Procedures UltraFET is a trademark of Intersil Corporation PSPICEG is a registered trademark of MicroSim Corporation SABERO is a Copyright of Analogy Inc http www intersil com or 407 727 9207 Copyright Intersil Corporation 1999 HUF75329D3 HUF75329D3S Absolute Maximum Ratings 25 Unless Otherwise Specified Drain to Source Voltage Note 1 Vpss Drain to Gate Voltage Ras 20kQ Note 1 VDGR Gate to Source Voltage seed eere peso bd ege a oe eda Ed Vas Drain Current Continuous Figure 23 ERR Per D RIA XD BEP eque Sr ID Pulsed Drain IDM Pulsed Avalanche 0 2 7 2 Eas Power Dissipation OI e qub dde doa Ra ER E Pp Derate Above 25 C veces ea REOR pees che e RU dn Operating and Storage Ty Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case for 1065 TL Package Body for 10s See Techbrief 334
11. ay Time bd B 7 ns Rise Time tr 30 ns Turn Off Delay Time td OFF 10 ns Fall Time tf 33 ns Turn Off Time toFF i x 65 ns GATE CHARGE SPECIFICATIONS Total Gate Charge Qg ror Vas 0 20 Vpp 30V 50 65 nC Gate Charge at 10V Qg 0 Vag OV to 10V 172 32 40 nc Threshold Gate Charge Vas 0Vto2V g REF 1 0m f 20 25 nc Figure 13 Gate to Source Gate Charge Qgs 5 nC Reverse Transfer Capacitance 13 nC 77 intersil HUF75329D3 HUF75329D3S Electrical Specifications T 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Ves OV 1060 s pF f 1MHz Output Capacitance Coss Figure 12 405 pF Reverse Transfer Capacitance Crss 95 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 20A 1 25 V Reverse Recovery Time trr Isp 20A dlgp dt 100A us 5 68 ns Reverse Recovered Charge QRR Isp 20A 15 100A us 120 nC Typical Performance Curves 1 2 25 1 0 a c 20 2 08 2 5 E 06 a a z o 4 10 a 0 4 a ul 5 5 02 a 0 0 0 25 50 75 100 125 150 175 25 50 75 100 125 15
12. p 70 is 1e 30 tox 1 RLDRAIN m model mweakmod type _n vto 2 91 kp 0 06 is 1e 30 tox 1 RSLC1 sw_vesp model stamod ron 1e 5 0 1 von 7 90 voff 4 90 51 RDBREAK sw vcsp model s1bmod ron 16 5 0 1 von 4 90 voff 7 90 RSLC2 27 Sw vcsp model s2amod 1 5 0 1 von 0 50 voff 2 50 ISCL RDBODY Sw vcsp model s2bmod ron 1e 5 roff 0 1 von 2 50 voff 0 50 50 DBREAK c ca n12 n8 1 72e 9 71 c cb n15 n14 1 52e 9 ESG 3 ORAN 11 c cin n6 n8 9 61 10 z EVTHRES 18 MWEAK d dbody n7 n71 model dbodymod LGATE EVTEMP DBODY d dbreak n72 n11 model dbreakmod GATE RGATE 6 EAM MMED EBREAK d dplcap n10 n5 2 model dplcapmod wee 9 20 I 4MSTRO i it n8 n17 2 1 LSOURCE GIN 8 gt SOURCE Lldrain n2 n5 1e 9 o 3 l lgate n1 n9 2 86e 9 RSOURCE l source n3 n7 2 69e 9 RLSOURCE k k1 i I lgate i l lsource I l lgate I I lsource 0 0085 S1A 9 952 RBREAK 12 15 m mmed n16 n6 n8 n8 model mmedmod 1u 1u 13 i 7 18 m mstrong n16 n6 n8 n8 model mstrongmod 1u w 1 m mweak n16 n21 n8 n8 model mweakmod 1u w 1u S1B 9 9 S2B RVTEME CA 13 CB 19 res rbreak n17 n18 1 tc1 1 05e 3 tc2 1 94e 7 14 HO l 1 res rdbody n71 n5 5 05e 3 2 21e 3 tc2 1 02e 6 VBAT res rdbreak n72 n5 2 14e 1 tc1 9 62e 4 tc2 1 23e 6 EGS EDS res rdrain n50 n16
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