intersil HUF75321D3 HUF75321D3S handbook
Contents
1. 1 02e 9 tt 3 21e 8 m 0 5 d model dbreakmod LDRAIN d model dplcapmod cjo 9e 10 is 1 30 n 10 0 85 DPLCAP 5 DRAIN m model mmedmod type _n vto 3 25 kp 1 75 is 1e 30 tox 1 10 wie 92 m model mstrongmod type _n vto 3 65 kp 32 is 1e 30 tox 1 RLDRAIN m model mweakmod type n vto 2 91 kp 0 07 is 1e 30 tox 1 RSLC1 sw_vesp model stamod ron 1 5 0 1 von 7 85 voff 4 85 51 RDBREAK sw vcsp model s bmod ron 16 5 0 1 von 4 85 voff 7 85 RSLC2 27 Sw vcsp model s2amod 1e 5 roff 0 1 von 0 voff 3 0 ISCL RDBODY Sw vcsp model s2bmod ron 1 5 0 1 von 3 0 voff 0 _ 50 DBREAK c ca n12 n8 9 96e 10 71 c cb n15 n14 9 83 10 ESG 3 ORAN 11 n6 n8 6 18 10 z EVTHRES 18 MWEAK d dbody n7 n71 model dbodymod LGATE EVTEMP DBODY d dbreak n72 n11 model dbreakmod GATE RGATE 6 EAM EBREAK d dplcap n10 n5 model dplcapmod 16 9 20 RLGATE Ie 1MSTRO i it n8 n17 1 LSOURCE CIN 8 SOURCE l ldrain n2 n5 1e 9 o 3 l lgate n1 n9 3 57e 9 RSOURCE l lsource n3 n7 4 25e 9 RLSOURCE S1A 9 992A m mmed n16 n6 n8 n8 model mmedmod 1u w 1u 1220 43 14 15 RBREAK m mstrong n16 n6 n8 n8 model mstrongmod 1u w 1u 8 13 17 18 m mweak n16 n21 n8 n8 model mweakmod 1u w 1u SIBo 5 S2B RVTEMP res rbreak n17 n18 1 tc1 1 05e 3 tc2 1 212. 100 ns T Ri 1 50 Vas 10V Turn On Delay Time td ON Reg 250 8 11 ns Rise Time tr 55 ns Turn Off Delay Time ta OFF 47 ns Fall Time tf 66 2 ns Turn Off Time torr 5 170 ns GATE CHARGE SPECIFICATIONS Total Gate Charge QgToT 20 Vpp 30V 36 44 nC Ip 20A Gate Charge at 10V Qg 10 Vas OV to 10V A 1 50 21 26 nC Threshold Gate Charge Vas 0Vto2V g REF 1 0 13 16 nC Figure 13 Gate to Source Gate Charge Qgs 2 3 nC Reverse Transfer Capacitance 9 nC 59 intersil HUF75321D3 HUF75321D3S Electrical Specifications T 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Vas OV 680 f 1MHz Output Capacitance Coss Figure 12 270 pF Reverse Transfer Capacitance Crss 60 5 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 20A 1 25 V Reverse Recovery Time trr Isp 20A dlgp dt 100A us 5 59 ns Reverse Recovered Charge QRR Isp 20A 15 100A us 82 nC Typical Performance Curves 1 2 25 d 10 o 20 5 amp 2 08 E t 15 E 0 6 2 amp o oa
3. 5 3 2 6 49e 1 RTHERM6 2 tl 8 61e 2 CTHERM2 SABER Thermal Model RTHERMS SABER thermal model HUF75321D template thermal_model th tl thermal_c th tl ctherm ctherm1 th 6 2 7e 3 ctherm ctherm2 6 5 3 7e 3 RTHERM4 ctherm ctherm3 5 4 1 2e 2 ctherm ctherm4 4 3 3 8 3 ctherm ctherm5 2 1 4e 2 ctherm ctherm6 2 tl 10 55 CTHERM3 CTHERM4 rtherm rtherm1 th 6 1 10e 3 rtherm rtherm2 6 5 2 72e 2 RTHERM5 rtherm rtherm3 5 4 7 67e 2 rtherm rtherm4 4 3 4 30e 1 rtherm rtherm5 3 2 6 49e 1 rtherm rtherm6 2 tl 8 61e 2 5 RTHERM6 CTHERM6 All Intersil semiconductor products are manufactured assembled and tested under ISO9000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site htt
4. 7 CA 13 19 res rdbody n71 n5 6 45e 3 tc1 2 01e 3 tc2 1 21e 6 5 14 ir 4 res rdbreak n72 n5 2 01e 1 tc1 3 62e 3 tc2 6 01e 7 VBAT res rdrain n50 n16 5 5e 3 tc 2 4e 2 tc2 1 02e 6 EGS EDS res rgate n9 n20 2 25 8 res ridrain n2 n5 10 22 res rlgate n1 n9 35 7 res rlsource n3 n7 42 5 res rsic1 n5 n51 1e 6 tc1 2 07e 4 tc2 4 67e 5 res rsic2 n5 n50 1e3 res rsource n8 n7 16 3e 3 tc1 0 t2 0 res rvtemp n18 n19 1 tc1 1 96e 3 tc2 1 39e 6 res rvthres n22 n8 1 tc1 3 01 3 tc2 8 85e 6 Spe ebreak n11 n7 n17 n18 2 59 54 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 Spe evtemp n20 n6 n18 n22 1 Spe evthres n6 n21 n19 n8 1 Sw vcsp s1a n6 n12 n13 n8 model s1amod sw vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 101 2 5 RVTHRES 65 intersil HUF75321D3 HUF75321D3S SPICE Thermal Model REV 24 February 1999 th JUNCTION HUF75321D CTHERM th 6 2 7e 3 CTHERM2 6 5 3 7e 3 CTHERMS 5 4 1 2 2 CTHERMA 4 3 3 8e 3 CTHERMS 3 2 1 4 2 CTHERM6 2 tl 10 55 RTHERM1 CTHERM1 RTHERM1 th 6 1 10 2 2 6 5 2 72e 2 RTHERM2 RTHERMS 5 4 7 67e 2 RTHERM4 4 3 4 30 1
5. 21 8 M 0 50 MODEL DBREAKMOD D RS 2 01e 1 TRS1 3 62e 3 TRS2 6 01e 7 MODEL DPLCAPMOD D 9 0e 10 IS 16 30 N 10M 0 85 MODEL MMEDMOD NMOS VTO 3 25 KP 1 75 IS 1e 30 N 10 TOX 1L 1u W 1 RG 2 25 MODEL MSTROMOD NMOS VTO 3 65 KP 32 00 IS 1 30 N 10 TOX 1L 1u W tu MODEL MWEAKMOD NMOS VTO 2 91 KP 0 07 IS 1e 30 N 10 TOX 1L 1u W 1u RG 22 5 RS 0 1 MODEL RBREAKMOD RES TC1 1 05e 3 TC2 1 21e 7 MODEL RDRAINMOD RES TC1 2 40e 2 TC2 1 02e 6 MODEL RSLCMOD RES TC1 2 07e 4 TC2 4 67 5 MODEL RSOURCEMOD RES TC1 0 TC2 0 MODEL RVTHRESMOD RES TC 3 01e 3 TC2 8 85e 6 MODEL RVTEMPMOD RES TC1 1 96e 3 TC2 1 39e 6 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH MODEL S2AMOD VSWITCH MODEL S2AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 7 85 VOFF 4 85 RON 1e 5 ROFF 0 1 VON 4 85 VOFF 7 85 RON 1e 5 ROFF 0 1 VON 0 00 VOFF 3 00 RON 1e 5 ROFF 0 1 VON 3 00 VOFF 0 00 ENDS NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 64 intersil HUF75321D3 HUF75321D3S SABER Electrical Model REV April 1998 template huf75321d n2 n1 n3 electrical n2 n1 n3 var iscl d model dbodymod is 7 47 13 cjo
6. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 7 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 1 2 y Ves Vps lp 2504A 1 0 0 8 NORMALIZED GATE THRESHOLD VOLTAGE 0 6 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 1000 Ves OV f 1MHz Ciss Cas Cap 800 Crss 1 T Ciss Coss Cap 9 600 E amp 400 4 5 D a 0 10 20 30 40 50 60 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 WAVEFORMS IN DESCENDING ORDER Vas GATE TO SOURCE VOLTAGE V Ip 20A Ip 10A Ip 5A 15 20 25 Qg GATE CHARGE nC NOTE Refer to Intersil Application Notes AN7254 and AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 62 intersil HUF75321D3 HUF75321D3S Test Circuits and Waveforms Vps VARY tp TO OBTAIN REQUIRED PEAK lAs Vas ov FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT DUT IG REF FIGURE 16 GATE CHARGE TEST CIRCUIT Vas DUT FIGURE 18 SWITCHING TIME TEST CIRCUIT FIGURE 15 UNCLAMPED ENERGY WAVEFORMS 24 E ak Ig REF 0 FIGURE 17 GATE CHARGE WAVEFORM 50 PUL
7. 10 m A E 2 8 02 5 0 0 25 50 75 100 125 150 175 0 5 50 75 100 125 150 175 CASE TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE Tc CASE TEMPERATURE C FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE 2 DUTY CYCLE DESCENDING ORDER 15 0 2 0 1 0 05 2 0 02 18 0 01 i 1 aH 4 z PDM O 2 lt 0 1 oz 3 tc 1 t 1 5 to NOTES 1 DUTY FACTOR D 4 42 4 SINGLE PULSE PEAK Ty X Zouc x Tc 0 01 105 104 103 10 10 100 t RECTANGULAR PULSE DURATION s FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 10 60 imtersil HUF75321D3 HUF75321D3S Typical Performance Curves continued 500 T TTTTTT T T T TTTT FOR TEMPERATURES 1 ABOVE 25 C PEAK 4 CURRENT AS FOLLOWS 96 100 150 tc 2 o x lt a 8 TRANSCONDUCTANCE F MAY LIMIT CURRENT IN THIS REGION 105 104 103 10 1071 10 10 t PULSE W
8. 5321D3ST Packaging JEDEC TO 251AA JEDEC TO 252AA DRAIN SOURCE FLANGE DRAIN GATE DRAIN GATE FLANGE SOURCE 58 CAUTION These devices are sensitive to electrostatic discharge follow proper ESD Handling Procedures UltraFET is a trademark of Intersil Corporation PSPICE is a registered trademark of MicroSim Corporation SABERO is a Copyright of Analogy Inc http www intersil com or 407 727 9207 Copyright Intersil Corporation 1999 HUF75321D3 HUF75321D3S Absolute Maximum Ratings 25 Unless Otherwise Specified UNITS Drain to Source Voltage Note 1 Vpss 55 V Drain to Gate Voltage Ras 20kQ Note 1 VpGR 55 V Gate to Source Voltage sss ee CE dre Vas 20 V Drain Current Goritinuous Figure 2 err Rer DRE Penh DEN PER EE Ip 20 A Pulsed Drain IDM Figure 4 Pulsed Avalanche 0 1 Eas Figures 6 14 15 Power Dissipation oa ped d due done 93 Derate Above 25 C iuis estes eno ER pees eke eed cad tua RO e dub ret 0 625 wc Operating and Storage Ty TstG 55 to 175 oc Maximum Temperature for Soldering Leads at 0 063in 1 6mm fr
9. ATi KU CA Data Sheet HUF75321D3 HUF75321D3S June 1999 File Number 4351 5 20A 55V 0 036 Ohm N Channel UltraFET Power MOSFETs These N Channel power MOSFETs manufactured using the ol innovative UltraFET process This advanced process technology achieves the lowest possible on resistance per silicon area resulting in outstanding performance This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge It was designed for use in applications where power efficiency is important such as switching regulators switching converters motor drivers relay drivers low voltage bus switches and power management in portable and battery operated products Features 20A 55V Simulation Models Temperature Compensating PSPICE and SABER Models Thermal Impedance SPICE and SABER Models Available on the WEB at www semi Intersil com families models htm Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature TB334 Guidelines for Soldering Surface Mount Components to PC Boards Formerly developmental type TA75321 Symbol Ordering Information D PART NUMBER PACKAGE BRAND HUF75321D3 TO 251AA 75321D G HUF75321D3S TO 252AA 75321D NOTE When ordering use the entire part number Add the suffix T to 5 obtain the TO 251AA variant tape and reel e g HUF7
10. IDTH s FIGURE 4 PEAK CURRENT CAPABILITY 300 Bs _ LMAX ATED z An 1 5 1 pss Vpp p 100 tay L R In lAs R 1 3 RATED BVpss Vpp 1 z _ 100 5 8 tc rI z 5 10 M i a 3 F OPERATION IN THIS H AREA MAY H LIMITED BY TDS ON Vbss MAX 55V Ll 1 1 0 01 0 1 1 10 1 10 100 200 tay TIME IN AVALANCHE ms Vps DRAIN TO SOURCE VOLTAGE V NOTE Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 5 FORWARD BIAS SAFE OPERATING AREA FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY PULSE DURATION 80us DUTY CYCLE 0 5 MAX lt E E ai tc tc tc 3 3 z z lt 4 5 5 2 PULSE DURATION 8045 DUTY CYCLE 0 5 MAX 25 C 0 1 5 3 0 4 5 6 0 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 7 SATURATION CHARACTERISTICS 7 5 0 1 5 3 0 4 5 6 0 7 5 Vas GATE TO SOURCE VOLTAGE V FIGURE 8 TRANSFER CHARACTERISTICS 61 intersil HUF75321D3 HUF75321D3S Typical Performance Curves continued m o 2 5 T T T PULSE DURATION 80us DUTY CYCLE 0 5 Vas 10V Ip 20A 9 a 2 0 P za 2 15 In tc N 19 lt tc o 2 0550 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 12 T lp 250A 1 1 1 0
11. SE WIDTH gt FIGURE 19 RESISTIVE SWITCHING WAVEFORMS 63 intersil HUF75321D3 HUF75321D3S PSPICE Electrical Model SUBCKT HUF75321D213 4 29 98 12 89 96 10 CB 15 149 83 10 LDRAIN 6 86 18 10 DPLCAP 5 die DRAIN 2 10 DBODY 7 5 DBODYMOD RSLC1 REDRAIN DBREAK 5 11 DBREAKMOD 5i DBREAK DPLCAP 10 5 DPLCAPMOD RSLC2 ESLC 11 EBREAK 11717 18 59 54 750 EDS 148 581 EGS 138681 RDRAIN DBODY ESG6 10681 ESG EBREAK EVTHRES 6 21 198 1 EVTHRES Ia 7 EVTEMP 20 6 18 22 1 I MWEAK LGATE EVTEMP RGATE Te ert men 20 RLGATE Ve gMSTRO LDRAIN 2 5 1e 9 LSOURCE LGATE 1 93 57e 9 CIN SOURCE LSOURCE 3 7 4 25e 9 7 3 RSOURCE MMED 16 6 8 8 MMEDMOD RLSOURCE MSTRO 16 6 8 8 MSTROMOD ai Jas MWEAK 16 21 8 8 MWEAKMOD 2 RBREAK 13 17 18 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 5 50e 3 SIBo 9 S2B RVTEMP RGATE 9 202 25 RLDRAIN 2510 4 19 RLGATE 1 9 35 7 RLSOURCE 3 7 42 5 EOS EDs 5 VBAT RSLC1 5 51 RSLCMOD 1e 6 RSLC2 5 50 1e3 8 RSOURCE 8 7 RSOURCEMOD 16 30e 3 22 RVTHRES 22 8 RVTHRESMOD 1 RVTHRES RVTEMP 18 19 RVTEMPMOD 1 IT 8 17 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD 52 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 101 2 5 MODEL DBODYMOD D IS 7 47e 13 RS 6 45e 3 TRS1 2 01e 3 TRS2 1 21e 6 1 02e 9 TT 3
12. om Case for 106 TL 300 9c Package Body for 10s See Techbrief 334 Tpkg 260 96 CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 Ty 259C to 150 C Electrical Specifications 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip 250uA Vas OV Figure 11 55 V Zero Gate Voltage Drain Current Ipss Vps 50V Ves OV gt 1 uA Vps 45V Vgs OV 150 C 250 Gate to Source Leakage Current lass Vas 20V 5 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH Vas Ip 250A Figure 10 2 4 Drain to Source On Resistance p 20 Vag 10V Figure 9 0 030 0 036 THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Figure 3 1 6 C W Thermal Resistance Junction to Ambient ReJA TO 251 TO 252 100 C W SWITCHING SPECIFICATIONS Vcs 10V Turn On Time ton Vpp 30V Ip 20A
13. p www intersil com 66 imtersil
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