intersil HUF75309P3 HUF75309D3 HUF75309D3S handbook
Contents
1. Turn On Time ton Vpp 30V Ip 19A 70 ns Turn On Delay Time HE ipse Ves 10 7 ns Rise Time tr 39 B ns Turn Off Delay Time td OFF 24 ns Fall Time tf 30 ns Turn Off Time torr E 80 ns GATE CHARGE SPECIFICATIONS Total Gate Charge QgToT 20 Vpp 30V 20 24 nC Gate Charge at 10V Vas OV to 10V 11 13 5 nC Threshold Gate Charge QgtH Vas OV to 2V 22 0mA 0 68 0 85 nC Gate to Source Gate Charge Qgs 1 8 nC Reverse Transfer Capacitance 5 5 nC 2 intersil HUF75309P3 HUF75309D3 HUF75309D3S Electrical Specifications T 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Ves OV 350 f 1MHz Output Capacitance Coss Figure 12 150 Reverse Transfer Capacitance Cnss 39 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 19A 1 25 V Reverse Recovery Time ter Isp 19A dlgp dt 100A us gt 50 ns Reverse Recovered Charge QRR Isp 19A digp dt 100A us 70 nC Typical Performance Curves 1 2 20 m 1 0 5 15 0 8 2 2 9 5 E 06 o 10 amp z 52. LILI 1075 104 103 10 107 100 101 t PULSE WIDTH s FIGURE 4 PEAK CURRENT CAPABILITY 100 TJ MAX RATED 200 0 SINGLE PULSE 0 145 1 3 BVpss Vpp T 100 0 2 L R In las R 1 3 RATED BVpss Vpp 1 2 a E rc 2 E o O 10 u z o 5 2 10 OPERATION IN THIS a AREA MAY BE a LIMITED BY rps oN E Vpss MAX 55V 1 1 1 10 100 200 0 001 0 01 0 1 1 10 DRAIN TO SOURCE VOLTAGE V tay TIME IN AVALANCHE ms NOTE Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 5 FORWARD BIAS SAFE OPERATING AREA FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 40 T PULSE DURATION 80us 55 C DUTY CYCLE 0 5 MAX lt 32 z 2 2 259 5 ___ ee dH Ves 6V 3 ass 3 z 16 a a Ves 5V GS PULSE DURATION 80us DUTY CYCLE 0 5 MAX 25 0 0 2 4 6 8 0 2 4 6 8 Vps DRAIN TO SOURCE VOLTAGE V Vas GATE TO SOURCE VOLTAGE V FIGURE 7 SATURATION CHARACTERISTICS FIGURE 8 TRANSFER CHARACTERISTICS 4 intersil HUF75309P3 HUF75309D3 HUF75309D3S Typical Performance Curves Continued 2 5 r r r r r PULSE DURATION 80us Vas 10V Ip 19A DUTY CYCLE 0 5 MAX bad o NORMALIZED DRAIN TO SOURCE ON RESISTANCE 5 amp 0 5 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATUR
3. FIGURE 19 RESISTIVE SWITCHING WAVEFORMS 6 intersil HUF75309P3 HUF75309D3 HUF75309D3S PSPICE Electrical Model SUBCKT HUF75309 2 1 3 CA 12 83 85e 10 CB 15 14 4 15e 10 CIN 6 83 17e 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 59 22 EDS 14 8 5 81 EGS 13 8 6 81 ESG6 10681 EVTHRES 6 21 198 1 EVTEMP 20 6 18 22 1 IT 8 17 1 GATE 10 LDRAIN 2 5 1e 9 LGATE 1 9 2 24e 9 LSOURCE 3 7 2 09e 9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 9 1e 3 RGATE 9 20 1 27 RLDRAIN 2 5 10 RLGATE 1 9 22 4 RLSOURCE 3 7 20 9 RSLC1 5 51 RSLCMOD 1 6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 4 0e 3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD 52 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 rev 30June97 LGATE RLGATE CA EVTEMP MEC 9 20 12 DPLCAP 5 10 RSLC1 51 RSLC2 ESLC _ 50 RDRAIN TO EVTHRES Oi 1 elus I MSTRO CIN 8 S1A 9 52 1 15 8 13 51 52 13 CB 14 ces 3 2 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 43 4 5 DBREAK 11 e MWEAK RSOURCE RBREAK RVTHRES MODEL DBODYMOD D IS 3 0e 13 RS 1 04e 2 TRS1 1 89e 3 TRS2 0 5 25 10 3 09e 8 M 0 5 MODEL DBREAKMOD D RS 2
4. 0 4 5 tr 5 02 5 0 0 0 0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 Tc CASE TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE TY CYCLE DESCENDING ORDER Tc CASE TEMPERATURE C CASE TEMPERATURE FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs DU 0 5 0 2 0 1 0 0 0 0 0 0 i 0 1 Zgyc NORMALIZED THERMAL IMPEDANCE SINGLE PULSE NOTES DUTY FACTOR D 1 42 LILI ty t2 lt PEAK Ty Ppm Zgjc Tc 1 1 42 42 12421244 0 01 105 104 FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 103 10 10 t RECTANGULAR PULSE DURATION s 100 101 3 intersil HUF75309P3 HUF75309D3 HUF75309D3S Typical Performance Curves Continued 300 Tc 259C FOR TEMPERATURES 4 ABOVE 259 DERATE 4 CURRENT AS FOLLOWS E A I los f 100 150 2 o x lt a B TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 1
5. 66e 1 TRS1 1 31e 4 TRS2 1 34e 5 MODEL DPLCAPMOD D 3 8e 10 IS 16 30 N 10 0 79 MODEL MMEDMOD NMOS VTO 3 45 KP 2 15 1e 30N 10 TOX 1L 1u W 1 RG 1 27 MODEL MSTROMOD NMOS VTO 3 95 KP 19 IS 1 30 N 10 TOX 1L du W 1u MODEL MWEAKMOD NMOS VTO 3 05KP 0 05 IS 1e 30 N 10 TOX 1 L 1u W 1u RG 12 7 RS 0 1 MODEL RBREAKMOD RES TC1 1 05e 3 TC2 1 21e 7 MODEL RDRAINMOD RES TC1 3 1e 2 TC2 3 7e 5 MODEL RSLCMOD RES TC1 2 71e 3 TC2 1 07e 5 MODEL RSOURCEMOD RES TC1 0 TC2 0 MODEL RVTHRESMOD RES 3 31e 3 TC2 4 31 6 MODEL RVTEMPMOD RES TC1 1 62e 3 TC2 1 29e 6 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH MODEL S2AMOD VSWITCH MODEL S2BMOD VSWITCH ENDS RON 1e 5 ROFF 0 1 VON 6 0 VOFF 3 0 RON 1e 5 ROFF 0 1 VON 3 0 VOFF 6 0 RON 1e 5 ROFF 0 1 VON 1 9 VOFF 4 9 RON 1e 5 ROFF 2 0 1 VON 4 9 VOFF 1 9 LDRAIN RLDRAIN DRAIN o2 DBODY LSOURCE SOURCE Eo pos RLSOURCE 18 RVTEMP 19 22 NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 7 intersil HUF75309P3 HUF75309D3 HUF75309D3S SABER Electrical Model REV February 1999 template huf75309 n2 n1 n3 electrical n2 n1
6. 9e 2 RTHERMA 4 3 4e 1 5 2 6e 1 RTHERM6 2 tl 9 5e 1 SABER Thermal Model SABER thermal model HUF75309 template thermal model th tl thermal c th tl ctherm ctherm1 th 6 8e 4 ctherm ctherm2 6 5 1e 3 ctherm ctherm3 5 4 2e 3 ctherm ctherm4 4 3 2 8e 3 ctherm ctherm5 2 5 5e 3 ctherm ctherm6 2 tl 1 6e 2 rtherm rtherm1 th 6 1e 3 rtherm rtherm2 6 5 7e 3 rtherm rtherm3 5 4 9e 2 rtherm rtherm4 4 3 4e 1 rtherm rtherm5 2 6e 1 rtherm rtherm6 2 tl 9 5e 1 All Intersil semiconductor products are manufactured assembled and tested under ISO9000 quality systems certification RTHERM1 RTHERM2 RTHERM4 RTHERM5 RTHERM6 th JUNCTION CTHERM1 2 CTHERM3 CTHERM4 CTHERM5 CTHERM6 Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For infor
7. AKHU CAU Data Sheet HUF75309P3 HUF75309D3 HUF75309D3S June 1999 File Number 4358 5 19A 55V 0 070 Ohm N Channel UltraFET Power MOSFETs These N Channel power MOSFETs are manufactured using the EN innovative UltraFET process This advanced process technology achieves the lowest possible on resistance per silicon area resulting in outstanding performance This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge It was designed for use in applications where power efficiency is important such as switching regulators switching converters motor drivers relay drivers low voltage bus switches and power management in portable and battery operated products Features 19A 55V Simulation Models Temperature Compensated PSPICE and SABER Models SPICE and SABER Thermal Impedance Models Available on the WEB at www semi Intersil com families models htm Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature TB334 Guidelines for Soldering Surface Mount Components to PC Boards Formerly developmental type TA75309 Symbol Ordering Information D PART NUMBER PACKAGE BRAND HUF75309P3 TO 220AB 75309P G HUF75309D3 TO 251AA 75309D HUF75309D3S TO 252AA 75309D S NOTE When ordering use the entire part number Add the suffix T to obt
8. E 1 2 lp 250A n 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C E NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE N FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE Ves Vps lp 2504A NORMALIZED GATE THRESHOLD VOLTAGE 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE Ves OV f 1 2 Ciss Cas Cap Cnss Coss gt CAPACITANCE pF Vps DRAIN TO SOURCE VOLTAGE V FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 Vas GATE TO SOURCE VOLTAGE V WAVEFORMS IN DESCENDING ORDER lp 19A Ip 15A Ip 10A Ip 5A 1 9 12 Qg GATE CHARGE nC NOTE Refer to Intersil Application Notes AN7254 and AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 5 intersil HUF75309P3 HUF75309D3 HUF75309D3S Test Circuits and Waveforms Vps VARY tp TO OBTAIN REQUIRED PEAK lAs Vas ov FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT DUT IG REF FIGURE 16 GATE CHARGE TEST CIRCUIT DUT FIGURE 18 SWITCHING TIME TEST CIRCUIT FIGURE 15 UNCLAMPED ENERGY WAVEFORMS 24 E Ig REF 0 FIGURE 17 GATE CHARGE WAVEFORM 50 PULSE WIDTH gt
9. TJ TstG 55 to 175 oc Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case for 106 TL 300 oc Package Body for 10s See Techbrief 334 Tpkg 260 96 CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 Ty 259C to 150 C Electrical Specifications 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip 250 Vag Figure 11 55 V Zero Gate Voltage Drain Current Ipss Vps 50V Ves OV 1 Vps 45V Vag OV 150 C 250 Gate to Source Leakage Current lass Vas 20V 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas TH Vas Vos Ip 250A Figure 10 2 2 4 Drain to Source On Resistance 19 Vas 10V Figure 9 0 060 0 070 Q THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Figure 3 2 7 Thermal Resistance Junction to Ambient ReJA TO 220 62 C W TO 251 TO 252 2 100 C W SWITCHING SPECIFICATIONS Vcs 10V
10. ain the TO 252AA variant in tape and reel e g HUF75309DSST Packaging JEDEC STYLE TO 220AB JEDEC TO 251AA SOURCE DRAIN DRAIN FLANGE GATE DRAIN FLANGE JEDEC TO 252AA DRAIN FLANGE GATE SOURCE 1 CAUTION These devices are sensitive to electrostatic discharge follow proper ESD Handling Procedures UltraFET is a trademark of Intersil Corporation PSPICEG is a registered trademark of MicroSim Corporation SABER is a Copyright of Analogy Inc http www intersil com or 407 727 9207 Copyright Intersil Corporation 1999 HUF75309P3 HUF75309D3 HUF75309D3S Absolute Maximum Ratings 25 C Unless Otherwise Specified UNITS Drain to Source Voltage Note 1 Vpss 55 V Drain to Gate Voltage Ras 20kQ Note 1 VpGR 55 V Gate to Source Voltage sss ee eser d CE dre Vas 20 V Drain Current Goritinuous Figure 2 err Rer DRE Penh DEN PER EE Ip 19 A Pulsed Drain IDM Figure 4 Pulsed Avalanche 0 1 EAS Figures 6 14 15 Power Dissipation e oa d Pa Papa eed ped d due done Pp 55 Derate Above 25 C iuis estes eno ER pees eke eed cad DT RO e dub ret edd c ar 0 37 wc Operating and Storage
11. d 1u w 1u SIB 2528 RVTEMP res rbreak n17 n18 1 tcl 1 05e 3 tc2 1 21 7 CA 13 19 res rdbody n71 n5 1 04 2 tcl 1 89 3 tc2 0 14 4 res rdbreak n72 n5 2 66e 1 1 31 4 tc2 1 34e 5 VBAT res rdrain n50 n16 9 1e 3 tc1 3 1e 2 tc2 3 7e 5 FUP EDS 3 res rgate n9 n20 1 8 res ridrain n2 n5 10 22 res rlgate n1 n9 22 4 res rlsource n3 n7 20 9 res rsic1 n5 n51 1e 6 tc1 2 71 3 tc2 1 07e 5 res rsic2 n5 n50 1e3 res rsource n8 n7 4 0e 2 tc1 0 tc2 0 res rvtemp n18 n19 1 tc1 1 62 3 tc2 1 29e 6 res rvthres n22 n8 1 tc1 3 31 3 tc2 4 31e 6 Spe ebreak n11 n7 n17 n18 59 22 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 Spe evtemp n20 n6 n18 n22 1 spe evthres n6 n21 n19 n8 1 Sw vcsp s1a n6 n12 n13 n8 model s1amod sw vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 isc iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 43 4 5 RVTHRES 8 intersil HUF75309P3 HUF75309D3 HUF75309D3S SPICE Thermal Model REV February 1999 HUF75309 CTHERM1 th 6 8 4 2 6 5 1e 3 CTHERNG 5 4 2e 3 CTHERMA 4 3 2 8 3 CTHERMS 3 2 5 5e 3 CTHERM6 2 tl 1 6e 2 RTHERM th 6 1e 3 2 6 5 7e 3 RTHERMS 5 4
12. mation regarding Intersil Corporation and its products see web site http www intersil com 9 intersil
13. n3 var i iscl d model dbodymod is 3 0e 13 cjo 5 25e 10 tt 3 09e 8 m 0 5 d model dbreakmod LDRAIN d model dplcapmod cjo 3 8e 10 is 1e 30 n 10 m 0 79 DPLCAP 5 DRAIN m model mmedmod type n vto 3 45 kp 2 is 1e 30 tox 1 10 Siir o2 m model mstrongmod type _n vto 3 95 kp 19 is 1e 30 tox 1 RLDRAIN m model mweakmod type _n vto 3 05 kp 0 05 is 1e 30 tox 1 RSLC1 Sw vcsp model s1amod 1e 5 roff 0 1 von 6 0 voff 3 0 51 RDBREAK sw vcsp model s1bmod ron 1e 5 roff 0 1 von 3 0 voff 6 0 RSLC2 27 sw vcsp model s2amod ron 1 5 0 1 von 1 9 voff 4 9 v RDBODY Sw vcsp model s2bmod 16 5 0 1 von 4 9 voff 1 9 _ 50 c ca n12 n8 3 85e 10 71 c cb n15 n14 4 15e 10 ESG MORA 11 c cin n6 n8 3 17e 10 P EVTHRES 21 7 14 MWEAK d dbody n7 n71 model dbodymod LGATE EVTEMP DBODY d dbreak n72 n11 model dbreakmod GATE RGATE 6 Baal EBREAK d dplcap n10 n5 model dplcapmod 1 6 Dee 9 20 MMED RLGATE MSTRO 7 i it n8 n17 1 LSOURCE CIN 8 2 SOURCE l ldrain n2 n5 1e 9 wee o 3 I gate n1 n9 2 24e 9 RSOURCE l lsource n3 n7 2 09e 9 RLSOURCE S1A 0 992A m mmed n16 n6 n8 n8 model mmedmod 1u w 1 1220 43 14 15 m mstrong n16 n6 n8 n8 model mstrongmod 1u w 1u 13 17 18 m mweak n16 n21 n8 n8 model mweakmo
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