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NEC PD23C32340 23C32380 handbook

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1. Output load 1TTL 100 pF Data Sheet M15711EJ2VODS 9 UPD23C32340 23 32380 Cautions on power application To ensure normal operation always apply power using CE following the procedure shown below 1 Input a high level to CE during and after power application 2 Hold the high level input to CE for 200 ns or longer wait time 3 Start normal operation after the wait time has elapsed Power Application Timing Chart 1 When CE is made high at power application Wait time Normal operation Input 200 ns or longer Power Application Timing Chart 2 When CE is made high after power application Wait time 200 ns or longer Normal operation Input Caution Other signals can be either high or low during the wait time 10 Data Sheet M15711EJ2VODS 23 32340 23 32380 Read Cycle Timing Chart 1 tskew AO to A20 Nae Input tace toc ICE Input toe gt JOE or OE Input toe ton ton be High Z High Z OE me 339 7 LEK WIE Notes 1 During WORD mode 1 is O15 2 tor is the time from inactivation of Chip Enable input CE or Output Enable input OE or OE to high impedance state output 3 During BYTE mode 08 to O14 are high impedance and O15 is 1 Data Sheet M15711EJ2VODS 11
2. 001007 Output Data Out X X Data Out Y X Data Out tor Data Out O810 O15 Output Data Out Y Remark Chip Enable CE and Output Enable OE or OE Active Data Sheet M15711EJ2VODS 13 23 32340 23 32380 Package Drawings 48 PIN PLASTIC TSOP I 12x20 detail of lead end BR 3 24 a o TETUER n NOTES ITEM MILLIMETERS 1 Each lead centerline is located within 0 10 mm of A 12 020 1 its true position T P at maximum material condition 0 45 2 A excludes mold flash Includes mold flash 12 4 mm MAX 0 o 54802 50 1 14 Data Sheet M15711EJ2VODS 23 32340 23 32380 48 PIN TAPE FBGA 8x6 gt INDEX MARK e H b ox AB Data Sheet M15711EJ2VODS x INDEX MARK ITEM MILLIMETERS lt gt m s mo yl 20 2 6 050 1 0 0 1
3. 0 97 0 10 0 27 0 05 0 70 0 4550 05 0 08 0 1 0 2 00 1 20 P48F9 80 BC3 15 UPD23C32340 23 32380 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the 23 32340 and 23 32380 Types of Surface Mount Device uPD23C32340GZ MJH uPD23C32340F9 BC3 Lu PD23C32380GZ MJH 23 32380 9 16 48 pin PLASTIC TSOP I 12 x 20 Normal bent 48 pin TAPE FBGA 8 x 6 48 pin PLASTIC TSOP I 12 x 20 Normal bent 48 pin TAPE FBGA 8 x 6 Data Sheet M15711EJ2VODS uUPD23C32340 23C32380 Revision History Edition Page Type of Location Description Date This Previous revision Previous edition This edition edition edition 2nd edition Throughout Throughout Modification Preliminary Data Sheet Data Sheet Feb 2003 p 9 9 Addition AC Characteristics Address skew time Note p 10 Addition Cautions on power application 11 10 Modification Read Cycle Timing Chart 1 p 15 p 14 Modification Package Drawings Preliminary version Standard version Data Sheet M15711EJ2VODS 17 23 32340 23 32380 18 Data Sheet M15711EJ2VODS NEC 23 32340 23C32380 NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gat
4. 23 32340 23C32380 Read Cycle Timing Chart 2 Page Access Mode Upper address Note 1 55 to 220 Input X to A20 ICE OE or OE Input Page address Note 1 A 1 Note Input 162 AQ Note 5 Note 5 teac teac 00 to O7 08 to O15 Note 4 Output sss Notes 1 The address differs depending on the product as follows Part Number Upper address Page address uPD23C32340 A2 to A20 1 A0 A1 uPD23C32380 A3 to A20 1 0 A1 2 2 During WORD mode 1 is O15 3 tor is the time from inactivation of Chip Enable input CE or Output Enable input OE or OE to high impedance state output 4 During BYTE mode 08 to O14 are high impedance and O15 is 1 5 The definition of page access time is as follows uPD23C32340 Page access time Upper address A2 to A20 CE input condition or OE input condition inputs condition teac Before tacc teac Before tce trac Before stabilizing of page address A 1 A0 A1 uPD23C32380 Page access time Upper address to A20 CE input condition or OE input condition inputs condition Before tacc teac Before tce trac Before stabilizing of page address 1 0 1 2 12 Data Sheet M15711EJ2VODS 23 32340 23 32380 WORD BYTE Switch Timing Chart 1 Input WORD BYTE Input IN ton tace ton
5. Input Address input pins to A20 are used differently in the WORD mode and the BYTE mode WORD mode 2M word by 16 bit to A20 are used as 21 bits address signals BYTE mode 4M word by 8 bit to A20 are used as the upper 21 bits of total 22 bits of address signal The least significant bit A 1 is combined to 015 O0 to O7 O8 to 014 Data outputs Output Data output pins 00 to O7 O8 to O14 are used differently in the WORD mode and the BYTE mode WORD mode 2M word by 16 bit The lower 15 bits of 16 bits data outputs to 00 to O14 The most significant bit O15 combined to 1 BYTE mode 4M word by 8 bit 8 bits data outputs to O0 to O7 and also O8 to 014 are high impedance O15 A 1 Data output 15 LSB Address input Output Input O15 A 1 are used differently in the WORD mode and the BYTE mode WORD mode 2M word by 16 bit The most significant output data bus O15 BYTE mode 4M word by 8 bit The least significant address bus 1 ICE Input activating signal Chip Enable When the OE is active output states are following High level High Z Low level Data out JOE or OE or DC Input Output enable signal The active level of OE is mask option The active level of OE Output Enable Don t care can be selected from high active low active and Don t care at order 3 Supply voltage GND Ground NC Not internally connected T
6. NC Note No Connection DC Don t Care A16 WORD GND O15 A 1 or or OE or DC GND Note Some signals be applied because this is not connected to the inside of the chip Remark Refer to Package Drawings for the 1 pin index mark Data Sheet M15711EJ2VODS 23 32340 23C32380 48 pin TAPE FBGA 8 x 6 uPD23C32340F9 xxx BC3 1 uPD23C32380F9 xxx BC3 1 Top View Bottom View 6 00000000 5 4 3 2 1 H Q AO to A20 Address inputs 0010 O7 O8 to 014 Data outputs O15 A 1 Data output 15 WORD mode LSB Address input BYTE mode WORD BYTE Mode select ICE Chip Enable or OE Output Enable Voc Supply voltage GND Ground Nc Noe No Connection DC Don t Care Note Some signals can be applied because this pin is not connected to the inside of the chip Remark Refer to Package Drawings for the index mark 4 Data Sheet M15711EJ2VODS 23 32340 23 32380 Input Output Pin Functions Pin name Input Output Function WORD BYTE Input The pin for switching WORD mode and BYTE mode High level WORD mode 2M word by 16 bit Low level BYTE mode 4M word by 8 bit 0 to A20 Address inputs
7. Each unused pin should be connected to GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 8 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function Data Sheet M15711EJ2VODS 19 23 32340 23C32380 These commodities technology or software must be exported accordance with the export administration regulations of the exporting country Diversion contrary to the law of that country is prohibited The information in this document is current as of February 2003 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Pl
8. 2 0 23 32340 v fS DATA SHEET MOS INTEGRATED CIRCUIT 23 32340 23C32380 32M BIT MASK PROGRAMMABLE ROM 4M WORD BY 8 BYTE MODE 2M WORD BY 16 BIT WORD MODE PAGE ACCESS MODE Description The uPD23C32340 and 23 32380 are 33 554 432 bits mask programmable ROM The word organization is selectable BYTE mode 4 194 304 words by 8 bits WORD mode 2 097 152 words by 16 bits The active levels of OE Output Enable Input can be selected with mask option The uPD23C32340 and 23 32380 are packed in 48 PLASTIC 5 1 and 48 pin TAPE FBGA Features Pin compatible with NOR Flash Memory Word organization 4 194 304 words by 8 bits BYTE mode 2 097 152 words by 16 bits WORD mode Page access mode BYTE mode 8 byte random page access 23 32340 16 byte random page access uPD23C32380 WORD mode 4 word random page access 23 32340 8 word random page access uPD23C32380 Operating supply voltage 2 7 V to 3 6 V Operating supply Access time voltage Page access time Power supply current Active mode mA MAX Standby current CMOS level input Voc ns 3 0V 0 3V 100 25 33V 03V 90 25 23 32340 23 32380 MAX The information in this document is subject to change without notice Before using this document please contirm that this is the latest version Not all products a
9. ameter Test condition Veo 2 30 V 0 3 V 233 V 0 3 V MIN TYP MIN Address access time tace 100 90 ns Page access time tac 25 25 ns Address skew time tskew Note 10 10 ns Chip enable access time 100 90 ns Output enable access time toe 25 25 ns Output hold time ton 0 0 ns Output disable time tor 0 25 0 25 ns WORD BYTE access time twe 100 90 ns Note tskew indicates the following three types of time depending on the condition 1 When switching CE from high level to low level tskew is the time from the CE low level input point until the next address is determined 2 When switching CE from low level to high level tskew is the time from the address change start point to the high level input point 3 When CE is fixed to low level tskew is the time from the address change start point until the next address is determined Since specs are defined for tskew only when is active is not subject to limitations when CE is switched from high level to low level following address determination or when the address is changed after CE is switched from low level to high level Remark tor is the time from inactivation of Chip Enable input CE or Output Enable input OE or OE to high impedance state output AC Test Conditions Input waveform Rise Fall time lt 5 ns X Test points 14 X Output waveform Test points X
10. e expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above MBE 02 11 1
11. e oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wriststrap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF THE APPLIED WAVEFORM OF INPUT PINS AND THE UNUSED INPUT PINS FOR CMOS Note Input levels of CMOS devices must be fixed CMOS devices behave differently than Bipolar or NMOS devices If the input of a CMOS device stays in an area that is between MAX and Vin MIN due to the effects of noise or some other irregularity malfunction may result Therefore not only the input waveform is fixed but also the waveform changes it is important to use the CMOS device under AC test conditions For unused input pins in particular CMOS devices should not be operated in a state where nothing is connected so input levels of CMOS devices must be fixed to high or low by using pull up or pull down circuitry
12. ease check with an NEC Electronics sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these Circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated ent
13. he signal can be connected Data Sheet M15711EJ2VODS 5 23 32340 23C32380 08 09 010 011 012 013 014 015 1 001 O1 02 1 03 1 04 4 05 4 06 O7 H Output Buffer A1 Li a 5 c gt Y Selector 2 4 3 i A6 o gt p asoc 8 L 4 151 4 Memory Matrix 8 5 3 3 2 097 152 words by 16 bits 5 120 4 2 8 4 194 304 words by 8 bits Lice A180 x 5 0 4 8 A150 i A16 0 H A17 O 80 A19 0 A20 0 I 4 6 Data Sheet M15711EJ2VODS 23 32340 23 32380 Mask Option The active levels of output enable pin or OE or DC are mask programmable and optional and can be selected from among 0 1 x shown the table below Option or OE or DC OE active level Don t care Operation modes for each option are shown in the tables below perm mode 0 Data out Standby mode Y Active Data out Standby High Z ee mode orion x Mode Output state Active Data out Standby High Z Remark L Low level in
14. irely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwis
15. nd or types are available in every country Please check with an NEC Electronics sales representative for avail ility and additional information Document M15711EJ2VODSOO 2nd edition The mark shows major revised points Date Published February 2003 NS CP K Printed in Japan NEC Electronics Corporation 2001 23 32340 23 32380 Ordering Information Part Number Package 1 023 3234062 23 32340 9 23 3238067 23 32380 9 xxx ROM code suffix No 48 pin PLASTIC 12 x 20 Normal bent 48 pin TAPE FBGA 8 x 6 48 pin PLASTIC 5 1 12 x 20 Normal bent 48 pin TAPE FBGA 8 x 6 Data Sheet M15711EJ2VODS 23 32340 23 32380 Pin Configurations xxx indicates active low signal 48 PLASTIC TSOP I 12 x 20 Normal bent uPD23C32340GZ xxx MJH PD23C32380GZ xxx MJH Marking Side 48 o 41 o 46 o 48 0 44 o 43 41 0 40 0 39 o 381 0 37 o 3681 0 35 341 0 331 0 321 0 30 29 O 28 o 2 26 o 25 AO to A20 Address inputs 0010 O7 O8 to 014 Data outputs O15 A 1 Data output 15 WORD mode LSB Address input BYTE mode WORD BYTE Mode select ICE Chip Enable or OE Output Enable Voc Supply voltage GND Ground
16. put H High level input Data Sheet M15711EJ2VODS 7 UPD23C32340 23C32380 Electrical Specifications Absolute Maximum Ratings Parameter Condition Supply voltage o 0 3 to 4 6 Input voltage 0 3 to Vcc 0 3 Output voltage 0 3 to Vcc 0 3 Operating ambient temperature 10 to 70 Storage temperature 65 to 150 Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability Capacitance TA 25 Parameter Test condition Input capacitance Output capacitance Vcc 2 7 to 3 6 V Parameter Test conditions High level input voltage Low level input voltage High level output voltage lon 100 uA Low level output voltage lo 2 1 mA Input leakage current 0 V to Vcc Output leakage current 0 V to Voc Chip deselected Power supply current ICE Vu Active mode 23 32340 lo OmA uPD23C32380 Standby current CE Vcc 0 2 V Standby mode 8 Data Sheet M15711EJ2VODS 23 32340 23 32380 AC Characteristics TA 10 to 70 Vcc 2 7 to 3 6 V Par

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