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TEXAS INSTRUMENTS TLV0831C TLV0831I TLV0832C TLV0832I

1. eR 20 mA Operating free air temperature range Ta C suffix 0 to 70 SUFIX 40 to 85 Storage temperature range stg xe x ask ERAT ei Cam RDUM AU cor 65 to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds P package 260 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTE 1 All voltage values except differential voltages are with respect to the network ground terminal recommended operating conditions UNIT Supply voltage see clock operating conditions 27 3 3 3 6 Clock frequency e B 3 3 V 10 600 Clock duty cycle see Note 2 40 60 Pulse duration CS high twH CS Setup time CS low or TLV0832 data valid before CLKT tsu Hold time TLV0832 data valid after th 9 ns 40 85 C suffix Operating free air temperature TA suffix NOTE 2 The clock duty cycle range ensures proper operation at all clock frequencies When a clock fr
2. CL 10pF 10kQ 80 125 tdis Output disable time DO after CST OL 100pF RL 2ka 250 ns t Conversion time multiplexer addressing clock ime not included periods parameters are measured under open loop conditions with zero common mode input voltage For conditions shown as MIN MAX use the appropriate value specified under recommended operating conditions NOTES 5 Total unadjusted error includes offset full scale linearity and multiplexer errors 6 The MSB first data is output directly from the comparator and therefore requires additional delay to allow for comparator response time LSB first data applies only to TLV0832 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 TLV0831C TLV08311 TLV0832C TLV0832I 3 VOLT 8 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS148 SEPTEMBER 1996 PARAMETER MEASUREMENT INFORMATION gt tsu lt su Vcc Vcc CLK 50 GND 2V OW Vcc Bi X 0 4 V 04V _ GND Figure 2 Data Output Timing Figure 1 TLV0832 Data Input Timing Vcc Test 1 9 Point N From Output RL e Under Test lt CL 52 N see Note A LOAD CIRCUIT 4 tr gt lt tr cs 50 9096 50 Z 90 10 GND 10 _ GND lt tis lt P 51 90 ro S2 closed 109 Output 750958 GND Output __820 GND VOLTAGE WAVEFORMS VOLTAG
3. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used TI s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1998 Texas Instruments Incorporated
4. 32 64 96 128 160 192 224 256 Output Code Figure 11 Differential Nonlinearity With Output Code T Vref 3 3 V TA 25 C F CLK lt 250 kHz 3 3 V 0 32 64 96 128 160 192 224 256 Output Code Figure 12 Integral Nonlinearity With Output Code Vref 3 3 V TA 25 F CLK z 250 kHz 0 32 64 96 128 160 192 224 256 Output Code Figure 13 Total Unadjusted Error With Output Code 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements
5. multiplexer addressing interval and DO is still in the high impedance state 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 TLV0831C TLV08311 TLV0832C TLV0832I 3 VOLT 8 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS148 SEPTEMBER 1 sequence of operation TLV0831 TC CODE TLV0832 1 2 3 4 5 10 11 12 13 14 18 19 20 21 T DIF EVEN 46 Data lt LSB First Data MUX Settling Time TLV0832 MUX ADDRESS CONTROL LOGIC TABLE MUX ADDRESS CHANNEL NUMBER SGL DIF ODD EVEN CHO CH1 L L L H H L H H n 2 vel L low level terminal polarity for the selected input chan 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV0831C TLV08311 TLV0832C TLV0832l 3 VOLT 8 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS148 SEPTEMBER 1996 absolute maximum ratings over recommended operating free air temperature range unless otherwise noted t Supply voltage Vac see Note 1 6 5 V Input voltage range Vj Logic 0 3 V to 0 3 V Analog R sete date 0 3 V to 0 3 V Input curtent olen 5
6. 1 TLV0832C TLV0832I 3 VOLT 8 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS148 SEPTEMBER 1996 TYPICAL CHARACTERISTICS TLV0831 SUPPLY CURRENT vs FREE AIR TEMPERATURE TLV0831 SUPPLY CURRENT vs CLOCK FREQUENCY 0 5 0 4 lt lt I 03 5 5 5 gt gt 5 S 02 o o 1 0 1 0 50 25 0 25 50 75 100 0 TA Free Air Temperature C Figure 8 OUTPUT CURRENT vs FREE AIR TEMPERATURE 100 200 300 400 500 f cLK Clock Frequency kHz Figure 9 loL DO loH DO 0 V lo Output Current mA loH DO 2 4 V 25 0 25 50 75 TA Free Air Temperature Figure 10 35 TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 100 Differential Nonlinearity LSB Integral Nonlinearity LSB Total Unadjusted Error LSB TLV0831C TLV08311I TLV0832C TLV0832l 3 VOLT 8 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS148 SEPTEMBER 1996 TYPICAL CHARACTERISTICS MARAA AAR A LA AAA ANANA UM MU V LEER UU PUN UV UNT VE MUR IM TW UWY Vref 3 3 V 25 C F CLK 250 kHz 3 3 V 0
7. E WAVEFORMS NOTE includes probe and jig capacitance Figure 3 Output Disable Time Test Circuit and Voltage Waveforms 35 TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 Eo unadj Unadjusted Offset Error LSB E Linearity Error LSB TLV0831C TLV08311I TLV0832C TLV0832l 3 VOLT 8 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS148 SEPTEMBER 1996 TYPICAL CHARACTERISTICS UNADJUSTED OFFSET ERROR vs REFERENCE VOLTAGE 16 Vi V 0V 14 12 m o 10 8 S 5 I 4 2 0 0 01 0 1 1 0 10 Vref Reference Voltage V Figure 4 LINEARITY ERROR vs FREE AIR TEMPERATURE 0 5 2 0 1 8 0 45 1 6 Q 14 I 0 4 5 12 a o 0 35 08 i 0 6 u 0 3 0 4 0 2 0 25 50 25 0 25 50 TA Free Air Tempertature C 6 75 100 35 TEXAS INSTRUMENTS LINEARITY ERROR vs REFERENCE VOLTAGE 3 3 f CLK 250 kHz TA 25 Vref Reference Voltage V Figure 5 LINEARITY ERROR vs CLOCK FREQUENCY Vref 3 3 V 3 3 V 85 25 40 C 0 100 200 300 400 500 600 700 800 Clock Frequency kHz Figure 7 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 9 TLV0831C TLV0831
8. K Start Flip Flop Shift Register gt CLK ODD EVEN TLV0832 _ A lt 1 5 19 M gt CLK T 4 4 e To Internal Circuits gt SGL DIF CEK Mra CH0 IN Analog Comparator Time R CH1 IN MUX Delay EN EN ner Ladder TLV0831 L only 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV0831C TLV08311 TLV0832C TLV0832l 3 VOLT 8 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS148 SEPTEMBER 1996 functional description TLV0831 and TLV0832 use sample data comparator structure that converts differential analog inputs by a successive approximation routine The input voltage to be converted is applied to an input terminal and is compared to ground single ended or to an adjacent input differential The TLV0832 input terminals can be assigned a positive or negative polarity The TLV0831 contains only one differential input channel with fixed polarity assignment therefore it does not require addressing The signal can be applied differentially between IN and IN to the TLV0831 or can be applied to IN with IN grounded as a single ended input When the signal input applied to the assigned positive terminal is less than the signal on the negative terminal the converter output is all zeros Chan
9. TLV 083144 TLV0831C TLV08311 TLV0832C TLV0832I 3 VOLT 8 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS148 SEPTEMBER 1996 8 Bit Resolution TLV0831 D OR P PACKAGE e 2 7Vt03 6 V Vcc VIEW Easy Microprocessor Interface or Standalone Operation Ratiometrically or With Reference Single Channel or Multiplexed Twin Channels With Single Ended or Differential Input Options Input Range 0 V to Vcc With Vcc Reference Inputs and Outputs Are Compatible With CS 1 8 TTL and MOS CHO 2 7 CLK Conversion Time of 32 us at CH1 3 6 DO f CLK 250 kHz GND 4 5 DI Designed to Be Functionally Equivalent to the National Semiconductor ADC0831 and ADC0832 at 3 V Supply Total Unadjusted Error 1 LSB TLV0832 D OR P PACKAGE TOP VIEW description These devices are 8 bit successive approximation analog to digital converters The TLV0831 has single input channels the TLV0832 has multiplexed twin input channels The serial output is configured to interface with standard shift registers or microprocessors The TLV0832 multiplexer is software configured for single ended or differential inputs The differential analog voltage input allows for common mode rejection or offset of the analog zero input voltage value In addition the voltage reference input can be adjusted to allow encoding any smaller analog voltage sp
10. an to the full 8 bits of resolution The operation of the TLV0831 and TLV0832 devices is very similar to the more complex TLV0834 and TLV0838 devices Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input signal value which gives the highest possible conversion resolution Typically REF is set equal to Vcc done internally on the TLV0832 The TLV0831C TLV0832C are characterized for operation from 0 C to 70 C The TLV08311 and TLV0832 are characterized for operation from 40 to 85 AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE PLASTIC DIP D P 0 C to 70 TLV0831CD TLV0832CD 0831 TLV0832CP 40 C to 85 C TLV0831ID TLV0832ID TLV0831IP TLV0832IP Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright 1996 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments soi ofall para Production processing does not necessarily include 4 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 TLV0831C TLV08311 TLV0832C TLV0832l 3 VOLT 8 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS148 SEPTEMBER 1996 functional block diagram CL
11. equency is used outside the recommended duty cycle range the minimum pulse duration high or low is 1 us 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 TLV0831C TLV08311 TLV0832C TLV0832l 3 VOLT 8 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS148 SEPTEMBER 1996 electrical characteristics over recommended range of operating free air temperature 3 3 V 250 kHz unless otherwise noted digital section C SUFFIX High level output source current High impedance state output 02 current DO Ci Input capacitance Output capacitance T Al parameters are measured under open loop conditions with zero common mode input voltage t All typical values are at 3 3 V TA 25 analog and converter section PARAMETER TEST CONDITIONST MIN UNIT 0 05 VIC Common mode input voltage to V 0 05 uA an Input current see Note soo ri REF Input resistance to REF 1 3 24 5 9 T All parameters are measured under open loop conditions with zero common mode input voltage t All typical values are at 3 3 V TA 25 NOTES 3 When channel is more positive than channel IN the digital output code is 0000 0000 Connected to each analog input are two on chip diodes that conduct forward current for analog input voltages one diode drop above Vcc Care must be taken during testing at low Vcc
12. levels 3 V because high level analog input voltage 3 6 V can especially at high temperatures cause the input diode to conduct and cause errors for analog inputs that are near full scale As long as the analog voltage does not exceed the supply voltage by more than 50 mV the output code is correct To achieve an absolute 0 to 3 3 V input range requires a minimum of 3 25 V for all variations of temperature and load 4 Standby input currents go in or out of the on or off channels when the A D converter is not performing conversion and the clock is in a high or low steady state conditions total device PARAMETER MIN MAX UNIT TLV0831 0 2 0 75 Supply current mA TLV0832 1 5 2 5 m t All typical values are at Vcc 3 3 V TA 25 35 TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TLV0831C TLV08311 TLV0832C TLV0832l 3 VOLT 8 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS148 SEPTEMBER 1996 operating characteristics Vref 3 3 V fici 250 kHz tr tr 20 ns TA 25 C unless otherwise noted PARAMETER TEST CONDITIONST MIN T MAX UNIT Supply voltage variation error 3 1 3 6 116 1 4 LSB Vref 3 8 V Total unadjusted error see Note 5 T to MAX NEN LSB YP Propagation delay time MSB first data 200 80 tod output data after CLKT 100 pF i 500 see Note 6 LSB first data 200 250
13. n followed by address information TLV0832 input configuration is assigned during the multiplexer addressing sequence The multiplexer address shifts into the converter through the data input DI line The multiplexer address selects the analog inputs to be enabled and determines whether the input is single ended or differential When the input is differential the polarity of the channel input is assigned In addition to selecting the differential mode the polarity may also be selected Either channel of the channel pair may be designated as the negative or positive input On each low to high transition of the clock input the data on DI is clocked into the multiplexer address shift register The first logic high on the input is the start bit A 2 bit assignment word follows the start bit on the TLV0832 On each successive low to high transition of the clock input the start bit and assignment word are shifted through the shift register When the start bit is shifted into the start location of the multiplexer register the input channel is selected and conversion starts The TLV0832 DI terminal to the multiplexer shift register is disabled for the duration of the conversion TLV0832 outputs the least significant bit LSB first data after the MSB first data stream The DI and DO terminals can be tied together and controlled by a bidirectional processor bit received on a single wire This is possible because DI is only examined during the
14. nel selection and input configuration are under software control using a serial data link from the controlling processor A serial communication format allows more functions to be included in a converter package with no increase in size In addition it eliminates the transmission of low level analog signals by locating the converter atthe analog sensor and communicating serially with the controlling processor This process returns noise free digital data to the processor A conversion is initiated by setting CS low which enables all logic circuits CS must be held low for the complete conversion process A clock input is then received from the processor An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle DO comes out of the high impedance state and provides leading low for one clock period of multiplexer settling time The SAR comparator compares successive outputs from the resistive ladder with the incoming analog signal The comparator output indicates whether the analog input is greater than or less than the resistive ladder output As the conversion proceeds conversion data is simultaneously output from DO with the most significant bit MSB first After eight clock periods the conversion is complete When CS goes high all internal registers are cleared At this time the output circuits go to the high impedance state If another conversion is desired CS must make a high to low transitio

TEXAS INSTRUMENTS TLV0831C TLV0831I TLV0832C TLV0832I

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