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MICROCHIP PIC10F200/202/204/206 Data Sheet (1)

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1. FIGURE 3 2 PIC10F204 206 BLOCK DIAGRAM SE 8 GPIO Data Bus Flash lt Program Counter lt 512 x12 or GPO ICSPDAT CIN 256 x12 UL S4 GP1 ICSPCLKICIN Ge 2 a e Los GP2 TOCKI COUT FOSC4 Stack 1 or rt AC Memory bytes GP3 MCLR VPP Stack 2 d File Registers Program 12 Bus RAM Addr 9 Instruction Reg Addr MUX i 5 Indirect Direct Addr Addr FSR Reg gt STATUS Reg 8 3 Device Reset Timer E Instruction Power on Seer wem DON x6 Watchdog 8 Timing Timer ya c Generation Internal RC W Reg Clock CIN TimerO Comparator YA MCLR X cin VDD Vss L pN cour 2007 Microchip Technology Inc DS41239D page 11 PIC10F200 202 204 206 TABLE 3 2 PIC10F200 202 204 206 PINOUT DESCRIPTION Input Output Type Type GPO ICSPDAT CIN GPO TTL CMOS Bidirectional I O pin Can be software programmed for internal weak pull up and wake up from Sleep on pin change ICSPDAT ST CMOS In Circuit Serial Programming data pin CIN AN Comparator input PIC10F 204 206 only GP1 ICSPCLK CIN GP1 TTL CMOS Bidirectional I O pin Can be software programmed for internal weak pull up and wake up from Sleep on pin change ICSPCLK ST CMOS In Circuit Serial Pro
2. 8 Lead PDIP Example XXXXXXXX PIC10F202 XXXXXNNN I P es 07 o D YYWW o 0520 8 Lead 2x3 DFN Example XXX BEO Y WW 610 NN 17 Legend XX X Customer specific information Y Year code last digit of calendar year YY Year code last 2 digits of calendar year WW Week code week of January 1 is week 01 NNN Alphanumeric traceability code e3 Pb free JEDEC designator for Matte Tin Sn i This package is Pb free The Pb free JEDEC designator 63 can be found on the outer packaging for this package o Note In the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for product specific information Ge eeoa l 2007 Microchip Technology Inc DS41239D page 81 PIC10F200 202 204 206 TABLE 14 1 8 LEAD 2x3 DFN MC TOP TABLE 14 2 6 LEAD SOT 23 OT MARKING PACKAGE TOP MARKING Part Number Marking Part Number Marking PIC10F200 I MC BAO PIC10F200 VOT OONN PIC10F200 E MC BBO PIC10F200 E OT OONN PIC10F202 VMC BCO PIC10F202 VOT 02NN PIC10F202 E MC BDO PIC10F202 E OT 02NN PIC10F204 I MC BEO PIC10F204 VOT 04NN PIC10F204 E MC BFO PIC10F204 E OT 04NN PIC10F206 I MC BGO PIC10F206 VOT
3. Standard Operating Conditions unless otherwise specified DO CHARACTERISTIC Operating Temperature 40xC lt TA lt 85 C industrial ee Sym Characteristic Min Typ Max Units Conditions D001 VDD Supply Voltage 2 0 5 5 V See Figure 12 1 D002 VDR RAM Data Retention Voltage 1 5 V Device in Sleep mode D003 VPOR VDD Start Voltage Vss V to ensure Power on Reset D004 SVDD VDD Rise Rate 0 05 Vims to ensure Power on Reset IDD Supply Current D010 175 275 pA VDD 2 0V 0 63 1 1 mA VDD 5 0V IPD Power down Current D020 0 1 1 2 pA VDD 2 0V 0 35 2 4 NA VDD 5 0V IWDT WDT Current D022 1 0 3 pA VDD 2 0V 7 16 NA VDD 5 0V ICMP Comparator Current D023 12 23 NA VDD 2 0V 44 80 pA VDD 5 0V IVREF Internal Reference Current 6 D024 85 115 pA VDD 2 0V 175 195 pA VDD 5 0V These parameters are characterized but not tested Note 1 Data in the Typical Typ column is based on characterization results at 25 C This data is for design guidance only and is not tested 2 This is the limit to which VDD can be lowered in Sleep mode without losing RAM data 3 The supply current is mainly a function of the operating voltage and frequency Other factors such as bus loading bus rate internal code execution pattern and temperature also have an impact
4. OPTION FIGURE 6 5 BLOCK DIAGRAM OF THE TIMERO WDT PRESCALER Tcy Fosc 4 Data Bus 0 GP2 TOCKI M Pin U t al M Sync U Em 2 gt TMPO Reg P E of X Cycles TOSE Tocs Psa 0 M 8 bit Prescaler U X 1 Watchdog 84 Timer 8 to 1 MUX lt PS lt 2 0 gt 1 PSA 0 ay WDT Enable bit MUX la PSAM Y WDT Time out Note 1 TOCS TOSE PSA PS lt 2 0 gt are bits in the OPTION register 2 TOCKI is shared with pin GP2 on the PIC10F200 202 204 206 AAA A AAA eee DS41239D page 32 O 2007 Microchip Technology Inc PIC10F200 202 204 206 7 0 TIMERO MODULE AND TMRO REGISTER PIC10F204 206 The TimerO module has the following features 8 bit timer counter register TMRO Readable and writable 8 bit software programmable prescaler Internal or external clock select Edge select for external clock External clock from either the TOCKI pin or from the output of the comparator Figure 7 1 is a simplified block diagram of the TimerO module Timer mode is selected by clearing the TOCS bit OPTION lt 5 gt In Timer mode the TimerO module will increment every instruction cycle without prescaler If TMRO register is written the increment is inhibited for the following two cycles Figure 7 2 and Figure 7 3 The user can work around this by writing an adjusted value to the TMRO register There are two types of Counter mode The first Cou
5. FIGURE 6 3 TIMERO TIMING INTERNAL CLOCK PRESCALE 1 2 E Q1 02 03 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 as Q1 Q2 Q3 Q4 AN a2Jas Q4 Q1 Q2 Q3 as AN AZ AZ as Q1 Q2 Q3 Q4 rogram i 1 i 1 1 1 1 1 Counter PC 1 X PC X PC 1 Y PC 2 Y PC 3 Y PC 4 Y PC 5 Y PC 6 Instruction MOVWE TMRO MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVE TMRO W Timero T0 X Tr EE NTO YA NTOH1K Instruction 4 4 i 4 4 4 4 Executed Write TMRO Read TMRO Read TMRO Read TMRO Read TMRO Read TMRO executed reads NTO reads NTO reads NTO reads NTO 1 reads NTO 2 TABLE 6 1 REGISTERS ASSOCIATED WITH TIMERO Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit2 Bit1 Bit O Power On All Other Reset Resets 01h TMRO TimerO 8 bit Real Time Clock Counter XXXX XXXX UUUU uuuu N A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 N A TRISGPIO VO Control Register 1111 1111 Legend Shaded cells not used by TimerO unimplemented x unknown u unchanged Note 1 The TRIS of the TOCKI pin is overridden when TOCS 1 6 1 Using Timer0 with an External 6 1 1 EXTERNAL CLOCK Clock PIC10F200 202 When an external clock input is used for TimerO it must meet certain requirements The external clock require ment is due to internal phase clock Tosc synchroniza tion Also there is a delay in the actual incrementing of TimerO after
6. These parameters are characterized but not tested Note 1 Data in the Typical Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested FIGURE 12 4 TIMERO CLOCK TIMINGS PIC10F200 202 204 206 TOCKI JJ Y 2 d ge 41 B lt 42 gt TABLE 12 5 TIMERO CLOCK REQUIREMENTS PIC10F200 202 204 206 Standard Operating Conditions unless otherwise specified Operating Temperature 40 C lt TA lt 85 C industrial AC CHARACTERISTICS 40 C lt TA x 125 C extended Operating Voltage VDD range is described in Section 12 1 DC Characteristics ae Sym Characteristic Min Typ Max Units Conditions 40 TtOH TOCKI High Pulse No Prescaler 0 5 Tcv 20 ns Width With Prescaler 10 ns 41 TtOL TOCKI Low Pulse No Prescaler 0 5 Tcv 20 ns Width With Prescaler 10 ns 42 TtOP TOCKI Period Tcv 40 ns Whichever is greater 20 or N N Prescale Value 1 2 4 256 These parameters are characterized but not tested Note 1 Data in the Typical Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 2007 Microchip Technology Inc DS41239D page 71 PIC10F200 202 204 206 NOTES DS41239D page 72 2007 Microchip Technology Inc PIC10F200 202 204 2
7. TDRT DRT Time out Internal Reset FIGURE 9 4 TIME OUT SEQUENCE ON POWER UP MCLR TIED TO VDD FAST VDD RISE TIME VDD ga MCLR Internal POR TDRT X DRT Time out Internal Reset DS41239D page 44 2007 Microchip Technology Inc PIC10F200 202 204 206 FIGURE 9 5 TIME OUT SEQUENCE ON POWER UP MCLR TIED TO VDD SLOW VDD RISE TIME E ee VDD MCLR uu Internal POR TDRT gt DRT Time out Internal Reset Note When VDD rises slowly the TDRT time out expires long before VDD has reached its final value In this example the chip will reset properly if and only if V1 gt VDD min 2007 Microchip Technology Inc DS41239D page 45 PIC10F200 202 204 206 9 5 Device Reset Timer DRT On the PIC10F200 202 204 206 devices the DRT runs any time the device is powered up The DRT operates on an internal oscillator The processor is kept in Reset as long as the DRT is active The DRT delay allows VDD to rise above VDD min and for the oscillator to stabilize The on chip DRT keeps the devices in a Reset condition for approximately 18 ms after MCLR has reached a logic high VIH MCLR level Programming GP3 MCLR VPP as MCLR and using an external RC network connected to the MCLR input is not required in most cases This allows savings in cost sensitive and or space restricted appli
8. Legend Shaded boxes Not used by Watchdog Timer unimplemented read as 0 u unchanged O 2007 Microchip Technology Inc DS41239D page 47 PIC10F200 202 204 206 9 7 Time out Sequence Power down and Wake up from Sleep Status Bits TO PD GPWUF CWUF The TO PD GPWUF and CWUF bits in the STATUS register can be tested to determine if a Reset condition has been caused by a power up condition a MCLR Watchdog Timer WDT Reset wake up on comparator change or wake up on pin change TABLE 9 5 TO PD GPWUF CWUF STATUS AFTER RESET CWUF GPWUF TO PD Reset Caused By 0 0 0 0 WDT wake up from Sleep 0 0 0 u WDT time out not from Sleep 0 0 1 0 MCLR wake up from Sleep 0 0 1 1 Power up 0 0 u u MCLR not during Sleep 0 1 1 0 Wake up from Sleep on pin change 1 0 1 0 Wake up from Sleep on comparator change Legend u unchanged x unknown unimplemented bit read as 0 g value depends on condition Note 1 The TO PD GPWUF and CWUF bits maintain their status u until a Reset occurs A low pulse on the MCLR input does not change the TO PD GPWUF or CWUF Status bits 9 8 Reset on Brown out FIGURE 9 8 BROWN OUT A Brown out Reset is a condition where device power PROTEC TIONSIRCUIT Z VDD dips below its minimum value but not to zero VDD and then recovers The device should be reset in the VDD event of a brown out R1 To
9. FIGURE 13 7 WDT TIME OUT vs VDD OVER TEMPERATURE NO PRESCALER 50 Typical Statistical Mean 25 C 451 Ne Max 125 C 2 A A Maximum Mean Worst Case Temp 36 40 C to 125 C ee ee umen bn E T ud nie Max 85 C i i Bee U a an eS ee E De up eie 30 25 Time ms 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 VDD V a AAA A aa DS41239D page 76 O 2007 Microchip Technology Inc PIC10F200 202 204 206 FIGURE 13 8 VoL vs loL OVER TEMPERATURE VDD 3 0V 0 8 Typical Statistical Mean 25 C 0 7 t Maximum Mean Worst Case Temp 30 1 EER ERGE oU EO RR 40 C to 125 C e Max 125 C AE ga e Ts EE M NU Mi uui NE E WT AE A omm E O gt 03l AAA Re An e Typical 25 C UU te 02 RE N TT Min Amt diem Cc eed EE tie sote 0 0 5 0 5 5 6 0 6 5 7 0 7 5 8 0 8 5 9 0 9 5 10 0 loL mA FIGURE 13 9 VoL vs lot OVER TEMPERATURE VDD 5 0V 0 45 Typical Statistical Mean 25 C 0 40 gt Maximum Mean Worst Case Temp 3o PUTT pn Tr 40 C to 125 C cx NS CI MEE ONDE a E Ede MD ee As 0 30 eere bn eden ETS M hor reer RE ER s 0 25 E o gt 0 20 0 15 0 10 0 05 0 00 5 0 5 5 6 0 6 5 7 0 7 5 8 0 8 5 9 0 9 5 10 0 loL mA
10. Reset 1 RD Port Note 1 See Table 3 2 for buffer type 2007 Microchip Technology Inc DS41239D page 25 PIC10F200 202 204 206 TABLE 5 2 SUMMARY OF PORT REGISTERS Value on Value oi Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit3 Bit2 Bit1 BitO Power On neo All Other Resets Reset N A TRISGPIO 1 0 Control Register eee KSE 1111 N A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 03h STATUS GPWUF CWUF TO PD Z DC C 00 1 1xxx da q guuu 2 06h GPIO GP3 GP2 GP1 GPO xxxx UUUU Legend Shaded cells are not used by PORT registers read as 0 unimplemented read as 0 x unknown u unchanged q 7 depends on condition Note 1 If Reset was due to wake up on pin change then bit 7 1 All other Resets will cause bit 7 0 2 If Reset was due to wake up on comparator change then bit 6 1 All other Resets will cause bit 6 0 5 4 VO Programming Considerations EXAMPLE 5 1 READ MODIFY WRITE INSTRUCTIONS ON AN 5 4 1 BIDIRECTIONAL I O PORTS 1 O PORT Some instructions operate internally as read followed Initial GPIO Settings by write operations The BCF and BsF instructions for GPIO 3 2 Inputs example read the entire port into the CPU execute the bit operation and rewrite the result Caution must be Y A gt G
11. Default is d 1 label Label name TOS Top of Stack PC Program Counter WDT Watchdog Timer counter TO Time out bit PD Power down bit dest Destination either the W register or the specified register file location bod Options GI Contents gt Assigned to lt gt Register bit field In the set of All instructions are executed within a single instruction cycle unless a conditional test is true or the program counter is changed as a result of an instruction In this case the execution takes two instruction cycles One instruction cycle consists of four oscillator periods Thus for an oscillator frequency of 4 MHz the normal instruction execution time is 1 us If a conditional test is true or the program counter is changed as a result of an instruction the instruction execution time is 2 us Figure 10 1 shows the three general formats that the instructions can have All examples in the figure use the following format to represent a hexadecimal number Oxhhh where h signifies a hexadecimal digit FIGURE 10 1 GENERAL FORMAT FOR INSTRUCTIONS Byte oriented file register operations 11 6 5 4 0 OPCODE d f FILE d 0 for destination W d 1 for destination f f 5 bit file register address Bit oriented file register operations 11 87 54 0 OPCODE b BIT Ff FILE 3 bit address 5 bit file register address bz
12. FIGURE 13 3 MAXIMUM IPD vs VDD SLEEP MODE ALL PERIPHERALS DISABLED 18 0 16 0 Typical Statistical Mean 25 C Maximum Mean Worst Case Temp 3c 40 C to 125 C 14 0 Max 125 C 12 0 GEREED RE ec PD N 10 0 IPD uA 8 0 6 0 4 0 2 0 0 0 4 0 5 0 5 5 VDD V 2 0 2 5 3 0 3 5 4 5 d DS41239D page 74 2007 Microchip Technology Inc PIC10F200 202 204 206 FIGURE 13 4 COMPARATOR IPD vs VDD COMPARATOR ENABLED 80 Typical Statistical Mean 25 C Etpe p Be EDD Maximum Mean Worst Case Temp 3c Maximum 1 40 4o 125C i IPD uA 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 VDD V FIGURE 13 5 TYPICAL WDT IPD vs VDD 9 8 4 Typical Statistical Mean 25 C E pee pL p yl Maximum Mean Worst Case Temp 30 7 4 40 C to 125 C bones sales ET Ar ewe ue 6 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 2007 Microchip Technology Inc DS41239D page 75 PIC10F200 202 204 206 FIGURE 13 6 MAXIMUM WDT IPD vs VDD OVER TEMPERATURE Typical Statistical Mean 25 C Maximum Mean Worst Case Temp 3c 40 C to 125 C 20 0 Max 125 C 45 0 AAA N EE EE AAA RT aom IPD uA Max 85 C a het bee 0 0 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 VDD V
13. abel CALL k 0 lt k lt 255 PC 13 Top of Stack k gt PC lt 7 0 gt STATUS lt 6 5 gt gt PC lt 10 9 gt 0 gt PC lt 8 gt None Subroutine call First return address PC 1 is PUSHed onto the stack The eight bit immediate address is loaded into PC bits lt 7 0 gt The upper bits PC lt 10 9 gt are loaded from STATUS lt 6 5 gt PC lt 8 gt is cleared CALL is a two cycle instruction Clear f label CLRF f O lt f lt 31 00h gt f 1 gt Z Z The contents of register f are cleared and the Z bit is set CLRW Syntax Operands Operation Status Affected Description CLRWDT Syntax Operands Operation Status Affected Description COMF Syntax Operands Operation Status Affected Description Clear W label CLRW None 00h gt W 127 Z The W register is cleared Zero bit Z is set Clear Watchdog Timer label CLRWDT None 00h gt WDT 0 WDT prescaler if assigned 1 TO 1 PD TO PD The CLRWDT instruction resets the WDT It also resets the prescaler if the prescaler is assigned to the WDT and not Timer0 Status bits TO and PD are set Complement f label COMF fd 0 lt f lt 31 d e 0 1 f gt dest Z The contents of register f are complemented If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f DS41239D page 54 2007 Microchip T
14. Power Down Mode Sleep for more details Subtract W from f label SUBWF fd 0 lt f lt 31 d e 0 1 f W gt dest C DC Z Subtract 2 s complement method the W register from register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f Swap Nibbles in f label SWAPF f d 0O lt f lt 31 d e 0 1 f lt 3 0 gt gt dest lt 7 4 gt f lt 7 4 gt gt dest lt 3 0 gt None The upper and lower nibbles of register f are exchanged If d is 0 the result is placed in W register If d is 1 the result is placed in register f 2007 Microchip Technology Inc DS41239D page 57 PIC10F200 202 204 206 TRIS Syntax Operands Operation Status Affected Description XORLW Syntax Operands Operation Status Affected Description Load TRIS Register XORWF label TRIS f Syntax f 6 Operands W gt TRIS register f None Operation TRIS register f f 6 or 7 is Status Affected loaded with the contents of the W D ee escription register Exclusive OR literal with W label XORLW k 0 lt k lt 255 W XOR k gt W Z The contents of the W register are XOR ed with the eight bit literal K The result is placed in the W register Exclusive OR W with f label XORWF fid 0 lt f lt 31 d e 0 1 W XOR f dest Z Exclusive OR the c
15. To change the prescaler from the WDT to the TimerO module use the sequence shown in Example 7 2 This sequence must be used even if the WDT is disabled A CLRWDT instruction should be executed before switching the prescaler 2007 Microchip Technology Inc DS41239D page 35 PIC10F200 202 204 206 EXAMPLE 7 2 CHANGING PRESCALER WDT TIMERO CLRWDT Clear WDT and prescaler MOVLW xxxx0xxx Select TMRO new prescale value and clock source OPTION FIGURE 7 5 BLOCK DIAGRAM OF THE TIMERO WDT PRESCALER GP2 TOCKI 2 Pin Tcv Fosc 4 Dx Data Bus 0 te m xc Z Comparator 1 M Sync Output U Em 2 gt TMPO Reg 10 Ki of X Cycles 1 TOSE Tocs PSA CMPTOCS 0 i M 8 bit Prescaler U X 1 Watchdog 8 Timer 8 to 1 MUX Le PS lt 2 0 gt 1 PSA 9 0 1 WDT Enable bit MUX 4 PSA Y WDT Time out Note 1 TOCS TOSE PSA PS lt 2 0 gt are bits in the OPTION register 2 TOCKI is shared with pin GP2 3 Bit CMPTOCS is located in the CMCONO register DS41239D page 36 2007 Microchip Technology Inc PIC10F200 202 204 206 8 0 COMPARATOR MODULE The comparator module contains one Analog comparator The inputs to the comparator are multiplexed with GPO and GP1 pins The output of the c
16. The prescaler is not readable or writable When the prescaler is assigned to the TimerO module prescale values of 1 2 1 4 1 256 are selectable Section 6 2 Prescaler details the operation of the prescaler A summary of registers associated with the TimerO module is found in Table 6 1 FIGURE 6 1 TIMERO BLOCK DIAGRAM Data Bus GP2 TOCKI Fosc 4 0 Pin PSOUT 8 Dx Sync with t internal TMRO Reg E Programmable Clocks PSOUT Prescaler Sync TOSE 2 Tcv delay SY 3 PS2 PS1 PS0 psa Tocs Note 1 Bits TOCS TOSE PSA PS2 PS1 and PSO are located in the OPTION register 2 The prescaler is shared with the Watchdog Timer Figure 6 5 FIGURE 6 2 TIMERO TIMING INTERNAL CLOCK NO PRESCALE e 01 02 03 04 01 02 03 04 Q1 Q2 Q3 as Q1 Q2 Q3 Q4 Q1 Q2 Q3 24 Q1 Q2 Q3 Q4 Q1 Q2 Q3 24 olozloalou rogram i 1 1 1 1 1 1 Counter PC 1 Y PC V PC 1 Y PC 2 Y PC 3 Y PC 4 Y PC 5 X PC 6 EEN MOVWF TMRO MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVF TMRO W TimerO C To Y TOET TO 2Y O NTO gt Y NTO 1X NTO 2K Instruction 4 4 4 E 4 4 Executed 3 d Write TMRO Read TMRO Read TMRO Read TMRO Read TMRO Read TMRO executed reads NTO reads NTO reads NTO reads NTO 1 reads NTO 2 2007 Microchip Technology Inc DS41239D page 29 PIC10F200 202 204 206
17. delay from the external clock edge to the timer incrementing FIGURE 6 4 TIMERO TIMING WITH EXTERNAL CLOCK External Clock Input or Prescaler Outputl2 Q11 Q21 Q31 Q4 Q11 AZI Q31 Q4 Q1I Q21 Q3 Q4 Q11 Q21 AZI Q4 Small pulse NX misses sampling External Clock Prescaler Output After Sampling Increment TimerO Q4 A A A TimerO TO X T0 1 y TO 2 Note 1 Delay from clock input change to TimerO increment is 3 Tosc to 7 Tosc Duration of Q Tosc Therefore the error in measuring the interval between two edges on Timer0 input 4 Tosc max 2 External clock if no prescaler selected prescaler output otherwise 3 The arrows indicate the points in time where sampling occurs 6 2 Prescaler An 8 bit counter is available as a prescaler for the TimerO module or as a postscaler for the Watchdog Timer WDT respectively see Section 9 6 Watch dog Timer WDT For simplicity this counter is being referred to as prescaler throughout this data sheet Note The prescaler may be used by either the TimerO module or the WDT but not both Thus a prescaler assignment for the TimerO module means that there is no prescaler for the WDT and vice versa The PSA and PS 2 0 bits OPTION lt 3 0 gt determine prescaler assignment and prescale ratio When assigned to the TimerO module all instructions writing to the TMRO register e g
18. 78 PIC 10F202 E P E nv fS MICROCHIP PIC10F200 202 204 206 Data Sheet 6 Pin 8 bit Flash Microcontrollers Note the following details of the code protection feature on Microchip devices Microchip products meet the specification contained in their particular Microchip Data Sheet Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets Most likely the person doing so is engaged in theft of intellectual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act If such acts allow unauthorized access to your software or other copyrighted work you may have a right to sue f
19. EET NEE CMM MMC C m C ccc cU GN CEN CENE CN NN CON 2007 Microchip Technology Inc DS41239D page 77 PIC10F200 202 204 206 FIGURE 13 10 VoH vs loH OVER TEMPERATURE VDD 3 0V 3 5 3 0 l fefe Bee fee eee Max 40 C i Typ 25 C 2 5 IA EH A PRO DO AE PUN ee D O penn E ER EE Min 125 C 2 0 p ed une esse ee Ee EE EE QI s rI o gt i 1 5 ped E peste emend EE parareman SEH SE Typical Statistical Mean 25 C 1 0 Maximum Mean Worst Case Temp 3o income EL ET de HER 40 C to 125 C elen bee ee bee bee bee ee bee bee 0 0 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 Jon mA FIGURE 13 11 Von vs loH OVER TEMPERATURE VDD 5 0V 5 5 5 0 Max 40 C es m A m Looe sies m Min 125 C VOH V EE E E dee ETT Typical Statistical Mean 25 C i 3 5 Maximum Mean Worst Case Temp 30 teen ae qM a exisse pea ae 40 C to 125 C 3 0 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 Jon mA EER ee ee ee J ee p DS41239D page 78 2007 Microchip Technology Inc PIC10F200 202 204 206 FIGURE 13 12
20. O6NN PIC10F206 E MC BHO PIC10F206 E OT O6NN Note NN represents the alphanumeric traceability code DS41239D page 82 2007 Microchip Technology Inc PIC10F200 202 204 206 6 Lead Plastic Small Outline Transistor OT SOT 23 Note Forthe most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging N 4 i E El d PIN 1 ID BY LASER MARK i 1 2 3L G e 1 D d e 1 I IW LJ Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 6 Pitch e 0 95 BSC Outside Lead Pitch el 1 90 BSC Overall Height A 0 90 1 45 Molded Package Thickness A2 0 89 1 30 Standoff A1 0 00 0 15 Overall Width E 2 20 3 20 Molded Package Width E1 1 30 1 80 Overall Length D 2 70 3 10 Foot Length L 0 10 0 60 Footprint L1 0 35 0 80 Foot Angle o 0 30 Lead Thickness c 0 08 0 26 Lead Width b 0 20 0 51 Notes 1 Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0 127 mm per side 2 Dimensioning and tolerancing per ASME Y14 5M BSC Basic Dimension Theoretically exact
21. Organization 2007 Microchip Technology Inc DS41239D page 23 PIC10F200 202 204 206 NOTES DS41239D page 24 2007 Microchip Technology Inc PIC10F200 202 204 206 5 0 1 0 PORT As with any other register the I O register s can be written and read under program control However read instructions eg MOVF GPIO W always read the I O pins independent of the pin s Input Output modes On Reset all VO ports are defined as input inputs are at high impedance since the I O control registers are all set 5 1 GPIO GPIO is an 8 bit I O register Only the low order 4 bits are used GP lt 3 0 gt Bits 7 through 4 are unimple mented and read as 0 s Please note that GP3 is an input only pin Pins GPO GP1 and GP3 can be config ured with weak pull ups and also for wake up on change The wake up on change and weak pull up functions are not pin selectable If GP3 MCLR is config ured as MCLR weak pull up is always on and wake up on change for this pin is not enabled 5 2 TRIS Registers The Output Driver Control register is loaded with the contents of the W register by executing the TRIS f instruction A 1 from a TRIS register bit puts the corre sponding output driver in a High Impedance mode A O puts the contents of the output data latch on the selected pins enabling the output buffer The excep tions are GP3 which is input only and the GP2 TOCKI COUT FOSCA pin which may be cont
22. Q4 AM AZ 03 as AM AZ Q3 as rogram i i i i i i i Counter PC 1 Y PC y Pcs1 y PC 2 Y PC 3 X PC 4 Y PCH X PC 6 Instruction MOVWF TMRO MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVE TMRO W MOVF TMRO W TimerO TO yY 70 17 YY TO 2Y NTO X Y NI NTO 2 XK Instruction 4 4 4 4 4 4 Executed Write TMRO Read TMRO Read TMRO Read TMRO Read TMRO Read TMRO executed reads NTO reads NTO reads NTO reads NTO 1 reads NTO 2 FIGURE 7 3 TIMERO TIMING INTERNAL CLOCK PRESCALE 1 2 len Q1 q2 a3 a4 A1 AZ AZ 24 Q1 Q2 Q3 as Q1 Q2 as Q4 AM AZ AZ Q4 Q1 a2 AZ as A1 AZ AZ as Q1 Q2 Q3 Q4 rogram i 1 1 1 1 1 1 1 Counter PC 1 Y PC y Pcs1 y PC 2 Y PC43 X PC 4 Y PC 5 X PC 6 Instructori MOVWF TMRO MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVF TMRO W Timeo 10 X T10 1 X 4 NI A INTIK Instruction 4 4 4 4 4 4 Executed wi Write TMRO Read TMRO Read TMRO Read TMRO Read TMRO Read TMRO executed reads NTO reads NTO reads NTO reads NTO 1 reads NTO 2 TABLE 7 1 REGISTERS ASSOCIATED WITH TIMERO Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Power On All Other Reset Resets 01h TMRO TimerO 8 bit Real Time Clock Counter XXXX XXXX uuuu uuuu 07h CMCONO CMPOUT COUTEN POL CMPTOCS CMPON CNREF CPREF CWU 1111 1111 uuuu uuuu N A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 N A TRISGPIO VO
23. Real Time Clock Counter xxxx xxxx 29 33 02h PCL Low order 8 bits of PC 1111 1111 22 03h STATUS GPWUF cWUF TO PD Z DC C 00 1 ixxx 19 04h FSR Indirect Data Memory Address Pointer 111x xxxx 23 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CALO FOSC4 1111 1110 21 06h GPIO GP3 GP2 GP1 GPO XXXX 25 07h CMCONO CMPOUT COUTEN POL CMPTOCS CMPON CNREF CPREF CWU 1111 1111 34 N A TRISGPIO 1 0 Control Register 1111 37 N A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PSO 1111 1111 20 Legend unimplemented read as 0 x unknown u unchanged g value depends on condition Note 1 The upper byte of the Program Counter is not directly accessible See Section 4 7 Program Counter for an explanation of how to access these bits 2 Other non Power up Resets include external Reset through MCLR Watchdog Timer and wake up on pin change Reset 3 See Table 9 1 for other Reset specific values 4 PIC10F204 206 only 5 PIC10F204 206 only On all other devices this bit is reserved and should not be used DS41239D page 18 2007 Microchip Technology Inc PIC10F200 202 204 206 4 4 STATUS Register This register contains the arithmetic status of the ALU the Reset status and the page preselect bit The STATUS register can be the destination for any instruction as with any other register If the STATUS register is the destination for an instruction tha
24. The PIC10F202 206 devices have a 2 deep 9 bit wide hardware PUSH POP stack A CALL instruction will PUSH the current value of Stack 1 into Stack 2 and then PUSH the current PC value incremented by one into Stack Level 1 If more than two sequential CALLs are executed only the most recent two return addresses are stored A RETLW instruction will POP the contents of Stack Level 1 into the PC and then copy Stack Level 2 contents into level 1 If more than two sequential RETLWs are executed the stack will be filled with the address previously stored in Stack Level 2 Note 1 The W register will be loaded with the lit eral value specified in the instruction This is particularly useful for the implementa tion of the data look up tables within the program memory 2 There are no Status bits to indicate stack overflows or stack underflow conditions 3 There are no instruction mnemonics called PUSH or POP These are actions that occur from the execution of the CALL and RETLW instructions DS41239D page 22 2007 Microchip Technology Inc PIC10F200 202 204 206 4 9 Indirect Data Addressing INDF and FSR Registers The INDF register is not a physical register Addressing INDF actually addresses the register whose address is contained in the FSR register FSR is a pointer This is indirect addressing 4 10 Indirect Addressing Register file 09 contains the value 10h Register file OA contain
25. f Literal and control operations except GOTO 11 8 7 0 OPCODE k literal k 8 bit immediate value Literal and control operations GOTO instruction 11 9 8 0 OPCODE k literal k 9 bit immediate value italics User defined term font is courier 2007 Microchip Technology Inc DS41239D page 51 PIC10F200 202 204 206 TABLE 10 2 INSTRUCTION SET SUMMARY Mnemonic Ie 12 Bit Opcode Status Description Cycles Notes Operands MSb LSp Affected ADDWF f d Add W and f 1 0001 11df ffff C DC Z 1 2 4 ANDWF f d AND W with f 1 0001 01df ffff Z 2 4 CLRF f Clear f 1 0000 O11f ffff Z 4 CLRW Clear W 1 0000 0100 0000 Z COMF f d Complement f 1 0010 Oldf ffff Z DECF f d Decrement f 1 0000 11df ffff Z 2 4 DECFSZ f d Decrementf Skip if O 10 0010 iidf ffff None 2 4 INCF f d Increment f 1 0010 10df ffff Z 2 4 INCFSZ f d__ Increment f Skip if O 10 0011 11d ffff None 2 4 IORWF f d Inclusive OR W with f 1 0001 00df ffff Z 2 4 MOVF f d Move f 1 0010 00df ffff Z 2 4 MOVWF f Move W tof 1 0000 001f ffff None 1 4 NOP No Operation 1 0000 0000 0000 None RLF f d Rotate left f through Carry 1 0011 Oldf ffff C 2 4 RRF f d Rotate right f through Carry 1 0011 00df ffff C 2 4 SUBWF f d Subtract W from f 1 0000 10df ffff C DC Z 1 2 4 SWAPF f d Swap f 1 0
26. from the state they were in at the last reading If a wake up on change occurs and the pins are not read before re entering Sleep a wake up will occur immediately even if no pins change while in Sleep mode Note The WDT is cleared when the device wakes from Sleep regardless of the wake up source 2007 Microchip Technology Inc DS41239D page 49 PIC10F200 202 204 206 9 10 Program Verification Code FIGURE 9 10 TYPICAL IN CIRCUIT Protection SERIAL PROGRAMMING If the code protection bit has not been programmed the CONNECTION on chip program memory can be read out for verification purposes l To Normal The first 64 locations and the last location Reset External Connections vector can be read regardless of the code protection Connector PIC10F20X bit setting Signals 5V VDD 9 11 ID Locations ov i Vss Four memory locations are designated as ID locations ae Mere where the user can store checksum or other code CLK GP4 identification numbers These locations are not 7 accessible during normal execution but are readable Data I O GPO and writable during Program Verify Use only the lower 4 bits of the ID locations and always i VDD program the upper 8 bits as 0s i S a To Normal 9 12 In Circuit Serial Programming Connections The PIC10F200 202 204 206 microcontrollers can be serially programmed while in the end a
27. instruction to be executed The PC value is increased by one every instruction cycle unless an instruction changes the PC For a GOTO instruction bits 8 0 of the PC are provided by the GOTO instruction word The Program Counter Low PCL is mapped to PC lt 7 0 gt For a CALL instruction or any instruction where the PCL is the destination bits 7 0 of the PC again are pro vided by the instruction word However PC 8 does not come from the instruction word but is always cleared Figure 4 5 Instructions where the PCL is the destination or modify PCL instructions include MOVWF PC ADDWF PC and BSF PC 5 Note Because PC lt 8 gt is cleared in the CALL instruction or any modify PCL instruction all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page 512 words long FIGURE 4 5 LOADING OF PC BRANCH INSTRUCTIONS GOTO Instruction PC PCL Instruction Word CALL or Modify PCL Instruction 87 0 PC PCL Instruction Word Reset to 0 4 7 1 EFFECTS OF RESET The PC is set upon a Reset which means that the PC addresses the last location in program memory i e the oscillator calibration instruction After executing MOVLW XX the PC will roll over to location 0000h and begin executing user code 4 8 Stack The PIC10F200 204 devices have a 2 deep 8 bit wide hardware PUSH POP stack
28. last character of the literature number is the version number e g DS30000A is version A of document DS30000 Errata An errata sheet describing minor operational differences from the data sheet and recommended workarounds may exist for current devices As device documentation issues become known to us we will publish an errata sheet The errata will specify the revision of silicon and revision of document to which it applies To determine if an errata sheet exists for a particular device please check with one of the following e Microchip s Worldwide Web site http www microchip com Your local Microchip sales office see last page The Microchip Corporate Literature Center U S FAX 480 792 7277 When contacting a sales office or the literature center please specify which device revision of silicon and data sheet include lit erature number you are using Customer Notification System Register on our web site at www microchip com cn to receive the most current information on all of our products 2007 Microchip Technology Inc DS41239D page 3 PIC10F200 202 204 206 NOTES DS41239D page 4 2007 Microchip Technology Inc PIC10F200 202 204 206 1 0 GENERAL DESCRIPTION 1 1 Applications The PIC10F200 202 204 206 devices from Microchip The PIC10F200 202 204 206 devices fit in applications Technology are low cost high performance 8 bit fully ranging from personal care appliances and security stat
29. or more operands which further specify the operation of the instruction The formats for each of the categories is presented in Figure 10 1 while the various opcode fields are summarized in Table 10 1 For byte oriented instructions f represents a file register designator and d represents a destination designator The file register designator specifies which file register is to be used by the instruction The destination designator specifies where the result of the operation is to be placed If d is 0 the result is placed in the W register If d is 1 the result is placed in the file register specified in the instruction For bit oriented instructions b represents a bit field designator which selects the number of the bit affected by the operation while f represents the number of the file in which the bit is located For literal and control operations k represents an 8 or 9 bit constant or literal value TABLE 10 1 OPCODE FIELD DESCRIPTIONS Field Description Register file address 0x00 to Ox7F Working register accumulator Literal field constant data or label f W b Bit address within an 8 bit file register k D Don t care location 7 0 or 1 The assembler will generate code with x 0 It is the recommended form of use for compatibility with all Microchip software tools d Destination select d 7 0 store result in W d 1 store result in file register
30. power dissipation un WA SAU IIR ED och ret oc Ind Muir Mei IO ACT Mies A Aca ZAC 800 mW Max current out Of MISS PIN RE EE EE ORE s EO plan RE EE a a ai eaa 80 mA Max cuirent into VDD Plica EE OE EG 80 mA Input clamp current lK VI lt 0 or VI gt Von 20 mA Output clamp current IOK VO lt 0 or Vo gt Von 20 mA Max output current sunk by any VO pin RR RR Ennan nnn 25 mA Max output current sourced by any VO pin sise 25 mA Max output current sourced by I O port sisi 75 mA Max output current sunk by I O port Note 1 Power dissipation is calculated as follows PDIS VDD x IDD Z lOH gt VDD VOH x lOH VOL x IOL TNOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 2007 Microchip Technology Inc DS41239D page 63 PIC10F200 202 204 206 FIGURE 12 1 PIC10F200 202 204 206 VOLTAGE FREQUENCY GRAPH 40 C x TA x 125 C 6 0 5 5 VDD Volts 0 4 10 20 25 Frequency MHz DS41239D page 64 2007 Microchip Technology Inc PIC10F200 202 204 206 12 1 DC Characteristics PIC10F200 202 204 206 Industrial
31. value shown without tolerances Microchip Technology Drawing C04 028B SSS SSS aa See 2007 Microchip Technology Inc DS41239D page 83 PIC10F200 202 204 206 8 Lead Plastic Dual In Line P 300 mil Body PDIP Note For the most current package drawings please see the Microchip Packaging Specification located at http Awww microchip com packaging N NOTE 1 7 E1 Z ZA ZI 1 2 3 Lg D lt E MH A2 d ME etl te b1 m b b H Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 100 BSC Top to Seating Plane A 210 Molded Package Thickness A2 115 130 195 Base to Seating Plane A1 015 Shoulder to Shoulder Width E 290 310 325 Molded Package Width E1 240 250 280 Overall Length D 348 365 400 Tip to Seating Plane L 115 130 150 Lead Thickness c 008 010 015 Upper Lead Width b1 040 060 070 Lower Lead Width b 014 018 022 Overall Row Spacing eB 430 Notes 1 Pin 1 visual index feature may vary but must be located with the hatched area S Significant Characteristic 2 3 Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 per side 4 Dimensioning and
32. 0 7 V loH 7 2 5 mA VDD 4 5V 40 C to 125 C Capacitive Loading Specs on Output Pins D101 All UO pins 50 pF Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested These parameters are for design guidance only and are not tested Note 1 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 2 Negative current is defined as coming out of the pin 3 This specification applies when GP3 MCLR is configured as an input with pull up disabled The leakage current of the MCLR circuit is higher than the standard UO logic 2007 Microchip Technology Inc DS41239D page 67 PIC10F200 202 204 206 TABLE 12 1 COMPARATOR SPECIFICATIONS Standard Operating Conditions unless otherwise stated Operating Temperature 40 C lt TA lt 125 C e Sym Characteristics Min Typt Max Units Comments D300 Vos Input Offset Voltage 5 0 10 mV VDD 1 572 D301 VCM Input Common Mode Voltage 0 Vpp 1 5 V D302 CMRR Common Mode Rejection Ratio 55 dB D303 TRT Response Time Falling 150 600 ns Note 1 Rising 200 1000 ns D304 TMc2coV Comparator Mode Change to 10 us Output Valid D305 Vivrf Internal Reference Volta
33. 011 10df ffff None 2 4 XORWF f d Exclusive OR W with f 1 0001 10df ffff Z 2 4 BIT ORIENTED FILE REGISTER OPERATIONS BCF fb Bit Clear f 1 0100 bbbf ffff None 2 4 BSF fb Bit Set f 1 0101 bbbf ffff None 2 4 BTFSC fb Bit Test f Skip if Clear 1 0110 bbbf ffff None BTFSS fb Bit Test f Skip if Set 10 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Call Subroutine 2 1001 kkkk kkkk None 1 CLRWDT Clear Watchdog Timer 1 0000 0000 0100 TO PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR literal with W 1 1101 kkkk kkkk Z MOVLW k Move literal to W 1 1100 kkkk kkkk None OPTION Load OPTION register 1 0000 0000 0010 None RETLW k Return place Literal in W 2 1000 kkkk kkkk None SLEEP Go into Standby mode 1 0000 0000 0011 TO PD TRIS f Load TRIS register 1 0000 0000 Offf None 3 XORLW k Exclusive OR literal to W 1 1111 kkkk kkkk Z Note 1 The 9th bit of the program counter will be forced to a 0 by any instruction that writes to the PC except for GOTO See Section 4 7 Program Counter 2 When an I O register is modified as a function of itself e g MOVF PORTB 1 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a 0 3 The instruction TRIS f where f 6 causes the contents of the W regis
34. 04 206 8 0 Comparator Module 9 0 Special Features of the CPU 10 0 Instruction Set Summary 11 0 Development SUpport 1 i Ded e aes cete tbe Er ere ec et ea teed Ee det ra dace 12 0 Electrical Characteristics i 13 0 DC and AC Characteristics Graphs and Tables seen 73 14 0 Packaging Informations eset dodo a ann The Microchip Web Site r ENEE ee d E Um COR at OE HE OR ERR Accu Customer Change Notification Service ES Customer SAPPE EER ER th Ae em NO GRA Eech OG DA ER ReaderiRespOnse EET Product Identification System RR TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Micro chip products To this end we will continue to improve our publications to better suit your needs Our publications will be refined and enhanced as new volumes and updates are introduced If you have any questions or comments regarding this publication please contact the Marketing Communications Department via E mail at docerrors mail microchip com or fax the Reader Response Form in the back of this data sheet to 480 792 4150 We welcome your feedback Most Current Data Sheet To obtain the most up to date version of this data sheet please register at our Worldwide Web site at http www microchip com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page The
35. 06 13 0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only The performance characteristics listed herein are not tested or guaranteed In some graphs or tables the data presented may be outside the specified operating range e g outside specified power supply range and therefore outside the warranted range Typical represents the mean of the distribution at 25 C Maximum or minimum represents mean 36 or mean 36 respectively where s is a standard deviation over each temperature range FIGURE 13 1 IDD vs VDD OVER Fosc IDD uA 1 400 1 200 1 000 800 600 400 Typical Statistical Mean 25 C Maximum Mean Worst Case Temp 30 40 C to 125 C ae er ees Cen E Maximum zz CS 40 nit Tisa 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 VDD V HH l DS41239D page 73 O 2007 Microchip Technology Inc PIC10F200 202 204 206 FIGURE 13 2 TYPICAL IPD vs VDD SLEEP MODE ALL PERIPHERALS DISABLED 0 45 0 35 0 30 0 25 IPD uA 0 20 0 15 0 10 0 05 0 40 Typical Statistical Mean 25 C Maximum Mean Worst Case Temp 3c 40 C to 125 C 0 0 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 VDD V
36. 1 128 can be assigned to the WDT under software control by writing to the OPTION register Thus a time out period of a nominal 2 3 seconds can be realized These peri ods vary with temperature VDD and part to part process variations see DC specs Under worst case conditions VDD Min Temperature Max max WDT prescaler it may take several seconds before a WDT time out occurs 9 6 2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the postscaler if assigned to the WDT and prevents it from timing out and generating a device Reset The SLEEP instruction resets the WDT and the postscaler if assigned to the WDT This gives the maximum Sleep time before a WDT wake up Reset DS41239D page 46 2007 Microchip Technology Inc PIC10F200 202 204 206 FIGURE 9 6 WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source Figure 6 5 0 Watchdog 1 y c z Postscaler Time M x 4 8 to 1 MUX Lag PS lt 2 0 gt WDT Enable PSA Configuration To Timer0 Figure 6 4 Bit 0 Y 1 T 4 PSA WDT Time out TABLE 9 4 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Address Name Bit 7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO Power On All Other Reset Resets N A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111
37. 2007 Microchip Technology Inc PIC10F200 202 204 206 4 6 OSCCAL Register The Oscillator Calibration OSCCAL register is used to calibrate the internal precision 4 MHz oscillator It contains seven bits for calibration Note Erasing the device will also erase the pre programmed internal calibration value for the internal oscillator The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later After you move in the calibration constant do not change the value See Section 9 2 2 Internal 4 MHz Oscillator REGISTER 4 3 OSCCAL REGISTER R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 0 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CALO FOSC4 bit 7 bit O Legend R Readable bit W Writable bit U Unimplemented bit read as n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 1 CAL lt 6 0 gt Oscillator Calibration bits 0111111 Maximum frequency 0000001 0000000 Center frequency 1111111 1000000 Minimum frequency bit O FOSC4 INTOSC 4 Output Enable bit 1 INTOSC 4 output onto GP2 0 GP2 TOCKI COUT applied to GP2 Note 1 Overrides GP2 TOCKI COUT control registers when enabled 2007 Microchip Technology Inc DS41239D page 21 PIC10F200 202 204 206 4 7 Program Counter As a program instruction is executed the Program Counter PC will contain the address of the next program
38. 206 9 0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other proces Sors are special circuits that deal with the needs of real time applications The PIC10F200 202 204 206 microcontrollers have a host of such features intended to maximize system reliability minimize cost through elimination of external components provide power saving operating modes and offer code protection These features are Reset Power on Reset POR Device Reset Timer DRT Watchdog Timer WDT Wake up from Sleep on pin change Wake up from Sleep on comparator change Sleep Code Protection ID Locations In Circuit Serial Programming TM The PIC10F200 202 204 206 devices have a Watch dog Timer which can be shut off only through Configu ration bit WDTE It runs off of its own RC oscillator for added reliability When using INTRC there is an 18 ms delay only on VDD power up With this timer on chip most applications need no external Reset circuitry The Sleep mode is designed to offer a very low current Power Down mode The user can wake up from Sleep through a change on input pins wake up from comparator change or through a Watchdog Timer time out 9 1 Configuration Bits The PIC10F200 202 204 206 Configuration Words consist of 12 bits Configuration bits can be pro grammed to select various device configurations One bit is the Watchdog Timer enable bit one bit is the MCLR enable bit and one bit is
39. 239D page 42 2007 Microchip Technology Inc PIC10F200 202 204 206 TABLE 9 2 RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr 03h PCL Addr 02h Power on Reset 00 1 1xxx MCLR Reset during normal operation 000u uuuu MCLR Reset during Sleep 0001 Ouuu WDT Reset during Sleep 0000 Ouuu WDT Reset normal operation 0000 uuuu Wake up from Sleep on pin change 1001 Ouuu Wake up from Sleep on comparator change 0101 Ouuu Legend u unchanged x unknown unimplemented bit read as 0 9 3 1 MCLR ENABLE The Power on Reset circuit and the Device Reset This Configuration bit when unprogrammed left in the 1 state enables the external MCLR function When programmed the MCLR function is tied to the internal VDD and the pin is assigned to be a VO See Figure 9 1 FIGURE 9 1 MCLR SELECT GPWU E o MCLRE GP3 MCLR VPP Internal MCLR 9 4 Power on Reset POR The PIC10F200 202 204 206 devices incorporate an on chip Power on Reset POR circuitry which provides an internal chip Reset for most power up situations The on chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper oper ation To take advantage of the internal POR program the GP3 MCLR VPP pin as MCLR and tie through a resistor to VDD or program the pin as GP3 An internal
40. 37 Configuration conan 38 AI LA 222 ru ae dee hi ER LE etes Operation Reference Configuration Bits Customer Change Notification Service 91 Customer Notification Service 91 Customer SUuDDort eem tm 91 D DC and AC Characteristics Graphs and Tables Development Support Digit Cathy ic EL CH e tga Suc E Errata ER chio bed At rh dete 3 F Family of Devices PIC10F200 202 204 206 c ooococccoccocccoconcconnonncnnncnnconnonnnns 5 VO Programming Considerations iese ee ee ee ee ID Locations annir Indirect Data Addressing Instruction Cycle Instruction Flow Pipelining Instruction Set Summary Internet Address iecore toten L oading Ro Ee 22 Memory Organization 15 Data Memory ns EE AR aient 16 Program Memory PIC10F200 204 15 Program Memory PIC10F202 206 16 Microchip Internet Web Site 91 MPLAB ASM30 Assembler Linker Librarian 60 MPLAB ICD 2 In Circuit Debugger 61 MPLAB ICE 2000 High Performance Universal In Circ it Emulator 5 EER ir iren 61 MPLAB ICE 4000 High Performance Universal In Circuit Emulator sees 61 MPLAB Integrated Development Environment Software 59 MPLAB PM3 Device Programmer 61 MPLINK Object Linker MPLIB Object Librarian 60
41. 39D page 61 PIC10F200 202 204 206 11 11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy to use low cost prototype programmer It connects to the PC via a COM RS 232 port MPLAB Integrated Development Environment software makes using the programmer simple and efficient The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins Larger pin count devices such as the PIC16C92X and PIC17C76X may be supported with an adapter socket The PICSTART Plus Development Programmer is CE compliant 11 12 PICkit 2 Development Programmer The PICkit 2 Development Programmer is a low cost programmer with an easy to use interface for pro gramming many of Microchip s baseline mid range and PIC 18F families of Flash memory microcontrollers The PICkit 2 Starter Kit includes a prototyping develop ment board twelve sequential lessons software and HI TECH s PICC Lite C compiler and is designed to help get up to speed quickly using PIC micro controllers The kit provides everything needed to program evaluate and develop applications using Microchip s powerful mid range Flash memory family of microcontrollers 11 13 Demonstration Development and Evaluation Boards A wide variety of demonstration development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully func tional systems Most boards incl
42. 91 80 4182 8400 Fax 91 80 4182 8422 India New Delhi Tel 91 11 4160 8631 Fax 91 11 4160 8632 India Pune Tel 91 20 2566 1512 Fax 91 20 2566 1513 Japan Yokohama Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Gumi Tel 82 54 473 4301 Fax 82 54 473 4302 Korea Seoul Tel 82 2 554 7200 Fax 82 2 558 5932 or 82 2 558 5934 Malaysia Penang Tel 60 4 646 8870 Fax 60 4 646 5086 Philippines Manila Tel 63 2 634 9065 Fax 63 2 634 9069 Singapore Tel 65 6334 8870 Fax 65 6334 8850 Taiwan Hsin Chu Tel 886 3 572 9526 Fax 886 3 572 6459 Taiwan Kaohsiung Tel 886 7 536 4818 Fax 886 7 536 4803 Taiwan Taipei Tel 886 2 2500 6610 Fax 886 2 2508 0102 Thailand Bangkok Tel 66 2 694 1351 Fax 66 2 694 1350 EUROPE Austria Wels Tel 43 7242 2244 39 Fax 43 7242 2244 393 Denmark Copenhagen Tel 45 4450 2828 Fax 45 4485 2829 France Paris Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Munich Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Milan Tel 39 0331 742611 Fax 39 0331 466781 Netherlands Drunen Tel 31 416 690399 Fax 31 416 690340 Spain Madrid Tel 34 91 708 08 90 Fax 34 91 708 08 91 UK Wokingham Tel 44 118 921 5869 Fax 44 118 921 5820 12 08 06 DS41239D page 94 2007 Microchip Technology Inc
43. CLRF 1 MOVWF 1 BSF 1 x etc will clear the prescaler When assigned to WDT a CLRWDT instruction will clear the prescaler along with the WDT The prescaler is neither readable nor writable On a Reset the prescaler contains all 0 s 6 2 1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control i e it can be changed on the fly during pro gram execution To avoid an unintended device Reset the following instruction sequence Example 6 1 must be executed when changing the prescaler assignment from TimerO to the WDT EXAMPLE 6 1 CHANGING PRESCALER TIMERO gt WDT CLRWDT Clear WDT CLRF TMRO Clear TMRO amp Prescaler MOVLW 00xx1111 b These 3 lines 5 6 7 OPTION jare required only if desired CLRWDT PPS 2 0 are 000 or 001 MOVLW 00xx1lxxx b Set Postscaler to OPTION desired WDT rate O 2007 Microchip Technology Inc DS41239D page 31 PIC10F200 202 204 206 To change the prescaler from the WDT to the TimerO EXAMPLE 6 2 CHANGING PRESCALER module use the sequence shown in Example 6 2 This WDT TIMERO seguence must be used even if the WDT is disabled A Br Clear WDT and CLRWDT instruction should be executed before pprescaler switching the prescaler MOVLW xxxx0xxx Select TMRO new prescale value and clock source
44. Control Register 2222 ITT 22 2 TERT Legend Shaded cells not used by TimerO unimplemented x unknown u unchanged Note 1 The TRIS of the TOCKI pin is overridden when TOCS 1 7 1 Using TimerO with an External Clock PIC10F204 206 When an external clock input is used for Timero it must meet certain requirements The external clock require ment is due to internal phase clock Tosc synchroniza tion Also there is a delay in the actual incrementing of TimerO after synchronization 7 1 1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used the external clock input is the same as the prescaler output The synchronization of an external clock with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks Figure 7 4 Therefore it is necessary for TOCKI or the comparator output to be high for at least 2 Tosc and a small RC delay of 2 TtOH and low for at least 2 Tosc and a small RC delay of 2 TtOH Refer to the electrical specification of the desired device When a prescaler is used the external clock input is divided by the asynchronous ripple counter type prescaler so that the prescaler output is symmetrical For the external clock to meet the sampling require ment the ripple counter must be taken into account Therefore it is necessary for TOCKI or the comparator output to have a period of at least 4 Tosc and a small RC delay of 4 T
45. ET WATCHDOG TIMER AND DEVICE RESET TIMER TIMING PIC10F200 202 204 206 Internal POR i 32 us DRT Timeout 2 Internal Reset Watchdog Timer i Reset D Note 1 UO pins must be taken out of High Impedance mode by enabling the output drivers in software 2 Runs on POR only ENE N EE EE NN _ _ _ _ _ _ _ _ A owW c ecc S ls DS41239D page 70 2007 Microchip Technology Inc PIC10F200 202 204 206 TABLE 12 4 RESET WATCHDOG TIMER AND DEVICE RESET TIMER PIC10F200 202 204 206 Standard Operating Conditions unless otherwise specified Operating Temperature 40 C lt TA lt 85 C industrial AC CHARACTERISTICS 40 C lt TA x 125 C extended Operating Voltage VDD range is described in Section 12 1 DC Characteristics in Sym Characteristic Min Typ Max Units Conditions 30 Tuc MCLR Pulse Width low 2 us VDD 5V 40 C to 85 C 5 us VDD 5 0V 31 TwDT Watchdog Timer Time out Period 10 16 29 ms VDD 5 0V Industrial no prescaler 10 16 31 ms VDD 5 0V Extended 32 TDRT Device Reset Timer Period stan 10 16 29 ms VDD 5 0V Industrial dard 10 16 31 ms VDD 5 0V Extended 34 Tioz l O High impedance from MCLR 2 us low
46. GPOJICSPDAT CIN De o 6 4 GP3 MCLR VPP N VSS 12 3 5 Vpb N LL GP1 ICSPCLK CIN gt 13 9 A4 GP2 TOCKI COUT FOSCA o D 8 Pin PDIP Pin Diagrams VL is umb N C apen a 8 GP3 MCLRIVeP e VDD 12 S 7 vss e E GP2 TOCK FOSC4 3 8 amp 8 Glas NIC e GPi ICSPCLK 4 5 5 GPO ICSPDAT D 7 nr NC lt 11 S 8 lt GP3 MCLRivep e voo gt 12 S 7 vss e GP2 TOCKI COUT FOSC4 13 D 6 NC e GP1 ICSPCLK CIN lt J4 GS 5 lt GPO ICSPDATICIN a 8 Pin DFN Pin Diagrams NIC gt 16 A 8 lt GP3 MCLR VPP N Vo e 2 S 7 vss N GP2 TOCKI FOSC4 u 6 NIC GP1 ICSPCLK P 4 2 pas GPO ICSPDAT NC ep lie 8 GP3 MCLRIVPP voo 2 7 a vss N GP2 TOCKI COUT FOSC4 lt gt S 6 4 NC GP1 ICSPCLK CIN 14 5 GPO ICSPDAT CIN DS41239D page 2 2007 Microchip Technology Inc PIC10F200 202 204 206 Table of Contents VOI General eege di 5 2 0 PIC10F200 202 204 206 Device Varieties 3 0 Architectural Overview 9 4 0 Memory Organization 15 N eb ves OAR HOE EDE IE OE EE ON OR ER HO Tere 25 6 0 Timer0 Module and TMRO Register PIC10F200 202 eccseceeceeeeeeeeneeeeeceeeerceseceeeeeceeeaeeaeseaecaeesaeeesaeeeaesaeeeeeseeeeeeaeeneeeateats 29 7 0 Timer0 Module and TMRO Register PIC10F2
47. IC10F204 206 The prescaler may be used by either the TimerO module or the Watchdog Timer but not both The prescaler assignment is controlled in software by the control bit PSA OPTION lt 3 gt Clearing the PSA bit will assign the prescaler to TimerO The prescaler is not readable or writable When the prescaler is assigned to the TimerO module prescale values of 1 2 1 4 1 256 are selectable Section 7 2 Prescaler details the operation of the prescaler A summary of registers associated with the Timer0 module is found in Table 7 1 FIGURE 7 1 TIMERO BLOCK DIAGRAM PIC1 0F204 206 TOCKI Pin gt Data Bus X Fosc 4 4 0 Es PSOUT 8 Internal Sync with Comparator 0 1 internal TMRO Reg Output Programmable Clocks PSOUT Prescalerl2 Sync TOSE 2 Tcv delay SYN CMPTOCS PS2 PS1 PS0 psa Tocs Note 1 Bits TOCS TOSE PSA PS2 PS1 and PS0 are located in the OPTION register 2 The prescaler is shared with the Watchdog Timer Figure 7 5 3 Bit CMPTOCS is located in the CMCONO register CMCON0 lt 4 gt 2007 Microchip Technology Inc DS41239D page 33 PIC10F200 202 204 206 FIGURE 7 2 TIMERO TIMING INTERNAL CLOCK NO PRESCALE i Q1 Q2 a3 AS AN AZ Q3 Q4 AM a2 a3 Q4 Q1 Q2 as as Q1 AZ Q3 as AM a2Ja3
48. MEMORY Memory Device Program Data PIC10F200 256 x 12 16x8 PIC10F202 512 x 12 24x 8 PIC10F204 256 x 12 16x8 PIC10F206 512 x 12 24x8 The PIC10F200 202 204 206 devices can directly or indirectly address its register files and data memory All Special Function Registers SFR including the PC are mapped in the data memory The PIC10F200 202 204 206 devices have a highly orthogonal symmetrical instruction set that makes it possible to carry out any operation on any register using any addressing mode This symmetrical nature and lack of special optimal situations make programming with the PIC10F200 202 204 206 devices simple yet efficient In addition the learning curve is reduced significantly The PIC10F200 202 204 206 devices contain an 8 bit ALU and working register The ALU is a general purpose arithmetic unit It performs arithmetic and Boolean functions between data in the working register and any register file The ALU is 8 bits wide and capable of addition subtrac tion shift and logical operations Unless otherwise mentioned arithmetic operations are two s comple ment in nature In two operand instructions one oper and is typically the W working register The other operand is either a file register or an immediate con stant In single operand instructions the operand is either the W register or a file register The W register is an 8 bit working register used for ALU operations It is not an add
49. O Option Registers a na rn ted 20 OSCCAL R gisler re HN EE 21 Oscillator Configurations 42 Oscillator Types Q ee o AME ec bere O 13 R Reader Response ees ee ed RR RR ee AA ee 92 Read Modifv Wie 26 Register File Map PIC10F200 204 ia i dere rti 17 PIC10F 202 206 ee ee RR orna ER Re Re ek ee 17 Registers Special Function 18 Reset esse in 41 Reset on Brown Out hot eee 48 S Ni EE RE ES 41 49 Software Simulator MPLAB IM 60 Special Features of the CPU 41 Special Function Registers SLACK PL M AI AOA Status Register T TimerO ll sie ct RR EU RR 29 33 Timer0 TMRO Module ee 29 33 TMRO with External Clock n 30 34 Timing Parameter Symbology and Load Conditions 69 TRIS Registers e ed Lotion tt indie 25 2007 Microchip Technology Inc DS41239D page 89 PIC10F200 202 204 206 W Wake up from Geen 49 Watchdog Timer WDT ee RA ee 41 46 i o TS 46 Programming Considerations 46 WWW Gl EE OE OE EE enit e ti pt us 91 WWW On Line Support 3 Z ZEtO DIts od a AE E 9 Go AAA eee DS41239D page 90 O 2007 Microchip Technology Inc PIC10F200 202 204 206 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www microchip com This web site is used as a means to make files and information easily available to custo
50. PIO latch GPIO pins used when these instructions are applied to a port where one or more pins are used as input outputs For GPIO lt 1 0 gt Outputs r 3 BCF GPIO 1 ppol ppll example a BSF operation on bit 2 of GPIO will cause BCF GPIO 0 pp10 ppll all eight bits of GPIO to be read into the CPU bit 2 to MOVLW 007h be set and the GPIO value to be written to the output TRIS GPIO ppl0 ppll latches If another bit of GPIO is used as a bidirectional VO pin say bit 0 and it is defined as an input at this time the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin overwriting the previous content As long as the pin stays in the Input mode no problem occurs Note 1 The user may have expected the pin val ues to be pp00 The 2nd BCF caused GP1 to be latched as the pin value High However if bit 0 is switched into Output mode later on 5 4 2 SUCCESSIVE OPERATIONS ON the content of the data latch may now be unknown VO PORTS Example 5 1 shows the effect of two sequential The actual write to an I O port happens at the end of an Read Modify Write instructions e g BCF BSF etc instruction cycle whereas for reading the data must be on an I O port valid at the beginning of the instruction cycle Figure 5 2 Therefore care must be exercised if a write followed by a read operation is carried out on the sa
51. S overrides Option control of GPPU and GPWU By executing the OPTION instruction the contents of the W register will be transferred to the OPTION regis ter A Reset sets the OPTION lt 7 0 gt bits Note If the TOCS bit is set to 1 it will override the TRIS function on the TOCKI pin REGISTER 4 2 OPTION REGISTER W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 GPWU GPPU TOCS TOSE PSA PS2 PS1 PSO bit 7 bit O Legend R Readable bit W Writable bit U Unimplemented bit read as n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 GPWU Enable Wake up on Pin Change bit GPO GP1 GP3 1 Disabled 0 Enabled bit 6 GPPU Enable Weak Pull ups bit GPO GP1 GP3 1 Disabled 0 Enabled bit 5 TOCS TimerO Clock Source Select bit 1 Transition on TOCKI pin overrides TRIS on the TOCKI pin 0 Transition on internal instruction cycle clock Fosc 4 bit 4 TOSE TimerO Source Edge Select bit 1 7 Increment on high to low transition on the TOCKI pin 0 7 Increment on low to high transition on the TOCKI pin bit 3 PSA Prescaler Assignment bit 1 Prescaler assigned to the WDT 0 Prescaler assigned to TimerO bit 2 0 PS 2 0 Prescaler Rate Select bits Bit Value TimerO Rate WDT Rate 000 1 2 1 1 001 1 4 1 2 010 1 8 1 4 011 1 16 1 8 100 1 32 1 16 101 1 64 1 32 110 1 128 1 64 111 1 256 1 128 DS41239D page 20
52. T time out occurred bit 3 PD Power Down bit bit 2 Z Zero bit EP instruction 1 After power up CLRWDT instruction or SLE 1 After power up or by the CLRWDT instruction 0 By execution of the SLEEP instruction 1 The result of an arithmetic or logic operation is zero 0 The result of an arithmetic or logic operation is not zero bit 1 DC Digit Carry Borrow bit for ADDWF and SUBWF instructions ADDWF 1 A carry from the 4th low order bit of the result occurred 0 A carry from the 4th low order bit of the result did not occur SUBWF 1 A borrow from the 4th low order bit of the result did not occur 0 A borrow from the 4th low order bit of the result occurred bit O C Carry Borrow bit for ADDWF SUBWF and RRF RLF instructions ADDWE SUBWE 1 A carry occurred RRF OF RLF 1 A borrow did not occur Load bit with LSb or MSb respectively 0 A carry did not occur 0 A borrow occurred Note 1 This bit is used on the PIC10F204 206 For code compatibility do not use this bit on the PIC10F200 202 2007 Microchip Technology Inc DS41239D page 19 PIC10F200 202 204 206 4 5 OPTION Register The OPTION register is a 8 bit wide write only register Note If TRIS bit is set to 0 the wake up on which contains various control bits to configure the change and pull up functions are disabled TimerO WDT prescaler and TimerO for that pin i e note that TRI
53. TTL INPUT THRESHOLD VIN vs VDD 1 7 1 5 1 3 1 1 VIN V 0 9 0 7 0 5 Typical Statistical Mean 25 C Maximum Mean Worst Case Temp 3o nenn TM i a 40 C to 125 C Max 40 C 2 0 2 5 3 0 3 5 4 0 4 5 VDD V 5 0 5 5 FIGURE 13 13 SCHMITT TRIGGER INPUT THRESHOLD VIN vs VDD 4 0 3 5 VIN V 0 5 Typical Statistical Mean 25 C 40 C to 125 C Maximum Mean Worst Case Temp 30 7 EES MEE DELE pee e GEESS Vin Max 125 C VIH Min 40 C 2 0 2 5 3 0 3 5 4 0 4 5 VDD V 5 0 5 5 2007 Microchip Technology Inc DS41239D page 79 PIC10F200 202 204 206 FIGURE 13 14 INTOSC INTERNAL OSCILLATOR POWERUP TIMES vs VDD 45 PB PEE e M STE o E D ZA VE I EEN Ma ZD N EO AE EE EG g 30 NS MM EE ee mme et dee o S 3 Max 85 C N sneer ea A ed ss A ne edes oh eee at MD PR nu Typical 25 C ee A A Max 40 C AG 0 nn tisse 5 EE a ROS EE Da SEE MED EE 0 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 VDD V DS41239D page 80 2007 Microchip Technology Inc PIC10F200 202 204 206 14 0 PACKAGING INFORMATION 14 4 Package Marking Information 6 Lead SOT 23A Example XXNN 02JR O O
54. UB 1 Fetch 3 Execute 3 4 BSF GPIO BITI Fetch 4 Flush Fetch SUB 1 Execute SUB 1 All instructions are single cycle except for any program branches These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed 2007 Microchip Technology Inc DS41239D page 13 PIC10F200 202 204 206 NOTES DS41239D page 14 2007 Microchip Technology Inc PIC10F200 202 204 206 4 0 MEMORY ORGANIZATION FIGURE 4 1 PROGRAM MEMORY MAP AND STACK FOR THE The PIC10F200 202 204 206 memories are organized PIC10F200 204 into program memory and data memory Data memory banks are accessed using the File Select Register PC lt 7 0 gt FSR CALL RETLW 9 4 1 Program Memory Organization for StackLevel the PIC10F200 204 SE The PIC10F200 204 devices have a 9 bit Program Counter PC capable of addressing a 512 x 12 A Reset Vector 0000h program memory space Only the first 256 x 12 0000h 00FFh for the On chip Program PIC10F200 204 are physically implemented see Memory Figure 4 1 Accessing a location above these gt boundaries will cause a wraparound within the first E 256 x 12 space PIC10F200 204 The effective S3 Reset vector is at 0000h see Figure 4 1 Location 5 OOFFh PIC10F200 204 contains the internal clock 2 oscillator calibration value This value s
55. are programmed with different serial numbers The serial numbers may be random pseudo random or sequential Serial programming allows each device to have a unique number which can serve as an entry code password or ID number 2007 Microchip Technology Inc DS41239D page 7 PIC10F200 202 204 206 NOTES DS41239D page 8 2007 Microchip Technology Inc PIC10F200 202 204 206 3 0 ARCHITECTURAL OVERVIEW The high performance of the PIC10F200 202 204 206 devices can be attributed to a number of architectural features commonly found in RISC microprocessors To begin with the PIC 10F200 202 204 206 devices use a Harvard architecture in which program and data are accessed on separate buses This improves band width over traditional von Neumann architectures where program and data are fetched on the same bus Separating program and data memory further allows instructions to be sized differently than the 8 bit wide data word Instruction opcodes are 12 bits wide making it possible to have all single word instructions A 12 bit wide program memory access bus fetches a 12 bit instruction in a single cycle A two stage pipeline overlaps fetch and execution of instructions Consequently all instructions 33 execute in a single cycle 1 us 4 MHz except for program branches The table below lists program memory Flash and data memory RAM for the PIC10F200 202 204 206 devices TABLE 3 1 PIC10F2XX
56. cations as well as allowing the use of the GP3 MCLR VPP pin as a general purpose input The Device Reset Time delays will vary from chip to chip due to VDD temperature and process variation See AC parameters for details Reset sources are POR MCLR WDT time out and wake up on pin change See Section 9 9 2 Wake up from Sleep Notes 1 2 and 3 TABLE 9 3 DRT DEVICE RESET TIMER PERIOD Oscillator POR Reset Subsequent Resets INTOSC 18 ms typical 10 us typical 9 6 Watchdog Timer WDT The Watchdog Timer WDT is a free running on chip RC oscillator which does not require any external components This RC oscillator is separate from the internal 4 MHz oscillator This means that the WDT will run even if the main processor clock has been stopped for example by execution of a SLEEP instruction During normal operation or Sleep a WDT Reset or wake up Reset generates a device Reset The TO bit STATUS lt 4 gt will be cleared upon a Watchdog Timer Reset The WDT can be permanently disabled by program ming the configuration WDTE as a 0 see Section 9 1 Configuration Bits Refer to the PIC10F200 202 204 206 Programming Specifications to determine how to access the Configuration Word 9 6 1 WDT PERIOD The WDT has a nominal time out period of 18 ms with no prescaler If a longer time out period is desired a prescaler with a division ratio of up to
57. cteristics for information on variation over voltage and temperature In addition a calibration instruction is programmed into the last address of memory which contains the calibra tion value for the internal oscillator This location is always uncode protected regardless of the code pro tect settings This value is programmed as a MOVLW xx instruction where xx is the calibration value and is placed at the Reset vector This will load the W register with the calibration value upon Reset and the PC will then roll over to the users program at address 0x000 The user then has the option of writing the value to the OSCCAL Register 05h or ignoring it OSCCAL when written to with the calibration value will trim the internal oscillator to remove process variation from the oscillator frequency 9 3 The device differentiates between various kinds of Reset Power on Reset POR MCLR Reset during normal operation MCLR Reset during Sleep WDT time out Reset during normal operation WDT time out Reset during Sleep Wake up from Sleep on pin change Wake up from Sleep on comparator change Reset Some registers are not reset in any way they are unknown on POR and unchanged in any other Reset Most other registers are reset to Reset state on Power on Reset POR MCLR WDT or Wake up on pin change Reset during normal operation They are not affected by a WDT Reset during Sleep or MCLR Reset during Sleep
58. des TOCS bit for TRIS control of GP2 2 When the comparator is turned on these control bits assert themselves When the comparator is off these bits have no effect on the device operation and the other control registers have precedence 3 PIC10F204 206 only 2007 Microchip Technology Inc DS41239D page 37 PIC10F200 202 204 206 8 1 Comparator Configuration The on board comparator inputs GPO CIN GP1 Note The comparator can have an inverted CIN as well as the comparator output GP2 COUT output see Figure 8 1 are steerable The CMCONO OPTION and TRIS registers are used to steer these pins see Figure 8 1 If the Comparator mode is changed the comparator output level may not be valid for the specified mode change delay shown in Table 12 1 FIGURE 8 1 BLOCK DIAGRAM OF THE COMPARATOR CPREF AX TOCKI GP2 COUT COUTEN OSCCAL Es 1 3 COUT Register Band Gap Buffer 0 6V 4 CNREF POL CMPON TOCKI Tx Tock Pin TOCKSEL CWU BE S Read CWUF CMCON TABLE 8 1 TMRO CLOCK SOURCE FUNCTION MUXING TOCS CMPTOCS COUTEN Source 0 x x Internal Instruction Cycle T 0 0 CMPOUT 1 0 1 CMPOUT T 1 0 CMPOUT 1 1 ii TOCKI DS41239D page 38 2007 Microchip Technology Inc PIC10F200 202 204 206 8 2 Comparator Operation A single comparator is shown in Figu
59. dressing INDF and FSR Registers 2 PIC10F204 only Unimplemented on the PIC10F200 and reads as 00h 3 Unimplemented read as 00h FIGURE 4 4 PIC10F202 206 REGISTER FILE MAP File Address 00h INDF 01h TMRO oen PCL 03h STATUS 04h FSR 05h OSCCAL 06h GPIO 07h CMCONOB 08h General Purpose Registers 1Fh Note 1 Not a physical register See Section 4 9 Indirect Data Addressing INDF and FSR Registers 2 PIC10F206 only Unimplemented on the PIC10F202 and reads as 00h 2007 Microchip Technology Inc DS41239D page 17 PIC10F200 202 204 206 4 3 2 SPECIAL FUNCTION REGISTERS The Special Function Registers SFRs are registers used by the CPU and peripheral functions to control the operation of the device Table 4 1 The Special Function Registers can be classified into two sets The Special Function Registers associated with the core functions are described in this section Those related to the operation of the peripheral features are described peripheral feature in the section for each TABLE 4 1 SPECIAL FUNCTION REGISTER SFR SUMMARY PIC10F200 202 204 206 Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power On Page Reset 2 00h INDF Uses Contents of FSR to Address Data Memory not a physical register XXXX XXXX 23 01h TMRO 8 bit
60. echnology Inc PIC10F200 202 204 206 DECF Syntax Operands Operation Status Affected Description DECFSZ Syntax Operands Operation Status Affected Description GOTO Syntax Operands Operation Status Affected Description Decrement f label DECF f d 0 lt f lt 31 d e 0 1 f 1 gt dest Z Decrement register f If is 0 the result is stored in the W register If d is 1 the result is stored back in register f Decrement f Skip if 0 label DECFSZ fd 0 lt f lt 31 d e 0 1 1o4 None skip if result 0 The contents of register f are decremented If is 0 the result is placed in the W register If d is 1 the result is placed back in register f If the result is 0 the next instruc tion which is already fetched is discarded and a NOP is executed instead making it a two cycle instruction Unconditional Branch label GOTO k 0 lt k lt 511 k gt PC lt 8 0 gt STATUS lt 6 5 gt gt PC lt 10 9 gt None GOTO is an unconditional branch The 9 bit immediate value is loaded into PC bits 8 0 The upper bits of PC are loaded from STATUS lt 6 5 gt GOTO is a two cycle instruction INCF Increment f Syntax label INCF fd Operands O lt f lt 31 d e 0 1 Operation f 1 dest Status Affected Z Description The contents of register f are incremented If d i
61. ed with the eight bit literal k The program counter is loaded from the top of the stack the return address This is a two cycle instruction Rotate Left f through Carry label RLF fd 0 lt f lt 31 d e 0 1 See description below C The contents of register f are rotated one bit to the left through the Carry flag If d is 0 the result is placed in the W register If d is 1 the result is stored back in register f C register f Rotate Right f through Carry label RRF f d O lt f lt 31 d e 0 1 See description below C The contents of register f are rotated one bit to the right through the Carry flag If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f Cr register f 7 SLEEP Syntax Operands Operation Status Affected Description SUBWF Syntax Operands Operation Status Affected Description SWAPF Syntax Operands Operation Status Affected Description Enter SLEEP Mode abel SLEEP None 00h gt WDT 0 gt WDT prescaler 1 TO 0 PD TO PD RBWUF Time out Status bit TO is set The Power down Status bit PD is cleared RBWUF is unaffected The WDT and its prescaler are cleared The processor is put into Sleep mode with the oscillator stopped See Section 9 9
62. engineer FAE for support Local sales offices are also available to help customers A listing of sales offices and locations is included in the back of this document Technical support is available through the web site at http support microchip com 2007 Microchip Technology Inc DS41239D page 91 PIC10F200 202 204 206 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod uct If you wish to provide your comments on organization clarity subject matter and ways in which our documentation can better serve you please FAX your comments to the Technical Publications Manager at 480 792 4150 Please list the following information and use this outline to provide us with your comments about this document To Technical Publications Manager Total Pages Sent RE Reader Response From Name Company Address City State ZIP Country Telephone FAX Application optional Would you like a reply YN Device PIC10F200 202 204 206 Literature Number DS41239D Questions 1 Whatare the best features of this document 2 How does this document meet your hardware and software development needs 3 Do you find the organization of this document easy to follow If not why 4 What additions to the document do you think would enhance the structure and subject 5 What deletions f
63. eripheral Features PIC10F200 202 41 0 pins 31 0 pins with individual direction control 1 input only pin High current sink source for direct LED drive Wake on change Weak pull ups 8 bit real time clock counter TMRO with 8 bit programmable prescaler Peripheral Features PIC10F204 206 4 VO pins 31 0 pins with individual direction control 1 input only pin High current sink source for direct LED drive Wake on change Weak pull ups 8 bit real time clock counter TMRO with 8 bit programmable prescaler 1 Comparator Internal absolute voltage reference Both comparator inputs visible externally Comparator output visible externally TABLE 1 1 PIC10F20X MEMORY AND FEATURES Device pee nee RTS VO Puch Comparator Flash words SRAM bytes PIC10F200 256 16 4 1 0 PIC10F202 512 24 4 1 0 PIC10F204 256 16 4 1 1 PIC10F206 512 24 4 1 1 2007 Microchip Technology Inc DS41239D page 1 PIC10F200 202 204 206 SOT 23 Pin Diagrams GPO ICSPDAT gt 116 a 6 lt GP3 MCLR VPP N Vss w 2 S 5 Vbp N LL GP1 ICSPCLK 13 5 4 lt gt GP2 TOCKI FOSC4 D
64. estborough MA Tel 774 760 0087 Fax 774 760 0088 Chicago Itasca IL Tel 630 285 0071 Fax 630 285 0075 Dallas Addison TX Tel 972 818 7423 Fax 972 818 2924 Detroit Farmington Hills MI Tel 248 538 2250 Fax 248 538 2260 Kokomo Kokomo IN Tel 765 864 8360 Fax 765 864 8387 Los Angeles Mission Viejo CA Tel 949 462 9523 Fax 949 462 9608 Santa Clara Santa Clara CA Tel 408 961 6444 Fax 408 961 6445 Toronto Mississauga Ontario Canada Tel 905 673 0699 Fax 905 673 6509 ASIA PACIFIC Asia Pacific Office Suites 3707 14 37th Floor Tower 6 The Gateway Habour City Kowloon Hong Kong Tel 852 2401 1200 Fax 852 2401 3431 Australia Sydney Tel 61 2 9868 6733 Fax 61 2 9868 6755 China Beijing Tel 86 10 8528 2100 Fax 86 10 8528 2104 China Chengdu Tel 86 28 8665 5511 Fax 86 28 8665 7889 China Fuzhou Tel 86 591 8750 3506 Fax 86 591 8750 3521 China Hong Kong SAR Tel 852 2401 1200 Fax 852 2401 3431 China Qingdao Tel 86 532 8502 7355 Fax 86 532 8502 7205 China Shanghai Tel 86 21 5407 5533 Fax 86 21 5407 5066 China Shenyang Tel 86 24 2334 2829 Fax 86 24 2334 2393 China Shenzhen Tel 86 755 8203 2660 Fax 86 755 8203 1760 China Shunde Tel 86 757 2839 5507 Fax 86 757 2839 5571 China Wuhan Tel 86 27 5980 5300 Fax 86 27 5980 5118 China Xian Tel 86 29 8833 7250 Fax 86 29 8833 7256 ASIA PACIFIC India Bangalore Tel
65. for debugging The MPASM Assembler features include Integration into MPLAB IDE projects User defined macros to streamline assembly code Conditional assembly for multi purpose source files Directives that allow complete control over the assembly process 11 3 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip s PIC18 family of microcontrollers and the dsPIC30 dsPIC33 and PIC24 family of digital signal controllers These compilers provide powerful integra tion capabilities superior code optimization and ease of use not found with other compilers For easy source level debugging the compilers provide symbol information that is optimized to the MPLAB IDE debugger 11 4 MPLINK Object Linker MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler It can link relocatable objects from precompiled libraries using directives from a linker script The MPLIB Object Librarian manages the creation and modification of library files of precompiled code When a routine from a library is called from a source file only the modules that contain that routine will be linked in with the application This allows large libraries to be used efficiently in many different applications The object linker library features include Efficient linking of single libraries ins
66. for code protection see Register 9 1 Clock Out REGISTER 9 1 CONFIGURATION WORD FOR PIC10F200 202 204 206 1 2 MCLRE CP WDTE bit 11 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set V Bit is cleared x Bit is unknown bit 11 5 Unimplemented Read as 0 bit 4 MCLRE GP3 MCLR Pin Function Select bit 1 GP3 MCLR pin function is MCLR bit3 CP Code Protection bit 1 Code protection off 0 Code protection on bit 2 WDTE Watchdog Timer Enable bit 1 WDT enabled 0 WDT disabled bit 1 0 Reserved Read as 0 0 GP3 MCLR pin function is digital I O MCLR internally tied to VDD Refer to the PIC 10F200 202 204 206 Memory Programming Specifications DS41228 to determine how to access the Configuration Word The Configuration Word is not user addressable during device operation INTRC is the only oscillator mode offered on the PIC10F200 202 204 206 2007 Microchip Technology Inc DS41239D page 41 PIC10F200 202 204 206 9 2 Oscillator Configurations 9 2 1 OSCILLATOR TYPES The PIC10F200 202 204 206 devices are offered with Internal Oscillator mode only INTOSC Internal 4 MHz Oscillator 9 2 2 INTERNAL 4 MHz OSCILLATOR The internal oscillator provides a 4 MHz nominal system clock see Section 12 0 Electrical Chara
67. ge 0 55 0 6 0 65 V 2 0V lt VDD lt 5 5V 40 C x TA lt 125 C extended These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 Response time is measured with one comparator input at VDD 1 5 2 100 mV to VDD 1 5 2 20 mV TABLE 12 2 PULL UP RESISTOR RANGES VDD Volts Temperature C Min Typ Max Units GP0 GP1 2 0 40 73K 105K 186K Q 25 73K 113K 187K Q 85 82K 123K 190K Q 125 86K 132k 190K Q 5 5 40 15K 21K 33K Q 25 15K 22K 34K Q 85 19K 26k 35K Q 125 23K 29K 35K Q GP3 2 0 40 63K 81K 96K Q 25 77K 93K 116K Q 85 82K 96k 116K Q 125 86K 100K 119K Q 5 5 40 16K 20k 22K Q 25 16K 21K 23K Q 85 24K 25k 28K Q 125 26K 27K 29K Q DS41239D page 68 2007 Microchip Technology Inc PIC10F200 202 204 206 12 4 Timing Parameter Symbology and Load Conditions PIC10F200 202 204 206 The timing parameter symbols have been created following one of the following formats 1 TppS2ppS 2 TppS T F Frequency T Time Lowercase subscripts pp and their meanings pp 2 to mc MCLR ck CLKOUT osc Oscillator cy Cycle time to TOCKI drt Device Reset Timer wdt Watchdog Timer io UO port wdt Watchdog Timer Uppercase letters and their meanings S F Fal
68. ge 27 PIC10F200 202 204 206 NOTES DS41239D page 28 2007 Microchip Technology Inc PIC10F200 202 204 206 6 0 TIMERO MODULE AND TMRO REGISTER PIC10F200 202 The TimerO module has the following features 8 bit timer counter register TMRO Readable and writable 8 bit software programmable prescaler Internal or external clock select Edge select for external clock Figure 6 1 is a simplified block diagram of the TimerO module Timer mode is selected by clearing the TOCS bit OPTION lt 5 gt In Timer mode the TimerO module will increment every instruction cycle without prescaler If TMRO register is written the increment is inhibited for the following two cycles Figure 6 2 and Figure 6 3 The user can work around this by writing an adjusted value to the TMRO register Counter mode is selected by setting the TOCS bit OPTION lt 5 gt In this mode TimerO will increment either on every rising or falling edge of pin TOCKI The TOSE bit OPTION lt 4 gt determines the source edge Clearing the TOSE bit selects the rising edge Restric tions on the external clock input are discussed in detail in Section 6 1 Using Timer0 with an External Clock PIC10F200 202 The prescaler may be used by either the TimerO module or the Watchdog Timer but not both The prescaler assignment is controlled in software by the control bit PSA OPTION lt 3 gt Clearing the PSA bit will assign the prescaler to TimerO
69. ging capability built into the Flash devices This feature along with Microchip s In Circuit Serial Programming ICSP protocol offers cost effective in circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment This enables a designer to develop and debug source code by setting breakpoints single step ping and watching variables and CPU status and peripheral registers Running at full speed enables testing hardware and applications in real time MPLAB ICD 2 also serves as a development programmer for selected PIC devices 11 10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability It features a large LCD display 128 x 64 for menus and error messages and a modu lar detachable socket assembly to support various package types The ICSP cable assembly is included as a standard item In Stand Alone mode the MPLAB PM3 Device Programmer can read verify and program PIC devices without a PC connection It can also set code protection in this mode The MPLAB PM3 connects to the host PC via an RS 232 or USB cable The MPLAB PM3 has high speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD MMC card for file storage and secure data applications 2007 Microchip Technology Inc DS412
70. gramming clock pin Name Function Description CIN AN Comparator input PIC10F 204 206 only GP2 TOCKI COUT GP2 TTL CMOS Bidirectional VO pin FOSC4 TOCKI ST Clock input to TMRO COUT CMOS Comparator output PIC10F 204 206 only FOSCA CMOS Oscillator 4 output GP3 MCLR VPP GP3 TTL Input pin Can be software programmed for internal weak pull up and wake up from Sleep on pin change MCLR ST Master Clear Reset When configured as MCLR this pin is an active low Reset to the device Voltage on GP3 MCLR VPP must not exceed VDD during normal device operation or the device will enter Programming mode Weak pull up always on if configured as MCLR VPP HV Programming voltage input VDD VDD P Positive supply for logic and I O pins Vss Vss P Ground reference for logic and I O pins Legend Input O Output I O Input Output P Power Not used TTL TTL input ST Schmitt Trigger input AN Analog input DS41239D page 12 2007 Microchip Technology Inc PIC10F200 202 204 206 3 1 Clocking Scheme Instruction Cycle The clock is internally divided by four to generate four non overlapping quadrature clocks namely Q1 Q2 Q3 and Q4 Internally the PC is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4 It is decoded and e
71. gy Inc PIC10F200 202 204 206 12 3 DC Characteristics PIC10F200 202 204 206 Industrial Extended DC CHARACTERISTICS Standard Operating Conditions unless otherwise specified 40 C x TA lt 85 C industrial 40 C lt TA x 125 C extended Operating voltage VDD range as described in DC specification Operating temperature un Sym Characteristic Min Typt Max Units Conditions VIL Input Low Voltage VO ports D030 with TTL buffer Vss 0 8 V Forall4 5 VDD x 5 5V D030A Vss 0 15VoD V Otherwise D031 with Schmitt Trigger Vss 0 2 VDD V buffer D032 MCLR TOCKI Vss 02VoD V VIH Input High Voltage VO ports D040 with TTL buffer 2 0 VDD V 45 lt VDD lt 5 5V D040A 0 25 VOD 0 8 VDD V Otherwise D041 with Schmitt Trigger 0 8VDD VDD V For entire VDD range buffer D042 MCLR TOCKI 0 8VDD VDD V D070 IPUR GPIO weak pull up current 50 250 400 pA VDD 5V VPIN VSS li Input Leakage Current 2 D060 1 0 ports 0 1 1 uA Vss lt VPIN lt VDD Pin at high imped ance D061 GP3 MCLR 07 5 pA Vss x VPIN lt VDD Output Low Voltage D080 1 0 ports 0 6 V loL 8 5 mA VDD 4 5V 40 C to 85 C DO80A 0 6 V loL 7 0 mA VDD 4 5V 40 C to 125 C Output High Voltage D090 VO ports VDD 0 7 LS V loH 3 0 mA VDD 4 5V 40 C to 85 C DO90A VDD
72. hnology Inc MicrocHip PIC10F200 202 204 206 6 Pin 8 Bit Flash Microcontrollers Devices Included In This Data Sheet PIC10F200 PIC10F202 PIC10F204 PIC10F206 High Performance RISC CPU Only 33 single word instructions to learn All single cycle instructions except for program branches which are two cycle 12 bit wide instructions 2 level deep hardware stack Direct Indirect and Relative Addressing modes for data and instructions 8 bit wide data path 8 Special Function Hardware registers Operating speed 4 MHz internal clock 1 us instruction cycle Special Microcontroller Features 4 MHz precision internal oscillator Factory calibrated to 1 In Circuit Serial Programming ICSPTM In Circuit Debugging ICD support Power on Reset POR Device Reset Timer DRT Watchdog Timer WDT with dedicated on chip RC oscillator for reliable operation Programmable code protection Multiplexed MCLR input pin Internal weak pull ups on VO pins Power Saving Sleep mode Wake up from Sleep on pin change Low Power Features CMOS Technology Operating Current lt 175 uA 2V 4 MHz typical Standby Current 100 nA 2V typical Low power high speed Flash technology 100 000 Flash endurance gt 40 year retention Fully static design Wide operating voltage range 2 0V to 5 5V Wide temperature range Industrial 40 C to 85 C Extended 40 C to 125 C P
73. hould never be overwritten Y 256 Word OOFFh vp 0100h NOOO as N 01FFh Note 1 Address 0000h becomes the effective Reset vector Location OOFFh contains the MOVLW XX internal oscillator calibration value 2007 Microchip Technology Inc DS41239D page 15 PIC10F200 202 204 206 4 2 Program Memory Organization for the PIC10F202 206 The PIC10F202 206 devices have a 10 bit Program Counter PC capable of addressing a 1024 x 12 program memory space Only the first 512 x 12 0000h 01FFh for the PIC10F202 206 are physically implemented see Figure 4 2 Accessing a location above these boundaries will cause a wraparound within the first 512 x 12 space PIC10F202 206 The effective Reset vector is at 0000h see Figure 4 2 Location 01FFh PIC10F202 206 contains the internal clock oscillator calibration value This value should never be overwritten FIGURE 4 2 PROGRAM MEMORY MAP AND STACK FOR THE PIC10F202 206 PC lt 8 0 gt CALL RETLW 10 7 Stack Level 1 Stack Level 2 Reset Vector 0000h On chip Program Memory D A o oo ER g Y 512 Words 01FFh COS 0200h AA Be N 02FFh Note 1 Address 0000h becomes the effective Reset vector Location 01FFh contains the MOVLW XX internal oscillator calibration value 4 3 Data Memory Organization Data memory is composed of registers or bytes of RAM Therefore data memo
74. ic Flash based CMOS microcontrollers They systems to low power remote transmitters receivers employ a RISC architecture with only 33 single word The Flash technology makes customizing application single cycle instructions All instructions are single programs transmitter codes appliance settings cycle 1 us except for program branches which take receiver frequencies etc extremely fast and conve two cycles The PIC10F200 202 204 206 devices nient The small footprint packages for through hole or deliver performance in an order of magnitude higher surface mounting make these microcontrollers well than their competitors in the same price category The suited for applications with space limitations Low cost 12 bit wide instructions are highly symmetrical result low power high performance ease of use and 1 0 ing in a typical 2 1 code compression over other 8 bit flexibility make the PIC10F200 202 204 206 devices microcontrollers in its class The easy to use and easy very versatile even in areas where no microcontroller to remember instruction set reduces development time use has been considered before e g timer functions significantly logic and PLDs in larger systems and coprocessor The PIC10F200 202 204 206 products are equipped applications with special features that reduce system cost and power requirements The Power on Reset POR and Device Reset Timer DRT eliminate the need for exter nal Reset circuitry INTRC Internal Oscil
75. icts a problem situation where VDD rises too slowly The time between when the DRT senses that MCLR is high and when MCLR and VDD actually reach their full value is too long In this situation when the Start up Timer times out VDD has not reached the VDD min value and the chip may not function correctly For such situations we recommend that external RC circuits be used to achieve longer POR delay times Figure 9 4 Note When the devices start normal operation exit the Reset condition device operat ing parameters voltage frequency temperature etc must be met to ensure operation If these conditions are not met the device must be held in Reset until the operating conditions are met For additional information refer to Application Notes AN522 Power Up Considerations DS00522 and AN607 Power up Trouble Shooting DS00607 2007 Microchip Technology Inc DS41239D page 43 PIC10F200 202 204 206 FIGURE 9 2 SIMPLIFIED BLOCK DIAGRAM OF ON CHIP RESET CIRCUIT VDD Power up Detect POR Power on Reset GP3 MCLR VPP gt MCLR Reset o gt S Q MCLRE R Q gt WDT Time out WOT Reset Start up Timer CHIP Reset Pin Change ON 10 us or 18 ms Sleep Wake up on pin change Reset FIGURE 9 3 TIME OUT SEQUENCE ON POWER UP MCLR PULLED LOW VDD y MCLR f s Internal POR
76. ified application 11 8 MPLAB ICE 4000 High Performance In Circuit Emulator The MPLAB ICE 4000 In Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high end PIC MCUs and dsPIC DSCs Software control of the MPLAB ICE 4000 In Circuit Emulator is provided by the MPLAB Integrated Development Environment which allows editing building downloading and source debugging from a single environment The MPLAB ICE 4000 is a premium emulator system providing the features of MPLAB ICE 2000 but with increased emulation memory and high speed perfor mance for dsPIC30F and PIC18XXXX devices Its advanced emulator features include complex triggering and timing and up to 2 Mb of emulation memory The MPLAB ICE 4000 In Circuit Emulator system has been designed as a real time emulation system with advanced features that are typically found on more expensive development tools The PC platform and Microsoft Windows 32 bit operating system were chosen to best make these features available in a simple unified application 11 9 MPLAB ICD 2 In Circuit Debugger Microchip s In Circuit Debugger MPLAB ICD 2 is a powerful low cost run time development tool connecting to the host PC via an RS 232 or high speed USB interface This tool is based on the Flash PIC MCUS and can be used to develop for these and other PIC MCUs and dsPIC DSCs The MPLAB ICD 2 utilizes the in circuit debug
77. imer selectable code protect high I O current capability and precision internal oscillator The PIC10F200 202 204 206 device uses serial programming with data pin GPO and clock pin GP1 2007 Microchip Technology Inc DS41239D page 5 PIC10F200 202 204 206 NOTES DS41239D page 6 2007 Microchip Technology Inc PIC10F200 202 204 206 2 0 PIC10F200 202 204 206 DEVICE VARIETIES A variety of packaging options are available Depend ing on application and production requirements the proper device option can be selected using the information in this section When placing orders please use the PIC10F200 202 204 206 Product Identification System at the back of this data sheet to specify the correct part number 2 1 Quick Turn Programming QTP Devices Microchip offers a QTP programming service for factory production orders This service is made available for users who choose not to program medium to high quantity units and whose code patterns have stabilized The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory Certain code and prototype verification procedures do apply before production shipments are available Please contact your local Microchip Technology sales office for more details 2 2 Serialized Quick Turn Programming SQTP Devices Microchip offers a unique programming service where a few user defined locations in each device
78. ith color coded context A multiple project manager Customizable data windows with direct edit of contents High level source code debugging Visual device initializer for easy register initialization Mouse over variable inspection Drag and drop variables from source to watch windows Extensive on line help Integration of select third party tools such as HI TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to Edit your source files either assembly or C One touch assemble or compile and download to PIC MCU emulator and simulator tools automatically updates all project information Debug using Source files assembly or C Mixed assembly and C Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm from the cost effective simulators through low cost in circuit debuggers to full featured emulators This eliminates the learning curve when upgrading to tools with increased flexibility and power 2007 Microchip Technology Inc DS41239D page 59 PIC10F200 202 204 206 11 2 MPASM Assembler The MPASM Assembler is a full featured universal macro assembler for all PIC MCUs The MPASM Assembler generates relocatable object files for the MPLINK Object Linker Intel standard HEX files MAP files to detail memory usage and symbol reference absolute LST files that contain source lines and generated machine code and COFF files
79. l P Period H High R Rise l Invalid high impedance V Valid L Low Z High impedance FIGURE 12 2 LOAD CONDITIONS PIC10F200 202 204 206 Legend CL 50pF for all pins 2007 Microchip Technology Inc DS41239D page 69 PIC10F200 202 204 206 TABLE 12 3 CALIBRATED INTERNAL RC FREQUENCIES PIC10F200 202 204 206 Standard Operating Conditions unless otherwise specified Operating Temperature 40 C x TA lt 85 C industrial AC CHARACTERISTICS 40 C x TA x 125 C extended Operating Voltage VDD range is described in Section 12 1 DC Characteristics jus Sym Characteristic SUN Min Typt Max Units Conditions F10 Fosc Internal Calibrated 1 3 96 4 00 4 04 MHz VDD 3 5V 25 C INTOSC 2 3 92 4 00 4 08 MHz 2 5V lt VDD lt 5 5V Frequency t 0 C lt TA lt 85 C industrial 5 3 80 4 00 4 20 MHz 2 0V lt VDD lt 5 5V 40 C lt TA 85 C industrial 40 C lt TA x 125 C extended These parameters are characterized but not tested T Data in the Typical Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 To ensure these oscillator frequency tolerances VDD and Vss must be capacitively decoupled as close to the device as possible 0 1 uF and 0 01 uF values in parallel are recommended 2 Under stable VDD conditions FIGURE 12 3 RES
80. lator mode is provided thereby preserving the limited number of UO available Power Saving Sleep mode Watchdog Timer and code protection features improve system cost power and reliability The PIC10F200 202 204 206 devices are available in cost effective Flash which is suitable for production in any volume The customer can take full advantage of Microchip s price leadership in Flash programmable microcontrollers while benefiting from the Flash programmable flexibility The PIC10F200 202 204 206 products are supported by a full featured macro assembler a software simula tor an in circuit debugger a C compiler a low cost development programmer and a full featured program mer All the tools are supported on IBM PC and compatible machines TABLE 1 1 PIC10F200 202 204 206 DEVICES Clock Maximum Frequency of Operation MHz 4 4 4 4 Memory Flash Program Memory 256 512 256 512 Data Memory bytes 16 24 16 24 IMEEM Timer Module s TMRO TMRO TMRO TMRO Wake up from Sleep on Pin Change Yes Yes Yes Yes Comparators Features VO Pins 3 3 3 3 Input Only Pins 1 Internal Pull ups Yes Yes Yes Yes In Circuit Serial Programming Yes Yes Yes Yes Number of Instructions 33 33 33 33 Packages 6 pin SOT 23 6 pin SOT 23 6 pin SOT 23 6 pin SOT 23 8 pin PDIP DFN 8 pin PDIP DFN 8 pin PDIP DFN 8 pin PDIP DEN The PIC10F200 202 204 206 devices have Power on Reset selectable Watchdog T
81. me I O port The sequence of instructions should allow the pin voltage to stabilize load dependent before the next instruction causes that file to be read into the CPU Otherwise the previous state of that pin may be read into the CPU rather than the new state When in doubt it is better to separate these instructions with a NOP or another instruction not accessing this VO port A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin wired OR wired AND The resulting high output currents may damage the chip DS41239D page 26 2007 Microchip Technology Inc PIC10F200 202 204 206 FIGURE 5 2 SUCCESSIVE 1 0 OPERATION PIC10F200 202 204 206 Write to GPIO Read GPIO Q1 Q2 Q3 Q4 Q1 Q2 Q3 AS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Y PGE X BERE XN PCTS Instruction Fetched voywe GPIO MOVF GPIO W NOP i NOP GP lt 2 0 gt i X 7 Port pin Port pin written here sampled here 1 1 SSS 1 14 Instruction 1 Executed MOVWF GPIO MOVE GPIO W NOP This example shows a write to GPIO followed by a read from GPIO Data setup time 0 25 Tcv TPD where Tcy instruction cycle TPD propagation delay Therefore at higher clock frequencies a write followed by a read may be problematic 2007 Microchip Technology Inc DS41239D pa
82. mers Accessible by using your favorite Internet browser the web site contains the following information Product Support Data sheets and errata application notes and sample programs design resources user s guides and hardware support documents latest software releases and archived software General Technical Support Frequently Asked Questions FAQ technical support requests online discussion groups Microchip consultant program member listing Business of Microchip Product selector and ordering guides latest Microchip press releases listing of seminars and events listings of Microchip sales offices distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip s customer notification service helps keep customers current on Microchip products Subscribers will receive e mail notification whenever there are changes updates revisions or errata related to a specified product family or development tool of interest To register access the Microchip web site at www microchip com click on Customer Change Notification and follow the registration instructions CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels Distributor or Representative Local Sales Office Field Application Engineer FAE Technical Support Development Systems Information Line Customers should contact their distributor representative or field application
83. module or as a postscaler for the Watchdog Timer WDT respectively see Figure 9 6 For simplicity this counter is being referred to as prescaler throughout this data sheet Note The prescaler may be used by either the TimerO module or the WDT but not both Thus a prescaler assignment for the TimerO module means that there is no prescaler for the WDT and vice versa The PSA and PS 2 0 bits OPTION lt 3 0 gt determine prescaler assignment and prescale ratio When assigned to the TimerO module all instructions writing to the TMRO register e g CLRF 1 MOVWF 1 BSF 1 x etc will clear the prescaler When assigned to WDT a CLRWDT instruction will clear the prescaler along with the WDT The prescaler is neither readable nor writable On a Reset the prescaler contains all 0 s 7 2 1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control i e it can be changed on the fly during pro gram execution To avoid an unintended device Reset the following instruction sequence Example 7 1 must be executed when changing the prescaler assignment from TimerO to the WDT EXAMPLE 7 1 CHANGING PRESCALER TIMERO gt WDT CLRWDT Clear WDT CLRF TMRO Clear TMRO amp Prescaler MOVLW 00xx1111 b These 3 lines 5 6 7 OPTION are required only if desired CLRWDT PS 2 0 are 000 or 001 MOVLW 00xx1lxxx b Set Postscaler to OPTION desired WDT rate
84. must be between Vss and VDD If the input voltage deviates from this range by more than 0 6V in either direction one of the diodes is forward biased and a latch up may occur A maximum source impedance of 10kQ is recommended for the analog sources Any external component connected to an analog input pin such as a capacitor or a Zener diode should have very little leakage current 2007 Microchip Technology Inc DS41239D page 39 PIC10F200 202 204 206 FIGURE 8 3 ANALOG INPUT MODE VDD Rs 10 kQ AVt 0 6V Gr AM gt ANN AIN CPIN L L ILEAKAGE Va 5 pF T VT 0 6V e 500 nA ME Qo Mu EE v Vss Legend CPIN Input Capacitance VT Threshold Voltage ILEAKAGE Leakage Current at the Pin Ric Interconnect Resistance Rs Source Impedance VA Analog Voltage TABLE 8 2 REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 vias All Other POR Resets 03h STATUS GPWUF CWUF TO PD Z DC C 00 1 1xxx qq0q guuu 07h CMCONO CMPOUT COUTEN POL CMPTOCS CMPON CNREF CPREF CWU 1111 1111 uuuu uuuu N A TRISGPIO VO Control Register 1111 1111 Legend x Unknown u Unchanged Unimplemented read as 0 g Depends on condition DS41239D page 40 2007 Microchip Technology Inc PIC10F200 202 204
85. n that is defined as a digital input may cause the input buffer to consume more current than is specified 8 6 Comparator Wake up Flag The comparator wake up flag is set whenever all of the following conditions are met e CWU 0 CMCONO lt 0 gt CMCONO has been read to latch the last known state of the CMPOUT bit MOVF CMCONO W Device is in Sleep The output of the comparator has changed state The wake up flag may be cleared in software or by another device Reset 8 7 Comparator Operation During Sleep When the comparator is active and the device is placed in Sleep mode the comparator remains active While the comparator is powered up higher Sleep currents than shown in the power down current specification will occur To minimize power consumption while in Sleep mode turn off the comparator before entering Sleep 8 8 Effects of a Reset A Power on Reset POR forces the CMCONO register to its Reset state This forces the Comparator module to be in the comparator Reset mode This ensures that all potential inputs are analog inputs Device current is minimized when analog inputs are present at Reset time The comparator will be powered down during the Reset interval 8 9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 8 3 Since the analog pins are connected to a digital output they have reverse biased diodes to VDD and Vss The analog input therefore
86. nter mode uses the TOCKI pin to increment Timer0 It is selected by setting the TOCS bit OPTION lt 5 gt setting the CMPTOCS bit CMCONO lt 4 gt and setting the COUTEN bit CMCONO lt 6 gt In this mode TimerO will increment either on every rising or falling edge of pin TOCKI The TOSE bit OPTION lt 4 gt determines the source edge Clearing the TOSE bit selects the rising edge Restrictions on the external clock input are discussed in detail in Section 7 1 Using Timer0 with an External Clock PIC10F204 206 The second Counter mode uses the output of the com parator to increment TimerO It can be entered in two different ways The first way is selected by setting the TOCS bit OPTION lt 5 gt and clearing the CMPTOCS bit CMCON lt 4 gt COUTEN CMCON lt 6 gt does not affect this mode of operation This enables an internal connection between the comparator and the TimerO The second way is selected by setting the TOCS bit OPTION lt 5 gt setting the CMPTOCS bit CMCONO lt 4 gt and clearing the COUTEN bit CMCONO lt 6 gt This allows the output of the compara tor onto the TOCKI pin while keeping the TOCKI input active Therefore any comparator change on the COUT pin is fed back into the TOCKI input The TOSE bit OPTION lt 4 gt determines the source edge Clear ing the TOSE bit selects the rising edge Restrictions on the external clock input as discussed in Section 7 1 Using Timer0 with an External Clock P
87. omparator can be placed on GP2 The CMCONO register shown in Register 8 1 controls the comparator operation A block diagram of the comparator is shown in Figure 8 1 REGISTER 8 1 CMCONO REGISTER R 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 CMPOUT COUTEN POL CMPTOCS CMPON CNREF CPREF CWU bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 CMPOUT Comparator Output bit 1 VIN gt VIN 0 VIN lt VIN bit 6 COUTEN Comparator Output Enable bit 2 1 Output of comparator is NOT placed on the COUT pin 0 Output of comparator is placed in the COUT pin bit 5 POL Comparator Output Polarity bit 2 1 Output of comparator not inverted 0 Output of comparator inverted bit 4 CMPTOCS Comparator TMRO Clock Source bit 2 1 TMRO clock source selected by TOCS control bit 0 Comparator output used as TMRO clock source bit 3 CMPON Comparator Enable bit 1 Comparator is on 0 Comparator is off bit 2 CNREF Comparator Negative Reference Select bit 2 1 CIN pin 0 Internal voltage reference bit 1 CPREF Comparator Positive Reference Select bit 2 1 CIN pin 0 CIN pin bit 0 CWU Comparator Wake up on Change Enable bit 1 Wake up on comparator change is disabled 0 Wake up on comparator change is enabled Note 1 Overri
88. on the current consumption a The test conditions for all IDD measurements in active operation mode are All VO pins tri stated pulled to Vss TOCKI VDD MCLR VDD WDT enabled disabled as specified b For standby current measurements the conditions are the same except that the device is in Sleep mode 4 Power down current is measured with the part in Sleep mode with all I O pins in high impedance state and tied to VDD or Vss 5 The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled 6 Measured with the comparator enabled A A A A E IATA O 2007 Microchip Technology Inc DS41239D page 65 PIC10F200 202 204 206 12 2 DC Characteristics PIC10F200 202 204 206 Extended Standard Operating Conditions unless otherwise specified Operating Temperature 40xC TA 125xC extended DC CHARACTERISTICS Param Ho Sym Characteristic Min Typ Max Units Conditions D001 VDD Supply Voltage 2 0 5 5 V See Figure 12 1 D002 VDR RAM Data Retention Voltage 1 5 V Device in Sleep mode D003 VPOR VDD Start Voltage Vss V to ensure Power on Reset D004 Svoo VDD Rise Rate 0 05 Vims to ensure Power on Reset IDD Supply Current D010 175 275 HA VDD 2 0V 0 63 1 1 mA VDD 5 0V IPD Power down Current D020 0 1 9 HA VDD 2 0V 0 35 15 HA VDD 5 0V IWDT WDT Curren
89. ontents of register f are moved to destination d If d is 0 destination is the W register If d is 1 the destination is file register f d 1 is useful as a test of a file register since status flag Z is affected MOVLW Move literal to W Syntax label MOVLW k Operands 0 lt k lt 255 Operation k gt W Status Affected None Description The eight bit literal k is loaded into the W register The don t cares will assembled as 0 s MOVWF Move W tof Syntax label MOVWF f Operands 0 lt f lt 31 Operation W gt f Status Affected None Description Move data from the W register to register f NOP No Operation Syntax label NOP Operands None Operation No operation Status Affected None Description No operation OPTION Load OPTION Register Syntax label OPTION Operands None Operation W gt Option Status Affected None Description The content of the W register is loaded into the OPTION register RE eee DS41239D page 56 2007 Microchip Technology Inc PIC10F200 202 204 206 RETLW Syntax Operands Operation Status Affected Description RLF Syntax Operands Operation Status Affected Description RRF Syntax Operands Operation Status Affected Description Return with literal in W label RETLW k 0 lt k lt 255 k 2 W TOS 5 PC None The W register is load
90. ontents of the W register with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f DS41239D page 58 2007 Microchip Technology Inc PIC10F200 202 204 206 11 0 DEVELOPMENT SUPPORT The PIC microcontrollers are supported with a full range of hardware and software development tools Integrated Development Environment MPLAB IDE Software Assemblers Compilers Linkers MPASM Assembler MPLAB C18 and MPLAB C30 C Compilers MPLINK Object Linker MPLIB Object Librarian MPLAB ASM30 Assembler Linker Library Simulators MPLAB SIM Software Simulator Emulators MPLAB ICE 2000 In Circuit Emulator MPLAB ICE 4000 In Circuit Emulator In Circuit Debugger MPLAB ICD 2 Device Programmers PICSTART Plus Development Programmer MPLAB PM3 Device Programmer PICkit 2 Development Programmer Low Cost Demonstration and Development Boards and Evaluation Kits 11 1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8 16 bit micro controller market The MPLAB IDE is a Windows operating system based application that contains A single graphical interface to all debugging tools Simulator Programmer sold separately Emulator sold separately n Circuit Debugger sold separately A full featured editor w
91. or relief under that Act Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED WRITTEN OR ORAL STATUTORY OR OTHERWISE RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ITS CONDITION QUALITY PERFORMANCE MERCHANTABILITY OR FITNESS FOR PURPOSE Microchip disclaims all liability arising from this information and its use Use of Microchip devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless Microchip from any and all damages claims suits or expenses resulting from such use No licenses are conveyed implicitly or otherwise under any Microchip intellectual property rights QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV ISO TS 16949 2002 Trademarks The Microchip name and logo the Microchip logo Accuron dsPIC KEELOQ KEELOQ logo microID MPLAB PIC PICmicro PICSTART PRO MATE PowerSmart rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U S A and other countries AmpLab FilterLab Linear Active Thermistor Migratable Memory MXDEV MXLAB PS logo SEEVAL SmartSensor and The Embedded Control Solutions Compan
92. pplication circuit This is simply done with two lines for clock and data and three other lines for power ground and the programming voltage This allows customers to manu facture boards with unprogrammed devices and then program the microcontroller just before shipping the product This also allows the most recent firmware or a custom firmware to be programmed The devices are placed into a Program Verify mode by holding the GP1 and GPO pins low while raising the MCLR VPP pin from VIL to ViHH see programming specification GP1 becomes the programming clock and GPO becomes the programming data Both GP1 and GPO are Schmitt Trigger inputs in this mode After Reset a 6 bit command is then supplied to the device Depending on the command 16 bits of program data are then supplied to or from the device depending if the command was a Load or a Read For complete details of serial programming please refer to the PIC10F200 202 204 206 Programming Specifications A typical In Circuit Serial Programming connection is shown in Figure 9 10 DS41239D page 50 2007 Microchip Technology Inc PIC10F200 202 204 206 10 0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories Byte oriented operations Bit oriented operations Literal and control operations Each PIC16 instruction is a 12 bit word divided into an opcode which specifies the instruction type and one
93. ration Status Affected Description BTFSC Syntax Operands Operation Status Affected Description Bit Clear f label BCE f b O lt f lt 31 O lt b lt 7 0 gt f lt b gt None Bit b in register f is cleared Bit Set f label BSF fb 0 lt f lt 31 O lt b lt 7 1 gt f lt b gt None Bit b in register f is set Bit Test f Skip if Clear label BTFSC fb 0 lt f lt 31 O lt b lt 7 skip if f lt b gt 0 None If bit b in register f is 0 then the next instruction is skipped If bit b is 0 then the next instruc tion fetched during the current instruction execution is discarded and a NOP is executed instead making this a two cycle instruction 2007 Microchip Technology Inc DS41239D page 53 PIC10F200 202 204 206 BTFSS Syntax Operands Operation Status Affected Description CALL Syntax Operands Operation Status Affected Description CLRF Syntax Operands Operation Status Affected Description Bit Test f Skip if Set label BTFSS f b O lt f lt 31 O lt b lt 7 skip if f lt b gt 1 None If bit b in register f is 1 then the next instruction is skipped If bit b is 1 then the next instruc tion fetched during the current instruction execution is discarded and a NOP is executed instead making this a two cycle instruction Subroutine Call
94. re 8 2 along with the relationship between the analog input levels and the digital output When the analog input at VIN is less than the analog input VIN the output of the comparator is a digital low level When the analog input at VIN is greater than the analog input VIN the output of the comparator is a digital high level The shaded areas of the output of the comparator in Figure 8 2 represent the uncertainty due to input offsets and response time See Table 12 1 for Common Mode Voltage FIGURE 8 2 SINGLE COMPARATOR Vin Result Vin 8 3 Comparator Reference An internal reference signal may be used depending on the comparator operating mode The analog signal that is present at VIN is compared to the signal at VIN and the digital output of the comparator is adjusted accordingly Figure 8 2 Please see Table 12 1 for internal reference specifications 8 4 Comparator Response Time Response time is the minimum time after selecting a new reference voltage or input source before the comparator output is to have a valid level If the com parator inputs are changed a delay must be used to allow the comparator to settle to its new state Please see Table 12 1 for comparator response time specifications 8 5 Comparator Output The comparator output is read through CMCONO register This bit is read only The comparator output may also be used internally see Figure 8 1 Note Analog levels on any pi
95. reset PIC10F200 202 204 206 devices when a 3 Brown out Reset occurs external brown out protection PIC10F20K circuits may be built as shown in Figure 9 7 and Figure 9 8 KE Q1 MELRO FIGURE 9 7 BROWN OUT PROTECTION CIRCUIT 1 E VDD Note 1 This brown out circuit is less expensive VDD although less accurate Transistor Q1 turns off when VDD is below a certain level such that R1 e _ 0 7V PIC10F20X VDD R14 RO 2 Pin must be confirmed as MCLR Note 1 This circuit will activate Reset when VDD goes below Vz 0 7V where Vz Zener voltage 2 Pin must be confirmed as MCLR DS41239D page 48 O 2007 Microchip Technology Inc PIC10F200 202 204 206 BROWN OUT PROTECTION CIRCUIT 3 FIGURE 9 9 vm Vss Capacitor VDD RST MCLR PIC10F20X Note This brown out protection circuit employs Microchip Technology s MCP809 micro controller supervisor There are 7 different trip point selections to accommodate 5V to 3V systems 9 9 Power Down Mode Sleep A device may be powered down Sleep and later powered up wake up from Sleep 9 9 1 SLEEP The Power Down mode is entered by executing a SLEEP instruction If enabled the Watchdog Timer will be cleared but keeps running the TO bit STATUS lt 4 gt is set the PD bit STATUS lt 3 gt is cleared and the oscilla
96. ressable register Depending on the instruction executed the ALU may affect the values of the Carry C Digit Carry DC and Zero Z bits in the STATUS register The C and DC bits operate as a borrow and digit borrow out bit respec tively in subtraction See the SUBWF and ADDWF instructions for examples A simplified block diagram is shown in Figure 3 1 and Figure 3 2 with the corresponding device pins described in Table 3 2 2007 Microchip Technology Inc DS41239D page 9 PIC10F200 202 204 206 FIGURE 3 1 PIC10F200 202 BLOCK DIAGRAM 9 10 8 GPIO Data Bus Flash lt Program Counter lt lt e 512 x12 or gt lt GPO ICSPDAT 256 x12 1 Ei GP1NCSPCLK RAM lt 4 GP2 TOCKI FOSC4 Program Stack 1 24 or 16 577 X GP3 MCLR VPP Memory Stack 2 bytes File Registers Program 12 Bus RAM Addr y 9 Instruction Reg Addr MUS Direct Addr 5 Indirest FSR Reg ri STATUS Reg 8 3 Device Reset Timer J L Instruction Power on Decore Na Reset N ALU Watchdog 8 Timing Tien Zoo Generation Internal RC W Reg Clock TimerO MCLR VDD Vss DS41239D page 10 2007 Microchip Technology Inc PIC10F200 202 204 206
97. rolled by various registers See Table 5 1 Note A read of the ports reads the pins not the output data latches That is if an output driver on a pin is enabled and driven high but the external system is holding it low a read of the port will indicate that the pin is low The TRIS registers are write only and are set output drivers disabled upon Reset TABLE 5 1 ORDER OF PRECEDENCE FOR PIN FUNCTIONS Priority GPO GP1 GP2 GP3 1 CIN CIN FOSC4 VMCLR 2 TRIS GPIO TRIS GPIO COUT 3 TOCKI 4 TRIS GPIO 5 3 VO Interfacing The equivalent circuit for an UO port pin is shown in Figure 5 1 All port pins except GP3 which is input only may be used for both input and output operations For input operations these ports are non latching Any input must be present until read by an input instruction e g MOVF GPIO W The outputs are latched and remain unchanged until the output latch is rewritten To use a port pin as output the corresponding direction control bit in TRIS must be cleared 0 For use as an input the corresponding TRIS bit must be set Any I O pin except GP3 can be programmed individually as input or output FIGURE 5 1 PIC10F200 202 204 206 EQUIVALENT CIRCUIT FOR A SINGLE VO PIN Data Bus eD Q Data VDD VDD Y T W B XN VO in Reg D Q pi IRIS Vss Vss
98. rom the document could be made without affecting the overall usefulness 6 Isthere any incorrect or misleading information what and where 7 How would you improve this document DS41239D page 92 2007 Microchip Technology Inc PIC10F200 202 204 206 PRODUCT IDENTIFICATION SYSTEM To order or obtain information e g on pricing or delivery refer to the factory or the listed sales office PART NO X IXX XXX T si M Examples Device Temperature Package Pattern a PIC10F200 I P Industrial temp PDIP Range package Pb free b PIC10F202T E OT Extended temp SOT 23 package Pb free Tape and Reel Device PIC10F200 c EE Extended temp DFN PIC10F202 pass PIC10F204 PIC10F206 PIC10F200T Tape amp Reel PIC10F202T Tape amp Reel PIC10F204T Tape amp Reel PIC10F206T Tape amp Reel Temperature 40 C to 85 C Industrial Range E 40 C to 125 C Extended Package P 300 mil PDIP Pb free OT SOT 23 6 LD Pb free MC DFN 8 LD 2x3 Pb free Pattern Special Requirements 2007 Microchip Technology Inc DS41239D page 93 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480 792 7277 Technical Support http support microchip com Web Address www microchip com Atlanta Duluth GA Tel 678 957 9614 Fax 678 957 1455 Boston W
99. ry for a device is specified by its register file The register file is divided into two functional groups Special Function Registers SFR and General Purpose Registers GPR The Special Function Registers include the TMRO reg ister the Program Counter PCL the STATUS register the I O register GPIO and the File Select Register FSR In addition Special Function Registers are used to control the I O port configuration and prescaler options The General Purpose registers are used for data and control information under command of the instructions For the PIC10F200 204 the register file is composed of 7 Special Function registers and 16 General Purpose registers see Figure 4 3 and Figure 4 4 For the PIC10F202 206 the register file is composed of 8 Special Function registers and 24 General Purpose registers see Figure 4 4 4 3 1 GENERAL PURPOSE REGISTER FILE The General Purpose Register file is accessed either directly or indirectly through the File Select Register FSR See Section 4 9 Indirect Data Addressing INDF and FSR Registers DS41239D page 16 2007 Microchip Technology Inc PIC10F200 202 204 206 FIGURE 4 3 PIC10F200 204 REGISTER FILE MAP File Address 00h INDF 01h TMRO 02h PCL 03h STATUS 04h FSR 05h OSCCAL 06h GPIO 07h CMCONO 08h Unimplemented OFh 10h General Purpose Registers 1Fh Note 1 Not a physical register See Section 4 9 Indirect Data Ad
100. s 0 the result is placed in the W register If d is 1 the result is placed back in register f INCFSZ Increment f Skip if 0 Syntax label INCFSZ fd Operands O lt f lt 31 d e 0 1 Operation f 1 gt dest skip if result 0 Status Affected None Description The contents of register f are incremented If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f If the result is 0 then the next instruction which is already fetched is discarded and a NOP is executed instead making ita two cycle instruction IORLW Inclusive OR literal with W Syntax label IORLW k Operands 0 lt k lt 255 Operation W OR k gt W Status Affected Z Description The contents of the W register are OR ed with the eight bit literal k The result is placed in the W register 2007 Microchip Technology Inc DS41239D page 55 PIC10F200 202 204 206 IORWF Inclusive OR W with f Syntax label IORWF f d Operands O lt f lt 31 d e 0 1 Operation W OR f dest Status Affected Z Description Inclusive OR the W register with register f If d is 0 the result is placed in the W register If d is 1 the result is placed back in register T MOVF Move f Syntax label MOVF fd Operands O lt f lt 31 d e 0 1 Operation f gt dest Status Affected Z Description The c
101. s the value OAh Load the value 09 into the FSR register A read of the INDF register will return the value of 10h Increment the value of the FSR register by one FSR 0A A read of the INDR register now will return the value of OAh Reading INDF itself indirectly FSR 0 will produce 00h Writing to the INDF register indirectly results in a no operation although Status bits may be affected A simple program to clear RAM locations 10h 1Fh using indirect addressing is shown in Example 4 1 FIGURE 4 6 EXAMPLE 4 1 HOW TO CLEAR RAM USING INDIRECT ADDRESSING MOVLW 0x10 initialize pointer MOVWF FSR to RAM NEXT CLRF INDF clear INDF register INCF FSR F inc pointer BTFSC FSR 4 all done GOTO NEXT CONTINUE NO clear next YES continue The FSR is a 5 bit wide register It is used in conjunc tion with the INDF register to indirectly address the data memory area The FSR lt 4 0 gt bits are used to select data memory addresses 00h to 1Fh Note PIC10F200 202 204 206 Do not use banking FSR 7 5 are unimplemented and read as 1 s DIRECT INDIRECT ADDRESSING PIC10F200 202 204 206 Direct Addressing 4 opcode 0 Location Select 00h Data OFh Indirect Addressing 4 FSR 0 Location Select Memory 10h 1Fh Bank 0 Note 1 For register map detail see Section 4 3 Data Memory
102. since these Resets are viewed as resumption of normal operation The exceptions to this are TO PD GPWUF and CWUF bits They are set or cleared differently in different Reset situations These bits are used in software to determine the nature of Reset See Table 9 1 for a full description of Reset states of all registers Note Erasing the device will also erase the pre programmed internal calibration value for the internal oscillator The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later TABLE 9 1 RESET CONDITIONS FOR REGISTERS PIC10F200 202 204 206 MCLR Reset WDT Time out Register Address Power on Reset Wake up On Pin Change Wake on Comparator Change W gggg gagu gggg gagu INDF 00h XXXX XXXX uuuu uuuu TMRO 01h XXXX XXXX uuuu uuuu PCL 02h 1111 1111 At CT STATUS 03h 00 1 1xxx q00q quuul STATUS 03h 00 1 1xxx qq0q quuu FSR 04h 111x xxxx 111u uuuu OSCCAL 05h 1111 1110 uuuu uuuu GPIO 06h XXXX uuuu CMCONG 07h 1111 1111 uuuu uuuu OPTION KEE Os RE TA TIT EER TRISGPIO 1111 se LT Legend u unchanged x unknown unimplemented bit read as 0 q value depends on condition Note 1 Bits 7 2 of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory 2 See Table 9 2 for Reset value for specific conditions 3 PIC10F204 206 only DS41
103. synchronization SYNCHRONIZATION When no prescaler is used the external clock input is the same as the prescaler output The synchronization of TOCKI with the internal phase clocks is accom plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks Figure 6 4 Therefore it is necessary for TOCKI to be high for at least 2 Tosc and a small RC delay of 2 TtOH and low for at least 2 Tosc and a small RC delay of 2 TtOH Refer to the electrical specification of the desired device When a prescaler is used the external clock input is divided by the asynchronous ripple counter type prescaler so that the prescaler output is symmetrical For the external clock to meet the sampling require ment the ripple counter must be taken into account Therefore it is necessary for TOCKI to have a period of atleast 4 Tosc and a small RC delay of 4 TtOH divided by the prescaler value The only requirement on TOCKI high and low time is that they do not violate the minimum pulse width requirement of TtOH Refer to parameters 40 41 and 42 in the electrical specification of the desired device DS41239D page 30 2007 Microchip Technology Inc PIC10F200 202 204 206 6 1 2 TIMERO INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks there is a small delay from the time the external clock edge occurs to the time the TimerO module is actually incremented Figure 6 4 shows the
104. t D022 1 0 18 uA lvo 2 0V 7 22 uA VpD 5 0V ICMP Comparator Current D023 12 27 pA Vpp 2 0V 42 85 pA VpD 5 0 VREF Internal Reference Current 6 D024 85 120 HA VDD 2 0V 175 200 HA VDD 5 0V These parameters are characterized but not tested Note 1 Data in the Typical Typ column is based on characterization results at 25 C This data is for design guidance only and is not tested 2 This is the limit to which VDD can be lowered in Sleep mode without losing RAM data 3 The supply current is mainly a function of the operating voltage and frequency Other factors such as bus loading bus rate internal code execution pattern and temperature also have an impact on the current consumption a The test conditions for all IDD measurements in active operation mode are All VO pins tri stated pulled to Vss TOCKI VDD MCLR VDD WDT enabled disabled as specified b For standby current measurements the conditions are the same except that the device is in Sleep mode 4 Power down current is measured with the part in Sleep mode with all VO pins in high impedance state and tied to VDD or Vss 5 The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled 6 Measured with the Comparator enabled ETE EE N EE EN NN eee DS41239D page 66 2007 Microchip Technolo
105. t affects the Z DC or C bits then the write to these three bits is disabled These bits are set or cleared according to the device logic Furthermore the TO and PD bits are not writable Therefore the result of an instruction with the STATUS register as destination may be different than intended For example CLRF STATUS will clear the upper three bits and set the Z bit This leaves the STATUS register as 000u uluu where u unchanged Therefore it is recommended that only BCF BSF and MOVWF instructions be used to alter the STATUS regis ter These instructions do not affect the Z DC or C bits from the STATUS register For other instructions which do affect Status bits see Section 10 0 Instruction Set Summary REGISTER 4 1 STATUS REGISTER R W 0 R W 0 R W 0 R 1 R 1 R W x R W x R W x GPWUF cwur TO PD Z DC C bit 7 bit O Legend R Readable bit W Writable bit U Unimplemented bit read as n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 GPWUF GPIO Reset bit 1 Reset due to wake up from Sleep on pin change 0 After power up or other Reset bit 6 CWUF Comparator Wake up on Change Flag bit 1 Reset due to wake up from Sleep on comparator change 0 After power up or other Reset conditions bit 5 Reserved Do not use Use of this bit may affect upward compatibility with future products bit 4 TO Time out bit 0 WD
106. tOH divided by the prescaler value The only requirement on TOCKI or the comparator output high and low time is that they do not violate the minimum pulse width requirement of TtOH Refer to parameters 40 41 and 42 in the electrical specification of the desired device DS41239D page 34 2007 Microchip Technology Inc PIC10F200 202 204 206 7 1 2 TIMERO INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks there is a small delay from the time the external clock edge occurs to the time the TimerO module is actually incremented Figure 7 4 shows the delay from the external clock edge to the timer incrementing FIGURE 7 4 TIMERO TIMING WITH EXTERNAL CLOCK External Clock Input or Prescaler Outputl2 ANNA 011021093104 Q11 Q2 Q3 Q4 Q11 Q2 Q3 I Q4 Q11 AZ Q3 Q4 Small pulse NX misses sampling External Clock Prescaler Output After Sampling Increment TimerO Q4 A A A TimerO TO X T0 1 y TO 2 Note 1 Delay from clock input change to TimerO increment is 3 Tosc to 7 Tosc Duration of Q Tosc Therefore the error in measuring the interval between two edges on Timer0 input 4 Tosc max 2 External clock if no prescaler selected prescaler output otherwise 3 The arrows indicate the points in time where sampling occurs 7 2 Prescaler An 8 bit counter is available as a prescaler for the TimerO
107. tead of many smaller files Enhanced code maintainability by grouping related modules together Flexible creation of libraries with easy module listing replacement deletion and extraction 11 5 MPLAB ASM30 Assembler Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices MPLAB C30 C Compiler uses the assembler to produce its object file The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file Notable features of the assembler include Support for the entire dsPIC30F instruction set Support for fixed point and floating point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 11 6 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC hosted environment by simulat ing the PIC MCUs and dsPIC DSCs on an instruction level On any given instruction the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller Registers can be logged to files for further run time analysis The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution actions on I O most peripherals and internal registers The MPLAB SIM Software Simulator fully supports symbolic deb
108. ter to be written to the tri state latches of PORTB A 1 forces the pin to a high impedance state and disables the output buffers 4 If this instruction is executed on the TMRO register and where applicable d 1 the prescaler will be cleared if assigned to TMRO DS41239D page 52 2007 Microchip Technology Inc PIC10F200 202 204 206 ADDWF Syntax Operands Operation Status Affected Description ANDLW Syntax Operands Operation Status Affected Description ANDWF Syntax Operands Operation Status Affected Description Add W andf label ADDWF fid O lt f lt 31 d e 0 1 W f gt dest C DC Z Add the contents of the W register and register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f AND literal with W label ANDLW k 0 lt k lt 255 W AND k gt W Z The contents of the W register are AND ed with the eight bit literal k The result is placed in the W register AND W with f label ANDWF fd 0 lt f lt 31 d e 0 1 W AND f dest Z The contents of the W register are AND ed with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f BCF Syntax Operands Operation Status Affected Description BSF Syntax Operands Ope
109. tolerancing per ASME Y14 5M BSC Basic Dimension Theoretically exact value shown without tolerances Microchip Technology Drawing C04 018B DS41239D page 84 2007 Microchip Technology Inc PIC10F200 202 204 206 8 Lead Plastic Dual Flat No Lead Package MC 2x3x0 9 mm Body DFN Note Forthe most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging i L K 1 E EXPOSED PAD NOTE 1 TOP VIEW BOTTOM VIEW A3 A1 NOTE2 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0 50 BSC Overall Height A 0 80 0 90 1 00 Standoff A1 0 00 0 02 0 05 Contact Thickness A3 0 20 REF Overall Length D 2 00 BSC Overall Width E 3 00 BSC Exposed Pad Length D2 1 30 1 75 Exposed Pad Width E2 1 50 1 90 Contact Width b 0 18 0 25 0 30 Contact Length L 0 30 0 40 0 50 Contact to Exposed Pad K 0 20 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Package may have one or more exposed tie bars at ends 3 Package is saw singulated 4 Dimensioning and tolerancing per ASME Y14 5M BSC Basic Dimension Theoretically exact value shown without tolerances REF Reference Dimension usually without tolerance for information purposes only Microchip Technology Dra
110. tor driver is turned off The I O ports maintain the status they had before the SLEEP instruction was executed driving high driving low or high impedance Note A Reset generated by a WDT time out does not drive the MCLR pin low For lowest current consumption while powered down the TOCKI input should be at VDD or Vss and the GP3 MCLR VPP pin must be at a logic high level if MCLR is enabled 9 9 2 WAKE UP FROM SLEEP The device can wake up from Sleep through one of the following events 1 An external Reset input on GP3 MCLR VPP pin when configured as MCLR 2 A Watchdog Timer time out Reset if WDT was enabled 3 A change on input pin GPO GP1 or GP3 when wake up on change is enabled 4 Acomparator output change has occurred when wake up on comparator change is enabled These events cause a device Reset The TO PD GPWUF and CWUF bits can be used to determine the cause of device Reset The TO bit is cleared if a WDT time out occurred and caused wake up The PD bit which is set on power up is cleared when SLEEP is invoked The GPWUF bit indicates a change in state while in Sleep at pins GPO GP1 or GP3 since the last file or bit operation on GP port The CWUF bit indicates a change in the state while in Sleep of the comparator output Note Caution Right before entering Sleep read the input pins When in Sleep wake up occurs when the values at the pins change
111. ude prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification The boards support a variety of features including LEDs temperature sensors switches speakers RS 232 interfaces LCD displays potentiometers and additional EEPROM memory The demonstration and development boards can be used in teaching environments for prototyping custom circuits and for learning about various microcontroller applications In addition to the PICDEM and dsPICDEM demon stration development board series of circuits Microchip has a line of evaluation kits and demonstration software for analog filter design KEELOQ security ICs CAN IrDA PowerSmart battery management SEEVAL evaluation system Sigma Delta ADC flow rate sensing plus many more Check the Microchip web page www microchip com and the latest Product Selector Guide DS00148 for the complete list of demonstration development and evaluation kits DS41239D page 62 2007 Microchip Technology Inc PIC10F200 202 204 206 12 0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient temperature under bas 40 C to 125 C Storage temperature sise mn ne tetuer aia 65 C to 150 C Voltage on VDD with respect tO VSS nn non RR RR 0 to 6 5V Voltage on MCLR with respect to VSE uen e t e e e bit 0 to 13 5V Voltage on all other pins with respect to Vase 0 3V to VDD 0 3V Total
112. ugging using the MPLAB C18 and MPLAB C30 C Compilers and the MPASM and MPLAB ASM30 Assemblers The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment making it an excellent economical software development tool DS41239D page 60 2007 Microchip Technology Inc PIC10F200 202 204 206 11 7 MPLAB ICE 2000 High Performance In Circuit Emulator The MPLAB ICE 2000 In Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC micro controllers Software control of the MPLAB ICE 2000 In Circuit Emulator is advanced by the MPLAB Inte grated Development Environment which allows edit ing building downloading and source debugging from a single environment The MPLAB ICE 2000 is a full featured emulator system with enhanced trace trigger and data monitor ing features Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors The architecture of the MPLAB ICE 2000 In Circuit Emulator allows expansion to support new PIC microcontrollers The MPLAB ICE 2000 In Circuit Emulator system has been designed as a real time emulation system with advanced features that are typically found on more expensive development tools The PC platform and Microsoft Windows 32 bit operating system were chosen to best make these features available in a simple un
113. weak pull up resistor is implemented using a transistor refer to Table 12 2 for the pull up resistor ranges This will eliminate external RC components usually needed to create a Power on Reset A maximum rise time for VDD is specified See Section 12 0 Electrical Characteristics for details When the devices start normal operation exit the Reset condition device operating parameters volt age frequency temperature must be met to ensure operation If these conditions are not met the devices must be held in Reset until the operating parameters are met A simplified block diagram of the on chip Power on Reset circuit is shown in Figure 9 2 Timer see Section 9 5 Device Reset Timer DRT circuit are closely related On power up the Reset latch is set and the DRT is reset The DRT timer begins counting once it detects MCLR to be high After the time out period which is typically 18 ms it will reset the Reset latch and thus end the on chip Reset signal A power up example where MCLR is held low is shown in Figure 9 3 VDD is allowed to rise and stabilize before bringing MCLR high The chip will actually come out of Reset TDRT msec after MCLR goes high In Figure 9 4 the on chip Power on Reset feature is being used MCLR and VDD are tied together or the pin is programmed to be GP3 The VDD is stable before the Start up Timer times out and there is no problem in getting a proper Reset However Figure 9 5 dep
114. wing C04 123B 2007 Microchip Technology Inc DS41239D page 85 PIC10F200 202 204 206 NOTES DS41239D page 86 2007 Microchip Technology Inc PIC10F200 202 204 206 APPENDIX A REVISION HISTORY Revision C August 2006 Added 8 Pin DFN Pin Diagram Revised Table 1 1 Reformated all Registers Revised Section 4 8 and added note Section 5 3 changed Figure reference to Figure 5 1 Tables 6 1 and 7 1 removed shading from TRISGPIO I O Control Register Sections 8 1 8 4 changed Table reference to Table 12 2 Section 14 1 Revised and replaced Package Marking Information and drawings Added Tables 14 1 amp 14 2 Added DFN Package drawing Revision D April 2007 Revised section 12 1 12 2 12 3 Table 1 1 12 1 12 3 12 4 Added Section 13 0 Replaced Package Draw ings Rev AP Removed instances of PICmicro and replaced it with PIC 2007 Microchip Technology Inc DS41239D page 87 PIC10F200 202 204 206 NOTES DS41239D page 88 2007 Microchip Technology Inc PIC10F200 202 204 206 INDEX A Assembler MPASM Aesembler eee 60 B Block Diagram On Chip Reset Circuit 44 TimerO TMRO WDT Prescaler Watchdog Timer RR ee ee 47 Brown Out Protection Circuit esses 48 C C Compilers MPLAB C18 MPLAB C30 BT AA EE e e ieee ice Clocking Scheme a d E 13 Code Protection rtr eren 41 50 Comparator Comparator Module
115. xecuted during the following Q1 through Q4 The clocks and instruction execution flow is shown in Figure 3 3 and Example 3 1 3 2 An instruction cycle consists of four Q cycles Q1 Q2 Q3 and Q4 The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute take another instruction cycle However due to the pipelining each instruction effectively executes in one cycle If an instruction causes the PC to change e g GOTO then two cycles are required to complete the instruction Example 3 1 Instruction Flow Pipelining A fetch cycle begins with the PC incrementing in Q1 In the execution cycle the fetched instruction is latched into the Instruction Register IR in cycle Q1 This instruction is then decoded and executed during the Q2 Q3 and Q4 cycles Data memory is read during Q2 operand read and written during Q4 destination write FIGURE 3 3 CLOCK INSTRUCTION CYCLE 91 92 AZ Qs Q1 Q2 Q3 Qs 91 92 Q3 Qs OSCH N V ZA Ex V JL LANAS NTN TN gt oN NA Q2 N V Internal C E EU PON iaa Q4 ITA X EE PC PC PC 1 PC 2 Fetch INST PC Execute INST PC 1 Fetch INST PC 1 Execute INST PC Fetch INST PC 2 Execute INST PC 1 EXAMPLE 3 1 INSTRUCTION PIPELINE FLOW 1 MOVLW 03H Fetch 1 Execute 1 2 MOVWF GPIO Fetch 2 Execute 2 3 CALL S
116. y are registered trademarks of Microchip Technology Incorporated in the U S A Analog for the Digital Age Application Maestro CodeGuard dsPICDEM dsPICDEM net dsPICworks ECAN ECONOMONITOR FanSense FlexROM fuzzyLAB In Circuit Serial Programming ICSP ICEPIC Mindi MiWi MPASM MPLAB Certified logo MPLIB MPLINK PICkit PICDEM PICDEM net PICLAB PICtail PowerCal Powerlnfo PowerMate PowerTool REAL ICE rfLAB rfPICDEM Select Mode Smart Serial SmartTel Total Endurance UNI O WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U S A and other countries SQTP is a service mark of Microchip Technology Incorporated in the U S A All other trademarks mentioned herein are property of their respective companies 2007 Microchip Technology Incorporated Printed in the U S A All Rights Reserved gt Printed on recycled paper Microchip received ISO TS 16949 2002 certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona Gresham Oregon and Mountain View California The Company s quality system processes and procedures are for its PIC MCUs and dsPIC DSCs KEELO code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchip s quality system for the design and manufacture of development systems is ISO 9001 2000 certified DS41239D page ii 2007 Microchip Tec

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