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ANALOG DEVICES ADuC824 MicroConverter Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU handbook

1. ADC INPUT VOLTAGE mV e o 19 364 SAMPLE COUNT 0 100 200 ADC RANGE 20mV 40mV 80mV 160mV 320mV 640mV 1 28V 2 56V Figure 20 Primary ADC Range Matching 34 Bipolar Unipolar Inputs The analog inputs on the ADuC824 can accept either unipolar or bipolar input voltage ranges Bipolar input ranges do not imply that the part can handle negative voltages with respect to system AGND Unipolar and bipolar signals on the AIN input on the primary ADC are referenced to the voltage on the respective AIN input For example if AIN is 2 5 V and the primary ADC is config ured for an analog input range of 0 mV to 20 mV the input voltage range on the AIN input is 2 5 V to 2 52 V If AIN is 2 5 V and the ADuC824 is configured for an analog input range of 1 28 V the analog input range on the AIN input is 1 22 V to 3 78 V i e 2 5 V 1 28 V As mentioned earlier the auxiliary ADC input is a single ended input with respect to the system AGND In this context a bipolar signal on the auxiliary ADC can only span 30 mV negative with respect to AGND before violating the voltage input limits for this ADC Bipolar or unipolar options are chosen by programming the Primary and Auxiliary Unipolar enable bits in the ADCOCON and ADCICON SFRs respectively T
2. ttp ee 29 Power Consumption aine reete 64 OFOH OFOM OPFOQL 2 onore int 30 Power Saving Modes ar eee teh 64 seg 30 Grounding and Board Layout Recommendations 64 GNOH GNOMJGNU L eec eto 30 ADuC824 System Self Identification 65 30 OTHER HARDWARE CONSIDERATIONS 65 PRIMARY AND AUXILIARY ADC DESCRIPTION 31 In Circuit Serial Download 65 ERE ER de 31 Embedded Serial Port Debugger 65 Primary ADC a 31 Single Pin Emulation Mode eee 65 ADC E 32 Enhanced Hooks Emulation Mode 66 PRIMARY AND AUXILIARY ADC NOISE Typical System Configuration 66 PERFORMANCE eei tii 33 QUICKSTART DEVELOPMENT 67 Analog Input Channels 2 2 2 33 OUTLINE 68 Primary and Auxiliary ADC Inputs 33 Revision MP 68 Analog Input Ranges 33 Programmable Gain Amplifier sees
3. gt lt 7 CYCLE 8 55 se 51 32 sa sa ss se DATA omn DATA 0 1 SHFTcLOK L DATA BIT 6 DATA BIT 7 L IT Figure 40 UART Serial Port Transmission Mode 0 Reception is initiated when the receive enable bit REN is 1 and the receive interrupt bit RI is 0 When RI is cleared the data is clocked into the RXD line and the clock pulses are output from the TXD line Mode 1 8 UART Variable Baud Rate Mode 1 is selected by clearing SMO and setting SM1 Each data byte LSB first is preceded by a start bit 0 and followed by a stop bit 1 Therefore 10 bits are transmitted on TXD or received on RXD The baud rate is set by the Timer 1 or Timer 2 overflow rate or a combination of the two one for transmission and the other for reception Transmission is initiated by writing to SBUF The write to SBUF signal also loads a 1 stop bit into the ninth bit position of the transmit shift register The data is output bit by bit until the stop bit appears on TXD and the transmit interrupt flag is automatically set as shown in Figure 41 START STOP BIT V 01 X be X be os X e X ov SCON 1 1 x SET INTERRUPT i e READY FOR MORE DATA Figure 41 UART Serial Port Transmission Mode 0 Reception is initiated when a 1 to 0 transition is detected on RXD Assuming a valid start bit was detected
4. 824 ANALOG DEVICES MicroConverter Dual Channel 16 24 Bit ADCs with Embedded FLASH MCU ADuC824 FEATURES High Resolution Sigma Delta ADCs Two Independent ADCs 16 and 24 Bit Resolution Programmable Gain Front End 24 Bit No Missing Codes Primary ADC 13 Bit p p Resolution 20 Hz 20 mV Range 18 Bit p p Resolution 20 Hz 2 56 V Range Memory 8 KB On Chip Flash EE Program Memory 640 Bytes On Chip Flash EE Data Memory Flash EE 100 Year Retention 100 Kcycles Endurance 256 Bytes On Chip Data RAM 8051 Based Core 8051 Compatible Instruction Set 12 58 MHz Max 32 kHz External Crystal On Chip Programmable PLL Three 16 Bit Timer Counters 26 Programmable I O Lines 11 Interrupt Sources Two Priority Levels Power Specified for 3 V and 5 V Operation Normal 3 mA 3 V Core CLK 1 5 MHz Power Down 20 pA 32 kHz Crystal Running On Chip Peripherals On Chip Temperature Sensor 12 Bit Voltage Output DAC Dual Excitation Current Sources Reference Detect Circuit Time Interval Counter TIC UART Serial I O I C Compatible SPI Serial 1 0 Watchdog Timer WDT Power Supply Monitor PSM APPLICATIONS Intelligent Sensors IEEE1451 2 Compatible Weigh Scales Portable Instrumentation Pressure Transducers 4 20 mA Transmitters GENERAL DESCRIPTION The ADuC824 is a complete smart transducer front end inte grating two high resolution sigma delta ADCs an 8 bit MCU and program data Flash EE Me
5. D7H T2CON RCAP2L RCAP2H TL2 TH2 TF2 EXF2 RCLK TCLK 2 TR2 CNT2 uii gt RESERVED RESERV EG RESERVED CFH CCH 0 co CBH CDH WDCON CHIPID EADRL PRES 2 PREO WDS WDE WDWR pits RESERVED RESERVED RESERVED RESERVED RESERVED C7H 0 C6H 5 1 C3H 1 COH 0 COH 10H C2H 06H Pape 2 PS PTI PXi PTO PX gt eret EDATA1 EDATA2 EDATA4 01 BDH BSH 0 _ 0 B9H B8H B9H BCH us um mmm P3 RD WR Ti TO INTi INTO TXD RXD BITS gt NOT USED NOT USED NOT USED NOT USED RESERVED RESERVED NOT USED B7H 1 BeH 1 B5H 1 BsH 1 B2H 1 1 1 EA 2 ES 1 1 IE IEIP2 BITS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED AFH 0 _0 ADH ACH 0 0 _0 ASH 0 soon ASH KOH x P2 TIMECON HTHSEC SEC MIN HOUR INTVAL BITS NOT USED ATH AAAGH 51 ASH SM ASH LAZH PAIN eon AIH A2H A4H ASH AGH SCON SBUF 2 I2CDAT SM0 SM1 SM2 REN TB8 RB8 1 R1 BITS gt NOT USED NO
6. these pins are pulled high by the internal pull up resis tors In this state they can also be used as inputs as input pins being externally pulled low they will source current because of the internal pull ups With 0s written to them both these pins will drive a logic low output voltage VOL and will be capable of sinking 10 mA compared to the standard 1 6 mA sink capa bility on the other port pins These pins also have various secondary functions described in Table XXI Table XXI Port 1 Alternate Pin Functions Pin Alternate Function P1 0 T2 Timer Counter 2 External Input T2EX Timer Counter 2 Capture Reload Trigger The remaining Port 1 pins 1 2 1 7 can only be configured as Analog Input ADC Analog Output DAC or Digital Input pins By power on default these pins are configured as Analog Inputs i e 1 written in the corresponding Port 1 register bit To configure any of these pins as digital inputs the user should write a 40 to these port bits to configure the corresponding pin as a high impedance digital input Port 2 is a bidirectional port with internal pull up resistors directly controlled via the P2 SFR SFR address A0 hex Port 2 pins that have 1 written to them are pulled high by the internal pull up resistors and in that state they can be used as inputs As inputs Port 2 pins being pulled externally low will source current because of the internal pull up resistors P
7. vary ratiometrically with the excitation current Resistor R1 must however have a low temperature coefficient to avoid errors in the reference voltage over temperature REV B ADuC824 QUICKSTART DEVELOPMENT SYSTEM The QuickStart Development System is a full featured low cost development tool suite supporting the ADuC824 The system consists of the following PC based Windows compatible hard ware and software development tools ADuC824 Evaluation Board Plug In Power Supply and Serial Port Cable 8051 Assembler C Compiler 2 Kcode Limited ADSIM Windows MicroConverter Code Simulator In Circuit Code Download Serial Downloader Serial Port Debugger CD ROM Documentation and Two Additional Prototype Devices Hardware Code Development Code Functionality In Circuit Debugger Miscellaneous Other Figures 54 shows the typical components of a QuickStart Devel opment System while Figure 55 shows a typical debug session A brief description of some of the software tools components in the QuickStart Development System is given below d cx SVS quic ss Mem Figure 54 Components of the QuickStart Development System REV B Download In Circuit Serial Downloader The Serial Downloader is a software program that allows the user to serially download an assembled program Intel Hex format file to the on chip program FLASH memory via the serial COMI port on a standard PC An Applicati
8. 43 B SER B eus 23 Watchdog Dimers 46 Stack Pointer SB 23 Power Supply Monitor 41 Data Pointer DPTR 23 Serial Peripheral Interface 2 48 Program Status Word PSW 23 I C Compatible Interface 50 Power Control PCON oct mtra 23 8051 COMPATIBLE ON CHIP PERIPHERALS 51 SPECIAL FUNCTION REGISTERS ss 24 Parallel VO Ports 0 3 51 SFR INTERFACE TO THE PRIMARY AND Mimers COUMTCTS voee sies ncs 51 AUXILIARY 25 TIMER COUNTER 0 AND 1 OPERATING MODES 54 5 T 25 UART 57 ADOMODE aos 26 Interrupt System 60 27 ADuC824 HARDWARE DESIGN CONSIDERATIONS 62 ADCIGON 28 Glock Oscillator iet ee e eee oe t tein reves ens 62 28 External Memory 62 ICON m 29 Power On Reset Operation 63 29 Power S pplies 63
9. 4 RESET VALUE OF STACK POINTER Figure 15 Lower 128 Bytes of Internal Data Memory Reset initializes the stack pointer to location 07 Hex and incre ments it once to start from locations 08 Hex which is also the first register RO of register bank 1 Thus if one is going to use more than one register bank the stack pointer should be initialized to an area of RAM not used for data storage REV B ADuC824 The SFR space is mapped to the upper 128 bytes of internal data memory space and accessed by direct addressing only It provides an interface between the CPU and all on chip peripherals A block diagram showing the programming model of the ADuC824 via the SFR area is shown in Figure 16 A complete SFR map is shown in Figure 17 640 BYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH EE DATA MEMORY 8 KBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH EE PROGRAM MEMORY 128 BYTE 8051 SPECIAL COMPATIBLE FUNCTION CORE REGISTER AREA 256 BYTES RAM DUAL SIGMA DELTA ADCs OTHER ON CHIP PERIPHERALS TEMPERATURE SENSOR CURRENT SOURCES 12 BIT DAC SERIAL WDT PSM TIC PLL Figure 16 Programming Model OVERVIEW OF MCU RELATED SFRs Accumulator SFR ACC is the Accumulator register and is used for math operations including addition subtraction integer multiplication and division and Boolean bit manipulations The mnemonics for accumulator specific instructions refer to the Accumul
10. Also because factory 5 V 25 C gain calibration coefficients are automatically present at power on an internal full scale calibration will only be required if the part is being operated at 3 V or at temperatures significantly different from 25 C The ADuC824 offers internal or system calibration facilities For full calibration to occur on the selected ADC the calibration logic must record the modulator output for two different input conditions These are zero scale and full scale points These points are derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration The result of the zero scale calibration conversion is stored in the Offset Calibration Registers for the appropriate ADC The result of the full scale calibration conversion is stored in the Gain Calibration Registers for the appropriate ADC With these readings the calibration logic can calculate the offset and the gain slope for the input to output transfer function of the converter During an internal zero scale or full scale calibration the re spective zero input and full scale input are automatically connected to the ADC input pins internally to the device A system calibration however expects the system zero scale and system full scale voltages to be applied to the external ADC pins before the calibration mode is initiated In this way external ADC errors are taken into
11. High 0 Low 3 PT1 Written by User to Select Timer 1 Interrupt Priority 1 High 0 Low 2 Written by User to Select External Interrupt 1 Priority 1 High 0 Low 1 PTO Written by User to Select Timer 0 Interrupt Priority 1 High 0 Low 0 Written by User to Select External Interrupt 0 Priority 1 High 0 Low 60 ADuC824 IEIP2 Secondary Interrupt Enable and Priority Register SFR Address A9H Power On Default Value Addressable PTI PPSM PSI ETI EPSM ESI Table XXXII IEIP2 SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 PTI Written by User to Select TIC Interrupt Priority 1 High 0 Low 5 PPSM Written by User to Select Power Supply Monitor Interrupt Priority 1 High 0 Low 4 PSI Written by User to Select Serial Port Interrupt Priority 417 High 0 Low 3 Reserved This Bit Must Be 0 2 ETI Written by User to Enable 1 or Disable 0 TIC Interrupt 1 EPSM Written by User to Enable 1 or Disable 0 Power Supply Monitor Interrupt 0 ESI Written by User to Enable 1 or Disable 0 Serial Port Interrupt Interrupt Priority The Interrupt Enable registers are written by the user to enable individual interrupt sources while the Interrupt Priorit
12. Master Slave Mode Bit Set by user to enable software master mode Cleared by user to enable hardware slave mode 2 I2CRS Reset Bit SLAVE MODE ONLY Set by user to reset the IC interface Cleared by user code for normal operation 1 I2CTX Direction Transfer Bit SLAVE MODE ONLY Set by the MicroConverter if the interface is transmitting Cleared by the MicroConverter if the interface is receiving 0 I2CI Interrupt Bit SLAVE MODE ONLY Set by the MicroConverter after a byte has been transmitted or received Cleared automatically when user code reads the I2CDAT SFR see I2CDAT below DCADD Address Register DCDAT Data Register Function Holds the peripheral address for Function The I2CDAT SFR is written by the the part It may be overwritten by user to transmit data over the user code Technical Note uC001 at interface or read by user code to read www analog com microconverter data just received by the PC interface describes the format of the stan Accessing I2CDAT automatically dard 7 bit address in detail clears any pending interrupt and SFR Address 9BH the I2CI bit in the I2CCON SFR Power On Default Value 55H User software should only access Bit Addressable No I2CDAT once per interrupt cycle SFR Address 9AH Power On Default Value 00H Bit Addressable No 50 REV B ADuC824 8051 COMPATIBLE ON CHIP PERIPHERALS This section gives a brief overview of the various secondary p
13. P1 2 must be driven high or low externally The voltage output from the DAC can also be configured to appear at this pin If the DAC output is not being used one or both of the excitation current sources 200 or 2 x 200 uA can be programmed to be sourced at this pin 4 P1 3 AIND IEXC2 I Port 1 3 This pin has no digital output driver it can function as a digital input for which 0 must be written to the port bit As a digital input P1 3 must be driven high or low externally This pin can provide an analog input AIN5 to the auxiliary ADC and one or both of the excitation current sources 200 HA or 2 x 200 can be programmed to be sourced at this pin 5 5 Analog Supply Voltage 3 or 5 6 AGND S Analog Ground Ground reference pin for the analog circuitry 7 REFIN I Reference Input Negative Terminal 8 REFIN I Reference Input Positive Terminal 9 11 P1 4 P1 6 I Port 1 4 to P1 6 These pins have no digital output drivers they can function as digital inputs for which 0 must be written to the respective port bit As a digital input these pins must be driven high or low externally These port pins also have the following analog functionality P1 4 AIN1 I Primary ADC Channel Positive Analog Input P1 5 AIN2 I Primary ADC Channel Negative Analog Input P1 6 AIN3 I Auxiliary ADC Input or muxed Primary ADC Channel Positive Analog Input 12 P1 7 AIN4 DAC Port 1 7 This pin has no digital output driver
14. UART port P3 1 TXD IO Transmitter Data Output asynchronous or Clock Output synchronous of serial UART port P3 2 INTO IO Interrupt 0 programmable edge or level triggered Interrupt input which can be programmed to one of two priority levels This pin can also be used as a gate control input to Timer P3 3 INTI IO Interrupt 1 programmable edge or level triggered Interrupt input which can be programmed to one of two priority levels This pin can also be used as a gate control input to Timerl 20 34 48 DVpp S Digital supply 3 V or 5 V 21 35 47 DGND S Digital ground ground reference point for the digital circuitry REV B 19 ADuC824 PIN FUNCTION DESCRIPTIONS continued No Mnemonic Type Description 22 25 P3 4 P3 7 P3 4 TO P3 5 T1 P3 6 WR P3 7 RD 26 SCLK 27 SDATA MOSI 28 31 P2 0 P2 3 32 XTALI 33 XTAL2 36 39 P2 4 P2 7 40 EA 41 PSEN 42 ALE 43 46 P0 0 P0 3 ADO AD3 49 52 P0 4 P0 7 AD4 AD7 IO IO IO IO IO IO IO IO IO IO IO IO P3 4 P3 7 are bidirectional port pins with internal pull up resistors Port 3 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs Port 3 pins being pulled externally low will source current because of the internal pull up resistors When driving a 0 to 1 output transition a strong pull up is active for two core clock periods of
15. emulators where users must replace the chip on their board with a header device that the emulator pod plugs into The only hardware concern is then one of determining if adequate space is available for the emulator pod to fit into the system enclosure Typical System Configuration A typical ADuC824 configuration is shown in Figure 53 It sum marizes some of the hardware considerations discussed in the previous paragraphs 66 Figure 53 also includes connections for typical analog mea surement application of the ADuC824 namely an interface to an RTD Resistive Temperature Device The arrangement shown is commonly referred to as a 4 wire RTD configuration Here the on chip excitation current sources are enabled to excite the sensor An external differential reference voltage is generated by the current sourced through resistor R1 This current also flows directly through the RTD which generates a differential voltage directly proportional to temperature This differential voltage is routed directly to the positive and negative inputs of the primary ADC AINI AIN2 respectively A second external resistor R2 is used to ensure that absolute analog input voltage on the negative input to the primary ADC stays within that specified for the ADuC824 i e AGND 100 mV It should also be noted that variations in the excitation current do not affect the measurement system as the input voltage from the RTD and reference voltage across
16. trHpx Data and Address Hold after RD 0 0 ns 4 trHpz Data Float after RD 89 21 70 ns 4 tLLDV ALE Low to Valid Data In 486 8tcogg 150 ns 4 tAVDV Address to Valid Data In 550 Otcogg 165 ns 4 ALE Low to RD Low 188 288 50 50 ns 4 tavwL Address Valid to RD Low 188 4tcogg 130 ns 4 TRLAZ RD Low to Address Float 0 0 ns 4 RD High to ALE High 39 119 40 tcogg 40 4 PORT 0 I O PORT 2 0 Figure 4 External Data Memory Read Cycle 10 REV B ADuC824 Parameter 12 58 MHz Core_Clk Variable Core_Clk Min Max Min Max Unit Figure EXTERNAL DATA MEMORY WRITE CYCLE WR Pulsewidth 377 100 5 5 tAVLL Address Valid after ALE Low 39 tcong 40 ns 5 Address Hold after ALE Low 44 35 ns 5 trrwr ALE Low to WR Low 188 288 3tcogg 50 3tcogg 50 ns 5 tAVWL Address Valid to WR Low 188 4tcong 130 ns 5 tovwx Data Valid to WR Transition 29 tcong 20 ns 5 tovwH Data Setup before WR EN 406 Itcogg 150 ns 5 twHOx Data and Address Hold after WR 29 tcogg 20 ns 5 twHLH WR High to ALE High 39 119 tconE 40 40 5 5 ALE tax tovwn gt XQ cem XX Figure 5 External Data Memory Write Cycle REV B 11 ADuC824 12 58 MHz Core_Clk Variable Core_Clk Parameter Min Typ
17. 0043 Hex 0053 WDS WDIR 1 005 The watchdog can be configured to generate an interrupt instead of reset when it times out This is used for logging errors or to examine the internal status of the microcontroller core to understand from a software debug point of view why a watchdog timeout occurred The watchdog interrupt is slightly different from the normal interrupts in that its priority level is always set to 1 and it is not possible to disable the interrupt via the global disable bit EA in the IE SFR This is done to ensure that the interrupt will always be responded to if a watchdog timeout occurs The watchdog will only produce an interrupt if the watchdog timeout is greater than zero 61 ADuC824 ADuC824 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design consider ations that must be addressed when integrating the ADuC824 into any hardware system Clock Oscillator As described earlier the core clock frequency for the ADuC824 is generated from an on chip PLL that locks onto a multiple 384 times of 32 768 kHz The latter is generated from an inter nal clock oscillator To use the internal clock oscillator connect 32 768 kHz parallel resonant crystal between and XTAL2 pins 32 and 33 as shown in Figure 43 As shown in the typical external crystal connection diagram in Figure 44 two internal 12 pF capacitors are provided on chip These are
18. 1 and 1 respectively i e core clock frequency 1 57 MHz and b SPI bit rate selection bits SPR1 and SPRO bits in SPICON SFR set to 0 and 0 respectively REV B SCLOCK CPOL 0 SCLOCK CPOL 1 MOSI ipsu BITS 6 1 LSB IN Figure 9 SPI Master Mode Timing CPHA 0 15 ADuC824 Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING CPHA 1 tss SS to SCLOCK Edge 0 ns 10 tsr SCLOCK Low Pulsewidth 330 ns 10 SCLOCK High Pulsewidth 330 ns 10 tpav Data Output Valid after SCLOCK Edge 50 ns 10 tpsu Data Input Setup Time before SCLOCK Edge 100 ns 10 tDHD Data Input Hold Time after SCLOCK Edge 100 ns 10 Data Output Fall Time 10 25 ns 10 tpg Data Output Rise Time 10 25 ns 10 tsp SCLOCK Rise Time 10 25 ns 10 tsp SCLOCK Fall Time 10 25 ns 10 tsrs SS High after SCLOCK Edge 0 ns 10 55 155 tors SCLOCK CPOL 0 SCLOCK CPOL 1 ipsu Figure 10 SPI Slave Mode Timing 1 16 REV B ADuC824 Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING CPHA 0 tss SS to SCLOCK Edge 0 ns 11 SCLOCK Low Pulsewidth 330 ns 11 SCLOCK High Pulsewidth 330 ns 11 tpav Data Output Valid after SCLOCK Edge 50 ns 11 tpsu Data Input Setup Time before SCLOCK Edge 100 ns 11 tDHD Data Input Hold Time after SCLOCK Edge 100 ns 11 tDF Data Output Fall Time 10 25 ns 11 tpg Data Output Rise Time 10 25 ns 11 tsp SCLOCK Rise Time 1
19. 16 See Table XI in ADC Description 15 Update Rate and Gain Range AIN 18 mV AIN 7 8 mV Range 20 mV AIN 1 V Range 2 56 At DC AIN 7 8 mV Range 20 mV At DC AIN 1 Range 2 56 At DC AIN 1 V Range 2 56 V 20 Hz Update Rate 50 Hz 60 Hz 1 Hz AIN 7 8 mV Range 20 mV 50 Hz 60 Hz 1 Hz AIN 1 V Range 2 56 V 50 Hz 60 Hz 1 Hz AIN 1 V Range 2 56 V 50 Hz 60 Hz 1 Hz 20 Hz Update Rate 50 Hz 60 Hz 1 Hz 20 Hz Update Rate Range 2 5 V 20 Hz Update Rate Output Noise Varies with Selected Update Rate ppm of FSR max typ nV C typ typ ppm C typ typ dBs typ dBs min dBs min dBs typ dBs typ dBs min dBs min dBs min dBs min dBs min Bits min Bits p p typ ppm of FSR max Offset Error 2 LSB typ Offset Error Drift 1 uv C typ Full Scale Error 2 5 LSB typ Gain Error Drift 0 5 ppm C Power Supply Rejection PSR 80 AIN 1 20 Hz Update Rate dBs min Normal Mode 50 Hz 60 Hz Rejection On AIN 60 50 Hz 60 Hz 1 Hz dBs min On REFIN 60 50 Hz 60 Hz 1 Hz 20 Hz Update Rate dBs min DAC PERFORMANCE DC Specifications Resolution 12 Bits Relative Accuracy t3 LSB typ Differential Nonlinearity 1 Guaranteed 12 Bit Monotonic LSB max Offset Error 50 mV max Gain Error 1 AVpp Range max Veer Range typ AC Specifications 7 Voltage Output Settling Time 15 Settling Time to 1 LSB of Final Value us ty
20. 16 I O lines Ports 0 and 2 are dedicated to bus functions during external program memory fetches Port 0 serves as a multiplexed address data bus It emits the low byte of the program counter PCL as an address and then goes into a float state awaiting the arrival of the code byte from the program memory During the 62 time that the low byte of the program counter is valid the signal ALE Address Latch Enable clocks this byte into an address latch Meanwhile Port 2 P2 emits the high byte of the program counter PCH then PSEN strobes the EPROM and the code byte is read into the ADuC824 ADuC824 EPROM 00 07 INSTRUCTION A0 A7 Figure 44 External Program Memory Interface Note that program memory addresses are always 16 bits wide even in cases where the actual amount of program memory used is less than 64 Kbytes External program execution sacrifices two of the 8 bit ports PO and P2 to the function of addressing the program memory While executing from external program memory Ports 0 and 2 can be used simultaneously for read write access to exter nal data memory but not for general purpose I O Though both external program memory and external data memory are accessed by some of the same pins the two are completely independent of each other from a software point of view For example the chip can read write external data memory while executing from external program memory Figure 45 sho
21. 3 16 69 19 79 2 00 69 19 79 16 255 5 35 1 15 255 5 35 16 ADC converting in bipolar mode NOTES Analog Input Channels The primary ADC has four associated analog input pins labelled AINI to AIN4 that can be configured as two fully differential input channels Channel selection bits in the ADCOCON SFR detailed in Table V allow three combinations of differential pair selection as well as an additional shorted input option AIN2 AIN2 The auxiliary ADC has three external input pins labelled AIN3 to AINS5 as well as an internal connection to the internal on chip temperature sensor All inputs to the auxiliary ADC are single ended inputs referenced to the AGND on the part Channel selection bits in the ADC1CON SFR detailed previously in Table VI allow selection of one of four inputs Two input multiplexers switch the selected input channel to the on chip buffer amplifier in the case of the primary ADC and directly to the sigma delta modulator input in the case of the auxiliary ADC When the analog input channel is switched the settling time of the part must elapse before a new valid word is available from the ADC REV ADC converting in bipolar mode In unipolar mode peak to peak resolution at 105 Hz is 15 bits Primary and Auxiliary ADC Inputs The output of the primary ADC multiplexer feeds into a high impedance input stage of the buffer amplifier As a result the primary ADC inputs can handle significant source impedance
22. 40 C 25 C and 85 C The results allow the specification of a minimum endurance figure over supply and temperature of 100 000 cycles with an endurance figure of 700 000 cycles being typical of operation at 25 C Retention quantifies the ability of the Flash EE memory to retain its programmed data over time Again the ADuC824 has been qualified in accordance with the formal JEDEC Retention Life time Specification A117 at a specific junction temperature 55 C As part of this qualification procedure the Flash EE memory is cycled to its specified endurance limit described above before data retention is characterized This means that the Flash EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash EE memory is repro grammed It should also be noted that retention lifetime based on an activation energy of 0 6 eV will derate with as shown in Figure 27 300 250 200 2 ADI SPECIFICATION 100 gt 55 150 100 50 0 40 50 60 70 80 90 100 110 T JUNCTION TEMPERATURE C Figure 27 Flash EE Memory Data Retention Using the Flash EE Program Memory The 8 Kbyte Flash EE Program Memory array is mapped into the lower 8 Kbytes of the 64 Kbytes program space addressable by the ADuC824 and is used to hold user code in typical applications The prog
23. Bit Designations Bit Name Description T Reserved for Future Use 6 BO Burnout Current Enable Bit Set by user to enable both transducer burnout current sources in the primary ADC signal paths Cleared by user to disable both transducer burnout current sources 5 ADCIIC Auxiliary ADC Current Correction Bit Set by user to allow scaling of the Auxiliary ADC by an internal current source calibration word 4 ADCOIC Primary ADC Current Correction Bit Set by user to allow scaling of the Primary ADC by an internal current source calibration word 3 I2PIN Current Source 2 Pin Select Bit Set by user to enable current source 2 200 to external pin 3 P1 2 DAC IEXCI Cleared by user to enable current source 2 200 uA to external 4 P1 3 AIN5 IEXC2 2 Current Source 1 Pin Select Bit Set by user to enable current source 1 200 to external pin 4 P1 3 AIN5 IEXC2 Cleared by user to enable current source 1 200 uA to external pin 3 P1 2 DAC IEXCI 1 Current Source 2 Enable Set by user to turn on excitation current source 2 200 uA Cleared by user to turn off excitation current source 2 200 uA 0 Current Source 1 Enable Bit Set by user to turn on excitation current source 1 200 uA Cleared by user to turn off excitation current source 1 200 uA Both current sources can be enabled to the same external pin yielding 400 current source ADCOH ADCOM ADCOL Primary ADC
24. DAC Clear Bit Set to 1 by user to enable normal DAC operation Cleared to 0 by used to reset DAC data registers DAC1 H to zero 0 DACEN DAC Enable Bit Set to 1 by user to enable normal DAC operation Cleared to 0 by used to power down the DAC DACH L DAC Data Register Function DAC Data Registers written by user to update the DAC output SFR Address DACL DAC Data Low Byte gt DACH DAC Data High Byte gt Power On Default Value 00H gt Both Registers Bit Addressable No gt Both Registers The 12 bit DAC data should be written into DACH L right justified such that DACL contains the lower eight bits and the lower nibble of DACH contains the upper four bits REV B E ADuC824 ON CHIP PLL The ADuC824 is intended for use with a 32 768 kHz watch crys tal A PLL locks onto a multiple 384 of this to provide a stable 12 582912 MHz clock for the system The core can operate at this frequency or at binary submultiples of it to allow power saving in cases where maximum core performance is not required The default core clock is the PLL clock divided by 8 or 1 572864 MHz The ADC clocks are also derived from the PLL clock with the modulator rate being the same as the crystal oscillator frequency The above choice of frequencies ensures that the modulators and the core will be synchronous regardless of the core clock rate The PLL control register is PLLCON PLLCON PLL Control Register SFR Addr
25. Fle 2 8 ges 0 30 0 012 j 0 15 0 006 0 20 0 008 gt gt lt 0 15 0 006 0 65 0 35 0 014 2 09 0 082 0 026 0 25 0 010 1 97 0 078 CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location Page 5 02 Data Sheet changed from REV A to REV B Edits to SPECIFICATIONS 2 21 21 43 29 932 d molem arp du beats avandia RORTO aad E 3 3 01 Data Sheet changed from REV 0 to REV A Edits to RESE F DescHphon 525 esn Bet o cnn idc e ee OR Rte ec uin eR ie e pe Un Re 0 RR 19 Edits to Fig re 12 1 SS eR baee au edes pd de x m adus 21 68 REV 02345 0 5 02 PRINTED IN U S A
26. Max Min Typ Max Unit Figure UART TIMING Shift Register Mode Serial Port Clock Cycle Time 0 95 12tcorE us 6 tovxH Output Data Setup to Clock 662 10tcorg 133 ns 6 tpvxH Input Data Setup to Clock 292 2tcorr 133 ns 6 txHDX Input Data Hold after Clock 0 0 ns 6 txHox Output Data Hold after Clock 42 2tcogg 117 ns 6 ALE O TXD OUTPUT CLOCK RXD OUTPUT DATA 12 X mr Figure 6 UART Timing Shift Register Mode REV B ADuC824 Parameter Min Max Unit Figure PC COMPATIBLE INTERFACE TIMING tr SCLOCK Low Pulsewidth 4 7 us 7 tH SCLOCK High Pulsewidth 4 0 us 7 tsHD Start Condition Hold Time 0 6 us 7 tpsu Data Setup Time 100 us 7 tDHD Data Hold Time 0 9 us 7 trsu Setup Time for Repeated Start 0 6 us 7 tpsu Stop Condition Setup Time 0 6 us 7 Bus Free Time between STOP 1 3 us T Condition and a START Condition tR Rise Time of Both SCLOCK and SDATA 300 ns 7 Fall Time Both SCLOCK SDATA 300 ns 7 tsup Pulsewidth of Spike Suppressed 50 ns 7 Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns REV B SDATA SCLK LPS L J STOP START CONDITION CONDITION Figure 7 l C Compatible Interface Timing 13 LS R REPEATED START ADuC824 Parameter Min Typ Max Unit Figure SPI MASTER MODE TIM
27. SPICON SFR Bit Designations Bit Name Description 7 ISPI SPI Interrupt Bit Set by MicroConverter at the end of each SPI transfer Cleared directly by user code or indirectly by reading the SPIDAT SFR 6 WCOL Write Collision Error Bit Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress Cleared by user code 5 SPE SPI Interface Enable Bit Set by user to enable the SPI interface Cleared by user to enable the interface 4 SPIM SPI Master Slave Mode Select Bit Set by user to enable Master Mode operation SCLOCK is an output Cleared by user to enable Slave Mode operation SCLOCK is an input 3 CPOL Clock Polarity Select Bit Set by user if SCLOCK idles high Cleared by user if SCLOCK idles low 2 CPHA Clock Phase Select Bit Set by user if leading SCLOCK edge is to transmit data Cleared by user if trailing SCLOCK edge is to transmit data 1 SPRI SPI Bit Rate Select Bits 0 SPRO These bits select the SCLOCK rate bit rate in Master Mode as follows SPR1 SPRO Selected Bit Rate SPRI SPRO Selected Bit Rate 0 0 2 1 0 8 0 1 4 1 1 16 In SPI Slave Mode SPIM 0 the logic level on the external SS pin Pin 13 can be read via the SPRO bit Bits should contain the same values for master and slave devices 48 REV B ADuC824 The SPIDAT SER is written by the user to transmit data over the SPI interface or read by user code to read data just rece
28. a control register DACCON and two data registers DACH L The DAC output can be programmed to appear at Pin 3 or Pin 12 It should be noted that in 12 bit mode the DAC voltage output will be updated as DAC soon as the DACL data SFR has been written therefore the DAC The ADuC824 incorporates a 12 bit voltage output DAC on chip data register should be updated as DACH first followed by DACL It has a rail to rail voltage output buffer capable of driving The following section gives a brief overview of the various peripher als also available on chip A summary of the SFRs used to control and configure these peripherals is also given DACCON DAC Control Register SFR Address FDH Power On Default Value 00H Bit Addressable No Table XVI DACCON SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 Reserved for Future Use 5 Reserved for Future Use 4 DACPIN DAC Output Pin Select Set by user to direct the DAC output to Pin 12 P1 7 AIN4 DAC Cleared by user to direct the DAC output to Pin 3 P1 2 DAC IEXCI 3 DACS8 DAC 8 Bit Mode Bit Set by user to enable 8 bit DAC operation In this mode the 8 bits in DACL SFR are routed to the 8 MSBs of the DAC and the 4 LSBs of the DAC are set to zero Cleared by user to operate the DAC in its normal 12 bit mode of operation 2 DACRN DAC Output Range Bit Set by user to configure DAC range of 0 Cleared by user to configure DAC range 0 2 5 V 1 DACCLR
29. as high 4000 readily accumulate on the human body and test equipment and can discharge without detection Although the ADuC824 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality a ESD SENSITIVE DEVICE Windows is a registered trademark of Microsoft Corporation 18 REV B ADuC824 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Description 1 P1 0 T2 IO Port 1 0 can function as a digital input or digital output and has a pull up configuration as described below for Port 3 P1 0 has an increased current drive sink capability of 10 mA and can also be used to provide a clock input to Timer 2 When Enabled Counter 2 is incremented in response to a negative transition on the T2 input pin 2 P1 1 T2EX IO Port 1 1 can function as a digital input or digital output and has a pull up configuration as described below for Port 3 P1 1 has an increased current drive sink capability of 10 mA and can also be used to provide a control input to Timer 2 When Enabled a negative transition on the T2EX input pin will cause a Timer 2 capture or reload event 3 P12 DAC IEXCI Port 1 2 This pin has no digital output driver it can function as a digital input for which 0 must be written to the port bit As a digital input
30. board in Figure 52c Whenever possible avoid large discontinuities in the ground plane s such as are formed by a long trace on the same layer since they force return signals to travel a longer path And of course make all connections to the ground plane directly with little or no trace separating the pin from its via to ground If the user plans to connect fast logic signals rise fall time lt 5 ns to any of the ADuC824 s digital inputs add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at ADuC824 input pins A value of 100 or 200 is usually sufficient to prevent high speed signals from coupling capacitively into the ADuC824 and affecting the accuracy of ADC conversions ADuC824 System Self Identification In some hardware designs it may be an advantage for the soft ware running on the ADuC824 target to identify the host Micro Converter For example code running on the ADuC824 may be used at future date to run on an ADuC816 MicroConverter host and the code may be required to operate differently The CHIPID SFR is a read only register located at SFR address C2 hex The top nibble of this byte is set to 0 to designate an ADuC824 host For an ADuC816 host the CHIPID SFR will contain the value 1 in the upper nibble REV OTHER HARDWARE CONSIDERATIONS To facilitate in circuit programming plus in circuit debug and emulation options users will want to implement som
31. connected internally directly to the XTALI and XTAL2 pins and the total input capacitances at both pins is detailed in the specification section of this data sheet The value of the total load capacitance required for the external crystal should be the value recommended by the crystal manufacturer for use with that specific crystal In many cases because of the on chip capacitors additional external load capacitors will not be required ADuC824 32 768kHz Figure 43 External Parallel Resonant Crystal Connections External Memory Interface In addition to its internal program and data memories the ADuC824 can access up to 64 Kbytes of external program memory ROM PROM etc and up to 16 Mbytes of external data memory SRAM select from which code space internal or external program memory to begin executing instructions tie the EA external access pin high or low respectively When EA is high pulled up to Vpp user program execution will start at address 0 of the internal 8 Kbytes Flash EE code space When EA is low tied to ground user program execution will start at address 0 of the external code space In either case addresses above IFFF hex 8K are mapped to the external space Note that a second very important function of the EA pin is described in the Single Pin Emulation Mode section of this data sheet External program memory if used must be connected to the ADuC824 as illustrated in Figure 44 Note that
32. in Normal Mode 3 3 ms typ After WDT Reset in Normal Mode 3 3 Controlled via WDCON SFR ms typ FLASH EE MEMORY RELIABILITY CHARACTERISTICS Endurance 100 000 Cycles min Data Retention 100 Years min POWER REQUIREMENTS DVpp and AVpp Can Be Set Independently Power Supply Voltages AVpp 3 V Nominal Operation 2 4 V min 3 6 V max AVpp 5 V Nominal Operation 4 75 V min 5 25 DVpp 3 V Nominal Operation 211 3 6 max DVpp 5 Nominal Operation 4 75 V min 5 25 V max REV B ADuC824 Parameter ADuC824BS Test Conditions Comments Unit POWER REQUIREMENTS continued Power Supply Currents Normal Mode 18 DVpp Current 4 DVpp 4 75 V to 5 25 V Core CLK 1 57 MHz mA max 2 1 DVpp 2 7 V to 3 6 V Core CLK 1 57 MHz mA max AVpp Current 170 AVpp 5 25 V Core CLK 1 57 MHz max DVpp Current 15 DVpp 4 75 V to 5 25 V Core CLK 12 58 MHz mA max 8 DVpp 2 7 V to 3 6 V Core CLK 12 58 MHz mA max AVpp Current 170 AVpp 5 25 V Core CLK 12 58 MHz max Power Supply Currents Idle Mode 18 DVpp Current 1 2 DVpp 4 75 V to 5 25 V Core CLK 1 57 MHz mA max 750 DVpp 2 7 V to 3 6 V Core CLK 1 57 MHz typ AVpp Current 140 Measured AVpp 5 25 V Core CLK 1 57 MHz uA typ DVpp Current 2 DVpp 4 75 V to 5 25 V Core CLK 12 58 MHz mA typ 1 DVpp 2 7 V to 3 6 V Core CLK 12 58 MHz mA typ AVpp Current 140 Measured at AVpp 5 25 V Core CLK 12 58 MHz uA typ Pow
33. is pulled low the part will execute code from the external program space otherwise the part defaults to code execution from its internal 8 Kbyte Flash EE program memory This internal code space can be downloaded via the UART serial port while the device is in circuit PROGRAM MEMORY SPACE READ ONLY FFFFH EXTERNAL PROGRAM MEMORY SPACE 2000H EA 1 EA 0 INTERNAL EXTERNAL 8 KBYTE PROGRAM FLASH EE MEMORY PROGRAM SPACE MEMORY 0000H Figure 13 Program Memory Map The data memory address space consists of internal and exter nal memory space The internal memory space is divided into four physically separate and distinct blocks namely the lower 128 bytes of RAM the upper 128 bytes of RAM the 128 bytes of special function register SFR area and a 640 byte Flash EE Data memory While the upper 128 bytes of RAM and the SFR area share the same address locations they are accessed through different address modes The lower 128 bytes of data memory can be accessed through direct or indirect addressing the upper 128 bytes of RAM can be accessed through indirect addressing and the SFR area is accessed through direct addressing Also as shown in Figure 13 the additional 640 Bytes of Flash EE Data Memory are available to the user and can be accessed indirectly via a group of control registers mapped into the Special Function Register SFR area Access to the Flash EE Data memory is discussed in detail late
34. is given by the formula Modes 1 and 3 Baud Rate Core Clk 32 x 65536 RCAP2H RCAP2L Table XXIX shows some commonly used baud rates and how they might be calculated from a core clock frequency of 1 5728 MHz and 12 5829 MHz Ideal Core SMOD THi Reload Actual Table Commonly Used Baud Rates Timer 2 Baud CLK Value Value Baud Error Ideal Core RCAP2H RCAP2L Actual 9600 12 58 1 7 F9h 9562 2 5 Baud CLK Value Value Baud Error 2400 12 58 1 27 E5h 2427 1 1 1200 12 58 1 55 1192 0 7 19200 12 58 1 FFh 20 19661 2 4 1200 1 57 1 1 F9h 1170 25 9600 12 58 1 FFh 41 D7h 9591 0 1 2400 12 58 1 FFh 164 5 2398 0 1 1200 12 58 2 FEh 72 B8h 1199 0 1 9600 1 57 1 FFh 5 FBh 9830 2 4 2400 1 57 1 FFh 20 ECh 2458 2 4 1200 1 57 1 FFh 41 D7h 1199 0 1 1 OVERFLOW NOTE OSC FREQ IS DIVIDED BY 2 NOT 12 CONTROL 7 SMOD TIMER 2 TT RX CLOCK TX CLOCK NOTE AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT TIMER 2 INTERRUPT CONTROL TRANSITION DETECTOR EXEN2 THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 42 Timer 2 UART Baud Rates REV B 59 ADuC824 INTERRUPT SYSTEM The ADuC824 provides a total of twelve interrupt sources with two priority levels The control and configuration of the interrupt system is carried out through three Interrupt rel
35. it can function as a digital input for which 0 must be written to the port bit As a digital input P1 7 must be driven high or low externally This pin can provide an analog input AIN4 to the auxiliary ADC or muxed Primary ADC Channel Negative Analog Input The voltage output from the DAC can also be configured to appear at this pin 13 SS I Slave Select Input for the SPI Interface A weak pull up is present on this pin 14 MISO IO Master Input Slave Output for the SPI Interface There is a weak pull up on this input pin 15 RESET I Reset Input A high level on this pin for 24 core clock cycles while the oscillator is running resets the device There is a weak pull down and a Schmitt trigger input stage on this pin External POR power on reset circuitry must be added to drive the RESET pin as described later in this data sheet 16 19 P3 0 P3 3 IO P3 0 P3 3 are bidirectional port pins with internal pull up resistors Port 3 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs Port 3 pins being pulled externally low will source current because of the internal pull up resistors When driving a 0 to 1 output transition a strong pull up is active for two core clock periods of the instruction cycle Port 3 pins also have various secondary functions described below P3 0 RXD IO Receiver Data Input asynchronous or Data Input Output synchronous of serial
36. namely TMOD TCON Control and configuration for Timers 0 and 1 T2CON Control and configuration for Timer 2 TMOD Timer Counter 0 and 1 Mode Register SFR Address 89H Power On Default Value 00H Bit Addressable No Gate C T 1 C T Table XXIII TMOD SFR Designations Bit Name Description 7 Gate Timer 1 Gating Control 6 C T Timer 1 Timer or Counter Select Bit Ul 1 Timer 1 Mode Select 1 Used with Bit 4 MO Timer 1 Mode Select Bit 0 1 1 1 Timer Counter 1 Stopped 3 Gate Timer 0 Gating Control 2 C T Timer 0 Timer or Counter Select Bit 1 Timer 0 Mode Select 1 Timer 0 Mode Select 0 Set by software to select counter operation input from T1 pin Cleared by software to select timer operation input from internal system clock Set by software to select counter operation input from TO pin Cleared by software to select timer operation input from internal system clock Set by software to enable timer counter 1 only while INT pin is high and TRI control bit is set Cleared by software to enable timer 1 whenever TRI control bit is set 0 THI operates as an 8 bit timer counter TL1 serves 5 bit prescaler 0 1 16 Bit Timer Counter and TL1 are cascaded there is no prescaler 0 8 Bit Auto Reload Timer Counter holds a value which is to be reloaded into each time it overflows Set by software to enable ti
37. program memory although reading the memory in parallel mode is still allowed This mode is deactivated by initiating a code erase command in serial download or parallel program ming modes Secure Mode This mode locks code in memory disabling parallel programming program and verify read commands as well as disabling the execution of a MOVC instruction from external memory which is attempting to read the op codes from internal memory This mode is deactivated by initiating a code erase command in serial download or parallel programming modes Serial Safe Mode This mode disables serial download capability on the device If Serial Safe mode is activated and an attempt is made to reset the part into serial download mode 1 RESET asserted and deasserted with PSEN low the part will interpret the serial download reset as a normal reset only Therefore it will not enter serial download mode but only execute a normal reset sequence Serial Safe mode can only be disabled by initiating a code erase command in parallel programming mode Using the Flash EE Data Memory The user Flash EE data memory array consists of 640 bytes that are configured into 160 00H to 9FH 4 byte pages as shown in Figure 30 REV 9FH BYTE 1 00H BYTE 1 Figure 30 Flash EE Data Memory Configuration As with other ADuC824 user peripheral circuits the interface to this memory space is via a group of registers mapped in th
38. rates are programmable and the ADC output resolution will vary with the programmed gain and output rate The device operates from a 32 kHz crystal with an on chip PLL generating a high frequency clock of 12 58 MHz This clock is in turn routed through a programmable clock divider from which the MCU core clock operating frequency is generated The microcontroller core is 8052 and therefore 805 1 instruction set compatible The microcontroller core machine cycle consists of 12 core clock periods of the selected core operating frequency 8 Kbytes of nonvolatile Flash EE program memory are provided on chip 640 bytes of nonvolatile Flash EE data memory and 256 bytes RAM are also integrated on chip The ADuC824 also incorporates additional analog functionality with a 12 bit DAC current sources power supply monitor and a bandgap reference On chip digital peripherals include a watchdog timer time interval counter three timers counters and three serial I O ports SPI UART and C compatible On chip factory firmware supports in circuit serial download and debug modes via UART as well as single pin emulation mode via the EA pin A functional block diagram of the ADuC824 is shown above with a more detailed block diagram shown in Figure 12 The part operates from a single 3 V or 5 V supply When operating from 3 V supplies the power dissipation for the part is below 10 mW The ADuC824 is housed in a 52 lead MQFP package One Techn
39. software while either ADC is active The update rate applies to both Primary and Auxiliary ADCs and is calculated as follows 1 1 3 x SSF X fuop Where Janc ADC Output Update Rate Modulator Clock Frequency 32 768 kHz SF Decimal Value of SF Register The allowable range for SF is 0Dhex to FFhex Examples of SF values and corresponding conversion update rate fapc and con value for the SF register is 45hex resulting in a default ADC update rate of just under 20 Hz Both ADC inputs are chopped to minimize offset errors which means that the settling time for a single conversion or the time to a first conversion result in continuous conversion mode is 2 X tapc mentioned earlier all calibration cycles will be carried out automatically with a maximum i e FFhex SF value to ensure optimum calibra tion performance Once a calibration cycle has completed the value in the SF register will be that programmed by user software Table VII SF SFR Bit Designations SF dec SF hex fapc Hz tapc ms 13 0D 105 3 9 52 69 45 19 79 50 34 255 FF 5 35 186 77 REV B 28 ADuC824 ICON Current Sources Control Register Used to control and configure the various excitation and burnout current source options available on chip SFR Address D5H Power On Default Value 00H Bit Addressable No BO ADCIIC ADCOIC I2PIN I1PIN I2EN I1EN Table VIII ICON SFR
40. the Auxiliary ADC to operate with a phase difference from the primary ADC the Auxiliary ADC will fall into step with the outputs of the primary ADC The result is that the first conversion time for the Auxiliary ADC will be delayed up to three outputs while the Auxiliary ADC update rate is synchronized to the Primary ADC Once ADCMODE has been written with a calibration mode the RDY0 1 bits ADCSTAT are immediately reset and the calibration commences On completion the appropriate calibration registers are written the relevant bits in ADCSTAT are written and the MD2 0 bits are reset to 000 to indicate the ADC is back in power down mode Any calibration request of the Auxiliary ADC while the temperature sensor is selected will fail to complete Although the RDYI bit will be set at the end of the calibration cycle no update of the calibration SFRs will take place and the ERR1 bit will be set Calibrations are performed at maximum SF see SF SFR value guaranteeing optimum calibration operation 26 REV B ADuC824 ADCOCON Primary ADC Control Register Used to configure the Primary ADC for range channel selection external Ref enable and unipolar or bipolar coding SFR Address D2H Power On Default Value 07H Bit Addressable No XREFO CHO UNIO RN2 RN1 RNO Table V ADCOCON SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 XREFO Primary ADC External Reference Select Bit Set by user to en
41. the instruction cycle The secondary functions of Port 3 pins are Timer Counter 0 Input Timer Counter 1 Input Write Control Signal Logic Output Latches the data byte from Port 0 into an external data memory Read Control Signal Logic Output Enables the data from an external data memory to Port 0 Serial interface clock for either the I C compatible or SPI interface As an input this pin is a Schmitt triggered input and a weak internal pull up is present on this pin unless it is outputting logic low Serial data I O for the C compatible interface or master output slave input for the SPI interface A weak internal pull up is present on this pin unless it is outputting logic low Port 2 is a bidirectional port with internal pull up resistors Port 2 pins that have 1s 8 11 written to them are pulled high by the internal pull up resistors and in that state can 16 19 be used as inputs As inputs Port 2 pins being pulled externally low will source current because of the internal pull up resistors Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24 bit external data memory space Input to the crystal oscillator inverter Output from the crystal oscillator inverter Port 2 is a bidirectional port with internal pull up resistors Port 2 pins that have 1s A12 A15 written to them are pulled high by the internal pull up resistors and in that st
42. user software SPICON DACL DACH DACCON ISPE SSPE SSPIM CPOL SPRI SPRO Bits RESERVED RESERVED RESERVED RESERVED FFH 0 FEH FDH FCH 0 FBH 0 FAH_1 F9H 0 ad EDH SPIDAT BITS RESERVED RESERVED NOT USED RESERVED RESERVED RESERVED F7H 0 F6H 0 FSH 0 F3H 0 2 oj FiH FOH 0 oH bail er 2 GNOL GNom GNOH GNiL GN1H MDO MDE MCO MDI 2 I2CRS I2CTX ane gt RESERVED RESERVED EFH O EEH 0 EDH 0 0 0 E8H E9H 55H EAH 55H EBH 53H 9AH EDH 59H BITS RESERVED RESERVED 5 0 E4H 0jE2H OJ EiH QJ EOH 0 00H EIH 00H E2H 00H E3H E4H 00H E5H NOXREEI ERRO T ERRI ADCSTAT ADCOL ADCOM ADCOH ADCiL ADC1H PSMCON BITS RESERVED DFH 0 DEH 0 DDH DCH 0 DBH 0 0 DSH 0 D8H D9H DAH DCH AC ASO PSW ADCMODE ADCOCON ADC1CON SF ICON PLLCON BITS RESERVED D7H 0 06 0 D5H 0 D2H 45H D5H
43. which shows gt 90 dB NMR at 50 Hz and gt 70 dB NMR at 60 Hz when SF 255 dec M il il 10 i 60 70 90 100 EREBUENEY Hz Figure 23 Filter Response SF 255 dec 36 Figures 24 and 25 show the NMR for 50 Hz 60 Hz across the full range of SF word 1 SF 13 dec to SF 255 dec GAIN dB 5 100 110 120 10 30 50 70 90 110 130 150 170 190 210 230 250 SF Decimal Figure 24 50 Hz Normal Mode Rejection vs SF GAIN dB 5 100 110 120 10 30 50 70 90 110 130 150 170 190 210 230 250 SF Decimal Figure 25 60 Hz Normal Mode Rejection vs SF ADC Chopping Both ADCs on the ADuC824 implement a chopping scheme whereby the ADC repeatability reverses its inputs The deci mated digital output words from the Sinc filters therefore have positive offset and negative offset term included As a result a final summing stage is included in each ADC so that each output word from the filter is summed and averaged with the previous filter output to produce a new valid output result to be written to the ADC data SFRs In this way while the ADC throughput or update rate is as discussed earlier and illustrated in Table VII t
44. 0 25 ns 11 tsp SCLOCK Fall Time 10 25 ns 11 tss SS to SCLOCK Edge 50 ns 11 2055 Data Output Valid after SS Edge 20 ns 11 tsps SS High after SCLOCK Edge 0 ns 11 REV B SCLOCK CPOL 0 SCLOCK 1 BITS 6 1 LSB Figure 11 SPI Slave Mode Timing CPHA 0 MISO tosu ton ADuC824 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE T4 25 C unless otherwise noted AVpp to AGND 0 3 V to 7 V Temperature Package Package AVpp to DGND 0 3Vto 47v Model Range Description Option DVppto AGND 0 3 V to 7 V ADuC824BS 40 C to 85 C 52 Lead Plastic 5 52 Dypp to DGND picoter daradara ys 0 3 V to 7 V Quad Flatpack AGND to DGND 0 3 V to 0 3 V AVpp to DVpp ace ve Teneo ote Se e nd 2Vto 5 V Analog Input Voltage to AGND 0 3 V to AVpp 0 3 V QuickStart Reference Input Voltage to AGND 0 3 V to AVpp 0 3 V Development AIN REFIN Current Indefinite 30 mA System Model Description Digital Input Voltage to DGND 0 3 V to DVpp 0 3 V Digital Output Voltage DGND 0 3 V to DVpp 03 EVAL ADUC824QS Development System for the ADuC824 3 MicroConverter containing Operating Temperature Range 40 C to 85 C Storage Temperature Range 65 to 150 Evaluation Bo
45. 34 Bipolar Unipolar 34 Burnout Currents 34 Excitation Currents 35 R tcrence 35 Reference 35 Sigma Delta Modulator 25 Digital 35 ADC 36 37 2 REV SPECIFICATIONS unless otherwise noted ADuC824 Mp 2 7 V to 3 6 V or 4 75 V to 5 25 2 7 V to 3 6 V or 4 75 V to 5 25 V REFIN 2 5 V REFIN AGND AGND DGND 0 V XTAL1 XTAL2 32 768 kHz Crystal all specifications to Tmax Parameter ADuC824BS Test Conditions Comments Unit ADC SPECIFICATIONS Conversion Rate 5 4 On Both Channels Hz min 105 Programmable in 0 732 ms Increments Hz max Primary ADC No Missing Codes 24 20 Hz Update Rate Bits min Resolution 13 Range 20 mV 20 Hz Update Rate Bits p p typ 18 Range 2 56 V 20 Hz Update Rate Bits p p typ Output Noise See Tables IX and X Output Noise Varies with Selected Integral Nonlinearity Offset Error Offset Error Drift Full Scale Error Gain Error Drift ADC Range Matching Power Supply Rejection PSR Common Mode DC Rejection On AIN On AIN On REFIN Common Mode 50 Hz 60Hz Rejection On AIN On REFIN Normal Mode 50 Hz 60 Hz Rejection On AIN On REFIN Auxiliary ADC No Missing Codes Resolution Output Noise Integral Nonlinearity in ADC Description 90 60 60 16
46. C824 is in power down mode again with TIC interrupt enabled the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053 hex The TIC related SFRs are described in Table XVI Note also that the timebase SFRs can be written initially with the current time the TIC can then be controlled and accessed by user software In effect this facilitates the implementation of a real time clock A block diagram of the TIC is shown in Figure 32 ITSO 1 INTERVAL TIMEBASE TIEN SECOND COUNTER T SEC MINUTE COUNTER MIN HOUR COUNTER HOUR INTERVAL TIMEOUT TIME INTERVAL COUNTER INTERRUPT 8 BIT INTERVAL COUNTER COMPARE COUNT INTVAL TIME INTERVAL INTVAL Figure 32 TIC Simplified Block Diagram REV B 43 ADuC824 TIMECON TIC Control Register SFR Address 1 Power On Default Value 00H Bit Addressable No ITS1 ITSO STI TII TIEN ICEN Table XVI TIMECON SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 Reserved for Future Use For future product code compatibility this bit should be written as a 1 5 ITS1 Interval Timebase Selection Bits 4 ITSO Written by user to determine the interval counter update rate ITS1 ITSO Interval Timebase 0 0 1 128 Second 0 1 Seconds 1 0 Minutes 1 1 Hours 3 STI Single Time Interval Bit Set by user to generate a single interval timeout
47. Conversion Result Registers These three 8 bit registers hold the 24 bit conversion result from the Primary ADC SFR Address ADCOH High Data Byte DBH ADCOM Middle Data Byte DAH ADCOL Low Data Byte D9H Power On Default Value 00H Three registers Bit Addressable No All Three registers ADCIH ADCIL Auxiliary ADC Conversion Result Registers These two 8 bit registers hold the 16 bit conversion result from the Auxiliary ADC SFR Address ADCIH High Data Byte DDH ADCIL Low Data Byte DCH Power On Default Value 00H Both Registers Bit Addressable No Both Registers REV B 29 ADuC824 OFOH OFOMI OFOL Primary ADC Offset Calibration Registers These three 8 bit registers hold the 24 bit offset calibration coefficient for the Primary ADC These registers are configured at power on with a factory default value 800000 However these bytes will be automatically overwritten if an internal or system zero scale calibration is initiated by the user via MD2 0 bits in the ADCMODE register SFR Address OFOH Primary ADC Offset Coefficient High Byte E3H OF0M Primary ADC Offset Coefficient Middle Byte E2H OFOL Primary ADC Offset Coefficient Low Byte EIH Power On Default Value 800000H and OFOL Respectively Bit Addressable No All Three Registers 1 Auxiliary ADC Offset Calibration Registers These two 8 bit registers hold the 16 bit offset calibration coefficient for the Auxiliary ADC These registe
48. EST POINTS LOAD REFERENCE 2e 0 2DVpp 0 1V POINTS Vioap Figure 2 Timing Waveform Characteristics REV B ADuC824 12 58 MHz Core_Clk Variable Core_Clk Parameter Min Max Min Max Unit Figure EXTERNAL PROGRAM MEMORY Pulsewidth 119 2tcorE 40 ns 3 Address Valid ALE Low 39 tcorr 40 ns 3 Address Hold after ALE Low 49 tcong 30 ns 3 ALE Low to Valid Instruction In 218 4tcogg 100 ns 3 ALE Low Low 49 tconE 30 ns 3 PSEN Pulsewidth 193 45 ns 3 PSEN Low to Valid Instruction In 133 105 ns 3 tpxix Input Instruction Hold after PSEN 0 0 ns 3 tpx1z Input Instruction Float after PSEN 54 tcorg 25 ns 3 taviv Address to Valid Instruction In 292 5tcogg 105 ns 3 7 PSEN Low to Address Float 25 25 ns 3 tpHax Address Hold after PSEN High 0 0 ns 3 LHLL ALE 0 PSEN 0 PORT 0 I O PORT 2 0 Figure 3 External Memory Read Cycle REV B 9 ADuC824 12 58 MHz Core_Clk Variable Core_Clk Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth 377 6tcogg 100 ns 4 TAVIL Address Valid after ALE Low 39 tcorr 40 ns 4 Address Hold after ALE Low 44 35 ns 4 tur DV RD Low to Valid Data In 232 5tcong 165 ns 4
49. FFICIENTS BEFORE BEING PROVIDED AS THE CONVERSION RESULT SEE PAGE 37 PROGRAMMABLE DIGITAL FILTER THE SINC3 FILTER REMOVES QUANTIZATION NOISE INTRODUCED BY THE MODULATOR THE UPDATE RATE AND BANDWIDTH OF THIS FILTER ARE PROGRAMMABLE VIA THE SF SFR SEE PAGE 35 Figure 18 Primary ADC Block Diagram 31 ADuC824 Auxiliary ADC assuming an external 2 5 V reference The single ended inputs The Auxiliary ADC is intended to convert supplementary inputs can be driven from AIN3 or AIN5 pins or directly from such as those from a cold junction diode or thermistor This ADC the on chip temperature sensor voltage A block diagram of the is not buffered and has a fixed input range of 0 V to 2 5 V Auxiliary ADC is shown in Figure 19 DIFFERENTIAL REFERENCE THE EXTERNAL REFERENCE INPUT TO THE ADuC824 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION THE EXTERNAL REFERENCE VOLTAGE IS SELECTED SIGMA DELTA ADC OUTPUT AVERAGE THE SIGMA DELTA ARCHITECTURE ENSURES AS PART OF THE CHOPPING 16 BITS NO MISSING IMPLEMENTATION EACH CODES THE ENTIRE DATA WORD OUTPUT SIGMA DELTA ADC IS FROM THE FILTER IS ANALOG INPUT CHOPPING VIA THE XREF1 BIT IN ADC1CON REFERENCE DETECT CIRCUITRY TESTS FOR OPEN OR SHORTED REFERENCES INPUTS THE INPUTS ARE ALTERNATELY REVERSED THROUGH THE CONVERSION CYCLE CHOPPING CHOPPED TO REMOVE DRIFT SUMMED AND AVERAGED ERRORS WITH ITS PREDECESSOR TO NULL ADC CHANNEL SEE PAGE 35 OFF
50. ING CPHA 1 SCLOCK Low Pulsewidth 630 ns 8 tsH SCLOCK High Pulsewidth 630 ns 8 tpav Data Output Valid after SCLOCK Edge 50 ns 8 tpsu Data Input Setup Time before SCLOCK Edge 100 ns 8 tDHD Data Input Hold Time after SCLOCK Edge 100 ns 8 Data Output Fall Time 10 25 ns 8 tpg Data Output Rise Time 10 25 ns 8 tsp SCLOCK Rise Time 10 25 ns 8 tsp SCLOCK Fall Time 10 25 ns 8 Characterized under the following conditions a Core clock divider bits CD2 CDI and bits in PLLCON SFR set to 0 1 and 1 respectively i e core clock frequency 1 57 MHz and b SPI bit rate selection bits SPR1 and SPRO bits in SPICON SFR set to 0 and 0 respectively SCLOCK CPOL 0 e ts tsr tsF SCLOCK CPOL 1 MOSI BITS 6 1 X LSB ipsu Figure 8 SPI Master Mode Timing CPHA 1 14 REV B ADuC824 Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING CPHA 0 ts SCLOCK Low Pulsewidth 630 ns 9 SCLOCK High Pulsewidth 630 ns 9 Data Output Valid after SCLOCK Edge 50 ns 9 tposu Data Output Setup before SCLOCK Edge 150 ns 9 tpsu Data Input Setup Time before SCLOCK Edge 100 ns 9 tpHD Data Input Hold Time after SCLOCK Edge 100 ns 9 tpr Data Output Fall Time 10 25 ns 9 tpg Data Output Rise Time 10 25 ns 9 tsp SCLOCK Rise Time 10 25 ns 9 tsp SCLOCK Fall Time 10 25 ns 9 Characterized under the following conditions Core clock divider bits CD2 CDI and CDO bits in PLLCON SFR set to 0
51. If SM2 is cleared RI will be set as soon as the byte of data has been received 4 REN Serial Port Receive Enable Bit Set by user software to enable serial port reception Cleared by user software to disable serial port reception 3 TB8 Serial Port Transmit Bit 9 The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3 2 RB8 Serial Port Receiver Bit 9 The ninth data bit received in Modes 2 and 3 is latched into RB8 For Mode 1 the stop bit is latched into RB8 1 TI Serial Port Transmit Interrupt Flag Set by hardware at the end of the eighth bit in Mode 0 or at the beginning of the stop bit in Modes 1 2 and 3 TI must be cleared by user software 0 RI Serial Port Receiver Interrupt Flag Set by hardware at the end of the eighth bit in mode 0 or halfway through the stop bit in Modes 1 2 and 3 RI must be cleared by software REV 25g ADuC824 Mode 0 8 Bit Shift Register Mode Mode 0 is selected by clearing both the SMO and 1 bits in the SFR SCON Serial data enters and exits through RXD TXD outputs the shift clock Eight data bits are transmitted or received Transmission is initiated by any instruction that writes to SBUF The data is shifted out of the RXD line The eight bits are trans mitted with the least significant bit LSB first as shown in Figure 40 MACHINE gt lt CYCLE 1 CYCLE 2 32 33 5 ss 56 s 52 5
52. If set a timeout will clear the TIEN bit Cleared by user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout 2 TIC Interrupt Bit Set when the 8 bit Interval Counter matches the value in the INTVAL SFR Cleared by user software 1 TIEN Time Interval Enable Bit Set by user to enable the 8 bit time interval counter Cleared by user to disable and clear the contents of the interval counter 0 TCEN Time Clock Enable Bit Set by user to enable the time clock to the time interval counters Cleared by user to disable the clock to the time interval counters and clear the time interval SFRs The time registers HTHSEC SEC MIN and HOUR can be written while TCEN is low 44 REV ADuC824 INTVAL Function SFR Address Power On Default Value Bit Addressable Valid Value HTHSEC Function SFR Address Power On Default Value Bit Addressable Valid Value SEC Function SFR Address Power On Default Value Bit Addressable Valid Value MIN Function SFR Address Power On Default Value Bit Addressable Valid Value HOUR Function SFR Address Power On Default Value Bit Addressable Valid Value REV User Time Interval Select Register User code writes the required time interval to this register When the 8 bit interval counter is equal to the time interval value loaded in the INTVAL SFR the TII bit TIMECON 2 bit is set and generates an i
53. Interrupt Service Routine will return the core to the instruction after that which enabled power down or SPI Interrupt Power down mode is terminated and the CPU services the SPI interrupt The RETI at the end of the ISR will return the core to the instruction after that which enabled power down It should be noted that the I C SPI power down interrupt enable bit SERIPD in the PCON SFR must first be set to allow this mode of operation INTO Interrupt Power down mode is terminated and the CPU services the INTO interrupt The RETI at the end of the ISR will return the core to the instruction after that which enabled power down It should be noted that the INTO power down interrupt enable bit INTOPD in the PCON SFR must first be set to allow this mode of operation Grounding and Board Layout Recommendations As with all high resolution data converters special attention must be paid to grounding and PC board layout of ADuC824 based designs in order to achieve optimum performance from the ADCs and DAC Although the ADuC824 has separate pins for analog and digital ground AGND and DGND the user must not tie these to two separate ground planes unless the two ground planes are con nected together very close to the ADuC824 as illustrated in the simplified example of Figure 52a In systems where digital and analog ground planes are connected together somewhere else at the system s power supply for example they cannot be co
54. R OPEN OR SHORTED REFERENCES INPUTS SEE PAGE 35 REFIN REFIN SIGMA DELTA ADC THE SIGMA DELTA ARCHITECTURE ENSURES 24 BITS NO MISSING CODES THE ENTIRE SIGMA DELTA ADC IS CHOPPED TO REMOVE DRIFT ERROR SEE PAGE 35 OUTPUT AVERAGE AS PART OF THE CHOPPING IMPLEMENTATION EACH DATA WORD OUTPUT FROM THE FILTER IS SUMMED AND AVERAGED WITH ITS PREDECESSOR TO NULL ADC CHANNEL OFFSET ERRORS SEE PAGE 36 AIN1 gt AIN2 AIN3 AIN4 ANALOG MULTIPLEXER A DIFFERENTIAL MULTIPLEXER ALLOWS SELECTION OF THREE FULLY DIFFERENTIAL PAIR OPTIONS AND ADDITIONAL INTERNAL SHORT OPTION AIN2 AIN2 THE MULTIPLEXER IS CONTROLLED VIA THE CHANNEL SELECTION BITS IN ADCOCON SEE PAGES 27 AND 33 mam 2 gt CHOP BUFFER AMPLIFIER THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE ANALOG INPUTS ALLOWING SIGNIFICANT EXTERNAL SOURCE IMPEDANCES REV B SEE PAGE 33 SIGMA DELTA MODULATOR THE MODULATOR PROVIDES A HIGH FREQUENCY 1 BIT DATA STREAM THE OUTPUT OF WHICH IS ALSO CHOPPED TO THE DIGITAL FILTER THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED ANALOG INPUT VOLTAGE SEE PAGE 35 DIGTAL OUTPUT SIGMA DELTA A D CONVERTER RESULT WRITTEN V TO ADCOH M L SIGMA DELTA PROSAMMABEE OUTPUT OUTPUT SERS MODULATOR DIGITAL AVERAGE SCALING O CHOP OUTPUT SCALING THE OUPUT WORD FROM THE DIGITAL FILTER IS SCALED THE CALIBRATION COE
55. SET ERRORS YIELDS EXCELLENT ADC OFFSET AND OFFSET DRIFT PERFORMANCE SEE PAGE 36 SEE PAGE 35 SEE PAGE 36 REFIN REFIN O O SIGMA DELTA A D CONVERTER AIN3O V RESULT WRITTEN V TO ADC1H L SFR BS OUTPUT OUTPUT s FILTER AVERAGE SCALING 5 ON CHIP TEMPERATURE SENSOR CHOP OUTPUT SCALING THE OUPUT WORD FROM THE DIGITAL FILTER IS SCALED BY THE CALIBRATION PROGRAMMABLE DIGITAL COEFFICIENTS BEFORE SIGMA DELTA FILTER BEING PROVIDED AS MODULATOR THE SINC FILTER REMOVES CONVERSION RESULT THE MODULATOR PROVIDES A QUANTIZATION NOISE INTRODUCED SEE PAGE 37 HIGH FREQUENCY 1 BIT DATA BY THE MODULATOR THE UPDATE STREAM THE OUTPUT OF WHICH RATE AND BANDWIDTH OF THIS IS ALSO CHOPPED TO THE FILTER ARE PROGRAMMABLE DIGITAL FILTER VIA THE SF SFR THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED SEE PAGE 35 ANALOG INPUT VOLTAGE SEE PAGE 35 ANALOG MULTIPLEXER A DIFFERENTIAL MULTIPLEXER ALLOWS SELECTION OF THREE EXTERNAL SINGLE ENDED INPUTS OR THE ON CHIP TEMP SENSOR THE MULTIPLEXER IS CONTROLLED VIA THE CHANNEL SELECTION BITS IN ADC1CON SEE PAGES 28 AND 33 Figure 19 Auxiliary ADC Block Diagram 32 ADuC824 PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE Tables IX X and XI below show the output rms noise in UV and output peak to peak resolution in bits rounded to the nearest 0 5 LSB for some typical output update rates on both the Primary and Au
56. T USED NOT USED NOT USED 9FH 0 9 9CH 0 9AH 0 99H 98H 0 oan GALL COUR P1 2 BITS NOT USED ED D NoT USED ED p 97H 1 1 94H 1 1 9 90H 1 NL EE USEI NOT USI NOT USEI USED NOT USI USEI USED TCON TMOD TLO TL1 THO TH1 ta 0 B 0 i P 0 0 on 0 acy uu g 979 gt RESERVED RESERVED 88H 00H 89H 8BH 8CH Po SP DPL DPH DPP PCON BITS 87H 1 86H 1 85H 1183H 1 82H 1 81H 80H 1 RESERVED 80H 81H 82H 83H 84H 87H 00H CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER UP TO FACTORY CALIBRATED VALUES SFR MAP KEY THESE BITS ARE CONTAINED IN THIS BYTE BIT MNEMONIC E0 mo 4 MNEMONIC BIT BIT ADDRESS 898 0 88H_0 88H T DEFAULT VALUE DEFAULT BIT VALUE SFR ADDRESS SFR NOTE SFRs WHOSE ADDRESSES END IN OR 8H ARE BIT ADDRESSABLE Figure 17 Special Function Register Locations and Reset Values ADuC824 SFR INTERFACE TO THE PRIMARY AND AUXILIARY ICON Current Source Control Register Allows user ADCS control of the various on chip current source Both ADCs are controlled and configured via a number of SFRs options that are mentioned here and described in more detail in the ADCOL M H following pages ADCSTAT ADC Status Register Holds general st
57. able the Primary ADC to use the external reference via REFIN REFIN Cleared by user to enable the Primary ADC to use the internal bandgap reference Vppp 1 25 V 5 Primary ADC Channel Selection Bits 4 CHO Written by the user to select the differential input pairs used by the Primary ADC as follows CHO Positive Input Negative Input 0 0 AINI AIN2 0 1 AIN3 AIN4 1 0 AIN2 AIN2 Internal Short 1 1 AIN3 AIN2 3 UNIO Primary ADC Unipolar Bit Set by user to enable unipolar coding i e zero differential input will result in 000000 hex output Cleared by user to enable bipolar coding zero differential input will result in 800000 hex output 2 RN2 Primary ADC Range Bits 1 RNI Written by the user to select the Primary ADC input range as follows 0 RNO RN2 RNI RNO Selected Primary ADC Input Range 2 5 V 0 0 0 20 mV 0 0 1 40 mV 0 1 0 80 mV 0 1 1 160 mV 1 0 0 320 mV 1 0 1 640 mV 1 1 0 1 28 V 1 1 1 2 56 V REV B 27 ADuC824 ADCICON Auxiliary ADC Control Register Used to configure the Auxiliary ADC for channel selection external Ref enable and unipolar or bipolar coding It should be noted that the Auxiliary ADC only operates a fixed input range of SFR Address D3H Power On Default Value 00H Bit Addressable No XREF1 1 UNI Table VI ADC1CON SFR Bit Designations Bit Name Description 7 Rese
58. account and minimized as a result of system calibration It should also be noted that to optimize calibration accuracy all ADuC824 ADC calibrations are carried out auto matically at the slowest update rate Internally in the ADuC824 the coefficients are normalized before being used to scale the words coming out of the digital filter The offset calibration coefficient is subtracted from the result prior to the multiplication by the gain coefficient All ADuC824 ADC specifications will only apply after a zero scale and full scale calibration at the operating point supply voltage temperature of interest From an operational point of view a calibration should be treated like another ADC conversion A zero scale calibration if required should always be carried out before a full scale calibration System software should monitor the relevant ADC RDY0O 1 bit in the ADCSTAT SER to determine end of calibration via a polling sequence or interrupt driven routine REV NONVOLATILE FLASH EE MEMORY Flash EE Memory Overview The ADuC824 incorporates Flash EE memory technology on chip to provide the user with nonvolatile in circuit reprogrammable code and data memory space Flash EE memory is a relatively recent type of nonvolatile memory technology and is based on a single transistor cell architecture This technology is basically an outgrowth of EPROM technology and was developed through the late 1980s Flash EE memory takes the flex
59. ain above 2 5 V for at least 10 ms before the RESET signal is deasserted low by which time the power supply must have reached at least a 2 7 V level The external POR circuit must be opera tional down to 1 2 V or less The timing diagram of Figure 47 illustrates this functionality under three separate events power up brownout and power down Notice that when RESET is asserted high it tracks the voltage on DVpp 2 5V MIN DVpp 1 2V MAX 10ms 1 2V MAX Figure 47 External POR Timing The best way to implement an external POR function to meet the above requirements involves the use of a dedicated POR chip such as the ADM809 ADM810 SOT 23 packaged PORs from Analog Devices Recommended connection diagrams for both active high ADM810 and active low ADM809 PORs are shown in Figure 48 and Figure 49 respectively REV Figure 48 External Active High POR Circuit Some active low POR chips such as the ADM809 can be used with a manual push button as an additional reset source as illustrated by the dashed line connection in Figure 49 POWER SUPPLY ADuC824 1 4 OPTIONAL MANUAL RESET PUSH BUTTON Figure 49 External Active Low POR Circuit Power Supplies The ADuC824 s operational power supply voltage range is 2 7 V to 5 25 V Although the guaranteed data sheet specifications are given only for power supplies within 2 7 V to 3 6 V or 5 of the nominal 5 V level the chip will function
60. al endurance at 25 C is 700 cycles 16 Retention lifetime equivalent at junction temperature 55 as Std 22 Method A117 Retention lifetime based on an activation energy of 0 6e V will derate with junction temperature as shown in Figure 27 in the Flash EE Memory description section of this data sheet V Power Supply current consumption is measured in Normal Idle and Power Down Modes under the following conditions Normal Mode Reset 0 4 V Digital pins open circuit Core changed via CD bits in PLLCON Core Executing internal software loop Idle Mode Reset 0 4 V Digital I O pins open circuit Core Clk changed via CD bits in PLLCON PCON 0 1 Core Execution suspended in idle mode Power Down Mode Reset 0 4 V All pins and P1 2 P1 7 pins 0 4 V All other digital I O pins are open circuit Core Clk changed via CD bits in PLLCON 1 1 Core Execution suspended in power down mode OSC turned ON or OFF via OSC PD bit PLLCON 7 in PLLCON SFR 18 power supply current will increase typically by 3 mA 3 V operation and 10 mA 5 V operation during Flash EE memory program or erase cycle Specifications subject to change without notice REV B 7 ADuC824 AVpp 2 7 V to 3 6 V or 4 75 V to 5 25 DVpp 2 7 V to 3 6 V or 4 75 V to 5 25 V TIMING SPEC IFICATIONS 2 3 all specifications 10 unless otherwise noted 32 768 kHz External Crysta
61. al interface that allows eight bits of data to be synchronously transmitted and received simultaneously i e full duplex It should be noted that the SPI physical interface is shared with the interface and therefore the user can only enable one or the other interface at any given time see SPE in SPICON below The system can be configured for Master or Slave operation and typically consists of four pins namely MISO Master In Slave Out Data I O Pin Pin 14 The MISO master in slave out pin is configured as an input line in master mode and an output line in slave mode The MISO line on the master data in should be connected to the MISO line in the slave device data out The data is transferred as byte wide 8 bit serial data MSB first MOSI Master Out Slave In Pin Pin 27 The MOSI master out slave in pin is configured as an output line in master mode and an input line in slave mode The MOSI line on the master data out should be connected to the MOSI line in the slave device data in The data is transferred as byte wide 8 bit serial data MSB first SCLOCK Serial Clock I O Pin Pin 26 The master clock is used to synchronize the data being transmitted and received through the MOSI and MISO data SPICON SPI Control Register lines A single data bit is transmitted and received in each SCLOCK period Therefore a byte is transmitted received after eight SCLOCK periods The SCLOCK pin is configured
62. ammers This array can also be programmed in circuit using the serial download mode provided 640 Byte Flash EE Data Memory space is also provided on chip This may be used a general purpose nonvolatile scratchpad area User access to this area is via a group of six SFRs This space can be programmed at a byte level although it must first be erased in 4 byte pages ADuC824 Flash EE Memory Reliability The Flash EE Program and Data Memory arrays on the ADuC824 are fully qualified for two key Flash EE memory characteristics namely Flash EE Memory Cycling Endurance and Flash EE Memory Data Retention 37 ADuC824 Endurance quantifies the ability of the Flash EE memory to be cycled through many Program Read and Erase cycles In real terms a single endurance cycle is composed of four independent sequential events These events are defined as a initial page erase sequence b read verify sequence c byte program sequence d second read verify sequence A single Flash EE Memory Endurance Cycle In reliability qualification every byte in both the program and data Flash EE memory is cycled from 00 hex to FFhex until a first fail is recorded signifying the endurance limit of the on chip Flash EE memory As indicated in the specification pages of this data sheet the ADuC824 Flash EE Memory Endurance qualification has been carried out in accordance with JEDEC Specification 117 over the industrial temperature range of
63. ard Junction Temperature 150 C Serial Port Cable Oa Thermal Impedance 90 C W Plug In Power Supply Lead Temperature Soldering Windows Serial Downloader WSD Vapor Phase 60 8 Re EAR REN 215 Windows Debugger DeBug Infrared 15 220 C Windows ADuC824 Simulator NOTES ADSIM Stresses above those listed under Absolute Maximum Ratings may cause perma Windows ADC Analysis Software nent damage to the device This is a stress rating only functional operation of the Program WASP device at these or any other conditions above those listed in the operational 8051 Assembler Metalink sections of this specification is not implied Exposure to absolute maximum rating C Compiler Keil Evaluation Co conditions for extended periods may affect device reliability E AGND DGND shorted internally on the ADuC824 Limited 2 Kcode Applies to P1 2 to P1 7 pins operating in analog digital input modes Example Code Documentation PIN CONFIGURATION 52 51 50 29 8 47 46 45 44 43 42 47 1 w 2 2 IDENTIFIER 38 3 37 4 36 5 35 ADuC824 54 7 33 8 Not to Scale 32 9 31 CAUTION gt N gt 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 ESD electrostatic discharge sensitive device Electrostatic charges
64. as an output in master mode and as an input in slave mode In master mode the bit rate polarity and phase of the clock are controlled by the CPOL CPHA SPRO and 1 bits in the SPICON SFR see Table XIX In slave mode the SPICON register will have to be configured with the phase and polarity CPHA and CPOL of the expected input clock In both master and slave mode the data is transmitted on one edge of the SCLOCK signal and sampled on the other It is important therefore that the CPHA and CPOL are configured the same for the master and slave devices SS Slave Select Input Pin Pin 13 The Slave Select SS input pin is only used when the ADuC824 is configured in slave mode to enable the SPI peripheral This line is active low Data is only received or transmitted in slave mode when the SS pin is low allowing the ADuC824 to be used in single master multislave SPI configurations If CPHA 1 then the SS input may be permanently pulled low With CPHA 0 then the SS input must be driven low before the first bit in a byte wide transmission or reception and return high again after the last bit in that byte wide transmission or reception In SPI Slave Mode the logic level on the external SS pin Pin 13 can be read via the SPRO bit in the SPICON SFR The following SFR registers are used to control the SPI interface SFR Address F8H Power On Default Value 04H Bit Addressable Yes ISPI WCOL SPE SPIM CPOL CPHA SPR1 SPRO Table XIX
65. ate and should be ignored Setting the run flag does not clear the registers Mode 1 16 Bit Timer Counter Mode 1 is the same as Mode 0 except that the timer register is running with all 16 bits Mode 1 is shown in Figure 35 INTERRUPT TLO THO i 8 BITS 8 BITS P3 4 TO CONTROL TRO GATE P3 2 INTO THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 35 Timer Counter 0 Mode 1 54 Mode 2 8 Bit Timer Counter with Auto Reload Mode 2 configures the timer register as an 8 bit counter TLO with automatic reload as shown in Figure 36 Overflow from TLO not only sets but also reloads TLO with the contents of THO which is preset by software The reload leaves THO unchanged INTERRUPT TFO gt P3 2 INTO THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 36 Timer Counter 0 Mode 2 Mode 3 Two 8 Bit Timer Counters Mode 3 has different effects on timer 0 and timer 1 Timer 1 in Mode 3 simply holds its count The effect is the same as setting TRI 0 Timer 0 in Mode 3 establishes TLO and THO as two separate counters This configuration is shown in Figure 37 TLO uses the timer 0 control bits C T Gate TRO INTO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls the timer 1 interrupt Mode 3 is provided f
66. ate they 20 23 can be used as inputs As inputs Port 2 pins being pulled externally low will source current because of the internal pull up resistors Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24 bit external data memory space External Access Enable Logic Input When held high this input enables the device to fetch code from internal program memory locations 0000H to 1FFFH When held low this input enables the device to fetch all instructions from external program memory determine the mode of code execution i e internal or external the EA pin is sampled at the end of an external RESET assertion or as part of a device power cycle may also be used as an external emula tion I O pin and therefore the voltage level at this pin must not be changed during normal mode operation as it may cause an emulation interrupt that will halt code execution Program Store Enable Logic Output This output is a control signal that enables the external program memory to the bus during external fetch operations It is active every six oscillator periods except during external data memory accesses This pin remains high during internal program execution PSEN can also be used to enable serial download mode when pulled low through a resistor at the end of an external RESET assertion or as part of a device power cycle Address Latch Enable Logic Ou
67. ated SFRs IE Interrupt Enable Register Interrupt Priority Register IEIP2 Secondary Interrupt Priority Interrupt Register IE Interrupt Enable Register SFR Address A8H Power On Default Value 00H Bit Addressable Yes EA EADC ET2 ES EX0 Table XXX IE SFR Bit Designations Bit Name Description 7 EA Written by User to Enable 1 or Disable 0 All Interrupt Sources 6 EADC Written by User to Enable 1 or Disable 0 ADC Interrupt 5 ET2 Written by User to Enable 1 or Disable 0 Timer 2 Interrupt 4 ES Written by User to Enable 1 or Disable 0 UART Serial Port Interrupt 3 ET1 Written by User to Enable 1 or Disable 0 Timer 1 Interrupt 2 Written by User to Enable 1 or Disable 0 External Interrupt 1 1 ETO Written by User to Enable 1 or Disable 0 Timer 0 Interrupt 0 Written by User to Enable 1 or Disable 0 External Interrupt 0 IP Interrupt Priority Register SFR Address B8H Power On Default Value 00H Bit Addressable Yes PADC PT2 PS PT1 PX1 PTO PX0 Table XXXI IP SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 PADC Written by User to Select ADC Interrupt Priority 1 High 0 Low 5 PT2 Written by User to Select Timer 2 Interrupt Priority 1 High 0 Low 4 PS Written by User to Select UART Serial Port Interrupt Priority 417
68. ator as A B SFR The B register is used with the ACC for multiplication and divi sion operations For other instructions it can be treated as a general purpose scratchpad register Stack Pointer SFR The SP register is the stack pointer and is used to hold an internal RAM address that is called the top of the stack The SP register is incremented before data is stored during PUSH and CALL execu tions While the stack may reside anywhere in on chip RAM the SP register is initialized to 07H after a reset This causes the stack to begin at location 08H Data Pointer The Data Pointer is made up of three 8 bit registers named DPP page byte DPH high byte and DPL low byte These are used to provide memory addresses for internal and external code access and external data access It may be ma nipulated as a 16 bit register DPTR DPH DPL although INC DPTR instructions will automatically carry over to DPP or as three independent 8 bit registers DPP DPH DPL REV Program Status Word SFR The PSW register is the Program Status Word which contains several bits reflecting the current status of the CPU as detailed in Table I SFR Address DOH Power ON Default Value 00H Bit Addressable Yes CY AC F0 RS1 RSO OV F1 P Table I PSW SFR Bit Designations Bit Name Description 7 Carry Flag 6 AC Auxiliary Carry Flag 5 FO General Purpose Flag 4 RS1 Register Bank Select Bit
69. atus of the Primary and Auxiliary ADCs ADCMODE ADC Mode Register Controls general modes of operation for Primary and Auxiliary ADCs ADCOCON Primary ADC Control Register Controls specific configuration of Primary ADC ADCICON Auxiliary ADC Control Register Controls specific configuration of Auxiliary ADC Primary ADC 24 bit conversion result held in these three 8 bit registers ADCIL H Auxiliary ADC 16 bit conversion result held in these two 8 bit registers OFOL M H Primary ADC 24 bit Offset Calibration Coefficient held in these three 8 bit registers OFIL H Auxiliary ADC 16 bit Offset Calibration Coefficient held in these two 8 bit registers GNOL M H Primary ADC 24 bit Gain Calibration Coefficient held in these three 8 bit registers GNIL H Auxiliary ADC 16 bit Gain Calibration Coefficient held in these two 8 bit registers SF Sinc Filter Register Configures the decimation factor for the Sinc3 filter and thus the Primary and Auxiliary ADC update rates ADCSTAT ADC Status Register This SFR reflects the status of both ADCs including data ready calibration and various ADC related error and warning conditions including reference detect and conversion overflow underflow flags SFR Address D8H Power On Default Value 00H Bit Addressable Yes RDYO RDY1 CAL NOXREF ERRO Table III ADCSTAT SFR Bit Designations Bit Name Description 7 RDYO Ready Bit for Pri
70. bit position of the transmit shift register The trans mission will start at the next valid baud rate clock The TI flag is set as soon as the stop bit appears on TXD Reception for Mode 2 is similar to that of Mode 1 The eight data bytes are input at RXD LSB first and loaded onto the receive shift register When all eight bits have been clocked in the following events occur The eight bits in the receive shift register are latched into SBUF The ninth data bit is latched into RB8 in SCON The Receiver interrupt flag RI is set if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and Either SM2 0 or SM2 1 and the received stop bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set Mode 3 9 Bit UART with Variable Baud Rate Mode 3 is selected by setting both SMO and SM1 In this mode the 8051 UART serial port operates in 9 bit mode with a variable baud rate determined by either Timer 1 or Timer 2 The opera tion of the 9 bit UART is the same as for Mode 2 but the baud rate can be varied as for Mode 1 In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 UART Serial Port Baud Rate Generation Mode 0 Baud Rate Generati
71. by user to turn on timer counter 0 Cleared by user to turn off timer counter 0 1 External Interrupt 1 Flag Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1 depending on bit IT state Cleared by hardware when the when the PC vectors to the interrupt service routine only if the interrupt was transition activated If level activated the external requesting source controls the request flag rather than the on chip hardware 2 ITI External Interrupt 1 IE1 Trigger Type Set by software to specify edge sensitive detection 1 1 to 0 transition Cleared by software to specify level sensitive detection i e zero level 1 External Interrupt 0 INTO Flag Set by hardware by a falling edge or zero level being applied to external interrupt pin INTO depending on bit ITO state Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition activated If level activated the external requesting source controls the request flag rather than the on chip hardware 0 ITO External Interrupt 0 IEO Trigger Type Set by software to specify edge sensitive detection 1 1 to 0 transition Cleared by software to specify level sensitive detection 1 zero level Timer Counter 0 and 1 Data Registers Each timer consists of two 8 bit registers These can be used as independent registers or combined to be a single 16 bit
72. cally cleared by the ADuC824 hardware unless otherwise stated 3 User software should not write 1s to reserved or unimplemented bits as they may be used in future products 290 REV B AIN3 AUXILIARY ADC 2 16 INS X A ADC TEMP BANDGAP SENSOR REFERENCE REFIN REF REFIN DETECT CURRENT SOURCE MUX P1 2 DAC IEXC1 gt P1 3 AIN5 IEXC2 P1 4 5 P1 7 AIN4 DAC 5 P2 0 A8 A16 2 P1 5 AIN2 P1 6 AIN3 PRIMARY ADC 24 BIT ADC ADC CONTROL AND CALIBRATION 640x8 DATA FLASH EE 8Kx8 PROGRAM FLASH EE DOWNLOADER DEBUGGER ASYNCHRONOUS SERIAL PORT 5 P2 1 A9 A17 8 P2 4 A12 A20 8 P2 5 A13 A21 8 P2 6 A14 A22 P2 7 A15 A23 8 P2 2 A10 A18 2 P2 3 A11 A19 P3 0 3 P3 1 TXD P3 2 INTO P3 3 INT1 P3 4 TO 8 P3 5 T1 P3 6 WR ADC CONTROL AND CALIBRATION ADuC824 12 BIT VOLTAGE OUTPUT DAC INTERVAL COUNTER PROG CLOCK DIVIDER SYNCHRONOUS SERIAL INTERFACE SP 5 SINGLE PIN EMULATOR EA RESET 2 Figure 12 Block Diagram 21 5 P3 7 RD ADuC824 ADuC824 MEMORY ORGANIZATION As with all 8051 compatible devices the ADuC824 has sepa rate address spaces for Program and Data memory as shown in Figure 13 and Figure 14 If the user applies power or resets the device while the EA pin
73. can be used to check that a transducer on the selected channel is still operational before attempting to take measurements The ADC employs a sigma delta conversion technique to realize up to 24 bits of no missing codes performance The sigma delta modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information A Sinc3 programmable low pass filter is then employed to decimate the modulator output data stream to give a valid data conversion result at programmable output rates from 5 35 Hz 186 77 ms to 105 03 Hz 9 52 ms A Chopping scheme is also employed to minimize ADC offset errors A block diagram of the Primary ADC is shown in Figure 18 BURNOUT CURRENTS TWO 100nA BURNOUT CURRENTS ALLOW THE USER TO EASILY DETECT IF A TRANSDUCER HAS BURNED OUT OR GONE OPEN CIRCUIT SEE PAGES 29 AND 34 ANALOG INPUT CHOPPING THE INPUTS ARE ALTERNATELY REVERSED THROUGH THE CONVERSION CYCLE CHOPPING YIELDS EXCELLENT ADC OFFSET AND OFFSET DRIFT PERFORMANCE SEE PAGE 36 PROGRAMMABLE GAIN AMPLIFIER THE PROGRAMMABLE GAIN AMPLIFIER ALLOWS EIGHT UNIPOLAR AND EIGHT BIPOLAR INPUT RANGES FROM 20mV TO 2 56V EXT VREF 2 5V SEE PAGE 34 DIFFERENTIAL REFERENCE THE EXTERNAL REFERENCE INPUT TO THE ADuC824 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION THE EXTERNAL REFERENCE VOLTAGE IS SELECTED VIA THE XREFO BIT IN ADCOCON REFERENCE DETECT CIRCUITRY TESTS FO
74. causes the current value in the Timer 2 registers TL2 and TH2 to be captured into regis ters RCAP2L and RCAP2H respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt The Capture Mode 1s illustrated in Figure 39 The baud rate generator mode is selected by RCLK 1 and or TCLK 1 In either case if Timer 2 is being used to generate the baud rate the TF2 interrupt flag will not occur Hence Timer 2 interrupts will not occur so they do not have to be disabled In this mode the EXF2 flag however can still cause interrupts and this can be used as a third external interrupt Baud rate generation will be described as part of the UART serial port operation in the following pages TIMER INTERRUPT THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 38 Timer Counter 2 16 Bit Autoreload Mode TRANSITION DETECTOR T2EX PIN CONTROL EXEN2 TL2 8 BITS TH2 8 BITS TIMER INTERRUPT THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 39 Timer Counter 2 16 Bit Capture Mode 56 REV B ADuC824 UART SERIAL INTERFACE while the SFR interface to the UART is comprised of the fol The serial port is full duplex meaning it can transmit and receive lowing registers simultaneously It is also receive buffered meaning it can com mence reception of a second byte before a previously re
75. ceived byte has been read from the receive register However if the first byte still has not been read by the time reception of the second byte is complete the first byte will be lost The physical interface SBUF The serial port receive and transmit registers are both accessed through the SBUF SFR SFR address 99 hex Writing to SBUF loads the transmit register and reading SBUF accesses a to the serial data network is via Pins RKD P3 0 and TXD P3 1 physically separate receive register SCON UART Serial Port Control Register SFR Address 98H Power On Default Value 00H Bit Addressable Yes SMO SM1 SM2 REN TB8 RB8 TI RI Table XXVII SCON SFR Bit Designations Bit Name Description 7 SMO UART Serial Mode Select Bits 6 SMI These bits select the Serial Port operating mode as follows SMO SMI Selected Operating Mode 0 0 Mode 0 Shift Register fixed baud rate Core 2 0 1 Mode 1 8 bit UART variable baud rate 1 0 Mode 2 9 bit UART fixed baud rate Core 64 or Core 32 1 1 Mode 3 9 bit UART variable baud rate 5 SM2 Multiprocessor Communication Enable Bit Enables multiprocessor communication in Modes 2 and 3 In Mode 0 SM2 should be cleared In Mode 1 if SM2 is set RI will not be activated if a valid stop bit was not received If SM2 is cleared RI will be set as soon as the byte of data has been received In Modes 2 or 3 if SM2 is set RI will not be activated if the received ninth data bit in RB8 is 0
76. character reception continues The start bit is skipped and the eight data bits are clocked into the serial port shift register When all eight bits have been clocked in the following events occur The eight bits in the receive shift register are latched into SBUF The ninth bit Stop bit is clocked into RB8 in SCON The Receiver interrupt flag RI is set if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and Either SM2 0 or SM2 1 and the received stop bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set 58 Mode 2 9 Bit UART with Fixed Baud Rate Mode 2 is selected by setting SMO and clearing SM1 In this mode the UART operates in 9 bit mode with a fixed baud rate The baud rate is fixed at Core_Clk 64 by default although by setting the SMOD bit in PCON the frequency can be doubled to 32 Eleven bits are transmitted or received a start bit 0 eight data bits a programmable ninth bit and a stop bit 1 The ninth bit is most often used as a parity bit although it can be used for anything including a ninth data bit if required To transmit the eight data bits must be written into SBUF The ninth bit must be written to TB8 in SCON When transmission is initiated the eight data bits from SBUF are loaded onto the transmit shift register LSB first The contents of TB8 are loaded into the ninth
77. citors and ensure the smaller capacitors are closest to each AVpp pin with trace lengths as short as possible Connect the ground terminal of each of these capacitors directly to the underlying ground plane Finally it should also be noticed that at all times the analog and digital ground pins on the ADuC824 should be referenced to the same system ground reference point Power Consumption The CORE values given represent the current drawn by DVpp while the rest and DAC are pulled by the AVpp pin and can be disabled in software when not in use The other on chip peripherals watchdog timer power supply monitor etc consume negligible current and are therefore lumped in with the CORE operating current here Of course the user must add any currents sourced by the parallel and serial I O pins and that sourced by the DAC in order to determine the total current needed at the ADuC824 s supply pins Also current draw from the DVDD supply will increase by approximately 5 mA during Flash EE erase and program cycles Power Saving Modes Setting the Idle and Power Down Mode bits PCON 0 and PCON 1 respectively in the PCON SFR described in Table II allows the chip to be switched from normal mode into idle mode and also into full power down mode In idle mode the oscillator continues to run but the core clock generated from the PLL is halted The on chip peripherals con tinue to receive the clock and remain fu
78. der Bits This number determines the frequency at which the microcontroller core will operate CD2 CDI Core Clock Frequency MHz 0 0 0 12 582912 6 291456 3 145728 1 572864 Default Core Clock Frequency 0 786432 0 393216 0 196608 0 098304 Or 42 REV ADuC824 TIME INTERVAL COUNTER TIC A time interval counter is provided on chip for counting longer intervals than the standard 8051 compatible timers are capable of The TIC is capable of timeout intervals ranging from 1 128th second to 255 hours Furthermore this counter is clocked by the crystal oscillator rather than the PLL and thus has the ability to remain active in power down mode and time long power down intervals This has obvious applications for remote battery powered sensors where regular widely spaced readings are required Six SFRs are associated with the time interval counter TIMECON being its control register Depending on the configuration of the ITO and bits in TIMECON the selected time counter register TCEN 32 768kHz EXTERNAL CRYSTAL 8 BIT PRESCALER HTHSEC HUNDREDTHS COUNTER overflow will clock the interval counter When this counter is equal to the time interval value loaded in the INTVAL SFR the TII bit TIMECON 2 is set and generates an interrupt if enabled See IEIP2 SFR description under Interrupt System later in this data sheet If the ADu
79. e ECON SFR which initiates an erase of all 640 byte locations in the Flash EE array This command coded in 8051 assembly would appear as MOV ECON 06H Erase all Command 2ms Duration Program a Byte In general terms a byte in the Flash EE array can only be pro grammed if it has previously been erased To be more specific a byte can only be programmed if it already holds the value FFH Because of the Flash EE architecture this erasure must happen at a page level therefore a minimum of four bytes 1 page will be erased when an erase command is initiated A more specific example of the Program Byte process is shown below In this example the user writes F3H into the second byte on Page 03H of the Flash EE Data Memory space while preserving the other three bytes already in this page As the user is only required to modify one of the page bytes the full page must be first read so that this page can then be erased without the exist ing data being lost This example coded in 8051 assembly would appear as MOV EADRL 03H Set Page Address Pointer MOV ECON 01H Read Page MOV EDATA2 0F3H Write New Byte MOV ECON 05H Erase Page MOV ECON 03H Write Page Program Flash EE REV ADuC824 USER INTERFACE TO OTHER ON CHIP ADuC824 10 100 pF It has two selectable ranges 0 V the inter PERIPHERALS nal bandgap 2 5 V reference and 0 V to AVpp It can operate in 12 bit or 8 bit mode The DAC has
80. e SFR space A group of four data registers 1 4 are used to hold 4 byte page data just accessed EADRL is used to hold the 8 bit address of the page to be accessed Finally ECON is an 8 bit control register that may be written with one of five Flash EE memory access commands to trigger various read write erase and verify functions These registers can be summarized as follows ECON SFR Address B9H Function Controls access to 640 Bytes Flash EE Data Space Default 00H EADRL SFR Address C6H Function Holds the Flash EE Data Page Address 640 Bytes gt 160 Page Addresses Default 00H EDATA 1 4 SFR Address BCH to respectively Function Holds Flash EE Data memory page write or page read data bytes Default EDATAI 2 00H EDATA3 4 gt 00H block diagram of the SFR interface to the Flash EE Data Memory array is shown in Figure 31 FUNCTION HOLDS THE 8 BIT PAGE ADDRESS POINTER FUNCTION HOLDS THE 4 BYTE PAGE DATA BYTE 1 BYTE 2 3 BYTE 4 ECON COMMAND INTERPRETER LOGIC FUNCTION RECEIVES COMMAND DATA Figure 31 Flash EE Data Memory Control and Configuration FUNCTION INTERPRETS THE FLASH COMMAND WORD 39 ADuC824 ECON Flash EE Memory Control SFR This SFR acts as a command interpreter and may be written with one of five command modes to enable various read program and erase cycles as detailed in Table XIII Table XIII ECON Flas
81. e falling edge of RESET 1 at power up or upon an external manual reset Note also that if any external circuitry uninten tionally pulls PSEN low during power up or reset events it could cause the chip to enter download mode and therefore fail to begin user code execution as it should To prevent this ensure that no external signals are capable of pulling the PSEN pin low except for the external PSEN jumper itself Embedded Serial Port Debugger From a hardware perspective entry to serial port debug mode is identical to the serial download entry sequence described above In fact both serial download and serial port debug modes can be thought of as essentially one mode of operation used in two differ ent ways Note that the serial port debugger is fully contained on the ADuC824 device unlike ROM monitor type debuggers and therefore no external memory is needed to enable in system debug sessions Single Pin Emulation Mode Also built into the ADuC824 is a dedicated controller for single pin in circuit emulation ICE using standard production ADuC824 devices In this mode emulation access is gained by connection to a single pin the EA pin Normally this pin is hard wired either high or low to select execution from internal or external program memory space as described earlier To enable single pin emulation mode however users will need to pull the EA pin high through a 1 resistor as shown in Figure 53 T
82. e simple connection points in their hardware that will allow easy access to download debug and emulation modes In Circuit Serial Download Access Nearly all ADuC824 designs will want to take advantage of the in circuit reprogrammability of the chip This is accomplished by a connection to the ADuC824 s UART which requires an external RS 232 chip for level translation if downloading code from a PC Basic configuration of an RS 232 connection is illustrated in Figure 53 with a simple ADM202 based circuit If users would rather not design an RS 232 chip onto a board refer to Application Note uC006 4 Wire UART to PC Interface for a simple and zero cost per board method of gaining in circuit serial download access to the ADuC824 In addition to the basic UART connections users will also need a way to trigger the chip into download mode This is accom plished via a 1 pull down resistor that can be jumpered onto the PSEN pin as shown in Figure 53 To get the ADuC824 into download mode simply connect this jumper and power cycle the device or manually reset the device if a manual reset button is available and it will be ready to receive a new program serially With the jumper removed the device will come up in normal mode and run the program whenever power is cycled or RESET is toggled Note that PSEN is normally an output as described in the Exter nal Memory Interface section and it is sampled as an input only on th
83. ect bit set in the ADCOCON SFR and an external 2 5 V reference the unipolar ranges are 0 mV to 20 mV 0 mV to 40 mV 0 mV 80 mV 0 mV to 160 mV 0 mV to 320 mV 0 mV to 640 mV 0 V to 1 28 V and 0 to 2 56 V while the bipolar ranges are 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1 28 and 2 56 V These are the nominal ranges that should appear at the input to the on chip PGA An ADC range matching specification of 2 typ across all ranges means that calibration need only be carried out at a single gain range and does not have to be repeated when the PGA gain range is changed Typical matching across ranges is shown in Figure 20 below Here the primary ADC is configured in bipolar mode with an external 2 5 V reference while just greater than 19 mV is forced on its inputs The ADC continuously converts the DC input voltage at an update rate of 5 35 Hz i e SF FFhex In total 800 conversion results are gathered The first 100 results are gathered with the primary ADC operating in the 20 mV range The ADC range is then switched to 40 mV and 100 more con version results are gathered and so on until the last group of 100 samples are gathered with the ADC configured in the 22 56 V range From Figure 20 The variation in the sample mean through each range i e the range matching is seen to be of the order of 2 uV The auxiliary ADC does not incorporate a PGA and is configured for a fixed single input range of 0 to
84. ed for Flash EE program ming is generated using on chip charge pumps to supply the high voltage program lines DATA 00 07 PROGRAM MODE PROGRAM SEE TABLE ADDRESS COMMAND 1 7 A13 NEGATIVE EDGE WRITE ENABLE ENTRY SEQUENCE GND STROBE Figure 29 Flash EE Memory Parallel Programming REV B PULL PSEN LOW DURING RESET FOR SERIAL DOWNLOAD MODE ADuC824 Table XII Flash EE Memory Parallel Programming Modes Port 3 Pins Programming 0 7 0 6 0 5 0 4 0 3 0 2 0 1 Mode X X X X 0 0 0 Erase Flash EE Program Data and Security Modes X X X X 0 0 1 Read Device Signature ID X X X 1 0 1 0 Program Code Byte X X X 0 0 1 0 Program Data Byte X X X 1 0 1 1 Read Code Byte X X X 0 0 1 1 Read Data Byte X X X X 1 0 0 Program Security Modes X X X X 1 0 1 Read Verify Security Modes All other codes Redundant Flash EE Program Memory Security The ADuC824 facilitates three modes of Flash EE program memory security These modes can be independently activated restricting access to the internal code space These security modes can be enabled as part of the user interface available on all ADuC824 serial or parallel programming tools referenced on the MicroConverter web page at www analog com microconverter The security modes available on the ADuC824 are described as follows Lock Mode This mode locks code in memory disabling parallel programming of the
85. enting timer counter functionality in soft ware Each Timer Counter consists of two 8 bit registers THx and TLx x 0 1 and 2 All three can be configured to operate either as timers or event counters In Timer function the TLx register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 12 core clock periods the maximum count rate is 1 12 of the core clock frequency In Counter function the TLx register is incremented by a 1 to 0 transition at its corresponding external input pin T0 or T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle follow ing the one in which the transition was detected Since it takes two machine cycles 24 core clock periods to recognize 1 to 0 transi tion the maximum count rate is 1 24 of the core clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it must be held for a minimum of one full machine cycle Remember that the core clock frequency is programmed via the CD0 2 selection bits in the PLLCON SFR 51 ADuC824 User configuration and control of all Timer operating modes is achieved via three SFRs
86. equally well at any power supply level between 2 7 V and 5 25 V Separate analog and digital power supply pins AVpp and DVpp respectively allow AVpp to be kept relatively free of noisy digital signals often present on the system DVDD line In this mode the part can also operate with split supplies that is using different voltage supply levels for each supply For example this means that the system can be designed to operate with a DVpp voltage level of 3 while the AVpp level can be at 5 V or vice versa if required A typical split supply configuration is show in Figure 50 DIGITAL SUPPLY ANALOG SUPPLY Figure 50 External Dual Supply Connections 63 ADuC824 As an alternative to providing two separate power supplies AVpp quiet by placing a small series resistor and or ferrite bead between it and DVpp and then decoupling AVpp separately to ground An example of this configuration is shown in Figure 51 With this configuration other analog circuitry such as op amps voltage reference etc can be powered from the AVpp supply line as well DIGITAL SUPPLY BEAD 1 60 Figure 51 External Single Supply Connections Notice that in both Figure 50 and Figure 51 a large value 10 reservoir capacitor sits on DVpp and a separate 10 capacitor sits on AVpp Also local small value 0 1 capacitors located at each VDD pin of the chip As per standard design prac tice be sure to include all of these capa
87. er Supply Currents Power Down Mode 18 Core CLK 1 57 MHz or 12 58 MHz DVpp Current 50 DVpp 4 75 V to 5 25 V Osc On TIC On max 20 DVpp 2 7 V to 3 6 V Osc On TIC On max AVpp Current 1 Measured at AVpp 5 25 V Osc On or Osc Off max DVpp Current 20 DVpp 4 75 V to 5 25 V Osc Off max 5 DVpp 2 7 V to 3 6 V Osc Off typ Typical Additional Power Supply Currents Core CLK 1 57 MHz AVpp DVpp 5 V Alpp and DIpp PSM Peripheral 50 typ Primary ADC 1 mA typ Auxiliary ADC 500 typ DAC 150 typ Dual Current Sources 400 typ NOTES 1 Temperature Range 40 85 C 2 These numbers are not production tested but are guaranteed by Design and or Characterization data on production release System Zero Scale Calibration can remove this error primary ADC is factory calibrated at 25 C with AVpp DVpp 5 V yielding this full scale error of 10 If user power supply or temperature conditions are significantly different than these an Internal Full Scale Calibration will restore this error to 10 uV A system zero scale and full scale calibration will remove this error altogether gt Gain Error Drift is a span drift To calculate Full Scale Error Drift add the Offset Error Drift to the Gain Error Drift times the full scale input 5 The auxiliary ADC is factory calibrated at 25 C with AVpp DVpp 5 yielding this full scale error of 2 5 LSB A system zero scale and f
88. eration of this interface as implemented is available from the MicroConverter Website at www analog com microconverter This interface can be configured as a Software Master or Hard ware Slave and uses two pins in the interface Serial Data I O Pin Serial Clock Three SFRs are used to control the I C compatible interface These are described below I2CCON Control Register SFR Address E8H Power On Default Value 00H Bit Addressable Yes MDO MDE MCO MDI RCM DCRS DCTX Table 2 SFR Bit Designations Bit Name Description 7 MDO Software Master Data Output Bit MASTER MODE ONLY This data bit is used to implement a master transmitter interface in software Data written to this bit will be outputted on the SDATA pin if the data output enable MDE bit is set 6 MDE Software Master Data Output Enable Bit MASTER MODE ONLY Set by user to enable the SDATA pin as an output Tx Cleared by the user to enable SDATA pin as an input Rx 5 MCO Software Master Clock Output Bit MASTER MODE ONLY This data bit is used to implement a master transmitter interface in software Data written to this bit will be outputted on the SCLOCK pin 4 MDI Software Master Data Input Bit MASTER MODE ONLY This data bit is used to implement a master receiver interface in software Data on the SDATA pin is latched into this bit on SCLOCK if the Data Output Enable MDE bit is 0 3 I2CM
89. eriph eral circuits are also available to the user on chip These remaining functions are fully 8051 compatible and are controlled via standard 8051 SFR bit definitions Parallel I O Ports 0 3 The ADuC824 uses four input output ports to exchange data with external devices In addition to performing general purpose I O some ports are capable of external memory operations others are multiplexed with an alternate function for the peripheral features on the device In general when a peripheral is enabled that pin may not be used as a general purpose I O pin Port 0 is an 8 bit open drain bidirectional I O port that is directly controlled via the Port 0 SFR SFR address 80 hex Port 0 pins that have 15 written to them via the Port 0 SFR will be configured as open drain and will therefore float In that state Port 0 pins can be used as high impedance inputs An external pull up resistor will be required on Port 0 outputs to force a valid logic high level externally Port 0 is also the multiplexed low order address and data bus during accesses to external pro gram or data memory In this application it uses strong internal pull ups when emitting 15 Port 1 is also an 8 bit port directly controlled via the SFR SFR address 90 hex The Port 1 pins are divided into two distinct pin groupings P1 0 and P1 1 pins on Port 1 are bidirectional digital I O pins with internal pull ups If P1 0 and P1 1 have 1s written to them via the
90. ess D7H Power On Default Value 03H Bit Addressable No Table XV PLLCON SFR Bit Designations Bit Name Description OSC_PD LOCK LTEA FINT CD2 CDI CDO Oscillator Power down Bit Set by user to halt the 32 kHz oscillator in power down mode Cleared by user to enable the 32 kHz oscillator in power down mode This feature allows the TIC to continue counting even in power down mode PLL Lock Bit This is a read only bit Set automatically at power on to indicate the PLL loop is correctly tracking the crystal clock If the external crystal becomes subsequently disconnected the PLL will rail and the core will halt Cleared automatically at power on to indicate the PLL is not correctly tracking the crystal clock This may be due to the absence of a crystal clock or an external crystal at power on In this mode the PLL output can be 12 58 MHz 20 Reserved for future use should be written with 0 Reading this bit returns the state of the external EA pin latched at reset or power on Fast Interrupt Response Bit Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency regardless of the configuration of the CD2 0 bits see below Once user code has returned from an interrupt the core resumes code execution at the core clock selected by the CD2 0 bits Cleared by user to disable the fast interrupt response feature CPU Core Clock Divi
91. h EE Memory Control Register Command Modes Command Byte Command Mode 01H READ COMMAND Results in four bytes being read into 1 4 from memory page address contained in EADRL 02H PROGRAM COMMAND Results in four bytes EDATAI 4 being written to memory page address in EADRL This write command assumes the designated write page has been pre erased 03H RESERVED FOR INTERNAL USE 03H should not be written to the ECON SFR 04H VERIFY COMMAND Allows the user to verify if data in EDATAI 4 is contained in page address designated by EADRL subsequent read of the ECON SFR will result in a zero being read if the verification is valid a nonzero value will be read to indicate an invalid verification 05H ERASE COMMAND Results in an erase of the 4 byte page designated in EADRL 06H ERASE ALL COMMAND Results in erase of the full Flash EE Data memory 160 page 640 bytes array 07H to FFH RESERVED COMMANDS Commands reserved for future use Flash EE Memory Timing The typical program erase times for the Flash EE Data Memory are Erase Full Array 640 Bytes 2 ms Erase Single Page 4 Bytes 2 ms Program Page 4 Bytes 250 us Read Page 4 Bytes Within Single Instruction Cycle Using the Flash EE Memory Interface As with all Flash EE memory architectures the array can be pro grammed in system at a byte level although it must be erased first the erasure being performed in page block
92. he emulator will then connect to the 2 pin header also shown in Figure 53 To be compatible with the standard connector that Application note uC006 is available at www analog com microconverter 65 ADuC824 200 400 CURRENT 10 P1 5 AIN2 DOWNLOAD DEBUG ENABLE JUMPER NORMALLY OPEN 4 1 DVpp V V 1 s 2 PIN HEADER FOR EMULATION ACCESS 5226060 ce ume 89 38 G 36 DVpp 32 766kHz 23 em 7 m M P 2 R2 x 20 5100 g on 27 V Y 4 15 16 17 18 19 89 21 9293 4 25 26 ADMS1O X NOT CONNECTED IN THIS EXAMPLE DVpp GND Y 9 PIN D SUB FEMALE 2 3 4 y 6 7 8 Figure 53 Typical System Configuration comes with the single pin emulator available from Accutron Limited www accutron com use a 2 pin 0 1 inch pitch Friction Lock header from Molex www molex com such as their part number 22 27 2021 Be sure to observe the polarity of this header As represented in Figure 53 when the Friction Lock tab is at the right the ground pin should be the lower of the two pins when viewed from the top Enhanced Hooks Emulation Mode ADuC824 also supports enhanced hooks emulation mode An enhanced hooks based emulator is available from Metalink Corporation www metaice com No special hardware support for these emulators needs to be designed onto the board since these are pod style
93. he full settling time through the ADC or the time to a first conversion result will actually be given by 2 tapc The chopping scheme incorporated in the ADuC824 ADC results in excellent dc offset and offset drift specifications and is extremely beneficial in applications where drift noise rejection and optimum EMI rejection are important factors REV B ADuC824 Calibration The ADuC824 provides four calibration modes that can be pro grammed via the mode bits in the ADCMODE SFR detailed in Table IV In fact every ADuC824 has already been factory calibrated The resultant Offset and Gain calibration coefficients for both the primary and auxiliary ADCs are stored on chip in manufacturing specific Flash EE memory locations At power on these factory calibration coefficients are automatically downloaded to the calibration registers in the ADuC824 SFR space Each ADC primary and auxiliary has dedicated calibration SFRs these have been described earlier as part of the general ADC SFR description However the factory calibration values in the ADC calibration SFRs will be overwritten if any one of the four calibration options are initiated and that ADC is enabled via the ADC enable bits in ADCMODE Even though an internal offset calibration mode is described below it should be recognized that both ADCs are chopped This chopping scheme inherently minimizes offset and means that an internal offset calibration should never be required
94. he input voltage on the analog input channel can be taken If the resultant volt age measured is full scale this indicates that the transducer has gone open circuit If the voltage measured is 0 V it indicates that the transducer has short circuited For normal operation these burnout currents are turned off by writing a 0 to the BO bit in the ICON SER The current sources work over the normal abso lute input voltage range specifications REV B ADuC824 Excitation Currents The ADuC824 also contains two identical 200 HA constant current sources Both source current from AVDD to Pin 3 IEXC1 or Pin 4 IEXC2 These current sources are con trolled via bits in the ICON SFR shown in Table VIII They can be configured to source 200 uA individually to both pins or combination of both currents i e 400 uA to either of the selected pins These current sources can be used to excite exter nal resistive bridge or RTD sensors Reference Input The ADuC824 s reference inputs REFIN and REFIN provide a differential reference input capability The common mode range for these differential inputs is from AGND to AVDD The nominal reference voltage VREF REFIN REFIN for specified operation is 2 5 V with the primary and auxil iary reference enable bits set in the respective ADCOCON and or ADCICON SFRs The part is also functional although not specified for perfor mance when the XREFO or XREF bits are 0 which enab
95. his programs the relevant ADC for either unipolar or bipolar operation Programming for either unipolar or bipolar operation does not change any of the input signal conditioning it simply changes the data output coding and the points on the transfer function where calibrations occur When an ADC is configured for unipolar operation the output coding is natural straight binary with a zero differential input voltage resulting in a code of 000 000 midscale voltage resulting in code of 100 000 and a full scale input voltage resulting in a code of 111 111 When an ADC is configured for bipolar operation the coding is offset binary with a negative full scale voltage resulting in a code of 000 000 a zero differential voltage resulting in a code of 100 000 and a positive full scale voltage resulting in a code of 111 111 Burnout Currents The primary ADC on the ADuC824 contains two 100 nA con stant current generators one sourcing current from AVDD to AIN and one sinking from AIN to AGND The currents are switched to the selected analog input pair Both currents are either on or off depending on the Burnout Current Enable BO bit in the ICON SFR see Table VIII These currents can be used to verify that an external transducer is still operational before attempting to take measurements on that channel Once the burnout currents are turned on they will flow in the exter nal transducer circuit and a measurement of t
96. ible in circuit reprogrammable features of EEPROM and combines them with the space efficient density features of EPROM see Figure 26 Because Flash EE technology is based on a single transistor cell architecture a Flash memory array like EPROM can be imple mented to achieve the space efficiencies or memory densities required by a given design Like EEPROM Flash memory can be programmed in system at a byte level although it must first be erased the erase being per formed in page blocks Thus Flash memory is often and more correctly referred to as Flash EE memory EPROM TECHNOLOGY EEPROM TECHNOLOGY SPACE EFFICIENT DENSITY IN CIRCUIT REPROGRAMMABLE FLASH EE MEMORY TECHNOLOGY Figure 26 Flash EE Memory Development Overall Flash EE memory represents a step closer to the ideal memory device that includes nonvolatility in circuit programma bility high density and low cost Incorporated in the ADuC824 Flash EE memory technology allows the user to update program code space in circuit without the need to replace one time programmable devices at remote operating nodes Flash EE Memory and the ADuC824 The ADuC824 provides two arrays of Flash EE Memory for user applications 8 Kbytes of Flash EE Program space are provided on chip to facilitate code execution without any external discrete ROM device requirements The program memory can be pro grammed using conventional third party memory progr
97. ister Used to control the operational mode of both ADCs SFR Address DIH Power On Default Value 00H Bit Addressable No ADCOEN ADCIEN MD2 MD1 MDO Table IV ADCMODE SFR Bit Designations Bit Name Description 7 Reserved Future Use 6 Reserved for Future Use 5 ADCOEN Primary ADC Enable Set by the user to enable the Primary ADC and place it in the mode selected in MD2 MDO below Cleared by the user to place the Primary ADC in power down mode 4 ADCIEN Auxiliary ADC Enable Set by the user to enable the Auxiliary ADC and place it in the mode selected in MD2 MDO below Cleared by the user to place the Auxiliary ADC in power down mode 3 Reserved for Future Use 2 MD2 Primary and Auxiliary ADC Mode bits 1 MDI These bits select the operational mode of the enabled ADC as follows 0 MD2 1 0 0 0 Power Down Mode Power On Default 0 0 1 Idle Mode In Idle Mode the ADC filter and modulator are held in a reset state although the modulator clocks are still provided 0 1 0 Single Conversion Mode In Single Conversion Mode a single conversion is performed on the enabled ADC On completion of the conversion the ADC data regis ters ADCOH M L and or ADC1H L are updated the relevant flags in the ADCSTAT SFR are written and power down is re entered with the MD2 MDO accordingly being written to 000 0 1 1 Continuous Conversion In continuous conversion mode the ADC data registe
98. ived by the SPI interface SPIDAT SPI Data Register Function SFR Address F7H Power On Default Value 00H Bit Addressable No Using the SPI Interface Depending on the configuration of the bits in the SPICON SFR shown in Table XIX the ADuC824 SPI interface will transmit or receive data in a number of possible modes Figure 33 shows all possible ADuC824 SPI configurations and the timing rela tionships and synchronization between the signals involved Also shown in this figure is the SPI interrupt bit ISPI and how it is triggered at the end of each byte wide communication SPI Interface Master Mode In master mode the SCLOCK pin is always an output and gener ates a burst of eight clocks whenever user code writes to the SPIDAT register The SCLOCK bit rate is determined by SPRO and SPRI in SPICON It should also be noted that the SS pin is not used in master mode If the ADuC824 needs to assert the SS pin on an external slave device a Port digital output pin should be used In master mode a byte transmission or reception is initiated CPOL f by a write to SPIDAT Eight clock periods are generated via the SCLOCK pin and the SPIDAT byte being transmitted via MOSI With each SCLOCK period a data bit is also sampled via MISO IPLE After eight clocks the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register The ISPI flag will be set automatically and an interrupt will
99. l Parameter Min Typ Max Unit Figure CLOCK INPUT External Clock Driven XTAL1 XTALI Period 30 52 us 1 tckL XTALI Width Low 15 24 us 1 tckH XTALI Width High 15 24 us 1 tckR XTALI Rise Time 20 ns 1 XTALI Fall Time 20 ns 1 1 tcorE ADuC824 Core Clock Frequency 0 098 12 58 MHz tcoRE ADuC824 Core Clock Period 0 636 us tcyc ADuC824 Machine Cycle Time 0 95 7 6 122 45 us NOTES AC inputs during testing are driven at DVpp 0 5 V for a Logic 1 and 0 45 V for a Logic 0 Timing measurements are made at Vy min for a Logic 1 and max for a Logic 0 as shown in Figure 2 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs A port pin begins to float when a 100 mV c loaded level occurs as shown in Figure 2 for 0 ALE PSEN outputs 100 pF Croan for all other outputs 80 pF unless otherwise noted hange from the ADuC824 internal PLL locks onto a multiple 384 times the external crystal frequency of 32 768 kHz to provide a Stable 12 583 MHz internal clock for the system The core can operate at this frequency or at a binary submultiple called Core selected via the PLLCON SFR This number is measured at the default Core operating frequency of 1 57 MHz ADuC824 Machine Cycle Time is nominally defined as 12 CLK Figure 1 XTAL1 Input DVpp 0 5V 0 2DVpp 0 9V Vioap TIMING Vioap 0 1V T
100. les the on chip internal bandgap reference In this mode the ADCs will see the internal reference of 1 25 V therefore halving all input ranges As a result of using the internal reference volt age a noticeable degradation in peak to peak resolution will result Therefore for best performance operation with an exter nal reference is strongly recommended In applications where the excitation voltage or current for the transducer on the analog input also drives the reference voltage for the part the effect of the low frequency noise in the excita tion source will be removed as the application is ratiometric If the ADuC824 is not used in a ratiometric application a low noise reference should be used Recommended reference voltage sources for the ADuC824 include the AD780 REF43 and REF192 It should also be noted that the reference inputs provide a high impedance dynamic load Because the input impedance of each reference input is dynamic resistor capacitor combinations on these inputs can cause dc gain errors depending on the output impedance of the source that is driving the reference inputs Reference voltage sources like those recommended above e g AD780 will typically have low output impedances and therefore decoupling capacitors the REFIN input would be recom mended Deriving the reference input voltage across an external resistor as shown in Figure 53 will mean that the reference input sees a significant external
101. low byte SFR Address CBhex CAhex respectively REV B 55 ADuC824 Timer Counter 2 Operating Modes The following paragraphs describe the operating modes for timer counter 2 The operating modes are selected by bits in the 2 SFR as shown in Table XXVI Table XXVI TIMECON SFR Bit Designations TCLK CAP2 TR2 MODE 0 0 1 16 Bit Autoreload 0 1 1 16 Bit Capture 1 X 1 Baud Rate X X 0 OFF 16 Bit Autoreload Mode In Autoreload mode there are two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then when Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2L and RCAP2H which are preset by software If EXEN2 1 then Timer 2 still performs the above but with the added feature that 1 to 0 transition at external input T2EX will also trigger the 16 bit reload and set EXF2 The autoreload mode is illustrated in Figure 38 TRANSITION DETECTOR 2 CONTROL EXEN2 TL2 TH2 AP2L 16 Bit Capture Mode In the Capture mode there are again two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then Timer 2 is a 16 bit timer or counter which upon overflowing sets bit TF2 the Timer 2 overflow bit which can be used to generate an inter rupt If EXEN2 1 then Timer 2 still performs the above but l to 0 transition on external input T2EX
102. mary ADC Set by hardware on completion of ADC conversion or calibration cycle Cleared directly by the user or indirectly by write to the mode bits to start another Primary ADC conversion or calibration The Primary ADC is inhibited from writing further results to its data or calibration registers until the RDYO bit is cleared 6 RDY1 Ready Bit for Auxiliary ADC Same definition as RDYO referred to the Auxiliary ADC 5 CAL Calibration Status Bit Set by hardware on completion of calibration Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration 4 NOXREF No External Reference Bit only active if Primary or Auxiliary ADC is active Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold When Set conversion results are clamped to all ones if using ext reference Cleared to indicate valid 3 ERRO Primary ADC Error Bit Set by hardware to indicate that the result written to the Primary ADC data registers has been clamped to all zeros or all ones After a calibration this bit also flags error conditions that caused the calibration registers not to be written Cleared by a write to the mode bits to initiate a conversion or calibration 2 ERRI Auxiliary ADC Error Bit Same definition as ERRO referred to the Auxiliary ADC 1 Reserved for Future Use Reserved for Future Use REV B 25 ADuC824 ADCMODE ADC Mode Reg
103. mer counter 0 only while INTO pin is high and TRO control bit is set Cleared by software to enable Timer 0 whenever TRO control bit is set 0 THO operates as an 8 bit timer counter TLO serves as 5 bit prescaler 0 1 16 Bit Timer Counter THO are cascaded there is no prescaler 0 8 Bit Auto Reload Timer Counter THO holds a value which is to be reloaded into TLO each time it overflows 1 1 TLO is an 8 bit timer counter controlled by the standard timer 0 control bits THO is an 8 bit timer only controlled by Timer 1 control bits 52 REV B ADuC824 TCON Timer Counter 0 and 1 Control Register SFR Address 88H Power On Default Value 00H Bit Addressable Yes TF1 TR1 TFO TRO IE1 IT1 IEO ITO These bits are not used in the control of timer counter 0 and 1 but are used instead in the control and monitoring of the external INTO and INTI interrupt pins Table XXIV TCON SFR Bit Designations Bit Name Description 7 TF1 Timer 1 Overflow Flag Set by hardware on a timer counter 1 overflow Cleared by hardware when the Program Counter PC vectors to the interrupt service routine 6 TR1 Timer 1 Run Control Bit Set by user to turn on timer counter 1 Cleared by user to turn off timer counter 1 5 Timer 0 Overflow Flag Set by hardware on a timer counter 0 overflow Cleared by hardware when the PC vectors to the interrupt service routine 4 TRO Timer 0 Run Control Bit Set
104. mory on a single chip This low power device accepts low level signals directly from a transducer The two independent ADCs Primary and Auxiliary include a temperature sensor and a allowing direct measurement of MicroConverter is a registered trademark of Analog Devices Inc SPI is a registered trademark of Motorola Inc is a registered trademark of Philips Semiconductors Inc REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM CURRENT SOURCE 8051 BASED MCU WITH ADDITIONAL PERIPHERALS 8 KBYTES FLASH EE PROGRAM MEMORY 640 BYTES FLASH EE DATA MEMORY 256 BYTES USER RAM INTERNAL BANDGAP CLOCK VREF DIVIDER 3 x 16 BIT TIMER COUNTERS 1 x TIME INTERVAL COUNTER ON CHIP MONITORS POWER SUPPLY MONITOR WATCHDOG TIMER EXTERNAL VREF DETECT UART AND SPI SERIAL REFIN REFIN XTAL1 XTAL2 low level signals The ADCs with on chip digital filtering are intended for the measurement of wide dynamic range low frequency signals such as those in weigh scale strain gauge pressure trans ducer or temperature measurement applications The ADC output data
105. n nected again near the ADuC824 since a ground loop would result In these cases tie the ADuC824 s AGND and DGND pins all to the analog ground plane as illustrated in Figure 52b In systems with only one ground plane ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa The ADuC824 can then be placed between the digital and analog sections as illustrated in Figure 52c REV B ADuC824 A i PLACE ANALOG PLACE DIGITAL COMPONENTS HERE COMPONENTS HERE AGND DGND B PLACE ANALOG puo PLACE DIGITAL i COMPONENTS COMPONENTS mat HERE AGND DGND i PLACE ANALOG 4 PLACE DIGITAL COMPONENTS COMPONENTS 3 COLE HERE GND Figure 52 System Grounding Schemes In all of these scenarios and in more complicated real life appli cations keep in mind the flow of current from the supplies and back to ground Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations For example do not power components on the analog side of Figure 52b with DVpp since that would force return currents from DVpp to flow through AGND Also try to avoid digital currents flowing under analog circuitry which could happen if the user placed a noisy digital chip on the left half of the
106. n blocks an analog modulator and a digital filter In the case of the ADuC824 ADCs the analog modulators consist of a difference amplifier an integrator block a comparator and a feedback DAC as illus trated in Figure 21 DIFFERENCE AMP ANALOG INPUT COMPARATOR HIGH FREQUENCY BITSTREAM TO DIGITAL FILTER INTEGRATOR Figure 21 Sigma Delta Modulator Simplified Block Diagram In operation the analog signal sample is fed to the difference amplifier along with the output of the feedback DAC The differ ence between these two signals is integrated and fed to the comparator The output of the comparator provides the input to the feedback DAC so the system functions as a negative feedback loop that tries to minimize the difference signal The digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the comparator This duty cycle data can be recovered as a data word using a subsequent digital filter stage The sampling frequency of the modulator loop is many times higher than the bandwidth of the input signal The integrator in the modulator shapes the quantization noise which results from the analog to digital con version so that the noise is pushed toward one half of the modulator frequency Digital Filter The output of the sigma delta modulator feeds directly into the digital filter The digital filter then band limits the response to a frequency
107. nctional The CPU status is preserved with the stack pointer program counter and all other internal registers maintain their data during idle mode Port pins and DAC output pins also retain their states and ALE and PSEN outputs go high in this mode The chip will recover from idle mode upon receiving any enabled interrupt or on receiving a hardware reset 64 power down mode both the PLL and the clock to the are stopped The on chip oscillator can be halted or can continue to oscillate depending on the state of the oscillator power down bit OSC_PD in the PLLCON SFR The TIC being driven directly from the oscillator can also be enabled during power down All other on chip peripherals however are shut down Port pins retain their logic levels in this mode but the DAC output goes to a high impedance state three state while ALE and PSEN outputs are held low During full power down mode the ADuC824 consumes a total of 5 typically There are five ways of terminating power down mode Asserting the RESET Pin 15 Returns to normal mode all registers are set to their default state and program execution starts at the reset vector once the Reset pin is de asserted Cycling Power All registers are set to their default state and program execution starts at the reset vector Time Interval Counter TIC Interrupt Power down mode is terminated and the CPU services the TIC interrupt the RETI at the end of the TIC
108. nsmit Clock Enable Set by user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3 Cleared by user to enable Timer 1 overflow to be used for the transmit clock 3 EXEN2 Timer 2 External Enable Flag Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port Cleared by user for Timer 2 to ignore events at 2 2 TR2 Timer 2 Start Stop Control Bit Set by user to start Timer 2 Cleared by user to stop Timer 2 1 CNT2 Timer 2 Timer or Counter Function Select Bit Set by user to select counter function input from external T2 pin Cleared by user to select timer function input from on chip core clock 0 CAP2 Timer 2 Capture Reload Select Bit Set by user to enable captures on negative transitions at T2EX if EXEN2 1 Cleared by user to enable auto reloads with Timer 2 overflows or negative transitions at T2EX when 2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to autoreload on Timer 2 overflow Timer Counter 2 Data Registers Timer Counter 2 also has two pairs 8 bit data registers associated with it These are used both timer data registers and timer capture reload registers TH2 and TL2 Timer 2 data high byte and low byte SFR Address CDhex CChex respectively RCAP2H and RCAP2L Timer 2 Capture Reload byte and
109. nterrupt if enabled See IEIP2 SFR description under Interrupt System later in this data sheet A6H 00H No 0 to 255 decimal Hundredths Seconds Time Register This register is incremented in 1 128 second intervals once TCEN in TIMECON is active The HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register A2H 00H No 0 to 127 decimal Seconds Time Register This register is incremented in 1 second intervals once TCEN in TIMECON is active The SEC SFR counts from 0 to 59 before rolling over to increment the MIN time register A3H 00H No 0 to 59 decimal Minutes Time Register This register is incremented in 1 minute intervals once TCEN in TIMECON is active The MIN counts from 0 to 59 before rolling over to increment the HOUR time register AAH 00H No 0 to 59 decimal Hours Time Register This register is incremented in 1 hour intervals once TCEN in TIMECON is active The HOUR SFR counts from 0 to 23 before rolling over to 0 A5H 00H No 0 to 23 decimal 45 ADuC824 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC824 enters an erroneous state possibly due to a programming error electrical noise or RFI The Watchdog function can be disabled by clearing the WDE Watchdog Enable bit in the Watchdog Control WDCON SFR When enabled the watchdog circuit will generate a system reset o
110. occur if enabled The value in the shift register will be latched into SPIDAT SAMPLE INPUT PATA OUTPUT SPI Interface Slave Mode In slave mode the SCLOCK is an input The SS pin must ISPLFLAG also be driven low externally during the byte communication SAMPLE INPUT Transmission is also initiated by a write to SPIDAT In slave DATA OUTPUT mode a data bit is transmitted via MISO and a data bit is received CPHA 0 via MOSI through each input SCLOCK period After eight clocks the transmitted byte will have been completely transmitted the ISPI FLAG input byte will be waiting in the input shift register The ISPI flag ee will be set automatically and an interrupt will occur if enabled Figure 33 SPI Timing All Modes The value in the shift register will be latched into SPIDAT only when the transmission reception of a byte has been completed The end of transmission occurs after the eighth clock has been received if CPHA 1 or when SS returns high if CPHA 0 REV 49 ADuC824 PC COMPATIBLE INTERFACE The ADuC824 supports a 2 wire serial interface mode which is compatible The C compatible interface shares its pins with the on chip SPI interface and therefore the user can only enable one or the other interface at any given time see SPE in SDATA Pin 27 SCLOCK Pin 26 SPICON previously An Application Note describing the op
111. ology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2002 ADuC824 TABLE OF CONTENTS FEATURES ge 1 NONVOLATILE FLASH EE MEMORY 37 GENERAL DESCRIPTION 1 Flash EE Memory Overview 37 SPECIBICATTIONYS eee ricco ss oontra rh 3 Flash EE Memory the 824 37 TIMING SPECIFICATIONS 8 ADuC824 Flash EE Memory Reliability 37 ABSOLUTE MAXIMUM 18 Using the Flash EE Program 38 PIN CONFIGURATION 509 18 Flash EE Program Memory Security 39 ORDERING GUIDE 6 i ies 18 Using the Flash EE Data 39 PIN FUNCTION DESCRIPTIONS 19 USER INTERFACE TO OTHER ON CHIP ADuC824 ADuC824 BLOCK DIAGRAM eee 21 PERIPHERALS 41 MEMORY 22 41 OVERVIEW MCU RELATED 23 On Chip 42 Accumulator deese e e 23 Time Interval Counter
112. on The baud rate in Mode 0 is fixed Mode 0 Baud Rate Core Clock Frequency 12 In these descriptions Core Clock Frequency refers to the core clock frequency selected via the CD0 2 bits in the PLLCON SFR Mode 2 Baud Rate Generation The baud rate in Mode 2 depends on the value of the SMOD bit in the PCON SFR If SMOD 0 the baud rate is 1 64 of the core clock If SMOD 1 the baud rate is 1 32 of the core clock Mode 2 Baud Rate 25 92 64 x Core Clock Frequency Mode 1 and 3 Baud Rate Generation The baud rates in Modes 1 and 3 are determined by the overflow rate in Timer 1 or Timer 2 or both one for transmit and the other for receive REV B ADuC824 Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows Modes 1 and 3 Baud Rate 2800 32 x Timer 1 Overflow Rate The Timer 1 interrupt should be disabled in this application The Timer itself can be configured for either timer or counter opera tion and in any of its three running modes In the most typical application it is configured for timer operation in the autoreload mode high nibble of TMOD 0100Binary In that case the baud rate is given by the formula Modes 1 and 3 Baud Rate 25 0 32 x Core Clock 12 x 256 1 A very low baud rate can also be achieved with Timer 1 by leaving the Timer 1 interrup
113. on Note uC004 detailing this serial download protocol is available from www analog com microconverter DeBug In Circuit Debugger The Debugger is a Windows application that allows the user to debug code execution on silicon using the MicroConverter UART serial port The debugger provides access to all on chip periph erals during a typical debug session as well as single step and break point code execution control ADSIM Windows Simulator The Simulator is a Windows application that fully simulates all the MicroConverter functionality including ADC and DAC peripherals The simulator provides an easy to use intuitive inter face to the MicroConverter functionality and integrates many standard debug features including multiple breakpoints single stepping and code execution trace capability This tool can be used both as a tutorial guide to the part as well as an efficient way to prove code functionality before moving to a hardware platform The QuickStart development tool suite software is freely available at the Analog Devices MicroConverter Website www analog com microconverter Figure 55 Typical Debug Session 67 ADuC824 OUTLINE DIMENSIONS Dimensions shown in mm and inches 52 Lead Plastic Quad Flatpack MQFP S 52 14 15 0 557 2 22 0 094 13 65 0 537 13 0 084 10 11 0 398 0 95 0 037 0 65 0 028 SEATING 8 25 5 VIEW sle sls PINS DOWN 5
114. onditions Comments Unit LOGIC OUTPUTS Not Including XTAL2 Von Output High Voltage 2 4 Vpp 5 Isource 80 uA V min 2 4 3 V IsouRCE 20 min Vor Output Low Voltage 0 4 8 mA SCLOCK SDATA MOSI max 0 4 10 mA P1 0 and P1 1 V max 0 4 Ig x 1 6 mA All Other Outputs V max Floating State Leakage Current 10 max Floating State Output Capacitance 5 pF typ POWER SUPPLY MONITOR PSM AVpp Trip Point Selection Range 2 63 Four Trip Points Selectable This Range min 4 63 Programmed via TPA1 0 in PSMCON max AVpp Power Supply Trip Point Accuracy 3 5 max DVpp Trip Point Selection Range 2 63 Four Trip Points Selectable in This Range V min 4 63 Programmed via TPD1 0 in PSMCON max DVpp Power Supply Trip Point Accuracy 13 5 max WATCHDOG TIMER WDT Timeout Period 0 Nine Timeout Periods in This Range ms min 2000 Programmed via PRE3 0 in WDCON ms max MCU CORE CLOCK RATE Clock Rate Generated via On Chip PLL MCU Clock Rate 98 3 Programmable via CD2 0 Bits in kHz min PLLCON SFR 12 58 MHz max START UP TIME At Power On 300 ms typ From Idle Mode 1 ms typ From Power Down Mode Oscillator Running OSC_PD Bit 0 in PLLCON SFR Wakeup with INTO Interrupt 1 ms typ Wakeup with SPI PC Interrupt 1 ms typ Wakeup with TIC Interrupt 1 ms typ Wakeup with External RESET 3 4 ms typ Oscillator Powered Down OSC_PD Bit 1 in PLLCON SFR Wakeup with External RESET 0 9 sec typ After External RESET
115. or applications requiring an extra 8 bit timer or counter When timer 0 is in Mode 3 timer 1 can be turned on and off by switching it out of and into its own Mode 3 or can still be used by the serial interface as a Baud Rate Generator In fact it can be used in any application not requiring an interrupt from timer 1 itself CORE CORE CLK CLK 12 0 e INTERRUPT 8 BITS TRO CONTROL 1 P3 4 TO TRO GATE P3 2 INTO CORE 5 INTERRUPT CLK 12 8 BITS CONTROL TR1 THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 37 Timer Counter 0 Mode 3 REV B ADuC824 T2CON Timer Counter 2 Control Register SFR Address C8H Power On Default Value 00H Bit Addressable Yes TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 Table XXV T2CON SFR Bit Designations Bit Name Description 7 2 Timer 2 Overflow Flag Set by hardware on a Timer 2 overflow TF2 will not be set when either RCLK or TCLK 1 Cleared by user software 6 EXF2 Timer 2 External Flag Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 Cleared by user user software 5 RCLK Receive Clock Enable Bit Set by user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3 Cleared by user to enable Timer 1 overflow to be used for the receive clock 4 Tra
116. ort 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24 bit external data memory space REV B Port 3 is a bidirectional port with internal pull ups directly controlled via the P2 SFR SFR address hex Port 3 pins that have 1 written to them are pulled high by the internal pull ups and in that state they can be used as inputs As inputs Port 3 pins being pulled externally low will source current because of the internal pull ups Port 3 pins also have various secondary func tions described in Table XXII Table XXII Port 3 Alternate Pin Functions Pin Alternate Function P3 0 RXD UART Input Pin or Serial Data I O in Mode 0 P3 1 TXD UART Output Pin or Serial Clock Output in Mode 0 3 2 INTO External Interrupt 0 P3 3 External Interrupt 1 P3 4 TO Timer Counter 0 External Input P3 5 1 Timer Counter 1 External Input P3 6 WR External Data Memory Write Strobe P3 7 RD External Data Memory Read Strobe The alternate functions of P1 0 P1 1 and Port 3 pins can only be activated if the corresponding bit latch in the 1 and P3 SFRs contains a 1 Otherwise the port pin is stuck at 0 Timers Counters The ADuC824 has three 16 bit Timer Counters Timer 0 Timer 1 and Timer 2 The Timer Counter hardware has been included on chip to relieve the processor core of the overhead inherent in implem
117. p 30 mV V max External Reference Inputs REFIN to REFIN Range 1 V min Average Reference Input Current 1 Both ADCs Enabled typ Average Reference Input Current Drift 0 1 nA V C typ Ext REF Trigger Voltage 0 3 Bit Active if lt 0 3 V V min 0 65 NOXREF Bit Inactive if Vggr gt 0 65 V V max ADC SYSTEM CALIBRATION Full Scale Calibration Limit 1 05 x FS V max Zero Scale Calibration Limit 1 05 x FS V min Input Span 0 8 x FS V min 2 1 x FS V max ANALOG DAC OUTPUTS Voltage Range 0 to VREF DACRN 0in DACCON SFR V typ 0 to AVpp DACRN 1 in DACCON SFR V typ Resistive Load 10 From DAC Output to AGND typ Capacitive Load 100 From DAC Output to AGND pF typ Output Impedance 0 5 typ 50 typ TEMPERATURE SENSOR Accuracy 2 C typ Thermal Impedance 90 C W typ REV ADuC824 Parameter ADuC824BS Test Conditions Comments Unit TRANSDUCER BURNOUT CURRENT SOURCES AIN Current 100 AIN is the Selected Positive Input to nA typ the Primary ADC AIN Current 100 AIN is the Selected Negative Input to nA typ the Auxiliary ADC Initial Tolerance 25 Drift t10 typ Drift 0 03 typ EXCITATION CURRENT SOURCES Output Current 200 Available from Each Current Source typ Initial Tolerance 25 C 10 typ Drift 200 ppm C typ Initial Current Matching 25 C Matching Between Both Current Sources ty
118. p Digital to Analog Glitch Energy 10 1 LSB Change at Major Carry nVs typ REV 824 Parameter ADuC824BS Test Conditions Comments Unit INTERNAL REFERENCE ADC Reference Reference Voltage 1 25 1 Initial Tolerance 25 C Vpp 2 5V V min max Power Supply Rejection 45 dBs typ Reference Tempco 100 ppm C typ DAC Reference Reference Voltage 2 5 t 196 Initial Tolerance 25 C Vpp 5 V V min max Power Supply Rejection 50 dBs typ Reference Tempco 100 ppm C typ ANALOG INPUTS REFERENCE INPUTS Primary ADC Differential Input Voltage Ranges External Reference Voltage 2 5 V RN2 RN1 RNO of ADCOCON Set to Bipolar Mode ADCOCON3 0 20 000 Unipolar Mode 0 to 20 mV mV 40 001 Unipolar Mode 0 to 40 mV mV 80 010 Unipolar Mode 0 to 80 mV mV 160 011 Unipolar Mode 0 to 160 mV mV 320 100 Unipolar Mode 0 to 320 mV mV 640 101 Unipolar Mode 0 to 640 mV mV 1 28 110 Unipolar Mode 0 to 1 28 22 56 111 Unipolar Mode 0 2 56 V Analog Input Current 1 nA max Analog Input Current Drift 5 pA C typ Absolute AIN Voltage Limits AGND 100 mV V min AVpp 100 mV V max Auxiliary ADC Input Voltage Range 10 0 to VREF Unipolar Mode for Bipolar Mode V See Note 11 Average Analog Input Current 125 Input Current Will Vary with Input nA V typ Average Analog Input Current Drift 2 Voltage on the Unbuffered Auxiliary ADC pA V C Absolute AIN Voltage Limits AGND 30 mV V min AVp
119. p Drift Matching 20 ppm C typ Line Regulation AVpp 1 AVpp 5 5 typ Load Regulation 0 1 typ Output Compliance AVpp 0 6 V max AGND min LOGIC INPUTS All Inputs Except SCLOCK RESET and XTALI Vint Input Low Voltage 0 8 DVpp 5 V V max 0 4 DVpp 3 V V max Vinu Input High Voltage 2 0 V min SCLOCK and RESET Only Schmitt Triggered Inputs VT 1 3 3 DVpp 25V V min V max 0 95 2 5 DVpp 3 V V min V max Vr 0 8 1 4 DVpp 5 V V min V max 0 4 1 1 DVpp 3 V V min V max Vr 0 3 0 85 DVpp 5 V V min V max 0 3 0 85 DVpp 3 V V min V max Input Currents Port 0 P1 2 P1 7 EA 10 Vin or Vpp max SCLOCK SDATA MOSI MISO SS 10 min 40 max Vin 0 V DVpp 5 V Internal Pull Up uA min uA max 10 Vin Vpp DVpp 25V uA max RESET 10 Vin 0 V DVpp 5 V max 35 min 105 max Vin DVpp 5 V min uA max Internal Pull Down P1 0 1 1 Ports 2 and 3 10 Vin DVpp 25V max 180 Vin 2 DVpp 25V uA min 660 uA max 20 Vin 450 mV DVpp 25V min 75 Input Capacitance 5 All Digital Inputs pF typ CRYSTAL OSCILLATOR XTAL1 AND XTAL2 Logic Inputs XTALI Only Vint Input Low Voltage 0 8 DVpp 5 V V max 0 4 DVpp 3 V V max Vinn Input High Voltage 3 5 DVpp 5 V V min 2 5 DVpp 23V V min Input Capacitance 18 pF typ XTAL2 Output Capacitance 18 pF typ REV B ADuC824 Parameter ADuC824BS Test C
120. ponse instead of a system reset when the watchdog timeout period has expired This interrupt is not disabled by the CLR EA instruction and it is also a fixed high priority interrupt If the watchdog is not being used to monitor the system it can alternatively be used as a timer The prescaler is used to set the timeout period in which an interrupt will be generated See also Note 1 Table XXXIV in the Interrupt System section 2 WDS Watchdog Status Bit Set by the Watchdog Controller to indicate that a watchdog timeout has occurred Cleared by writing a 0 or by an external hardware reset It is not cleared by a watchdog reset 1 WDE Watchdog Enable Bit Set by user to enable the watchdog and clear its counters If this bit is not set by the user within the watchdog timeout period the watchdog will generate a reset or interrupt depending on WDIR Cleared under the following conditions User writes 0 Watchdog Reset 70 Hardware Reset PSM Interrupt 0 WDWR Watchdog Write Enable Bit To write data into the WDCON SFR involves a double instruction sequence The WDWR bit must be set and the very next instruction must be a write instruction to the WDCON SFR e g CLR EA disable interrupts while writing to WDT SETB WDWR allow write to WDCON MOV WDCON 72h enable for 2 05 timeout SET B EA enable interrupts again if 46 REV B ADuC824 POWER SUPPLY MONITOR As its name suggests the Power Suppl
121. r as part of the Flash EE memory section in this data sheet The external data memory area can be expanded up to 16 Mbytes This is an enhancement of the 64 KByte external data memory space available on standard 8051 compatible cores The external data memory is discussed in more detail in the ADuC824 Hardware Design Considerations section E DATA MEMORY SPACE READ WRITE FFFFFFH PAGE 159 640 BYTES FLASH EE DATA MEMORY ACCESSED INDIRECTLY VIA SFR CONTROL REGISTERS PAGE 0 00H EXTERNAL DATA INTERNAL pod DATA MEMORY 24 BIT SPACE ADDRESS FFH SPECIAL SPACE ACCESSIBLE FUNCTION BY REGISTERS UPPER 128 INDIRECT ACCESSIBLE ADDRESSING By piRECT ONLY ADDRESSING 80H ONLY 80H 7FH ACCESSIBLE BY Eco DIRECT AND INDIRECT ADDRESSING 00H 000000H Figure 14 Data Memory Map The lower 128 bytes of internal data memory are mapped as shown in Figure 15 The lowest 32 bytes are grouped into four banks of eight registers addressed as RO through R7 The next 16 bytes 128 bits locations 20 Hex through 2 FHex above the regis ter banks form a block of directly addressable bit locations at bit addresses 00H through 7FH The stack can be located any where in the internal memory address space and the stack depth can be expanded up to 256 bytes GENERAL PURPOSE AREA BANKS BIT ADDRESSABLE SELECTED BIT ADDRESSES VIA 1 BITS IN PSW FOUR BANKS OF EIGHT REGISTERS RO R7
122. r interrupt WDS if the user program fails to set the watchdog WDE bit within a predetermined amount of time see PRE3 0 bits in WDCON The watchdog timer itself is a 16 bit counter that is clocked at 32 768 kHz The watchdog time out interval can be adjusted via the PRE3 0 bits in WDCON Full Control and Status of the watchdog timer function can be controlled via the watchdog timer control SFR WDCON The WDCON SFR can only be written by user software if the double write sequence described in WDWR below is initiated on every write access to the WDCON SFR WDCON Watchdog Timer Control Register SFR Address COH Power On Default Value 10H Bit Addressable Yes PRE3 PRE2 PREO WDIR WDS WDE WDWR Table XVII WDCON SFR Bit Designations Bit Name Description 7 PRE3 Watchdog Timer Prescale Bits 6 PRE2 The Watchdog timeout period is given by the equation twp 2735 2 5 0 PRE 7 32 768 kHz 4 PREO PRE3 PRE2 PREI PREOTimout Period ms Action 0 0 0 0 15 6 Reset or Interrupt 0 0 0 1 31 2 Reset or Interrupt 0 0 1 0 62 5 Reset or Interrupt 0 0 1 1 125 Reset or Interrupt 0 1 0 0 250 Reset or Interrupt 0 1 0 1 500 Reset or Interrupt 0 1 1 0 1000 Reset or Interrupt 0 1 1 1 2000 Reset or Interrupt 1 0 0 0 0 0 Immediate Reset PRE3 0 gt 1001 Reserved 3 WDIR Watchdog Interrupt Response Enable Bit If this bit is set by the user the watchdog will generate an interrupt res
123. ram memory Flash EE memory arrays can be pro grammed in one of two modes namely Serial Downloading In Circuit Programming As part of its factory boot code the ADuC824 facilitates serial code download via the standard UART serial port Serial down 38 load mode is automatically entered on power up if the external pin PSEN is pulled low through an external resistor as shown in Figure 28 Once in this mode the user can download code to the program memory array while the device is sited in its target application hardware A PC serial download executable is pro vided as part of the ADuC824 QuickStart development system The Serial Download protocol is detailed in a MicroConverter Applications Note uC004 available from the ADI MicroConverter Website at www analog com microconverter TO CONFIGURE THE ADuC824 Figure 28 Flash EE Memory Serial Download Mode Programming Parallel Programming The parallel programming mode is fully compatible with conven tional third party Flash or EEPROM device programmers A block diagram of the external pin configuration required to support parallel programming is shown in Figure 29 In this mode Ports 0 1 and 2 operate as the external data and address bus interface ALE operates as the Write Enable strobe and Port 3 is used as a general configuration port that configures the device for various program and erase operations during parallel programming The high voltage 12 V supply requir
124. register depending on the timer mode configuration THO and TLO Timer 0 high byte and low byte SFR Address 8Chex 8Ahex respectively and TL1 Timer 1 high byte and low byte SFR Address 8Dhex 8Bhex respectively REV 53 ADuC824 TIMER COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for timer counters 0 and 1 Unless otherwise noted assume that these modes of operation are the same for timer 0 as for timer 1 Mode 0 13 Bit Timer Counter Mode 0 configures an 8 bit timer counter with a divide by 32 pre scaler Figure 34 shows mode 0 operation TLO THO 5 BITS 8 BITS CONTROL INTERRUPT TFO P3 4 TO TRO GATE P3 2 INTO THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 34 Timer Counter 0 Mode 0 In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the timer overflow flag The overflow flag can then be used to request an interrupt The counted input is enabled to the timer when TRO 1 and either Gate 0 or INTO 1 Setting Gate 1 allows the timer to be controlled by external input INTO to facilitate pulsewidth measurements is a control bit in the special function regis ter TCON Gate is in TMOD The 13 bit register consists of all eight bits of THO and the lower five bits of TLO The upper three bits of TLO are indetermin
125. rs are configured at power on with a factory default value of 8000Hex However these bytes will be automatically overwritten if an internal or system zero scale calibration is initiated by the user via the MD2 0 bits in the ADCMODE register SFR Address OFIH Auxiliary ADC Offset Coefficient High Byte E5H OFIL Auxiliary ADC Offset Coefficient Low Byte E4H Power On Default Value 8000H OF1H and OFIL Respectively Bit Addressable No Both Registers GNOH GNOMIGNOL Primary ADC Gain Calibration Registers These three 8 bit registers hold the 24 bit gain calibration coefficient for the Primary ADC These registers are configured at power on with a factory calculated internal full scale calibration coefficient Every device will have an individual coefficient However these bytes will be automatically overwritten if an internal or system full scale calibration is initiated by the user via MD2 0 bits in the ADCMODE register SFR Address GNOH Primary ADC Gain Coefficient High Byte EBH GNOM Primary ADC Gain Coefficient Middle Byte EAH GNOL Primary ADC Gain Coefficient Low Byte E9H Power On Default Value Configured at factory final test see notes above Bit Addressable No All Three Registers GN1H GNIL Auxiliary ADC Gain Calibration Registers These two 8 bit registers hold the 16 bit gain calibration coefficient for the Auxiliary ADC These registers are configured at power on with a factory calculated internal full scale calibration coefficient Eve
126. rs are regularly updated at the selected update rate see SF register 1 0 0 Internal Zero Scale Calibration Internal short is automatically connected to the enabled ADC s 1 0 1 Internal Full Scale Calibration Internal or External as determined by XREFO and XREF bits in is automatically connected to the ADC input for this calibration 1 1 0 System Zero Scale Calibration User should connect system zero scale input to the ADC input pins as selected by and bits in the ADCO ICON register 1 1 1 System Full Scale Calibration User should connect system full scale input to the ADC input pins as selected by and bits in the ADC0 1 CON register NOTES 2 3 Any change to the MD bits will immediately reset both ADCs write to the MD2 0 bits with change is also treated as reset See exception to this Note 3 below If ADCOCON is written when ADOEN 1 or if ADOEN is changed from 0 to 1 then both ADCs are also immediately reset In other words the Primary ADC is given priority over the Auxiliary ADC and any change requested on the primary ADC is immediately responded to On the other hand if ADC1CON is written or if ADCIEN is changed from 0 to 1 only the Auxiliary ADC is reset For example if the Primary ADC is continuously converting when the Auxiliary ADC change or enable occurs the primary ADC continues undisturbed Rather than allow
127. rved for Future Use 6 XREFI Auxiliary ADC External Reference Bit Set by user to enable the Auxiliary ADC to use the external reference via REFIN REFIN Cleared by user to enable the Auxiliary ADC to use the internal bandgap reference 5 ACHI Auxiliary ADC Channel Selection Bits 4 ACHO Written by the user to select the single ended input pins used to drive the Auxiliary ADC as follows ACHI ACHO Positive Input Negative Input 0 0 AIN3 AGND 0 1 AIN4 AGND 1 0 Temp Sensor AGND Temp Sensor routed to the ADC input 1 1 AIN5 AGND 3 UNII Auxiliary ADC Unipolar Bit Set by user to enable unipolar coding i e zero input will result in 0000 hex output Cleared by user to enable bipolar coding zero input will result in 8000 hex output 2 Reserved for Future Use 1 Reserved Future Use 0 Reserved for Future Use NOTES 1 When the temperature sensor is selected user code must select internal reference via XREFI bit above and clear the bit ADC1CON 3 to select bipolar coding 2 The temperature sensor is factory calibrated to yield conversion results 8000H at 0 C 3 A 1 change in temperature will result in 1 LSB change in the ADCIH register ADC conversion result SF Sinc Filter Register version time tapc are shown in Table VII the power on default The number in this register sets the decimation factor and thus the output update rate for the Primary and Auxiliary ADCs This SFR cannot be written by user
128. ry device will have an individual coefficient However these bytes will be automatically overwritten if an internal or system full scale calibration is initiated by the user via MD2 0 bits in the ADCMODE register SFR Address GNIH Auxiliary ADC Gain Coefficient High Byte EDH GNIL Auxiliary ADC Gain Coefficient Low Byte ECH Power On Default Value Configured at factory final test see notes above Bit Addressable No Both Registers These registers can be overwritten by user software only if Mode bits MD0 2 ADCMODE SFR are zero 30 REV B PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview The ADuC824 incorporates two independent sigma delta ADCs Primary and Auxiliary with on chip digital filtering intended for the measurement of wide dynamic range low frequency signals such as those in weigh scale strain gauge pressure trans ducer or temperature measurement applications Primary ADC This ADC is intended to convert the primary sensor input The input is buffered and can be programmed for one of 8 input ranges from 20 mV to 2 56 V being driven from one of three differ ential input channel options AIN1 2 AIN3 4 or AIN3 2 The input channel is internally buffered allowing the part to handle significant source impedances on the analog input allowing R C filtering for noise rejection or RFI reduction to be placed on ADuC824 the analog inputs if required On chip burnout currents can also be turned on These currents
129. s 3 RSO RS1 RSO Selected Bank 0 0 0 0 1 1 1 0 2 1 1 3 2 OV Overflow Flag 1 Fl General Purpose Flag 0 Power Control SFR The Power Control PCON register contains bits for power saving options and general purpose status flags as shown in Table II SFR Address 87H Power ON Default Value 00H Bit Addressable No SMOD SERIPD INTOPD ALEOFF PD IDL Table II PCON SFR Bit Designations Bit Name Description 7 SMOD Double UART Baud Rate 6 SERIPD PC SPI Power Down Interrupt Enable 5 INTOPD INTO Power Down Interrupt Enable 4 ALEOFF Disable ALE Output 3 General Purpose Flag Bit 2 General Purpose Flag 1 PD Power Down Mode Enable 0 IDL Idle Mode Enable 23 ADuC824 SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general purpose register banks reside in the SFR area The SFR registers include control configuration and data registers that provide an interface between the CPU and all on chip peripherals Figure 17 shows a full SFR memory map and SFR contents on RESET NOT USED indicates unoccupied SFR locations Unoc cupied locations in the SFR address space are not implemented i e no register exists at this location If an unoccupied location is read an unspecified value is returned SFR locations reserved for future use are shaded RESERVED and should not be accessed by
130. s 4 byte pages in this case A typical access to the Flash EE Data array will involve setting up the page address to be accessed in the EADRL SFR config uring the EDATAI 4 with data to be programmed to the array the EDATA SFRs will not be written for read accesses and finally writing the ECON command word which initiates one of the six modes shown in Table XIII 40 It should be noted that a given mode of operation is initiated as soon as the command word is written to the ECON SFR The core microcontroller operation on the ADuC824 is idled until the requested Program Read or Erase mode is completed In practice this means that even though the Flash EE memory mode of operation is typically initiated with a two machine cycle instruction to write to the ECON SFR the next instruc tion will not be executed until the Flash EE operation is complete 250 us or 2 ms later This means that the core will not respond to Interrupt requests until the Flash EE operation is complete although the core peripheral functions like Counter Timers will continue to count and time as configured throughout this period Erase All Although the 640 byte User Flash EE array is shipped from the factory pre erased i e Byte locations set to FFH it is nonethe less good programming practice to include an erase all routine as part of any configuration setup code running on the ADuC824 An ERASE ALL command consists of writing 06H to th
131. s and are tailored for direct connection to external resistive type sensors like strain gauges or Resistance Temperature Detectors RTDs The auxiliary ADC however is unbuffered resulting in higher analog input current on the auxiliary ADC It should be noted that this unbuffered input path provides a dynamic load to the driving source Therefore resistor capacitor combinations on the input pins can cause dc gain errors depending on the output impedance of the source that is driving the ADC inputs Analog Input Ranges The absolute input voltage range on the primary ADC is restricted to between AGND 100 mV to AVDD 100 mV Care must be taken in setting up the common mode voltage and input voltage range so that these limits are not exceeded otherwise there will be a degradation in linearity performance 33 ADuC824 The absolute input voltage range on the auxiliary ADC is restricted to between AGND 30 mV to AVDD 30 mV The slightly negative absolute input voltage limit does allow the possibility of monitoring small signal bipolar signals using the single ended auxiliary ADC front end Programmable Gain Amplifier The output from the buffer on the primary ADC is applied to the input of the on chip programmable gain amplifier PGA The PGA can be programmed through eight different unipolar input ranges and bipolar ranges The PGA gain range is programmed via the range bits in the ADCOCON SFR With the external refer ence sel
132. s is a read only bit and directly reflects the state of the AVDD comparator Read 1 indicates the AVDD supply is above its selected trip point Read 0 indicates the AVDD supply is below its selected trip point 5 PSMI Power Supply Monitor Interrupt Bit This bit will be set high by the MicroConverter if either CMPA or CMPD are low indicating low analog or digital supply The PSMI bit can be used to interrupt the processor Once CMPD and or CMPA return and remain high a 250 ms counter is started When this counter times out the PSMI interrupt is cleared PSMI can also be written by the user However if either com parator output is low it is not possible for the user to clear PSMI 4 TPDI DVDD Trip Point Selection Bits 3 TPDO These bits select the DVDD trip point voltage as follows TPDI TPDO Selected DVDD Trip Point V 0 0 4 63 0 1 3 08 1 0 2 93 1 1 2 63 TPAI AVDD Trip Point Selection Bits 1 These bits select the AVDD trip point voltage as follows 1 TPAO Selected AVDD Trip Point V 0 0 4 63 0 1 3 08 1 0 2 93 1 1 2 63 0 PSMEN Power Supply Monitor Enable Bit Set to 1 by the user to enable the Power Supply Monitor Circuit Cleared to 0 by the user to disable the Power Supply Monitor Circuit REV 47 ADuC824 SERIAL PERIPHERAL INTERFACE The ADuC824 integrates a complete hardware Serial Peripheral Interface SPI interface on chip SPI is an industry standard syn chronous seri
133. significantly lower than one half of the modulator frequency In this manner the 1 bit output of the comparator is translated into a band limited low noise output from the ADuC824 ADCs The ADuC824 filter is a low pass Sinc or sinx x filter whose primary function is to remove the quantization noise introduced at the modulator The cutoff frequency and decimated output data rate of the filter are programmable via the SF Sinc Filter SFR as described in Table VII 35 ADuC824 Figure 22 shows the frequency response of the ADC chan nel at the default SF word of 69 dec or 45 hex yielding an overall output update rate of just under 20 Hz It should be noted that this frequency response allows frequency components higher than the ADC Nyquist frequency to pass through the ADC in some cases without significant attenuation These components may therefore be aliased and appear in band after the sampling process It should also be noted that rejection of mains related frequency components 1 50 Hz and 60 Hz is seen to be at level of gt 65 dB at 50 Hz and gt 100 dB at 60 Hz This confirms the data sheet specifications for 50 Hz 60 Hz Normal Mode Rejec tion NMR at a 20 Hz update rate 0 10 20 30 40 50 60 70 80 90 100 110 FREQUENCY Hz Figure 22 Filter Response SF 69 dec The response of the filter however will change with SF word as can be seen in Figure 23
134. source impedance External decoupling on the REFIN REFIN pins would not be recommended in this type of circuit configuration Reference Detect The ADuC824 includes on chip circuitry to detect if the part has a valid reference for conversions or calibrations If the voltage between the external REFIN and REFIN pins goes below 0 3 V or either the REFIN or REFIN inputs is open circuit the ADuC824 detects that it no longer has a valid reference In this case the NOXREF bit of the ADCSTAT SFR is set to a 1 If the ADuC824 is performing normal conversions and the NOXREF bit becomes active the conversion results revert to all 1s Therefore it is not necessary to continuously monitor the status of the REV B NOXREF bit when performing conversions It is only necessary to verify its status if the conversion result read from the ADC Data Register is all 15 If the ADuC824 is performing either an offset or gain calibration and the NOXREF bit becomes active the updating of the respec tive calibration registers is inhibited to avoid loading incorrect coefficients to these registers and the appropriate ERRO or ERRI bits in the ADCSTAT SFR are set If the user is concerned about verifying that a valid reference is in place every time a cali bration is performed the status of the ERRO or ERRI bit should be checked at the end of the calibration cycle Sigma Delta Modulator sigma delta ADC generally consists of two mai
135. t enabled and configuring the timer to run as a 16 bit timer high nibble of TMOD 0100Binary and using the Timer 1 interrupt to do a 16 bit software reload Table XXVIII below shows some commonly used baud rates and how they might be calculated from a core clock frequency of 1 5728 MHz and 12 58 MHz Generally speaking a 5 error is tolerable using asynchronous start stop communications Table XXVIII Commonly Used Baud Rates Timer 1 Timer 2 Generated Baud Rates Baud rates can also be generated using Timer 2 Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted received Because Timer 2 has a 16 bit autoreload mode a wider range of baud rates is possible using Timer 2 Modes 1 and 3 Baud Rate 1 16 x Timer 2 Overflow Rate Therefore when Timer 2 is used to generate baud rates the timer increments every two clock cycles and not every core machine cycle as before Hence it increments six times faster than Timer 1 and therefore baud rates six times faster are possible Because Timer 2 has 16 bit autoreload capability very low baud rates are still possible Timer 2 is selected as the baud rate generator by setting the TCLK and or RCLK in T2CON The baud rates for transmit and receive can be simultaneously different Setting RCLK and or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 42 In this case the baud rate
136. tput This output is used to latch the low byte and page byte for 24 bit data address space accesses of the address to external memory during external code or data memory access cycles It is activated every six oscillator periods except during an external data memory access It can be disabled by setting the PCON 4 bit in the PCON SFR P0 0 P0 3 pins are part of Port 0 which is an 8 bit open drain bidirectional port Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs external pull up resistor will be required on PO outputsto force a valid logic high level externally Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this application it uses strong internal pull ups when emitting 1s P0 4 P0 7 pins are part of Port 0 which is an 8 bit open drain bidirectional I O port Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this application it uses strong internal pull ups when emitting 15 Input Output S Supply NOTES 1 In the following descriptions SET implies a Logic 1 state and CLEARED implies a Logic 0 state unless otherwise stated 2 In the following descriptions SET and CLEARED also imply that the bit is set or automati
137. ull scale calibration will remove this error altogether DAC linearity and AC Specifications are calculated using reduced code range of 48 to 4095 0 to VREF reduced code range of 48 to 3995 0 to Vpp 8 Error is a measure of the span error of the DAC general terms the bipolar input voltage range to the primary ADC is given by Range apc t Vgge 29 125 where REFIN to REFIN voltage and 1 25 V when internal ADC ggg is selected RN decimal equivalent of RN2 RN1 e g 2 5 V and RN2 RN1 1 1 0 the Rangeapc 1 28 V In unipolar mode the effective range is 0 V to 1 28 V in our example 101 25 V is used as the reference voltage to the ADC when internal is selected via XREFO and bits in ADCOCON and ADCICON respectively bipolar mode the Auxiliary ADC can only be driven to a minimum of 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits The bipolar range is still Vppp to Vggg however the negative voltage is limited to 30 mV 12 pins configured in I C compatible mode or SPI mode pins configured as digital inputs during this test 13 Pins configured in I C compatible mode only Flash EE Memory Reliability Characteristics apply to both the Flash EE program memory and Flash EE data memory Endurance is qualified to 100 Kcycles as Std 22 method A117 and measured at 40 C 25 C and 85 C typic
138. ws a hardware configuration for accessing up to 64 Kbytes of external RAM This interface is standard to any 8051 compatible MCU ADuC824 Figure 45 External Data Memory Interface 64 K Address Space If access to more than 64 Kbytes of RAM is desired a feature unique to the ADuC824 allows addressing up to 16 Mbytes of external RAM simply by adding an additional latch as illustrated in Figure 46 REV ADuC824 ADuC824 ADuC824 Figure 46 External Data Memory Interface 16 MBytes Address Space In either implementation Port 0 serves as a multiplexed address data bus It emits the low byte of the data pointer DPL as an address which is latched by a pulse of ALE prior to data being placed on the bus by the ADuC824 write operation or the SRAM read operation Port 2 P2 provides the data pointer page byte DPP to be latched by ALE followed by the data pointer high byte DPH If no latch is connected to P2 DPP is ignored by the SRAM and the 8051 standard of 64 Kbyte external data memory access is maintained Detailed timing diagrams of external program and data memory read and write access can be found in the timing specification sections of this data sheet Power On Reset Operation External POR power on reset circuitry must be implemented to drive the RESET pin of the ADuC824 The circuit must hold the RESET pin asserted high whenever the power supply DVpp is below 2 5 V Furthermore Vpp must rem
139. xiliary ADCs The numbers are typical and are generated at a differential input voltage of 0 V The output update rate is selected via the SF7 SFO bits in the Sinc Filter SF SFR It is important to note that the peak to peak resolu tion figures represent the resolution for which there will be no code flicker within a six sigma limit Table IX Primary ADC Typical Output RMS Noise pV Typical Output RMS Noise vs Input Range and Update Rate Output RMS Noise in pV SF Data Update Input Range Word Rate Hz 20mV 40mV 80mV 160mV 320mV 640mV 1 28 2 56V 13 105 3 1 50 1 50 1 60 1 75 3 50 4 50 6 70 11 75 69 19 79 0 60 0 65 0 65 0 65 0 65 0 95 1 40 2 30 255 5 35 0 35 0 35 0 37 0 37 0 37 0 51 0 82 1 25 Table X Primary ADC Peak to Peak Resolution Bits Peak to Peak Resolution vs Input Range and Update Rate Peak to Peak Resolution in Bits SF Data Update Input Range Word Rate Hz 20mV 40 80 160mV 320mV 640mV 1 28 2 56 V 13 105 3 12 13 14 15 15 15 5 16 16 69 19 79 13 14 15 16 17 17 5 18 18 5 255 5 35 14 15 16 17 18 18 5 18 8 19 2 Table XI Auxiliary ADC Typical Output RMS Noise vs Update Rate Peak to Peak Resolution vs Update Rate Output RMS Noise in pV Peak to Peak Resolution in Bits SF Data Update Input Range SF Data Update Input Range Word Rate Hz 2 5V Word Rate Hz 2 5V 13 105 3 10 75 13 105
140. y Monitor once enabled monitors both supplies AVDD or DVDD on the ADuC824 It will indicate when any of the supply pins drop below one of four user selectable voltage trip points from 2 63 V to 4 63 V For correct operation of the Power Supply Monitor function AVpp must be equal to or greater than 2 7 V Monitor function is controlled via the PSMCON SFR If enabled via the IEIP2 PSMCON SFR This bit will not be cleared until the failing power supply has returned above the trip point for at least 250 ms This monitor function allows the user to save working registers to avoid possible data loss due to the low supply condi tion and also ensures that normal code execution will not resume until a safe supply level has been well established The supply monitor is also protected against spurious glitches trig gering the interrupt circuit SFR the monitor will interrupt the core using the PSMI bit in the PSMCON Power Supply Monitor Control Register SFR Address DFH Power On Default Value DEH Bit Addressable No CMPD CMPA PSMI TPD1 TPDO 1 PSMEN Table XVIII PSMCON SFR Bit Designations Bit Name Description 7 CMPD DVDD Comparator Bit This is a read only bit and directly reflects the state of the DVDD comparator Read 1 indicates the DVDD supply is above its selected trip point Read 0 indicates the DVDD supply is below its selected trip point 6 CMPA AVDD Comparator Bit Thi
141. y registers allow the user to select one of two priority levels for each interrupt An interrupt of a high priority may interrupt the service routine of a low priority interrupt and if two interrupts of different priority occur at the same time the higher level interrupt will be serviced first An interrupt cannot be interrupted by another interrupt of the same priority level If two interrupts of the same priority level occur simulta neously a polling sequence is observed as shown in Table XXXIII Table XXXIII Priority within an Interrupt Level Source Priority Description PSMI 1 Highest Power Supply Monitor Interrupt WDS 2 Watchdog Interrupt IEO 3 External Interrupt 0 RDYO RDY1 4 ADC Interrupt 5 Timer Counter 0 Interrupt 1 6 External Interrupt 1 7 Timer Counter 1 Interrupt 12 ISPI 8 Interrupt RI TI 9 Serial Interrupt 2 EXF2 10 Timer Counter 2 Interrupt TII 11 Lowest Time Interval Counter Interrupt REV Interrupt Vectors When an interrupt occurs the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter The interrupt vector addresses are shown in Table XXXIV Table XXXIV Interrupt Vector Addresses Source Vector Address 0003 000B Hex 1 0013 TF1 001 Hex RI TI 0023 Hex TF2 EXF2 002B Hex RDYO RDYI ADC 0033 Hex IPC ISPI 003B Hex PSMI

ANALOG DEVICES ADuC824 MicroConverter Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU handbook

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