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ANALOG DEVICES ADuC816 MicroConverter Dual-Channel 16-Bit ADCs with Embedded FLASH MCU handbook

Contents

1. 33 INTERRUPT SYSTEM 0 0 00 ccc tenes 60 Analog Input Channels 33 Int rrupt Priority lez EDGE ds 61 Primary and Auxiliary ADC Inputs 33 ADuC816 HARDWARE DESIGN CONSIDERATIONS 62 Analog Input Ranges 33 Clock Oscillator dete ec ee Wigs Rr mH REESE 62 Programmable Gain Amplifier 34 External Memory Interface 62 Bipolar Unipolar Inputs 34 Power On Reset Operation 65 Burnout Currents See ve ye ERU eI OI 34 Power Supplies 63 Excitation Currents 34 Power Consumption 64 Reference Input iiie eee e e rye eee 34 Power Saving Modes 64 Reference Detect isses cc ee cea e eee d Ren 35 Grounding and Board Layout Recommendations 64 Sigma Delta Modulator 35 ADuC816 System Self Identification 65 Digital E EN AA 35 OTHER HARDWARE CONSIDERATIONS 65 ADC Chopping 36 In Circuit Serial Download Access 65 Calibration ere eor ear dye e d dee ee 36 Embedded Serial Port Debugger 65 NONVOLATILE FLASH EE MEMORY 31 Sing
2. 6 ANALOG DEVICES MicroConverter Dual Channel 16 Bit ADCs with Embedded Flash MCU ADuC816 FUNCTIONAL BLOCK DIAGRAM FEATURES High Resolution Sigma Delta ADCs Dual 16 Bit Independent ADCs Programmable Gain Front End 16 Bit No Missing Codes Primary ADC 13 Bit p p Resolution 20 Hz 20 mV Range 16 Bit p p Resolution 20 Hz 2 56 V Range Memory 8 Kbytes On Chip Flash EE Program Memory 640 Bytes On Chip Flash EE Data Memory Flash EE 100 Year Retention 100 Kcycles Endurance 256 Bytes On Chip Data RAM 8051 Based Core 8051 Compatible Instruction Set 12 58 MHz Max 32 kHz External Crystal On Chip Programmable PLL Three 16 Bit Timer Counters 26 Programmable I O Lines 11 Interrupt Sources Two Priority Levels Power Specified for 3 V and 5 V Operation Normal 3 mA 3 V Core CLK 1 5 MHz Power Down 20 pA 32 kHz Crystal Running On Chip Peripherals On Chip Temperature Sensor 12 Bit Voltage Output DAC Dual Excitation Current Sources Reference Detect Circuit Time Interval Counter TIC UART Serial I O 12 and SPI Serial I O Watchdog Timer WDT Power Supply Monitor PSM APPLICATIONS Intelligent Sensors IEEE1451 2 Compatible Weigh Scales Portable Instrumentation Pressure Transducers 4 20 mA Transmitters GENERAL DESCRIPTION The ADuC816 is a complete smart transducer front end inte grating two high resolution sigma delta ADCs an 8 bit MCU and program data Flash E
3. 100 110 120 10 30 250 70 90 110 130 150 170 190 210 230 250 SF Decimal Figure 23 50 Hz Normal Mode Rejection vs SF GAIN dB 100 110 120 10 30 50 70 290 110 130 150 170 190 210 230 250 SF Decimal Figure 24 60 Hz Normal Mode Rejection vs SF ADC Chopping Both ADCs on the ADuC816 implement a chopping scheme whereby the ADC repeatability reverses its inputs The deci mated digital output words from the Sinc filters therefore have a positive offset and negative offset term included As a result a final summing stage is included in each ADC so that each output word from the filter is summed and averaged with the previous filter output to produce a new valid output result to be written to the ADC data SFRs In this way while the ADC throughput or update rate is as discussed earlier and illustrated in Table VII the full settling time through the ADC or the time to a first conversion result will actually be given by 2 x tapc The chopping scheme incorporated in the ADuC816 ADC results in excellent dc offset and offset drift specifications and is extremely beneficial in applications where drift noise rejection and optimum EMI rejection are important factors 36 Calibration The ADuC816 provides four calibration modes t
4. ss se s1 2 ss sa ss se DATA oun DATA BIT 1 TXD SHIFTCLock LL TI L DATA BIT 6 DATA BIT 7 J _ La Figure 39 UART Serial Port Transmission Mode 0 Reception is initiated when the receive enable bit REN is 1 and the receive interrupt bit RI is 0 When RI is cleared the data is clocked into the RXD line and the clock pulses are output from the TXD line Mode 1 8 Bit UART Variable Baud Rate Mode 1 is selected by clearing SMO and setting SM1 Each data byte LSB first is preceded by a start bit 0 and followed by a stop bit 1 Therefore 10 bits are transmitted on TXD or received on RXD The baud rate is set by the Timer 1 or Timer 2 overflow rate or a combination of the two one for transmission and the other for reception Transmission is initiated by writing to SBUF The write to SBUF signal also loads a 1 stop bit into the ninth bit position of the transmit shift register The data is output bit by bit until the stop bit appears on TXD and the transmit interrupt flag is automatically set as shown in Figure 40 START STOP BIT rxo oo X o2 X os X 04 X os X oe X or SCON LM 4 x SET INTERRUPT i e READY FOR MORE DATA Figure 40 UART Serial Port Transmission Mode 0 Reception is initiated when 1 to 0 transition is detected on RXD Assuming a valid start bit was detected character reception continues The start bit is skipped and t
5. 33 ADuC816 The absolute input voltage range on the auxiliary ADC is restricted to between AGND 30 mV to AVDD 30 mV The slightly negative absolute input voltage limit does allow the possibility of monitoring small signal bipolar signals using the single ended auxiliary ADC front end Programmable Gain Amplifier The output from the buffer on the primary ADC is applied to the input of the on chip programmable gain amplifier PGA The PGA can be programmed through eight different unipolar input ranges and bipolar ranges The PGA gain range is programmed via the range bits in the ADCOCON SFR With the external refer ence select bit set in the ADCOCON SFR and an external 2 5 reference the unipolar ranges are 0 mV to 20 mV 0 mV to 40 mV 0 mV to 80 mV 0 mV 160 mV 0 mV 320 mV 0 mV to 640 mV and 0 V to 1 28 V and 0 to 2 56 V while the bipolar ranges are 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1 28 V and 2 56 V These are the nominal ranges that should appear at the input to the on chip PGA An ADC range matching specification of 0 5 LSB typ across all ranges means that calibration need only be carried out at a single gain range and does not have to be repeated when the PGA gain range is changed The auxiliary ADC does not incorporate a PGA and is configured for a fixed single input range of 0 to Bipolar Unipolar Inputs The analog inputs on the ADuC816 can accept either uni polar or bipola
6. 10 max Vin 0 V DVpp 5 V 35 min 105 max min uA max Vpp DVpp 5 V Internal Pull Down P1 0 P1 1 Ports 2 and 3 10 uA max Vin DVpp 5 V 180 min Vin 2 V DVpp 25V 660 uA max 20 min Vin 450 mV DVpp 25V 75 max Input Capacitance 5 pF typ All Digital Inputs CRYSTAL OSCILLATOR XTAL1 AND XTAL2 Logic Inputs XTALI Only Vint Input Low Voltage 0 8 V max DVpp 5 V 0 4 V max DVpp 3 V Vine Input High Voltage 3 5 V min DVpp 5 V 2 5 V min DVpp 23V XTALI Input Capacitance 18 pF typ XTAL2 Output Capacitance 18 pF typ REV 0 ADuC816 SPECIFICATIONS Parameter ADuC816BS Unit Test Conditions Comments LOGIC OUTPUTS Not Including XTAL2Y Output High Voltage 2 4 V min Vpp 5 V Isource 80 uA 2 4 V min Vpp 3 V IsouRCE 20 Vor Output Low Voltage 0 4 V max 15 8 mA SCLOCK SDATA MOSI 0 4 V max Isng 10 mA P1 0 and P1 1 0 4 Ignx 1 6 mA All Other Outputs max Floating State Leakage Current 10 max Floating State Output Capacitance 5 pF typ POWER SUPPLY MONITOR PSM AVpp Trip Point Selection Range 2 63 V min Four Trip Points Selectable in This Range 4 63 V max Programmed via TPA1 0 in AVpp Power Supply Trip Point Accuracy 3 5 max DVpp Trip Point Selection Range 2 63 V min Four Trip Points Selectable in This Range 4 63 V max Programmed via TPD1 0 in PPMCON DVpp Power Supply Trip
7. 2 SFR as shown in Table XXVI Table XXVI TIMECON SFR Bit Designations RCLK or TCLK CAP2 TR2 MODE 0 0 1 16 Bit Autoreload 0 1 1 16 Bit Capture 1 X 1 Baud Rate X X 0 OFF 16 Bit Autoreload Mode In Autoreload mode there are two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then when Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2L and RCAP2H which are preset by software If EXEN2 1 then Timer 2 still performs the above but with the added feature that 1 to 0 transition at external input T2EX will also trigger the 16 bit reload and set EXF2 The autoreload mode is illustrated in Figure 37 below C T2 0 a a CONTROL 2 1 RELOAD TRANSITION DETECTOR TL2 8 BITS RCAP2L RCAP2H 16 Bit Capture Mode In the Capture mode there are again two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then Timer 2 is a 16 bit timer or counter which upon overflowing sets bit TF2 the Timer 2 overflow bit which can be used to generate an inter rupt If EXEN2 1 then Timer 2 still performs the above but l to 0 transition on external input T2EX causes the current value in the Timer 2 registers TL2 and TH2 to be captured into regis ters RCAP2L and RCAP2H respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be
8. 2 56 V REV 0 27 ADuC816 ADCICON Auxiliary ADC Control Register Used to configure the Auxiliary ADC for channel selection external Ref enable and unipolar or bipolar coding It should be noted that the Auxiliary ADC only operates on a fixed input range of SFR Address D3H Power On Default Value 00H Bit Addressable No XREF1 1 Table VI ADC1CON SFR Designations Bit Name Description 7 Reserved for Future Use 6 XREFI Auxiliary ADC External Reference Bit Set by user to enable the Auxiliary ADC to use the external reference via REFIN REFIN Cleared by user to enable the Auxiliary ADC to use the internal bandgap reference 5 ACHI Auxiliary ADC Channel Selection Bits 4 ACHO Written by the user to select the single ended input pins used to drive the Auxiliary ADC as follows ACHI ACHO Positive Input Negative Input 0 0 AIN3 AGND 0 1 AIN4 AGND 1 0 Temp Sensor AGND Temp Sensor routed to the ADC input 1 1 AIN5 AGND 3 UNII Auxiliary ADC Unipolar Bit Set by user to enable unipolar coding i e zero input will result in 0000 hex output Cleared by user to enable bipolar coding zero input will result in 8000 hex output 2 Reserved for Future Use 1 Reserved for Future Use 0 Reserved Future Use NOTES 1 When the temperature sensor is selected user code must select internal reference via XREFI
9. 200 uA to external Pin 3 P1 2 DAC TEXC1 1 Current Source 2 Enable Bit Set by user to turn on excitation current source 2 200 uA Cleared by user to turn off excitation current source 2 200 uA 0 IIEN Current Source 1 Enable Bit Set by user to turn on excitation current source 1 200 uA Cleared by user to turn off excitation current source 1 200 uA Both current sources can be enabled to the same external pin yielding a 400 uA current source ADCOH ADCOM Primary ADC Conversion Result Registers These two 8 bit registers hold the 16 bit conversion result from the Primary ADC SFR Address ADCOH High Data Byte DBH ADCOM Middle Data Byte DAH Power On Default Value 00H Both Registers Bit Addressable No Both Registers ADCIH ADCIL Auxiliary ADC Conversion Result Registers These two 8 bit registers hold the 16 bit conversion result from the Auxiliary ADC SFR Address ADCIH High Data Byte DDH ADCIL Low Data Byte DCH Power On Default Value 00H Both Registers Bit Addressable No Both Registers REV 0 29 ADuC816 OFOH OFOM Primary ADC Offset Calibration Registers These two 8 bit registers hold the 16 bit offset calibration coefficient for the Primary ADC These registers are configured at power on with a factory default value of 8000Hex However these bytes will be automatically overwritten if an internal or system zero scale calibration is initiated by the user via MD2 0 bits in the ADCMODE regis
10. 8051 SPECIAL COMPATIBLE FUNCTION CORE REGISTER AREA 256 BYTES RAM Figure 16 Programming Model PLL OVERVIEW OF MCU RELATED SFRS Accumulator SFR ACC is the Accumulator register and is used for math operations including addition subtraction integer multiplication and division and Boolean bit manipulations The mnemonics for accumulator specific instructions refer to the Accumulator as A B SFR The B register is used with the ACC for multiplication and divi sion operations For other instructions it can be treated as a general purpose scratchpad register Stack Pointer SFR The SP register is the stack pointer and is used to hold an internal RAM address that is called the top of the stack The SP register is incremented before data is stored during PUSH and CALL executions While the Stack may reside anywhere in on chip the SP register is initialized to 07H after a reset This causes the stack to begin at location 08H Data Pointer The Data Pointer is made up of three 8 bit registers named DPP page byte DPH high byte and DPL low byte These are used to provide memory addresses for internal and external code access and external data access It may be manipulated as a 16 bit register DPTR DPH DPL although INC DPTR instructions will automatically carry over to DPP or as three independent 8 bit registers DPP DPH DPL REV 0 Program Status Word SFR The PSW register is the Prog
11. C typ Thermal Impedance 074 90 C W typ REV 0 ADuC816 Parameter ADuC816BS Unit Test Conditions Comments TRANSDUCER BURNOUT CURRENT SOURCES AIN Current 100 AIN is the Selected Positive Input to the Primary ADC AIN Current 100 AIN is the Selected Negative Input the Auxiliary ADC Initial Tolerance 25 Drift t10 typ Drift 0 03 typ EXCITATION CURRENT SOURCES Output Current 200 typ Available from Each Current Source Initial Tolerance 25 t10 typ Drift 200 ppm C typ Initial Current Matching 25 1 Matching Between Both Current Sources Drift Matching 20 ppm C typ Line Regulation AVpp 1 typ AVpp 5 5 Load Regulation 0 1 typ Output Compliance AVpp 0 6 V max AGND min LOGIC INPUTS All Inputs Except SCLOCK RESET and XTALI Vint Input Low Voltage 0 8 V max DVpp 5 V 0 4 V max 3 V Vm Input High Voltage 2 0 V min SCLOCK and RESET Only Schmitt Triggered Inputs 1 3 3 V min V max DVpp 5 V 0 95 2 5 V min V max DVpp 3 V Ve 0 8 1 4 V min V max DVpp 5 V 0 4 1 1 V min V max 3 V Vr 0 3 0 85 min V max DVpp 5 V 0 3 0 85 V min V max DVpp 3 V Input Currents Port 0 P1 2 P1 7 EA __ 10 uA max Vin 0 V or SCLOCK SDATA MOSI MISO SS 10 min 40 max min uA max 0 V DVpp 5 V Internal Pull Up 10 uA max Vin DVpp 5V RESET
12. ECON SFR Address B9H Function Controls access to 640 Bytes Flash EE Data Space Default 00H EADRL SFR Address C6H Function Holds the Flash EE Data Page Address 640 Bytes gt 160 Page Addresses Default 00H EDATA 1 4 SFR Address BFH respectively Function Holds Flash EE Data memory page write or page read data bytes Default EDATAI 2 00H EDATA3 4 gt 00H A block diagram of the SFR interface to the Flash EE Data Memory array is shown in Figure 30 REV 0 FUNCTION HOLDS THE 8 BIT PAGE ADDRESS POINTER FUNCTION HOLDS THE 4 BYTE PAGE DATA BYTE 1 BYTE 2 BYTE3 4 BYTE 1 BYTE 2 3 BYTE 4 ECON COMMAND INTERPRETER LOGIC FUNCTION RECEIVES COMMAND DATA Figure 30 Flash EE Data Memory Control and Configuration ECON Flash EE Memory Control SFR This SFR acts as a command interpreter and may be written with one of five command modes to enable various read program and erase cycles as detailed in Table XIII FUNCTION INTERPRETS THE FLASH COMMAND WORD Table XIII ECON Flash EE Memory Control Register Command Modes Command Byte Command Mode 01H READ COMMAND Results in four bytes being read into EDATA1 4 from memory page address contained in EADRL 02H PROGRAM COMMAND Results in four bytes EDATA1 4 being written to memory page address in EADRL This write command assumes the designated write
13. RESERVED RESERVED RESERVED RESERVED AFH 0 AEH 0O0jADH O ACH 0 ABH o aan OO ASH o sn zoo AH 2 TIMECON HTHSEC SEC MIN HOUR INTVAL BITS NOT USED AGH ASH A ASHE ACH AIH A2H ASH AGH SCON SBUF I2CDAT I2CDAT SMO RBS RI BITS NOT USED NOT USED NOT USED NOT USED 0 9EH o ocH 0 99H P1 T2EX T2 BITS smells sigs rt ese allots Sean a een NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED TCON TMOD TLO TL1 THO TH1 TF1 TR1 TFO TRO IE1 ITi IEO ITO BITS gt 0 SCH 0 18 _ 0 8AH 0 89 _ 0 68 550 88H 89H sP DPL DPH DPP PCON BITS RESERVED RESERVED 87H 1 86H 85H 1 82H 1 80H FFH 81H 82H _ 83H 84H 87H CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER UP TO FACTORY CALIBRATED VALUES SFR MAP KEY THESE BITS ARE CONTAINED IN THIS BYTE BIT MNEMONIC CE0 BIT BIT ADDRESS gt js9H_ DEFAULT BIT VALUE SFR NOTE 88H MNEMONIC 7 DEFAULT VALUE SFR ADDRESS SFRs WHOSE ADDRESSES END IN O
14. and into its own Mode 3 or can still be used by the serial interface as a Baud Rate Generator In fact it can be used in any application not requiring an interrupt from timer 1 itself TLO 8 BITS 1 P3 4 T0 TRO GATE 1 P3 2 INTO gt INTERRUPT CORE THO CLK 12 8 BITS TRI CONTROL THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 36 Timer Counter 0 Mode 3 REV 0 ADuC816 T2CON Timer Counter 2 Control Register SFR Address C8H Power On Default Value 00H Bit Addressable Yes TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 Table XXV T2CON SFR Bit Designations Bit Name Description 7 TF2 Timer 2 Overflow Flag Set by hardware on a timer 2 overflow TF2 will not be set when either RCLK or TCLK 1 Cleared by user software 6 EXF2 Timer 2 External Flag Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 Cleared by user user software 5 RCLK Receive Clock Enable Bit Set by user to enable the serial port to use timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3 Cleared by user to enable timer 1 overflow to be used for the receive clock 4 TCLK Transmit Clock Enable Bit Set by user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3 Cleared by user to enable timer 1 overflow to be used for the transmit clock 3 EXEN
15. must be written to the respective port bit As a digital input these pins must be driven high or low externally These port pins also have the following analog functionality Primary ADC Channel Positive Analog Input Primary ADC Channel Negative Analog Input Auxiliary ADC Input or muxed Primary ADC Channel Positive Analog Input Port 1 7 This pin has no digital output driver it can function as a digital input for which 0 must be written to the port bit As a digital input P1 7 must be driven high or low externally This pin can provide an analog input AIN4 to the auxiliary ADC or muxed Primary ADC Channel Negative Analog Input The voltage output from the DAC can also be configured to appear at this pin Slave Select Input for the SPI Interface A weak pull up is present on this pin Master Input Slave Output for the SPI Interface There is a weak pull up on this input pin Reset Input A high level on this pin for 24 core clock cycles while the oscillator is running resets the device There is a weak pull down and a Schmitt trigger input stage on this pin P3 0 P3 3 are bidirectional port pins with internal pull up resistors Port 3 pins that have 13 written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs Port 3 pins being pulled externally low will source current because of the internal pull up resistors When driving a 0 to 1 output transition a strong pull up is ac
16. running with all 16 bits Mode 1 is shown in Figure 34 CORE P3 4 TO TLO 8 BITS 8 BITS INTERRUPT TRO GATE P3 2 INTO THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 34 Timer Counter 0 Mode 1 54 Mode 2 8 Bit Timer Counter with Autoreload Mode 2 configures the timer register as an 8 bit counter TLO with automatic reload as shown in Figure 35 Overflow from TLO not only sets but also reloads TLO with the contents of THO which is preset by software The reload leaves THO unchanged CORE CLK P3 4 TO TRO INTERRUPT RELOAD GATE THO P3 2 INTO 8 BITS THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 35 Timer Counter 0 Mode 2 Mode 3 Two 8 Bit Timer Counters Mode 3 has different effects on timer 0 and timer 1 Timer 1 in Mode 3 simply holds its count The effect is the same as setting TRI 0 Timer 0 in Mode 3 establishes TLO and THO as two separate counters This configuration is shown in Figure 36 TLO uses the timer 0 control bits C T Gate TRO INTO and is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls the timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When timer 0 is in Mode 3 timer 1 can be turned on and off by switching it out of
17. 0 390 9 91 0 557 14 15 0 537 13 65 0 012 0 30 iS 13 T 0 006 0 15 0 008 0 20 X 114 0 006 0 15 0 0256 0 014 0 35 0 082 2 09 0 65 0 010 0 25 0 078 1 97 c 68 REV 0 C00436 2 5 2 01 rev 0 PRINTED IN U S A
18. 000 000 midscale voltage resulting in a code of 100 000 and a full scale input voltage resulting in a code of 111 111 When an ADC is configured for bipolar operation the coding is offset binary with a negative full scale voltage resulting a code of 000 000 a zero differential voltage resulting in a code of 100 000 and a positive full scale voltage resulting in a code of 111 111 34 Burnout Currents The primary ADC on the ADuC816 contains two 100 nA con stant current generators one sourcing current from AVDD to AIN and one sinking from AIN to AGND The currents are switched to the selected analog input pair Both currents are either on or off depending on the Burnout Current Enable BO bit in the ICON SFR see Table These currents can be used to verify that an external transducer is still operational before attempting to take measurements on that channel Once the burnout currents are turned on they will flow in the exter nal transducer circuit and a measurement of the input voltage on the analog input channel can be taken If the resultant volt age measured is full scale this indicates that the transducer has gone open circuit If the voltage measured is 0 V it indicates that the transducer has short circuited For normal operation these burnout currents are turned off by writing a 0 to the BO bit in the ICON SER The current sources work over the normal abso lute input voltage range sp
19. 12 It DAC should be noted that in 12 bit mode the DAC voltage output will be updated as soon as the DACL data SFR has been writ ten therefore the DAC data registers should be updated as DACH first followed by DACL The ADuC816 incorporates a 12 bit voltage output DAC on chip It has a rail to rail voltage output buffer capable of DACCON DAC Control Register SFR Address FDH Power On Default Value 00H Bit Addressable No DACPIN DACS DACRN DACCLR DACEN Table XIV DACCON SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 Reserved for Future Use 5 Reserved for Future Use 4 DACPIN DAC Output Pin Select Set by the user to direct the DAC output to Pin 12 P1 7 AIN4 DAC Cleared by user to direct the DAC output to Pin 3 P1 2 DAC IEXCI 3 DAC8 DAC 8 bit Mode Bit Set by user to enable 8 bit DAC operation In this mode the 8 bits in DACL SFR are routed to the 8 MSBs of the DAC and the 4 LSBs of the DAC are set to zero Cleared by user to operate the DAC in its normal 12 bit mode of operation 2 DACRN DAC Output Range Bit Set by user to configure DAC range of 0 AVpp Cleared by user to configure DAC range of 0 2 5 V 1 DACCLR DAC Clear Bit Set to 1 by user to enable normal DAC operation Cleared to 0 by user to reset DAC data registers DACI H to zero 0 DACEN DAC Enable Bit Set to 1 by user to enable normal DAC operation Cleared to 0 b
20. 16 16 255 5 35 14 15 16 16 16 16 16 16 1 resolution at these range update rate settings is limited only by the number of bits available from the ADC Effective resolution at these range update rate settings is greater than 16 bits as indicated by the rms noise table shown in Table IX Table XI Auxiliary ADC Typical Output RMS Noise vs Update Rate Output RMS Noise in Peak to Peak Resolution vs Update Rate Peak to Peak Resolution in Bits SF Data Update Input Range SF Data Update Input Range Word Rate Hz 2 5V Word Rate Hz 2 5V 13 105 3 10 75 13 105 3 16 69 19 79 2 00 69 19 79 16 255 5 35 1 15 255 5 35 16 NOTE NOTES ADC converting in bipolar mode Analog Input Channels The primary ADC has four associated analog input pins labelled AINI to AIN4 which can be configured as two fully differential input channels Channel selection bits in the ADCOCON SFR detailed in Table V allow three combinations of differential pair selection as well as an additional shorted input option AIN2 AIN2 The auxiliary ADC has three external input pins labelled AIN3 to AIN5 as well as an internal connection to the internal on chip temperature sensor All inputs to the auxiliary ADC are single ended inputs referenced to the AGND on the part Channel selection bits in the ADCICON SFR detailed previously in Table VI allow selection of one of four inputs Two input multiple
21. 29 tcong 50 ns 5 tovwH Data Setup before WR mE 406 Itcogg 150 ns 5 twHOX Data and Address Hold after WR 29 tcong 50 ns 5 ALE 0 twain PSEN 0 tiw twi wh gt WR tavwe t tavwx p gt tavwH gt mo Xe DXX Figure 5 External Data Memory Write Cycle REV 0 11 ADuC816 12 58 MHz Core_Clk Variable Core_Clk Parameter Min Typ Max Min Typ Max Unit Figure UART TIMING Shift Register Mode txrxr Serial Port Clock Cycle Time 0 95 2tconE us 6 tovxH Output Data Setup to Clock 662 10tcorg 133 ns 6 tpvxH Input Data Setup to Clock 292 2tcong 133 ns 6 txHDX Input Data Hold after Clock 0 0 ns txHox Output Data Hold after Clock 42 21 117 ns 6 ALE 0 TXD OUTPUT CLOCK RXD OUTPUT DATA RXD INPUT DATA SY NZ ENS AUN LN eX Figure 6 UART Timing in Shift Register Mode 12 REV 0 ADuC816 Parameter Min Max Unit Figure I C COMPATIBLE INTERFACE TIMING tL SCLOCK Low Pulsewidth 4 7 us 7 ty SCLOCK High Pulsewidth 4 0 us 7 tsHD Start Condition Hold Time 0 6 us 7 tpsu Data Setup Time 100 us 7 tDHD Data Hold Time 0 9 us 7 trsu Setup Time for Repeated Start 0 6 7 tpsu Stop Condition Setup Time 0 6 us 7 BUF Bus Free Time between a STOP 1 3 us 7 Condition and a START Condition tg Rise Time of Both SCLOCK and SDATA 300 ns 7 tr Fall Time of Both SCLOCK and SDATA 300 ns 7 t
22. An Application Note uC004 detailing this serial download protocol is available from www analog com microconverter DeBug In Circuit Debugger The Debugger is a Windows application that allows the user to debug code execution on silicon using the MicroConverter UART serial port The debugger provides access to all on chip periph erals during a typical debug session as well as single step and break point code execution control ADSIM Windows Simulator The Simulator is a Windows application that fully simulates all the MicroConverter functionality including ADC and DAC peripherals The simulator provides an easy to use intuitive inter face to the MicroConverter functionality and integrates many standard debug features including multiple breakpoints single stepping and code execution trace capability This tool can be used both as a tutorial guide to the part as well as an efficient way to prove code functionality before moving to a hardware platform The QuickStart development tool suite software is freely available at the Analog Devices MicroConverter Website www analog com microconverter Figure 54 Typical Debug Session 67 ADuC816 OUTLINE DIMENSIONS Dimensions shown in inches and mm 52 Lead MQFP S 52 0 557 14 15 2 094 2 39 0 537 13 65 0 081 5 19 0 398 10 11 0 037 0 95 0 390 9 91 0 026 0 65 SEATING PLANE TOP VIEW PINS DOWN 0 398 10 11
23. Mode Timing CPHA 1 REV 0 ADuC816 Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING CPHA 0 tss SS to SCLOCK Edge 0 ns 11 ts SCLOCK Low Pulsewidth 330 ns 11 SCLOCK High Pulsewidth 330 ns 11 tpav Data Output Valid after SCLOCK Edge 50 ns 11 tpsu Data Input Setup Time before SCLOCK Edge 100 ns 11 tpHD Data Input Hold Time after SCLOCK Edge 100 ns 11 Data Output Fall Time 10 25 ns 11 tpg Data Output Rise Time 10 25 ns 11 tsp SCLOCK Rise Time 10 25 ns 11 tsp SCLOCK Fall Time 10 25 ns 11 tss SS to SCLOCK Edge 50 ns 11 tposs Data Output Valid after SS Edge 20 ns 11 tsEs SS High after SCLOCK Edge 0 ns 11 SCLOCK CPOL 0 t SR SF SCLOCK CPOL 1 MISO MOSI TIP tosu tou Figure 11 SPI Slave Mode Timing CPHA 0 REV 0 17 ADuC816 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION T4 25 C unless otherwise noted 52 Lead MQFP AVpp to AGND 0 3 V to 7 V AVppto DGND 0 3 V to 7 V DVppto AGND 0 3 V to 7 V DVppto DGND 0 3 V to 7 V AGND to DGND 0 3 V to 0 3 V AVpp to DVpp CA 2 V to 5 V INDENTIFIER Analog Input Voltage to AGND 0 3 V to AVpp 0 3 V Reference Input Voltage to AGND 0 3 V to AVpp 0 3 V ADuC816 AIN REFIN Current Indefinite 30 mA TOP VIEW Dig
24. OUTPUT SIGMA DELTA ADC IS FROM THE FILTER IS CHOPPED TO REMOVE DRIFT ERROR SUMMED AND AVERAGED WITH ITS PREDECESSOR TO NULL ADC CHANNEL OFFSET ERRORS SEE PAGE 36 SEE PAGE 35 DIGTAL OUTPUT RESULT WRITTEN TO ADCOH M OUTPUT SERS SCALING OUTPUT AVERAGE N OUTPUT SCALING THE OUPUT WORD FROM THE DIGITAL FILTER IS SCALED THE CALIBRATION COEFFICIENTS BEFORE BEING PROVIDED AS THE CONVERSION RESULT SEE PAGE 37 PROGRAMMABLE DIGITAL FILTER THE SINC3 FILTER REMOVES QUANTIZATION NOISE INTRODUCED BY THE MODULATOR THE UPDATE RATE AND BANDWIDTH OF THIS FILTER ARE PROGRAMMABLE VIA THE SF SFR SEE PAGE 35 Figure 18 Primary ADC Block Diagram 31 ADuC816 Auxiliary ADC assuming an external 2 5 V reference The single ended inputs The Auxiliary ADC is intended to convert supplementary inputs can be driven from AIN3 AIN5 pins or directly from such as those from a cold junction diode or thermistor This ADC the on chip temperature sensor voltage A block diagram of the is not buffered and has a fixed input range of 0 V to 2 5 V Auxiliary ADC is shown in Figure 19 DIFFERENTIAL REFERENCE THE EXTERNAL REFERENCE INPUT TO THE ADuC816 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION THE EXTERNAL REFER ENCE VOLTAGE IS SELECTED VIA THE XREF1 BIT IN ADC1CON REFERENCE DETECT CIRCUITRY TESTS FOR OPEN OR SHORTED REFERENCES INPUTS SIGMA DELTA ADC THE SIGMA DELTA OUTPUT AVERAG
25. Offset Error 2 LSB typ Offset Error Drift 1 typ Full Scale Error 2 5 LSB typ Gain Error Drift 0 5 ppm C typ Power Supply Rejection PSR 80 dBs typ 1 V 20 Hz Update Rate Normal Mode 50 Hz 60 Hz Rejection On AIN 60 dBs typ 50 Hz 60 Hz 1 Hz On REFIN 60 dBs typ 50 Hz 60 Hz 1 Hz 20 Hz Update Rate DAC PERFORMANCE DC Specifications Resolution 12 Bits Relative Accuracy T LSB typ Differential Nonlinearity 1 LSB max Guaranteed 12 Bit Monotonic Offset Error 50 mV max Gain Error AVpp Range typ Range AC Specifications 6 Voltage Output Settling Time 15 us typ Settling Time to 1 LSB of Final Value Digital to Analog Glitch Energy 10 nVs typ 1 LSB Change at Major Carry REV 0 ADuC816 SPECIFICATIONS Parameter ADuC816BS Unit Test Conditions Comments INTERNAL REFERENCE ADC Reference Reference Voltage 1 25 1 min max Initial Tolerance 25 C Vpp 5 V Power Supply Rejection 45 dBs typ Reference Tempco 100 ppm C typ DAC Reference Reference Voltage 2 5 t 1 V min max Initial Tolerance 25 C Vpp 5 V Power Supply Rejection 50 dBs typ Reference Tempco 100 ppm C typ ANALOG INPUTS REFERENCE INPUTS Primary ADC Differential Input Voltage Ranges External Reference Voltage 2 5 V RN2 RN1 RNO of ADCOCON Set to Bipolar Mode ADCOCON 3 0 20 mV 000 Unipolar Mode 0 mV to 20 mV 40 mV 001 Unipolar Mode 0 mV to 40 mV 80 mV 010 Unipolar Mode 0 mV to
26. The ISPI flag will be set automatically and an interrupt will occur if enabled The value in the shift register will be latched into SPIDAT SPI Interface Slave Mode ED In slave mode the SCLOCK is an input The SS pin must also be driven low externally during the byte communication Transmission is also initiated by a write to SPIDAT In slave mode a data bit is transmitted via MISO and a data bit is received via MOSI through each input SCLOCK period After eight clocks the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register The ISPI flag will be set automatically and an interrupt will occur if enabled The value in the shift register will be latched into SPIDAT only when the transmission reception of a byte has been completed The end of transmission occurs after the eighth clock has been received if CPHA 1 or when SS returns high if CPHA 0 49 ADuC816 PC COMPATIBLE INTERFACE The ADuC816 supports a 2 wire serial interface mode which is compatible The C compatible interface shares its pins with the on chip SPI interface and therefore the user can only enable one or the other interface at any given time see SPE in SDATA Pin 27 SCLOCK Pin 26 SPICON previously An Application Note describing the operation of this interface as implemented is available from the MicroConverter Website at www analog com microconverter This interface can be configure
27. Written by User to Select UART Serial Port Interrupt Priority 1 High 0 Low 3 PT1 Written by User to Select Timer 1 Interrupt Priority 1 High 0 Low 2 PXI Written by User to Select External Interrupt 1 Priority 1 High 0 Low 1 PTO Written by User to Select Timer 0 Interrupt Priority 1 High 0 Low 0 Written by User to Select External Interrupt 0 Priority 1 High 0 Low 60 REV 0 ADuC816 IEIP2 Secondary Interrupt Enable and Priority Register SFR Address A9H Power On Default Value Addressable PTI PPSM PSI ETI EPSM ESI Table XXXII IEIP2 SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 PTI Written by User to Select TIC Interrupt Priority 1 High 0 Low 5 PPSM Written by User to Select Power Supply Monitor Interrupt Priority 1 High 0 Low 4 PSI Written by User to Select Serial Port Interrupt Priority 1 High 0 Low 3 Reserved This Bit Must Be 0 2 ETI Written by User to Enable 1 or Disable 0 TIC Interrupt 1 EPSM Written by User to Enable 1 or Disable 0 Power Supply Monitor Interrupt 0 ESI Written by User to Enable 1 or Disable 0 SPI PC Serial Port Interrupt Interrupt Priority Table XXXIV Interrupt Vector Addresses The Interrupt Enable registers are writte
28. a watchdog 1 6 External Interrupt 1 timeout occurs The watchdog will only produce an interrupt if the watch 1 7 Timer Counter 1 Interrupt dog timeout is greater than zero 12 ISPI 8 2 Interrupt RI TI 9 Serial Interrupt TF2 EXF2 10 Timer Counter 2 Interrupt TII 11 Lowest Time Interval Counter Interrupt Interrupt Vectors When an interrupt occurs the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter The interrupt vector addresses are shown in Table XXXIV REV 0 61 ADuC816 ADuC816 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design consider ations that must be addressed when integrating the ADuC816 into any hardware system Clock Oscillator As described earlier the core clock frequency for the ADuC816 is generated from an on chip PLL that locks onto a multiple 384 times of 32 768 kHz The latter is generated from an inter nal clock oscillator To use the internal clock oscillator connect 32 768 kHz parallel resonant crystal between XTALI and XTAL2 pins 32 and 33 as shown in Figure 42 As shown in the typical external crystal connection diagram in Figure 42 two internal 12 pF capacitors are provided on chip These are connected internally directly to the XTAL1 and XTAL2Z pins and the total input capacitances at both pins is detailed in the specification section of this dat
29. at factory final test see notes above Bit Addressable No Both Registers GNIH GNIL Auxiliary ADC Gain Calibration Registers These two 8 bit registers hold the 16 bit gain calibration coefficient for the Auxiliary ADC These registers are configured at power on with a factory calculated internal full scale calibration coefficient Every device will have an individual coefficient However these bytes will be automatically overwritten if an internal or system full scale calibration is initiated by the user via 2 0 bits in the ADCMODE register SFR Address GNIH Auxiliary ADC Gain Coefficient High Byte EDH GNIL Auxiliary ADC Gain Coefficient Low Byte ECH Power On Default Value Configured at factory final test see notes above Bit Addressable No Both Registers NOTE These registers can be overwritten by user software only if Mode bits MD0 2 ADCMODE SFR are zero 30 REV 0 PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION OVERVIEW The ADuC816 incorporates two independent sigma delta ADCs Primary and Auxiliary with on chip digital filtering intended for the measurement of wide dynamic range low frequency signals such as those in weigh scale strain gauge pressure trans ducer or temperature measurement applications Primary ADC This ADC is intended to convert the primary sensor input The input is buffered and can be programmed for one of 8 input ranges from 20 mV to 2 56 V being driven from one of three differ ADuC8
30. be accessed through indirect addressing and the SFR area is accessed through direct addressing Also as shown in Figure 13 the additional 640 Bytes of Flash EE Data Memory are available to the user and can be accessed indirectly via a group of control registers mapped into the Special Function Register SFR area Access to the Flash EE Data Memory is discussed in detail later as part of the Flash EE Memory section in this data sheet The external data memory area can be expanded up to 16 MBytes This is an enhancement of the 64 KByte external data memory space available on standard 8051 compatible cores The external data memory is discussed in more detail in the ADuC816 Hardware Design Considerations section 22 DATA MEMORY SPACE READ WRITE 9FH FFFFFFH PAGE 159 640 BYTES FLASH EE DATA MEMORY ACCESSED INDIRECTLY VIA SFR CONTROL REGISTERS PAGE 0 00H EXTERNAL DATA MEMORY INTERNAL DATA MEMORY AEN SPACE ADDRESS FFH SPECIAL FFH SPACE ACCESSIBLE FUNCTION UPPEH BY REGISTERS 128 INDIRECT ACCESSIBLE ADDRESSING BY DIRECT ADDRESSING 80H 80H 7FH ACCESSIBLE LOWER 128 AND INDIRECT ADDRESSING 00H 000000H Figure 14 Data Memory Map The lower 128 bytes of internal data memory are mapped as shown in Figure 15 The lowest 32 bytes are grouped into four banks of eight registers addressed as RO through R7 The next 16 bytes 128 bits locations 20Hex through 2FHex above the regis
31. byte and low byte SFR Address 8Dhex 8Bhex respectively REV 0 b3 ADuC816 TIMER COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for timer counters 0 and 1 Unless otherwise noted it should be assumed that these modes of operation are the same for timer 0 as for timer 1 Mode 0 13 Bit Timer Counter Mode 0 configures an 8 bit timer counter with a divide by 32 prescaler Figure 33 shows mode 0 operation TLO 5 BITS CONTROL P3 4 TO INTERRUPT TRO GATE P3 2 INTO THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 33 Timer Counter 0 Mode 0 In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the timer overflow flag The overflow flag can then be used to request an interrupt The counted input is enabled to the timer when TRO 1 and either Gate 0 or INTO 1 Setting Gate 1 allows the timer to be controlled by external input INTO to facilitate pulsewidth measurements TRO is a control bit in the special function regis ter TCON Gate is in TMOD The 13 bit register consists of all eight bits of THO and the lower five bits of TLO The upper three bits of TLO are indeterminate and should be ignored Setting the run flag does not clear the registers Mode 1 16 Bit Timer Counter Mode 1 is the same as Mode 0 except that the timer register is
32. input also drives the reference voltage for the part the effect of the low frequency noise in the excita tion source will be removed as the application is ratiometric If the ADuC816 is not used in a ratiometric application a low noise reference should be used Recommended reference voltage sources for the ADuC816 include the AD780 REF43 and REF192 It should also be noted that the reference inputs provide a high impedance dynamic load Because the input impedance of each reference input is dynamic resistor capacitor combinations on these inputs can cause dc gain errors depending on the output impedance of the source that is driving the reference inputs Reference voltage sources like those recommended above e g AD780 will typically have low output impedances and therefore decoupling capacitors on the REFIN input would be recom REV 0 ADuC816 mended Deriving the reference input voltage across an external resistor as shown in Figure 52 will mean that the reference input sees a significant external source impedance External decoupling on the REFIN and REFIN pins would not be recommended in this type of circuit configuration Reference Detect The ADuC816 includes on chip circuitry to detect if the part has a valid reference for conversions or calibrations If the voltage between the external REFIN and REFIN pins goes below 0 3 V or either the REFIN or REFIN inputs is open circuit the ADuC816 detects
33. on the ADuC816 ADCSTAT ADC Status Register This SFR reflects the status of both ADCs including data ready calibration and various ADC related error and warning condi tions including reference detect and conversion overflow underflow flags SFR Address D8H Power On Default Value 00H Bit Addressable Yes RDYO RDYI1 CAL NOXREF ERRO ERRI1 Table ADCSTAT SFR Bit Designations Bit Name Description 7 RDYO Ready Bit for Primary ADC Set by hardware on completion of ADC conversion or calibration cycle Cleared directly by the user or indirectly by write to the mode bits to start another Primary ADC conversion or calibration The Primary ADC is inhibited from writing further results to its data or calibration registers until the RDYO bit is cleared 6 RDY1 Ready Bit for Auxiliary ADC Same definition as RDYO referred to the Auxiliary ADC 5 CAL Calibration Status Bit Set by hardware on completion of calibration Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration 4 NOXREF No External Reference Bit only active if Primary or Auxiliary ADC is active Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold When Set conversion results are clamped to all ones if using ext reference Cleared to indicate valid 3 ERRO Primary ADC Error Bit Set by hardware to indicate that the result
34. page has been pre erased 03H RESERVED FOR INTERNAL USE 03H should not be written to the ECON SFR 04H VERIFY COMMAND Allows the user to verify if data in EDATAI 4 is contained in page address designated by EADRL subsequent read of the ECON SFR will result in a zero being read if the verification is valid a nonzero value will be read to indicate an invalid verification 05H ERASE COMMAND Results in an erase of the 4 byte page designated in EADRL 06H ERASE ALL COMMAND Results in erase of the full Flash EE Data memory 160 page 640 bytes array RESERVED COMMANDS Commands reserved for future use 07H to FFH 39 ADuC816 Flash EE Memory Timing The typical program erase times for the Flash EE Data Memory are Erase Full Array 640 Bytes 2 ms Erase Single Page 4 Bytes 2 ms Program Page 4 Bytes 250 us Read Page 4 Bytes Within Single Instruction Cycle Using the Flash EE Memory Interface As with all Flash EE memory architectures the array can be pro grammed in system at a byte level although it must be erased first the erasure being performed in page blocks 4 byte pages in this case A typical access to the Flash EE Data array will involve setting up the page address to be accessed in the EADRL SFR config uring the EDATAI 4 with data to be programmed to the array the EDATA SFRs will not be written for read accesses and finally writing the ECON command word
35. style emulators where users must replace the chip on their board with a header device that the emulator pod plugs into The only hardware concern is then one of determining if adequate space is available for the emulator pod to fit into the system enclosure 66 Typical System Configuration A typical ADuC816 configuration is shown in Figure 52 It sum marizes some of the hardware considerations discussed in the previous paragraphs Figure 52 also includes connections for a typical analog measure ment application of the ADuC816 namely an interface to an RTD Resistive Temperature Device The arrangement shown is commonly referred to as a 4 wire RTD configuration Here the on chip excitation current sources are enabled to excite the sensor external differential reference voltage is generated by the current sourced through resistor R1 This current also flows directly through the RTD which generates a differential voltage directly proportional to temperature This differential voltage is routed directly to the positive and negative inputs of the primary ADC AINI AIN2 respectively A second external resistor R2 is used to ensure that absolute analog input voltage on the negative input to the primary ADC stays within that specified for the ADuC8106 i e AGND 100 mV REV 0 ADuC816 It should also be noted that variations in the excitation current do not affect the measurement system as the input voltage from th
36. which initiates one of the six modes shown in Table XIII It should be noted that a given mode of operation is initiated as soon as the command word is written to the ECON SFR The core microcontroller operation on the ADuC816 is idled until the requested Program Read or Erase mode is completed In practice this means that even though the Flash EE memory mode of operation is typically initiated with a two machine cycle instruction to write to the ECON SFR the next instruc tion will not be executed until the Flash EE operation is complete 250 us or 2 ms later This means that the core will not respond to Interrupt requests until the Flash EE operation is complete although the core peripheral functions like Counter Timers will continue to count and time as configured throughout this period 40 Although the 640 byte User Flash EE array is shipped from the factory pre erased 1 Byte locations set to it is nonethe less good programming practice to include an erase all routine as part of any configuration setup code running on the ADuC816 An ERASE ALL command consists of writing 06H to the ECON SFR which initiates an erase of all 640 byte locations in the Flash EE array This command coded in 8051 assembly would appear as MOV ECON 06H Erase all Command 2ms Duration Program a Byte In general terms a byte in the Flash EE array can only be pro grammed if it has previousl
37. written to the Primary ADC data registers has been clamped to all zeros or all ones After a calibration this bit also flags error conditions that caused the calibration registers not to be written Cleared by a write to the mode bits to initiate a conversion or calibration 2 1 Auxiliary ADC Error Same definition as ERRO referred to the Auxiliary ADC Reserved for Future Use Reserved Future Use or 1 D REV 0 25 ADuC816 ADCMODE ADC Mode Register Used to control the operational mode of both ADCs SFR Address DIH Power On Default Value 00H Bit Addressable No ADCOEN ADCIEN MD2 MD1 Table ADCMODE SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 Reserved for Future Use 5 ADCOEN Primary ADC Enable Set by the user to enable the Primary ADC and place it in the mode selected in MD2 MDO below Cleared by the user to place the Primary ADC in power down mode 4 ADCIEN Auxiliary ADC Enable Set by the user to enable the Auxiliary ADC and place it in the mode selected in MD2 MD0 below Cleared by the user to place the Auxiliary ADC in power down mode 3 Reserved for Future Use 2 MD2 Primary and Auxiliary ADC Mode bits 1 MDI These bits select the operational mode of the enabled ADC as follows 0 MD2 1 0 0 0 Power Down Mode Power On Default 0 0 1 Idle Mode In Idle Mode the ADC filte
38. 16 the analog inputs if required On chip burnout currents can also be turned on These currents can be used to check that a transducer on the selected channel is still operational before attempting to take measurements The ADC employs a sigma delta conversion technique to realize up to 16 bits of no missing codes performance The sigma delta modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information A Sinc3 programmable low pass filter is then employed to decimate the modulator output data stream to give a valid data conversion result at programmable output rates from 5 35 Hz 186 77 ms ential input channel options AIN1 2 AIN3 4 or AIN3 2 The input channel is internally buffered allowing the part to handle significant source impedances on the analog input allowing R C filtering for noise rejection or RFI reduction to be placed on BURNOUT CURRENTS TWO 100nA BURNOUT CURRENTS ALLOW THE USER TO EASILY DETECT IF A TRANSDUCER HAS BURNED OUT OR GONE OPEN CIRCUIT SEE PAGE 29 AND 34 AIN1 AIN2 AIN3 ANALOG INPUT CHOPPING THE INPUTS ARE ALTERNATELY REVERSED THROUGH THE CONVERSION CYCLE CHOPPING YIELDS EXCELLENT ADC OFFSET AND OFFSET DRIFT PERFORMANCE SEE PAGE 36 VJ AVpp PROGRAMMABLE GAIN AMPLIFIER THE PROGRAMMABLE GAIN AMPLIFIER ALLOWS EIGHT UNIPOLAR AND EIGHT BIPOLAR INPUT RANGES FROM 20 2 56V EXT
39. 2 Timer 2 External Enable Flag Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port Cleared by user for Timer 2 to ignore events at T2EX 2 TR2 Timer 2 Start Stop Control Bit Set by user to start timer 2 Cleared by user to stop timer 2 1 CNT2 Timer 2 Timer or Counter Function Select Bit Set by user to select counter function input from external T2 pin Cleared by user to select timer function input from on chip core clock 0 CAP2 Timer 2 Capture Reload Select Bit Set by user to enable captures on negative transitions at T2EX if EXEN2 1 Cleared by user to enable auto reloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to autoreload on Timer 2 overflow Timer Counter 2 Data Registers Timer Counter 2 also has two pairs of 8 bit data registers associated with it These are used as both timer data registers and timer capture reload registers TH2 and TL2 Timer 2 data high byte and low byte SFR Address CDhex CChex respectively RCAP2H and RCAP2L Timer 2 Capture Reload byte and low byte SFR Address CBhex CAhex respectively REV 0 55 ADuC816 Timer Counter 2 Operating Modes The following paragraphs describe the operating modes for timer counter 2 The operating modes are selected by bits in the
40. 20 Hz Update Rate 16 Bits p p typ Range 2 56 V 20 Hz Update Rate p p Resolution at this Range Update Rate Setting Is Limited Only by the Number of Bits Available from ADC Output Noise See Table IX and X Output Noise Varies with Selected in ADC Description Update Rate and Gain Range Integral Nonlinearity LSB max Offset Error 3 typ Offset Error Drift 10 nV C typ Full Scale Error 10 typ Range 20 mV to 640 mV 0 5 LSB typ Range 1 28 V to 2 56 V Gain Error Drift 0 5 ppm C typ ADC Range Matching 0 5 LSB typ AIN 18 mV Power Supply Rejection PSR 95 dBs typ AIN 7 8 mV Range 20 mV 80 dBs typ AIN 1 V Range 2 56 Common Mode DC Rejection On AIN 95 dBs typ At DC AIN 7 8 mV Range 20 mV 90 dBs typ At DC AIN 1 V Range 2 56 On REFIN 90 dBs typ At DC 1 V Range 2 56 Common Mode 50 Hz 60 Hz Rejection 20 Hz Update Rate On AIN 95 dBs typ 50 Hz 60 Hz 1 Hz AIN 7 8 mV Range 20 mV 90 dBs typ 50 Hz 60 Hz 1 Hz AIN 1 V Range 2 56 V On REFIN 90 dBs typ 50 Hz 60 Hz 1 Hz AIN 1 V Range 2 56 V Normal Mode 50 Hz 60 Hz Rejection On AIN 60 dBs typ 50 Hz 60 Hz 1 Hz 20 Hz Update Rate On REFIN 60 dBs typ 50 Hz 60 Hz 1 Hz 20 Hz Update Rate Auxiliary ADC No Missing Codes 16 Bits min Resolution 16 Bits p p typ Range 2 5 V 20 Hz Update Rate Output Noise See Table XI Output Noise Varies with Selected in ADC Description Update Rate Integral Nonlinearity 1 LSB max
41. 51 SFR bit definitions Parallel I O Ports 0 3 The ADuC816 uses four input output ports to exchange data with external devices In addition to performing general purpose I O some ports are capable of external memory operations others are multiplexed with an alternate function for the peripheral features on the device In general when a peripheral is enabled that pin may not be used as a general purpose I O pin Port 0 is an 8 bit open drain bidirectional I O port that is directly controlled via the Port 0 SFR SFR address 80 hex Port 0 pins that have 1s written to them via the Port 0 SFR will be configured as open drain and will therefore float In that state Port 0 pins can be used as high impedance inputs An external pull up resistor will be required on Port 0 outputs to force a valid logic high level externally Port 0 is also the multiplexed low order address and data bus during accesses to external pro gram or data memory In this application it uses strong internal pull ups when emitting 1s Port 1 is also 8 bit port directly controlled via the P1 SFR SFR address 90 hex The Port 1 pins are divided into two distinct pin groupings P1 0 and 1 1 pins Port 1 are bidirectional digital I O pins with internal pull ups If P1 0 and P1 1 have 1s written to them via the P1 SFR these pins are pulled high by the internal pull up resis tors In this state they can also be used as inputs as input pins being externally pu
42. 80 mV 160 mV 011 Unipolar Mode 0 mV to 160 mV 320 mV 100 Unipolar Mode 0 mV to 320 mV 640 mV 101 Unipolar Mode 0 mV to 640 mV 1 28 110 Unipolar Mode 0 V to 1 28 V t2 56 V 111 Unipolar Mode 0 V to 2 56 V Analog Input Current 1 nA max Analog Input Current Drift pA C typ Absolute AIN Voltage Limits AGND 100 mV V min AVpp 100 mV V max Auxiliary ADC Input Voltage Range 0 to VREF V Unipolar Mode for Bipolar Mode See Note 11 Average Analog Input Current 125 nA V typ Input Current Will Vary with Input Average Analog Input Current Drift t2 pA V C typ Voltage on the Unbuffered Auxiliary ADC Absolute AIN Voltage Limits AGND 30 mV V min AVpp 30 mV V max External Reference Inputs REFIN to REFIN Range 1 V min Average Reference Input Current 1 typ Both ADCs Enabled Average Reference Input Current Drift 0 1 nA V C typ NO Ext REF Trigger Voltage 0 3 V min NOXREF Bit Active if Vggr lt 0 3 V 0 65 V max NOXREF Bit Inactive if Vger gt 0 65 V ADC SYSTEM CALIBRATION Full Scale Calibration Limit 1 05 x FS V max Zero Scale Calibration Limit 1 05 x FS V min Input Span 0 8 x FS V min 2 1 x FS V max ANALOG DAC OUTPUTS Voltage Range 0 to VREF V typ DACRN 0 in DACCON SFR 0 to AVpp V typ DACRN 1 in DACCON SFR Resistive Load 10 kQ typ From DAC Output to AGND Capacitive Load 100 pF typ From DAC Output to AGND Output Impedance 0 5 Q typ Ismx 50 LA typ TEMPERATURE SENSOR Accuracy t2
43. E ANALOG INPUT CHOPPING THE INPUTS ARE ALTERNATELY REVERSED THROUGH THE CONVERSION CYCLE CHOPPING YIELDS EXCELLENT ADC OFFSET AND OFFSET DRIFT PERFORMANCE ARCHITECTURE ENSURES AS PART OF THE CHOPPING 16 BITS NO MISSING IMPLEMENTATION EACH CODES THE ENTIRE DATA WORD OUTPUT SIGMA DELTA ADC IS FROM THE FILTER IS CHOPPED TO REMOVE DRIFT SUMMED AND AVERAGED ERRORS WITH ITS PREDECESSOR TO NULL ADC CHANNEL SEE PAGE 35 OFFSET ERRORS SEE PAGE 36 SEE PAGE 35 SEE PAGE 36 REFIN REFIN SIGMA DELTA A D CONVERTER DIGTAL OUTPUT RESULT WRITTEN SIGMA TO ADC1H L SFRs DELTA MODULATOR OUTPUT AVERAGE OUTPUT SCALING ON CHIP O TEMPERATURE SENSOR OUTPUT SCALING THE OUPUT WORD FROM THE DIGITAL FILTER IS SCALED BY THE CALIBRATION PROGRAMMABLE DIGITAL COEFFICIENTS BEFORE SIGMA DELTA FILTER BEING PROVIDED AS MODULATOR THE SINC FILTER REMOVES THE CONVERSION RESULT THE MODULATOR PROVIDES A QUANTIZATION NOISE INTRODUCED SEE PAGE 37 HIGH FREQUENCY 1 BIT DATA BY THE MODULATOR THE UPDATE STREAM THE OUTPUT OF WHICH RATE AND BANDWIDTH OF THIS 15 ALSO CHOPPED TO THE FILTER ARE PROGRAMMABLE DIGITAL FILTER VIA THE SF SFR THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED SEE PAGE 35 ANALOG INPUT VOLTAGE SEE PAGE 35 ANALOG MULTIPLEXER A DIFFERENTIAL MULTIPLEXER ALLOWS SELECTION OF THREE EXTERNAL SINGLE ENDED INPUTS OR THE ON CHIP TEMP SENSOR THE MULTIPLEXER IS CONTROLLED VIA THE CHANNEL SE
44. E Memory on a single chip This low power device accepts low level signals directly from a transducer The two independent ADCs Primary and Auxiliary include a temperature sensor and a PGA allowing direct measurement of low level signals The ADCs with on chip digital filtering are MicroConverter is a registered trademark of Analog Devices Inc SPI is a registered trademark of Motorola Inc I C is a registered trademark of Philips Semiconductors Inc REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices AIN2 CURRENT IEXC1 SOURCE MUX Q IEXC2 VOLTAGE O P AIN5 DAC TEMP SENSOR INTERNAL PROG BANDGAP CLOCK VREF DIVIDER 8051 BASED MCU WITH ADDITIONAL PERIPHERALS 8 KBYTES FLASH EE PROGRAM MEMORY 640 BYTES FLASH EE DATA MEMORY 256 BYTES USER RAM 3 x 16 BIT TIMER COUNTERS 1 x TIME INTERVAL COUNTER ON CHIP MONITORS POWER SUPPLY MONITOR WATCHDOG TIMER EXTERNAL VREF 2 UART AND SPI SERIAL I O DETECT REFIN REFIN XTAL1 XTAL2 intended for the measurement of wide dynamic range low frequency signals such as those in weigh scale strain gauge pressure transdu
45. ERIAL PORT UART bd a gt lt a SINGLE PIN EMULATOR DAY 4 DGND amp Figure 12 Block Diagram 21 ADuC816 MEMORY ORGANIZATION As with all 8051 compatible devices the ADuC816 has sepa rate address spaces for Program and Data memory as shown in Figure 13 and Figure 14 If the user applies power or resets the device while the EA pin is pulled low the part will execute code from the external pro gram space otherwise the part defaults to code execution from its internal 8 Kbyte Flash EE program memory This internal code space can be downloaded via the UART serial port while the device is in circuit PROGRAM MEMORY SPACE READ ONLY EXTERNAL PROGRAM MEMORY SPACE 2000H 1FFFH EA 0 EXTERNAL PROGRAM EA 1 INTERNAL 8 KBYTE FLASH EE PROGRAM MEMORY MEMORY SPACE 0000H Figure 13 Program Memory Map The data memory address space consists of internal and exter nal memory space The internal memory space is divided into four physically separate and distinct blocks namely the lower 128 bytes of RAM the upper 128 bytes of RAM the 128 bytes of special function register SFR area and a 640 byte Flash EE Data memory While the upper 128 bytes of RAM and the SFR area share the same address locations they are accessed through different address modes The lower 128 bytes of data memory can be accessed through direct or indirect addressing the upper 128 bytes of RAM can
46. Edge 50 ns 9 2050 Data Output Setup before SCLOCK Edge 150 ns 9 tpsu Data Input Setup Time before SCLOCK Edge 100 ns 9 tDHD Data Input Hold Time after SCLOCK Edge 100 ns 9 tpr Data Output Fall Time 10 25 ns 9 Data Output Rise Time 10 25 ns 9 tsp SCLOCK Rise Time 10 25 ns 9 tsp SCLOCK Fall Time 10 25 ns 9 Characterized under the following conditions Core clock divider bits CD2 1 and CDO bits in PLLCON SFR set to 0 1 and 1 respectively i e core clock frequency 1 57 MHz and b SPI bit rate selection bits SPR1 and SPRO bits in SPICON SFR set to 0 and 0 respectively SCLOCK CPOL 0 I ta le ts SCLOCK tsp tsp a Nm C MOSI ais T ipsu tou Figure 9 SPI Master Mode Timing CPHA 0 REV 0 15 ADuC816 Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING CPHA 1 tss SS to SCLOCK Edge 0 ns 10 ts SCLOCK Low Pulsewidth 330 ns 10 SCLOCK High Pulsewidth 330 ns 10 tpav Data Output Valid after SCLOCK Edge 50 ns 10 tpsu Data Input Setup Time before SCLOCK Edge 100 ns 10 tpup Data Input Hold Time after SCLOCK Edge 100 ns 10 Data Output Fall Time 10 25 ns 10 tpg Data Output Rise Time 10 25 ns 10 tsp SCLOCK Rise Time 10 25 ns 10 tsp SCLOCK Fall Time 10 25 ns 10 tsEs SS High after SCLOCK Edge 0 ns 10 SCLOCK CPOL 0 SCLOCK CPOL 1 MISO t t DSU DHD 16 BITS 6 1 X LSB Figure 10 SPI Slave
47. H Power On Default Value 00H Bit Addressable No Using the SPI Interface Depending on the configuration of the bits in the SPICON SFR shown in Table XIX the ADuC816 SPI interface will transmit or receive data in a number of possible modes Figure 32 shows all possible ADuC816 SPI configurations and the timing rela tionships and synchronization between the signals involved Also shown in this figure is the SPI interrupt bit ISPI and how it is triggered at the end of each byte wide communication SPI Interface Master Mode In master mode the SCLOCK pin is always an output and gener ates a burst of eight clocks whenever user code writes to the SPIDAT register The SCLOCK bit rate is determined by SPRO and SPRI in SPICON It should also be noted that the SS pin is not used in master mode If the ADuC816 needs to assert the SS pin on an external slave device a Port digital output pin should be used In master mode a byte transmission or reception is initiated CPOL 1 by a write SPIDAT Eight clock periods are generated via the i i SCLOCK pin and the SPIDAT byte being transmitted via MOSI With each SCLOCK period a data bit is also sampled via MISO CPOL 0 After eight clocks the transmitted byte will have been completely CPHA 1 ISPI FLAG SAMPLE INPUT DATA OUTPUT CPHA 0 REV 0 transmitted and the input byte will be waiting in the input shift register
48. Hz AVpp Current 170 max AVpp 5 25 V Core CLK 1 57 MHz DVpp Current 15 mA max DVpp 4 75 V to 5 25 V Core CLK 12 58 MHz 8 mA max DVpp 2 7 V to 3 6 V Core CLK 12 58 MHz AVpp Current 170 max AVpp 5 25 V Core CLK 12 58 MHz Power Supply Currents Idle Mode 17 DVpp Current 1 2 mA max DVpp 4 75 V to 5 25 V Core CLK 1 57 MHz 750 typ DVpp 2 7 V to 3 6 V Core CLK 1 57 MHz AVpp Current 140 typ Measured AVpp 5 25 V Core CLK 1 57 MHz DVpp Current 2 mA typ DVpp 4 75 V to 5 25 V Core CLK 12 58 MHz 1 mA typ DVpp 2 7 V to 3 6 V Core CLK 12 58 MHz AVpp Current 140 typ Measured at AVpp 5 25 V Core CLK 12 58 MHz Power Supply Currents Power Down 17 Core CLK 1 57 MHz or 12 58 MHz DVpp Current 50 uA max DVpp 4 75 V to 5 25 V Osc On TIC On 20 uA max DVpp 2 7 V to 3 6 V Osc On TIC On AVpp Current 1 uA max Measured at AVpp 5 25 V Osc On or Osc Off DVpp Current 20 uA max DVpp 4 75 V to 5 25 V Osc Off 5 typ DVpp 2 7 V to 3 6 Osc Off Typical Additional Power Supply Currents Core CLK 1 57 MHz AVpp DVpp 5 V AIpp and DIpp PSM Peripheral 50 typ Primary ADC 1 mA typ Auxiliary ADC 500 typ DAC 150 typ Dual Current Sources 400 typ NOTES Temperature Range 40 to 85 These numbers are not production tested but are guaranteed by Design and or Characterization data on production release 3The primary ADC is factory calib
49. KX PCH XX Figure 3 External Program Memory Read Cycle REV 0 ga ADuC816 12 58 MHz Core_Clk Variable Core_Clk Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth 377 6tcogg 100 ns 4 tAVLL Address Valid after ALE Low 39 tcong 40 ns 4 Address Hold after ALE Low 44 tcong 35 ns 4 trrpv RD Low to Valid Data In 232 5tcogg 165 ns 4 RHDX Data and Address Hold after RD 0 0 ns 4 tRHDZ Data Float after RD 89 2tcogg 70 ns 4 ALE Low to Valid Data In 486 8tcogg 150 ns 4 tAVDV Address to Valid Data In 550 165 ns 4 LWL ALE Low to RD Low 188 288 3tcong 50 50 ns 4 tavwL Address Valid to RD Low 188 4tcogg 130 ns 4 tRLAZ RD Low to Address Float 0 0 ns 4 yHLH RD High to ALE High 39 119 tcorr 40 tcorr 40 4 PORT 0 2 0 Figure 4 External Data Memory Read Cycle 10 REV 0 ADuC816 12 58 MHz Core_Clk Variable Core_Clk Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY WRITE CYCLE twLwH WR Pulsewidth 377 6tcong 100 ns 5 TAVLL Address Valid after ALE Low 39 tcorg 40 ns 5 trax Address Hold after ALE Low 44 tcorr 35 ns 5 LWL ALE Low to WR Low 188 288 3tcong 50 50 ns 5 tAVWL Address Valid to WR Low 188 4tcong 130 ns 5 tovwx Data Valid to WR Transition
50. LECTION BITS IN ADC1CON SEE PAGE 28 AND 33 Figure 19 Auxiliary ADC Block Diagram 32 REV 0 ADuC816 PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE Tables IX X and XI below show the output rms noise in UV and output peak to peak resolution in bits rounded to the nearest 0 5 LSB for some typical output update rates on both the Primary and Auxiliary ADCs The numbers are typical and are generated at a differential input voltage of 0 V The output update rate is selected via the SF7 SFO bits in the Sinc Filter SF SFR It is important to note that the peak to peak resolu tion figures represent the resolution for which there will be no code flicker within a six sigma limit Table IX Primary ADC Typical Output RMS Noise pV Typical Output RMS Noise vs Input Range and Update Rate Output RMS Noise in pV SF Data Update Input Range Word Rate Hz 20mV 40mV 80mV 160mV 320mV 640mV 1 28 2 56V 13 105 3 1 50 1 50 1 60 1 75 3 50 4 50 6 70 11 75 69 19 79 0 60 0 65 0 65 0 65 0 65 0 95 1 40 2 30 255 5 35 0 35 0 35 0 37 0 37 0 37 0 51 0 82 1 25 Table X Primary ADC Peak to Peak Resolution Bits Peak to Peak Resolution vs Input Range and Update Rate Peak to Peak Resolution in Bits SF Data Update Input Range Word Rate Hz 20mV 40mV 80mV 160mV 320mV 640mV 1 28 2 56 V 13 105 3 12 13 14 15 15 15 5 16 16 69 19 79 13 14 15 16 16 16
51. M This interface is standard to any 8051 compatible MCU ADuC816 Figure 44 External Data Memory Interface 64 K Address Space If access to more than 64 Kbytes of RAM is desired a feature unique to the ADuC816 allows addressing up to 16 Mbytes of external RAM simply by adding an additional latch as illustrated in Figure 45 REV 0 ADuC816 ADuC816 ADuC816 Figure 45 External Data Memory Interface 16 Bytes Address Space In either implementation Port 0 serves as a multiplexed address data bus It emits the low byte of the data pointer DPL as an address which is latched by a pulse of ALE prior to data being placed on the bus by the ADuC816 write operation or the SRAM read operation Port 2 P2 provides the data pointer page byte DPP to be latched by ALE followed by the data pointer high byte DPH If no latch is connected to P2 DPP is ignored by the SRAM and the 8051 standard of 64 Kbyte external data memory access is maintained Detailed timing diagrams of external program and data memory read and write access can be found in the timing specification sections of this data sheet Power On Reset Operation External POR power on reset circuitry must be implemented to drive the RESET pin of the ADuC816 The circuit must hold the RESET pin asserted high whenever the power supply DVpp is below 2 5 V Furthermore must remain above 2 5 V for at lea
52. N or OFF via OSC PD bit PLLCON 7 in PLLCON SFR power supply current will typically increase by 3 mA 3 V operation and 10 mA 5 V operation during a Flash EE memory program or erase cycle Specifications subject to change without notice REV 0 7 ADuC816 AVpp 2 7 V to 3 6 V or 4 75 V to 5 25 V 2 7 V to 3 6 V or 4 75 V to 5 25 V all TIMING SPEC IFICATIONS 2 3 specifications to Tmax unless otherwise noted 32 768 kHz External Crystal Parameter Min Typ Max Unit Figure CLOCK INPUT External Clock Driven 1 tck XTALI Period 30 52 us 1 tckL XTALI Width Low 15 16 us 1 tckH XTALI Width High 15 16 us 1 tckR XTALI Rise Time 20 ns 1 XTALI Fall Time 20 ns 1 1 tcorE ADuC816 Core Clock Frequency 0 098 12 58 MHz 1 ADuC816 Core Clock Period 0 636 us tcyc ADuC816 Machine Cycle Time 0 95 7 6 122 45 NOTES AC inputs during testing are driven at DVpp 0 5 V for a Logic 1 and 0 45 V for a Logic 0 Timing measurements are made at Vy min for a Logic 1 and max for a Logic 0 as shown in Figure 2 For timing purposes a port pin is no longer floating when 100 mV change from load voltage occurs A port pin begins to float when a 100 mV change from the loaded Voy Voz level occurs as shown in Figure 2 for Port0 ALE PSEN outputs 100 pF Croan for all other outputs 80 pF unless otherwise noted ADuC816 internal PLL locks onto a multiple 384 times th
53. ON RDYo RDY1 CAL NOXREF ERRO ERRI BITS gt RESERVED RESERVED DFH 0 DOH 0 Bett LOBM 0 DIH 0 08 0 D8H DAH 00H DBH DCH DDH DFH DEH AG RSi R50 ov H Psw ADCMODE ADCOCON ADCICON SF ICON PLLCON BITS RESERVED D7H 0 D6H 0 DSH 0 04H S70 DSH 0 D2H 0 DIH ODOH lt 0 DOH DIH D2H 07H D3H D4H 45H DSH D7H T2CON RCAP2L RCAP2H TL2 TH2 TF2 2 Reik EXEN2 TR2 2 2 RED RESERVED ESTNE 0 CEH o cAH o Cd od dou Set oin caa sooi ODN oor WDCON CHIPID EADRL PRES PRE2 PRE1 PREO WDIR WDS WDE grs gt RESERVED RESERVED RESERVED RESERVED RESERVED __ 1 o COH 10H 16H T Pr PS Pr m PTO PX ans IP ECON EDATA1 EDATA2 EDATA3 EDATA4 BFH 0 BEH 0 BDH 0 BCH 0 BBH 0 BAH BoH 0 B8H_0 BCH BFH ws Um T nam P3 RD WR Ti TO INTO BITS gt NOT USED NOT USED NOT USED NOT USED RESERVED RESERVED NOT USED B7H 1 BSH __1 1 BsH 1 B2H 1 1 BOH 1 ol Eeh IE IEIP2 EA 2 1 1 BITS gt RESERVED RESERVED
54. Pin Pin 26 48 Program Status Word SFR 23 SS Slave Select Input Pin Pin 13 48 Power Control SFR Sn cesses 23 Using the SPI Interface 0 eee 49 SPECIAL FUNCTION REGISTERS 24 SPI Interface Master Mode 49 SFR INTERFACE TO THE PRIMARY AND SPI Interface Slave Mode 49 AUXILIARY bored ie ett ipte 25 TC COMPATIBLE INTERFACE 50 ADCSTAT ADC Status Register 25 8051 COMPATIBLE ON CHIP PERIPHERALS 51 ADCMODE ADC Mode Register 26 Parallel I O Ports 0 3 e eeuse e aa 51 ADCOCON Primary ADC Control Register 27 Timers Counters 5 Lene n Ret Ee RU EAR ERR 51 ADCICON Auxiliary ADC Control Register 28 TIMER COUNTER 0 AND 1 OPERATING MODES 54 SF Sinc Filter Register 28 Mode 0 13 Bit Timer Counter 54 ICON Current Sources Control Register 29 Mode 1 16 Bit Timer Counter 54 ADCOH ADCOM Primary ADC Conversion Result Mode 2 8 Bit Timer Counter with Autoreload 54 Registers crede ey HU HD eget alata d d sa EA 29 Mode 3 Two 8 Bit Timer Counters 54 ADCIH ADCIL Auxiliary ADC Conversion Result Timer Co
55. Point Accuracy 3 5 max WATCHDOG TIMER WDT Timeout Period 0 ms min Nine Timeout Periods in This Range 2000 ms max Programmed via PRE3 0 in WDCON MCU CORE CLOCK RATE Clock Rate Generated via On Chip PLL MCU Clock Rate 98 3 kHz min Programmable via CD2 0 Bits in PLLCON SFR 12 58 MHz max START UP TIME At Power On 300 ms typ From Idle Mode 1 ms typ From Power Down Mode Oscillator Running OSC_PD Bit 0 in PLLCON SFR Wake Up with INTO Interrupt 1 ms typ Wake Up with SPI C Interrupt 1 ms typ Wake Up with TIC Interrupt 1 ms typ Wake Up with External RESET 3 4 ms typ Oscillator Powered Down OSC_PD Bit 1 in PLLCON SFR Wake Up with External RESET 0 9 sec typ After External RESET in Normal Mode 3 3 ms typ After WDT Reset in Normal Mode 3 3 ms typ Controlled via WDCON SFR FLASH EE MEMORY RELIABILITY CHARACTERISTICS Endurance 100 000 Cycles min Data Retention 100 Years min POWER REQUIREMENTS DVpp and AVpp Can Be Set Independently Power Supply Voltage AVpp 3 V Nominal Operation 2 V min 3 6 V max AVpp 5 V Nominal Operation 4 75 V min 5 25 V max DVpp 3 V Nominal Operation 2 7 V min 3 6 V max DVpp 5 V Nominal Operation 4 75 V min 5 25 V max REV 0 ADuC816 Parameter ADuC816BS Unit Test Conditions Comments POWER REQUIREMENTS continued Power Supply Currents Normal Mode 6 17 DVpp Current 4 mA max DVpp 4 75 V to 5 25 V Core CLK 1 57 MHz 2 1 mA max DVpp 2 7 V to 3 6 V Core CLK 1 57 M
56. R 8H ARE BIT ADDRESSABLE Figure 17 Special Function Register Locations and Reset Values 24 REV 0 ADuC816 SFR INTERFACE TO THE PRIMARY AND AUXILIARY ICON Current Source Control Register Allows ADCS user control of the various on chip current Both ADCs are controlled and configured via a number of SFRs source options that are mentioned here and described in more detail in the ADCOH M Primary ADC 16 bit conversion result held in following pages these two 8 bit registers ADCSTAT ADC Status Register Holds general status of the Primary and Aosiliaty ADCs ADCIH L Auxiliary ADC 16 bit conversion result held in these two 8 bit registers ADCMODE xs C Mode pe d s it OFOH M Primary ADC 16 bit Offset Calibration Coeffi GPODSTAHOROE cient held in these two 8 bit registers OFIH L Auxiliary ADC 16 bit Offset Calibration Coeffi BPE FIM CODHEBIRHOR OR Aunty i cient held in these two 8 bit registers ADOICON Auxlay Control Register COTOS Primary 16 bit Gain Calibration Coeff cient held in these two 8 bit registers SE Sine Filter Regit Conggure the Auxiliary ADC 16 bit Gain Calibration Coeffi factor for the Sinc3 filter and thus the Primary and uxiliary ADC update fate cient held in these two 8 bit registers To maintain code compatibility with the ADuC824 it is the low byte SFR associated with these register groups that is omitted
57. SF Sinc Filter SFR as described in Table VII Figure 21 shows the frequency response of the ADC chan nel at the default SF word of 69 dec or 45 hex yielding an overall output update rate of just under 20 Hz It should be noted that this frequency response allows frequency components higher than the ADC Nyquist frequency to pass through the ADC in some cases without significant attenuation These components may therefore be aliased and appear in band after the sampling process It should also be noted that rejection of mains related frequency components i e 50 Hz and 60 Hz is seen to be at level of gt 65 dB at 50 Hz and gt 100 dB at 60 Hz This confirms the data sheet specifications for 50 Hz 60 Hz Normal Mode Rejec tion NMR at a 20 Hz update rate 0 10 20 30 40 50 60 70 80 90 FREQUENCY Hz 100 110 Figure 21 Filter Response SF 69 dec The response of the filter however will change with SF word as can be seen in Figure 22 which shows gt 90 dB at 50 Hz and gt 70 dB at 60 Hz when SF 255 dec 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY Hz Figure 22 Filter Response SF 255 dec 35 ADuC816 Figures 23 and 24 show the NMR for 50 Hz and 60 Hz across the full range of SF word 1 SF 13 dec to SF 255 dec 60 GAIN dB
58. SLAVE MODE ONLY Set by user to reset the interface Cleared by user code for normal C operation 1 I2CTX Direction Transfer Bit SLAVE MODE ONLY Set by the MicroConverter if the interface is transmitting Cleared by the MicroConverter if the interface is receiving 0 I2CI Interrupt Bit SLAVE MODE ONLY Set by the MicroConverter after a byte has been transmitted or received Cleared automatically when user code reads the I2CDAT SFR see I2CDAT below DCADD Address Register DCDAT Data Register Function Holds the peripheral address for Function The I2CDAT SFR is written by the the part It may be overwritten by user to transmit data over the IC user code Technical Note uC001 at interface or read by user code to read www analog com microconverter data just received by the interface describes the format of the stan Accessing I2CDAT automatically dard 7 bit address in detail clears any pending interrupt and SFR Address 9BH the I2CI bit in the I2CCON SFR Power On Default Value 55H User software should only access Bit Addressable No I2CDAT once per interrupt cycle SFR Address 9AH Power On Default Value 00H Bit Addressable No 50 REV 0 ADuC816 8051 COMPATIBLE ON CHIP PERIPHERALS This section gives a brief overview of the various secondary periph eral circuits are also available to the user on chip These remaining functions are fully 8051 compatible and are controlled via standard 80
59. SPICON register will have to be configured with the phase and polarity CPHA and CPOL of the expected input clock In both master and slave mode the data is transmitted on one edge of the SCLOCK signal and sampled on the other It is important therefore that the CPHA and CPOL are configured the same for the master and slave devices SS Slave Select Input Pin Pin 13 The Slave Select SS input pin is only used when the ADuC816 is configured in slave mode to enable the SPI peripheral This line is active low Data is only received or transmitted in slave mode when the SS pin is low allowing the ADuC816 to be used in single master multislave SPI configurations If CPHA 1 then the SS input may be permanently pulled low With CPHA 0 then the SS input must be driven low before the first bit in a byte wide transmission or reception and return high again after the last bit in that byte wide transmission or reception In SPI Slave Mode the logic level on the external SS pin Pin 13 can be read via the SPRO bit in the SPICON SFR The following SFR registers are used to control the SPI interface SPICON SPI Control Register SFR Address F8H Power On Default Value 04H Bit Addressable Yes ISPI WCOL SPE SPIM CPOL CPHA SPR1 SPRO Table XIX SPICON SFR Bit Designations Bit Name Description 7 ISPI SPI Interrupt Bit Set by MicroConverter at the end of each SPI transfer Cleared directly by user code or indirect
60. VREF 2 5V SEE PAGE 34 DIFFERENTIAL REFERENCE THE EXTERNAL REFERENCE INPUT TO THE ADuC816 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION THE EXTERNAL REFERENCE VOLTAGE IS SELECTED VIA THE XREFO BIT IN ADCOCON REFERENCE DETECT CIRCUITRY TESTS FOR OPEN OR SHORTED REFERENCES INPUTS SEE PAGE 35 REFIN REFIN BUFFER dece 9 CHOP AGND ANALOG MULTIPLEXER A DIFFERENTIAL MULTIPLEXER ALLOWS SELECTION OF THREE FULLY DIFFERENTIAL PAIR OPTIONS AND ADDITIONAL INTERNAL SHORT OPTION AIN2 AIN2 THE MULTIPLEXER IS CONTROLLED VIA THE CHANNEL SELECTION BITS IN ADCOCON SEE PAGES 27 AND 33 REV 0 BUFFER AMPLIFIER THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE ANALOG INPUTS ALLOWING SIGNIFICANT EXTERNAL SOURCE IMPEDANCES SEE PAGE 33 SIGMA DELTA MODULATOR SIGMA DELTA MODULATOR THE MODULATOR PROVIDES A HIGH FREQUENCY 1 BIT DATA STREAM THE OUTPUT OF WHICH IS ALSO CHOPPED TO THE DIGITAL FILTER THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED ANALOG INPUT VOLTAGE SEE PAGE 35 SIGMA DELTA A D CONVERTER PROGRAMMABLE DIGITAL to 105 03 Hz 9 52 ms A Chopping scheme is also employed to minimize ADC offset errors A block diagram of the Primary ADC is shown in Figure 18 SIGMA DELTA ADC THE SIGMA DELTA ARCHITECTURE ENSURES 16 BITS NO MISSING CODES THE ENTIRE OUTPUT AVERAGE AS PART OF THE CHOPPING IMPLEMENTATION EACH DATA WORD
61. W The ADuC816 is housed in a 52 lead MQFP package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 2001 ADuC816 TABLE OF CONTENTS FEATURES 1 0 0 e e 1 Using the Flash EE Memory Interface 40 GENERAL DESCRIPTION esses 1 Erase AlL ivre d trt RICE m T e acai 40 SPECIFICATIONS i ev 3 Program a Byte 40 TIMING SPECIFICATIONS 8 USER INTERFACE TO OTHER ON CHIP ADuC816 ABSOLUTE MAXIMUM RATINGS 18 PERIPHERALS 5 rau erst CR 41 ORDERING GUIDE sees 18 oot SIM 41 PIN FUNCTION DESCRIPTIONS 19 On Ghip PEL Fem tcr 42 ADuC816 BLOCK DIAGRAM 21 Time Interval Counter TIC 43 MEMORY ORGANIZATION 22 Watchdog Timer 4 te E wk Rua WR XE 46 OVERVIEW MCU RELATED SERS 23 Power Supply Monitor 47 Accumulator SFR eens 23 SERIAL PERIPHERAL INTERFACE 48 23 MISO Master In Slave Out Data Pin Pin 14 48 Stack Pointer SER 23 MOSI Master Out Slave In Pin Pin 27 48 Data 4c see tee prb A owe AR e 23 SCLOCK Serial Clock
62. a sheet The value of the total load capacitance required for the external crystal should be the value recommended by the crystal manufacturer for use with that specific crystal In many cases because of the on chip capacitors additional external load capacitors will not be required ADuC816 XTAL1 32 768kHz 12pF ca V 33 TO INTERNAL XTAL2 12 PLL Figure 42 External Parallel Resonant Crystal Connections External Memory Interface In addition to its internal program and data memories the ADuC8106 can access up to 64 Kbytes of external program memory ROM PROM etc and up to 16 Mbytes of external data memory SRAM To select from which code space internal or external program memory to begin executing instructions tie the EA external access pin high or low respectively When EA is high pulled up to Vpp user program execution will start at address 0 of the internal 8 Kbytes Flash EE code space When EA is low tied to ground user program execution will start at address 0 of the external code space In either case addresses above IFFF hex 8K are mapped to the external space Note that a second very important function of the EA pin is described in the Single Pin Emulation Mode section of this data sheet External program memory if used must be connected to the ADuC816 as illustrated in Figure 43 Note that 16 I O lines Ports 0 and 2 are dedicated to bus functions during external
63. ach VDD pin of the chip As per standard design prac tice be sure to include all of these capacitors and ensure the smaller capacitors are closest to each AVpp pin with trace lengths as short as possible Connect the ground terminal of each of these capacitors directly to the underlying ground plane Finally it should also be noticed that at all times the analog and digital ground pins on the ADuC816 should be referenced to the same system ground reference point Power Consumption The CORE values given represent the current drawn by DVpp while the rest and DAC are pulled by the AVpp pin and can be disabled in software when not in use The other on chip peripherals watchdog timer power supply monitor etc consume negligible current and are therefore lumped in with the CORE operating current here Of course the user must add any currents sourced by the parallel and serial I O pins and that sourced by the DAC in order to determine the total current needed at the ADuC816 s supply pins Also current draw from the DVDD supply will increase by approximately 5 mA during Flash EE erase and program cycles Power Saving Modes Setting the Idle and Power Down Mode bits PCON 0 and PCON 1 respectively in the PCON SFR described in Table II allows the chip to be switched from normal mode into idle mode and also into full power down mode In idle mode the oscillator continues to run but the core clock generated fro
64. all on chip peripherals Figure 17 shows a full SFR memory map and SFR contents on RESET NOT USED indicates unoccupied SFR locations Unoc cupied locations in the SFR address space are not implemented i e no register exists at this location If an unoccupied location is read an unspecified value is returned SFR locations reserved for future use are shaded RESERVED and should not be accessed by user software SPICON DACL DACH DACCON ISPI GOL SPE 1 CPOE SPAT eire RESERVED RESERVED RESERVED RESERVED FFH 0 FEH o FDH o rcH 1 F9H o rsH o FBH gt opin TECH con FOH B SPIDAT RESERVED RESERVED NOT USED RESERVED RESERVED RESERVED FOH F7H 00H I2CCON GNOM GNOH GN1L GN1H MDO mco 2cm I2CRS I2CTX 2 SSSR EFH 0 EEH o EDH o ECH o EBH ojEaH o roH o EUH COH EDM TESH OFOM OFOH OF1L OF1H RESERVED E7H o EsH o E2H o eon o BITS DL ESH ADCSTAT ADCOM ADCOH ADCIL ADC1H PSMC
65. at programmed by user software Table VII SF SFR Bit Designations SF dec SF hex fapc Hz tapc ms 13 0 105 3 9 52 69 45 19 79 50 34 255 5 35 186 77 REV 0 28 ADuC816 ICON Current Sources Control Register Used to control and configure the various excitation and burnout current source options available on chip SFR Address D5H Power On Default Value 00H Bit Addressable No BO ADCIIC ADCOIC I2PIN I1PIN I2EN I1EN Table VIII ICON SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 BO Burnout Current Enable Bit Set by user to enable both transducer burnout current sources in the primary ADC signal paths Cleared by user to disable both transducer burnout current sources 5 ADCIIC Auxiliary ADC Current Correction Bit Set by user to allow scaling of the Auxiliary ADC by an internal current source calibration word 4 ADCOIC Primary ADC Current Correction Bit Set by user to allow scaling of the Primary ADC by an internal current source calibration word 3 I2PIN Current Source 2 Pin Select Bit Set by user to enable current source 2 200 to external Pin 3 P1 2 DAC IEXCI Cleared by user to enable current source 2 200 uA to external Pin 4 P1 3 AIN5 IEXC2 2 I1PIN Current Source 1 Pin Select Bit Set by user to enable current source 1 200 to external Pin 4 P1 3 AIN5 IEXC2 Cleared by user to enable current source 1
66. bit above and clear the bit ADC1CON 3 to select bipolar coding 2 The temperature sensor is factory calibrated to yield conversion results 8000H at 0 C 3 1 C change in temperature will result in a 1 LSB change in the ADCIH register ADC conversion result SF Sinc Filter Register value for the SF register is 45 hex resulting in a default ADC The number in this register sets the decimation factor and thus the output update rate for the Primary and Auxiliary ADCs This SFR cannot be written by user software while either ADC is active The update rate applies to both Primary and Auxiliary ADCs and is calculated as follows 1 1 Where fanc ADC Output Update Rate Modulator Clock Frequency 32 768 kHz SF Decimal Value of SF Register The allowable range for SF is 0Dhex to FFhex Examples of SF values and corresponding conversion update rate fapc and con version time tapc are shown in Table VII the power on default update rate of just under 20 Hz Both ADC inputs are chopped to minimize offset errors which means that the settling time for a single conversion or the time to a first conversion result in continuous conversion mode is 2 tapc As mentioned earlier all calibration cycles will be carried out automatically with a maximum 1 FFhex SF value to ensure optimum calibra tion performance Once a calibration cycle has completed the value in the SF register will be th
67. cer or temperature measurement applications The ADC output data rates are programmable and the ADC output resolution will vary with the programmed gain and output rate The device operates from a 32 kHz crystal with an on chip PLL generating a high frequency clock of 12 58 MHz This clock is in turn routed through a programmable clock divider from which the MCU core clock operating frequency is generated The microcontroller core is an 8052 and therefore 8051 instruction set compatible The microcontroller core machine cycle consists of 12 core clock periods of the selected core operating frequency 8 Kbytes of nonvolatile Flash EE program memory are provided on chip 640 bytes of nonvolatile Flash EE data memory and 256 bytes RAM are also integrated on chip The ADuC816 also incorporates additional analog functionality with a 12 bit DAC current sources power supply monitor and a bandgap reference On chip digital peripherals include a watchdog timer time interval counter three timers counters and three serial I O ports SPI UART and PC compatible On chip factory firmware supports in circuit serial download and debug modes via UART as well as single pin emulation mode via the EA pin A functional block diagram of the ADuC816 is shown above with a more detailed block diagram shown in Figure 12 The part operates from a single 3 V or 5 V supply When operating from 3 V supplies the power dissipation for the part is below 10 m
68. changed from 0 to 1 then both ADCs are also immediately reset In other words the Primary ADC is given priority over the Auxiliary ADC and any change requested on the primary ADC is immediately responded to On the other hand if ADCICON is written or if ADCIEN is changed from 0 to 1 only the Auxiliary ADC is reset For example if the Primary ADC is continuously converting when the Auxiliary ADC change or enable occurs the primary ADC continues undisturbed Rather than allow the Auxiliary ADC to operate with a phase difference from the primary ADC the Auxiliary ADC will fall into step with the outputs of the primary ADC The result is that the first conversion time for the Auxiliary ADC will be delayed up to three outputs while the Auxiliary ADC update rate is synchronized to the Primary ADC Once ADCMODE has been written with a calibration mode the RDY0 1 bits ADCSTAT are immediately reset and the calibration commences On completion the appropriate calibration registers are written the relevant bits in ADCSTAT are written and the MD2 0 bits are reset to 000 to indicate the ADC is back in power down mode Any calibration request of the Auxiliary ADC while the temperature sensor is selected will fail to complete Although the RDYI bit will be set at the end of the calibration cycle no update of the calibration SFRs will take place and the ERRI bit will be set Calibrations are performed at maximum SF see SF SFR value guaranteeing opt
69. d as a Software Master or Hard ware Slave and uses two pins in the interface Serial Data I O Pin Serial Clock Three SFRs are used to control the I C compatible interface These are described below I2CCON Control Register SFR Address E8H Power On Default Value 00H Bit Addressable Yes MDO MDE MCO MDI RCM DCRS DCTX Table XX I2CCON SFR Bit Designations Bit Name Description 7 MDO Software Master Data Output Bit MASTER MODE ONLY This data bit is used to implement a master transmitter interface in software Data written to this bit will be output on the SDATA pin if the data output enable MDE bit is set 6 MDE Software Master Data Output Enable Bit MASTER MODE ONLY Set by user to enable the SDATA pin as an output Tx Cleared by the user to enable SDATA pin as an input Rx 5 MCO Software Master Clock Output Bit MASTER MODE ONLY This data bit is used to implement a master transmitter interface in software Data written to this bit will be outputted on the SCLOCK pin 4 MDI Software Master Data Input Bit MASTER MODE ONLY This data bit is used to implement a master receiver interface in software Data on the SDATA pin is latched into this bit on SCLOCK if the Data Output Enable MDE bit is 0 3 I2CM Master Slave Mode Bit Set by user to enable software master mode Cleared by user to enable hardware slave mode 2 I2CRS Reset Bit
70. d externally low will source current because of the internal pull up resistors When driving a 0 to 1 out put transition a strong pull up is active for two core clock periods of the instruction cycle Port 3 pins also have various secondary functions described below Timer Counter 0 Input Timer Counter 1 Input Write control signal logic output Latches the data byte from Port 0 into an external data memory Read control signal logic output Enables the data from an external data memory to Port 0 Serial interface clock for either the C compatible or SPI interface As an input this pin is a Schmitt triggered input and a weak internal pull up is present on this pin unless it is outputting logic low Serial data I O for the C compatible interface or master output slave input for the SPI interface A weak internal pull up is present on this pin unless it is outputting logic low Port 2 is a bidirectional port with internal pull up resistors Port 2 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs Port 2 pins being pulled externally low will source current because of the internal pull up resistors Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24 bit external data memory space Input to the crystal oscillator inverter Output from the crystal oscillator
71. e SFRs can be written initially with the current time the TIC can then be controlled and accessed by user software In effect this facilitates the implementation of a real time clock A block diagram of the TIC is shown in Figure 31 HUNDREDTHS COUNTER HTHSEC INTERVAL L p MINUTE COUNTER TIMEBASE TIEN SELECTION SECOND COUNTER MUX SEC INTERVAL TIMEOUT TIME INTERVAL COUNTER lt lt COUNT NECS INTERRUPT HOUR COUNTER HOUR 8 BIT INTERVAL COUNTER TIME INTERVAL INTVAL Figure 31 TIC Simplified Block Diagram REV 0 43 ADuC816 TIMECON TIC CONTROL REGISTER SFR Address AIH Power On Default Value 00H Bit Addressable No ITS1 ITSO STI TII TIEN TCEN Table XVI TIMECON SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 Reserved for Future Use For future product code compatibility this bit should be written as a 1 5 ITS1 Interval Timebase Selection Bits 4 ITSO Written by user to determine the interval counter update rate ITS1 ITSO Interval Timebase 0 0 1 128 Second 0 1 Seconds 1 0 Minutes 1 1 Hours 3 STI Single Time Interval Bit Set by user to generate a single interval timeout If set a timeout will clear the TIEN bit Cleared by user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout 2 TII TIC Interru
72. e the user can download code to the program memory array while the device is sited in its target application hardware A PC serial download executable is provided as part of the ADuC816 QuickStart devel opment system The Serial Download protocol is detailed in a MicroConverter Applications Note uC004 available from the ADI MicroConverter Website at www analog com microconverter TO CONFIGURE THE ADuC816 ADuC816 PSEN Figure 27 Flash EE Memory Serial Download Mode Programming Parallel Programming The parallel programming mode is fully compatible with conven tional third party Flash or EEPROM device programmers A block diagram of the external pin configuration required to support parallel programming is shown in Figure 28 In this mode Ports 0 1 and 2 operate as the external data and address bus interface ALE operates as the Write Enable strobe and Port 3 is used as a general configuration port that configures the device for various program and erase operations during parallel programming The high voltage 12 V supply required for Flash EE program ming is generated using on chip charge pumps to supply the high voltage program lines 38 PULL PSEN LOW DURING RESET FOR SERIAL DOWNLOAD MODE PROGRAM DATA 00 07 ADuC816 PROGRAM MODE SEE TABLE XII PROGRAM ADDRESS COMMAND A0 A13 ENABLE P2 0 A0 P1 7 A13 NEGATIVE EDGE WRITE ENABLE ENTRY SEQUENCE GND STROBE Figure 28 Flash EE M
73. e AIN voltage limits The bipolar range is still to Vggg however the negative voltage is limited to 30 mV Pins configured in C compatible mode or SPI mode pins configured as digital inputs during this test P Pins configured in I C compatible mode only PFlash EE Memory Reliability Characteristics apply to both the Flash EE program memory and Flash EE data memory V Endurance is qualified to 100 Kcycles as Std 22 method A117 and measured at 40 C 25 C and 85 C typical endurance at 25 C is 700 Kcycles PRetention lifetime equivalent at junction temperature Ty 55 C as Std 22 Method A117 Retention lifetime based on an activation energy of 0 6eV will derate with junction temperature as shown in Figure 27 in the Flash EE Memory description section of this data sheet l Power Supply current consumption is measured in Normal Idle and Power Down Modes under the following conditions Normal Mode Reset 0 4 V Digital pins open circuit Core Clk changed via CD bits in PLLCON Core Executing internal software loop Idle Mode Reset 0 4 V Digital I O pins open circuit Core Clk changed via CD bits in PLLCON PCON 0 1 Core Execution suspended in idle mode Power Down Mode Reset 0 4 V All PO pins and P1 2 P1 7 pins 0 4 V All other digital I O pins are open circuit Core Clk changed via CD bits in PLLCON 1 1 Core Execution suspended in power down mode OSC turned O
74. e RTD and reference voltage across R1 vary ratiometrically with the excitation current Resistor R1 must however have a low temperature coefficient to avoid errors in the reference volt age over temperature QUICKSTART DEVELOPMENT SYSTEM The QuickStart Development System is a full featured low cost development tool suite supporting the ADuC816 The system consists of the following PC based Windows compatible hard ware and software development tools ADuC816 Evaluation Board Plug In Power Supply and Serial Port Cable 8051 Assembler C Compiler 2 Kcode Limited ADSIM Windows MicroConverter Code Simulator In Circuit Code Download Serial Downloader In Circuit Debugger Misc Other Hardware Code Development Code Functionality Serial Port Debugger CD ROM Documentation and Two Additional Prototype Devices Figures 53 shows the typical components of a QuickStart Devel opment System while Figure 54 shows a typical debug session A brief description of some of the software tools components in the QuickStart Development System is given below we N MicroConverter Fi Figure 53 Components of the QuickStart Development System REV 0 Download In Circuit Serial Downloader The Serial Downloader is a software program that allows the user to serially download an assembled program Intel Hex format file to the on chip program FLASH memory via the serial COMI port on a standard PC
75. e external crystal frequency of 32 768 kHz to provide a Stable 12 583 MHz internal clock for the system The core can operate at this frequency or at a binary submultiple called Core Clk selected via the PLLCON SFR gt This number is measured at the default Core Clk operating frequency of 1 57 MHz ADuC816 Machine Cycle Time is nominally defined as 12 Specifications subject to change without notice tex Figure 1 XTAL1 Input DVpp 0 5V 0 2DVpp 0 9V TEST POINTS 0 2DVpp 0 1V 0 45V Figure 2 Timing Waveform Characteristics g REV 0 ADuC816 12 58 MHz Core_Clk Variable Core_Clk Parameter Min Max Min Max Unit Figure EXTERNAL PROGRAM MEMORY tLHLL ALE Pulsewidth 119 2tcorE 40 ns 3 tAVLL Address Valid to ALE Low 39 tcong 40 ns 3 rlAX Address Hold after ALE Low 49 tcong 30 ns 3 ALE Low to Valid Instruction In 218 4tcogg 100 ns 3 ALE Low PSEN Low 49 tcong 30 ns 3 tprPH PSEN Pulsewidth 193 3tcong 45 ns 3 tpriv PSEN Low to Valid Instruction In 133 105 ns 3 tpxrx Input Instruction Hold after PSEN 0 0 ns 3 tpxiz Input Instruction Float after PSEN 54 tcong 25 ns 3 taviv Address to Valid Instruction In 292 5tcogg 105 ns 3 tPLAZ PSEN Low to Address Float 25 25 ns 3 Address Hold after PSEN High 0 0 ns 3 LHLL ALE 0 PSEN 0 PORT 0 PORT 2 0
76. e in circuit programming plus in circuit debug and emulation options users will want to implement some simple connection points in their hardware that will allow easy access to download debug and emulation modes In Circuit Serial Download Access Nearly all ADuC816 designs will want to take advantage of the in circuit reprogrammability of the chip This is accomplished by a connection to the ADuC816 s UART which requires an external RS 232 chip for level translation if downloading code from a PC Basic configuration of an RS 232 connection is illustrated in Figure 52 with a simple ADM202 based circuit If users would rather not design an RS 232 chip onto a board refer to the appli cation note 006 4 Wire UART to PC Interface for a simple and zero cost per board method of gaining in circuit serial download access to the ADuC816 NOTE Application note uC006 is available at www analog com microconverter In addition to the basic UART connections users will also need a way to trigger the chip into download mode This is accom plished via a 1 pull down resistor that can be jumpered onto the PSEN pin as shown in Figure 52 To get the ADuC816 into download mode simply connect this jumper and power cycle the device or manually reset the device if a manual reset button is available and it will be ready to receive a new program serially With the jumper removed the device will come up in normal mode and run the pro
77. e is terminated and the CPU services the TIC interrupt the RETI at the end of the TIC Interrupt Service Routine will return the core to the instruction after that which enabled power down or SPI Interrupt Power down mode is terminated and the CPU services the SPI interrupt The RETI at the end of the ISR will return the core to the instruction after that which enabled power down It should be noted that the I C SPI power down interrupt enable bit SERIPD in the PCON SFR must first be set to allow this mode of operation INTO Interrupt Power down mode is terminated and the CPU services the INTO interrupt The at the end of the ISR will return the core to the instruction after that which enabled power down It should be noted that the INTO power down interrupt enable bit INTOPD in the PCON SFR must first be set to allow this mode of operation Grounding and Board Layout Recommendations As with all high resolution data converters special attention must be paid to grounding and PC board layout of ADuC816 based designs in order to achieve optimum performance from the ADCs and DAC Although the ADuC816 has separate pins for analog and digital ground AGND and DGND the user must not tie these to two separate ground planes unless the two ground planes are con nected together very close to the ADuC816 as illustrated in the simplified example of Figure 51 In systems where digital and analog ground planes are connec
78. ecifications Excitation Currents The ADuC816 also contains two identical 200 HA constant current sources Both source current from AVDD to Pin 3 IEXC1 or Pin 4 IEXC2 These current sources are con trolled via bits in the ICON SFR shown in Table They can be configured to source 200 uA individually to both pins or a combination of both currents i e 400 to either of the selected pins These current sources can be used to excite exter nal resistive bridge or RTD sensors Reference Input The ADuC816 s reference inputs REFIN and REFIN provide a differential reference input capability The common mode range for these differential inputs is from AGND to AVDD The nominal reference voltage VREF REFIN REFIN for specified operation is 2 5 V with the primary and auxil iary reference enable bits set in the respective ADCOCON and or ADCICON SFRs The part is also functional although not specified for perfor mance when the XREFO or XREFI bits are 0 which enables the on chip internal bandgap reference In this mode the ADCs will see the internal reference of 1 25 V therefore halving all input ranges As a result of using the internal reference volt age a noticeable degradation in peak to peak resolution will result Therefore for best performance operation with an exter nal reference is strongly recommended In applications where the excitation voltage or current for the transducer on the analog
79. emory Parallel Programming Table XII Flash EE Memory Parallel Programming Modes Port 3 Pins Programming 0 7 0 6 0 5 0 4 0 3 0 2 0 1 Mode X X X X 0 0 0 Erase Flash EE Program Data and Security Modes X X X X 0 0 1 Read Device Signature ID X X X 1 0 1 0 Program Code Byte X X X 0 0 1 0 Program Data Byte 1 0 1 1 Read Code Byte X X X 0 0 1 1 Read Data Byte X X X X 1 0 0 Program Security Modes X X X X 1 0 1 Read Verify Security Modes All Other Codes Redundant Flash EE Program Memory Security The ADuC816 facilitates three modes of Flash EE program memory security These modes can be independently activated restricting access to the internal code space These security modes can be enabled as part of the user interface available on all ADuC816 serial or parallel programming tools referenced on the MicroConverter web page at www analog com microconverter The security modes available on the ADuC816 are described as follows Lock Mode This mode locks code in memory disabling parallel program ming of the program memory although reading the memory in parallel mode is still allowed This mode is deactivated by initi ating a code erase command in serial download or parallel programming modes Secure Mode This mode locks code in memory disabling parallel programming program and verify read commands as well as disabling the execution of a instruction from external memory which is at
80. errupt system is carried out through three Interrupt related SFRs IE Interrupt Enable Register IP Interrupt Priority Register IEIP2 Secondary Interrupt Priority Interrupt Register IE Interrupt Enable Register SFR Address ASH Power On Default Value 00H Bit Addressable Yes EA EADC ET2 ES 1 EX0 Table XXX IE SFR Bit Designations Bit Name Description 7 EA Written by User to Enable 1 or Disable 0 All Interrupt Sources 6 EADC Written by User to Enable 1 or Disable 0 ADC Interrupt 5 ET2 Written by User to Enable 1 or Disable 0 Timer 2 Interrupt 4 ES Written by User to Enable 1 or Disable 0 UART Serial Port Interrupt 3 1 Written by User to Enable 1 or Disable 0 Timer 1 Interrupt 2 EXI Written by User to Enable 1 or Disable 0 External Interrupt 1 1 Written by User to Enable 1 or Disable 0 Timer 0 Interrupt 0 Written by User to Enable 1 or Disable 0 External Interrupt 0 IP Interrupt Priority Register SFR Address B8H Power On Default Value 00H Bit Addressable Yes PADC PT2 PS 1 PTO PXO0 Table XXXI IP SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 PADC Written by User to Select ADC Interrupt Priority 1 High 0 Low 5 PT2 Written by User to Select Timer 2 Interrupt Priority 1 High 0 Low 4 PS
81. gh nibble of TMOD 0100Binary and using the Timer 1 interrupt to do a 16 bit software reload Table XXVIII below shows some commonly used baud rates and how they might be calculated from a core clock frequency of 1 5728 MHz and 12 58 MHz Generally speaking a 5 error is tolerable using asynchronous start stop communications Table XXVIII Commonly Used Baud Rates Timer 1 Ideal Core SMOD TH1 Reload Actual Baud CLK Value Value Baud Error 9600 12 58 1 7 F9h 9362 2 5 2400 12 58 1 27 E5h 2427 1 1 1200 12 58 1 55 C9h 1192 0 7 1200 1 57 1 7 F9h 1170 2 5 Timer 2 Generated Baud Rates Baud rates can also be generated using Timer 2 Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted received Because Timer 2 has a 16 bit autoreload mode a wider range of baud rates is possible using Timer 2 NOTE OSC FREQ IS DIVIDED BY 2 NOT 12 CONTROL PIN 8 BITS a NOTE AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT T2EX CONTROL TRANSITION DETECTOR EXEN2 Modes 1 and 3 Baud Rate 1 16 x Timer 2 Overflow Rate Therefore when Timer 2 is used to generate baud rates the timer increments every two clock cycles and not every core machine cycle as before Hence it increments six times faster than Timer 1 and therefore baud rates six times faster are possible Because Timer 2 has 16 bit autorel
82. gister SFR Address 89H Power On Default Value 00H Bit Addressable No Gate CIT 1 MO Gate C T MO Table XXIII TMOD SFR Bit Designations Bit Name Description 7 Gate Timer 1 Gating Control 6 C T Timer 1 Timer or Counter Select Bit 5 1 Timer 1 Mode Select 1 Used with MO Bit 4 MO Timer 1 Mode Select Bit 0 1 0 1 1 Timer Counter 1 Stopped 3 Gate Timer 0 Gating Control 2 C T Timer 0 Timer or Counter Select Bit 1 1 Timer 0 Mode Select Bit 1 0 MO Timer 0 Mode Select Bit 0 1 0 Set by software to select counter operation input from T1 pin Cleared by software to select timer operation input from internal system clock Set by software to select counter operation input from TO pin Cleared by software to select timer operation input from internal system clock Set by software to enable timer counter 1 only while INT 1 pin is high and TRI control bit is set Cleared by software to enable timer 1 whenever TRI control bit is set 0 operates as an 8 bit timer counter TL1 serves as 5 bit prescaler 0 1 16 Bit Timer Counter TH1 and TL1 are cascaded there is no prescaler 0 8 Bit Auto Reload Timer Counter holds a value which is to be reloaded into TL1 each time it overflows Set by software to enable timer counter 0 only while INTO pin is high and TRO control bit is set Cleared by software to enable Timer 0 whenever TRO control bit is set 0 THO operates as an 8 b
83. gram whenever power is cycled or RESET is toggled Note that PSEN is normally an output as described in the Exter nal Memory Interface section and it is sampled as an input only on the falling edge of RESET i e at power up or upon an external manual reset Note also that if any external circuitry unintentionally pulls PSEN low during power up or reset events it could cause the chip to enter download mode and therefore fail to begin user code execution as it should To prevent this ensure that no external signals are capable of pulling the PSEN pin low except for the external PSEN jumper itself Embedded Serial Port Debugger From a hardware perspective entry to serial port debug mode is identical to the serial download entry sequence described above In fact both serial download and serial port debug modes can be thought of as essentially one mode of operation used in two different ways Note that the serial port debugger is fully contained on the ADuC816 device unlike ROM monitor type debuggers and therefore no external memory is needed to enable in system debug sessions Single Pin Emulation Mode Also built into the ADuC816 is a dedicated controller for single pin in circuit emulation ICE using standard production ADuC816 devices In this mode emulation access is gained by connection to a single pin the EA pin Normally this pin is hard wired either high or low to select execution from internal or e
84. hat can be pro grammed via the mode bits in the ADCMODE SFR detailed in Table IV In fact every ADuC816 has already been factory calibrated The resultant Offset and Gain calibration coefficients for both the primary and auxiliary ADCs are stored on chip in manufacturing specific Flash EE memory locations At power on these factory calibration coefficients are automatically downloaded to the calibration registers in the ADuC816 SFR space Each ADC primary and auxiliary has dedicated calibration SFRs these have been described earlier as part of the general ADC SFR description However the factory calibration values in the ADC calibration SFRs will be overwritten if any one of the four calibration options are initiated and that ADC is enabled via the ADC enable bits in ADCMODE Even though an internal offset calibration mode is described below it should be recognized that both ADCs are chopped This chopping scheme inherently minimizes offset and means that an internal offset calibration should never be required Also because factory 5 V 25 C gain calibration coefficients are automatically present at power on an internal full scale calibration will only be required if the part is being operated at 3 V or at temperatures significantly different from 25 C The ADuC816 offers internal or system calibration facilities For full calibration to occur on the selected ADC the calibration logic must record the modulator output for tw
85. he eight data bits are clocked into the serial port shift register When all eight bits have been clocked in the following events occur The eight bits in the receive shift register are latched into SBUF The ninth bit Stop bit is clocked into RB8 in SCON The Receiver interrupt flag RI is set if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and Either SM2 0 or SM2 1 and the received stop bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set 58 Mode 2 9 Bit UART with Fixed Baud Rate Mode 2 is selected by setting SMO and clearing SM1 In this mode the UART operates in 9 bit mode with a fixed baud rate The baud rate is fixed at Core CIk 64 by default although by setting the SMOD bit in PCON the frequency can be doubled to Core CIk 32 Eleven bits are transmitted or received a start bit 0 eight data bits a programmable ninth bit and a stop bit 1 The ninth bit is most often used as a parity bit although it can be used for anything including a ninth data bit if required To transmit the eight data bits must be written into SBUF The ninth bit must be written to TB8 in SCON When transmission is initiated the eight data bits from SBUF are loaded onto the transmit shift register LSB first The contents of TB8 are loaded into the ninth bit position of the transmit shift register The trans mission wi
86. ication A117 at a specific junction temperature Tj 55 As part of this qualification procedure the Flash EE memory is cycled to its specified endurance limit described above before data retention is characterized This means that the Flash EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash EE memory is repro grammed It should also be noted that retention lifetime based on an activation energy of 0 6 eV will derate with Ty as shown in Figure 26 300 250 200 ADI SPECIFICATION 1 100 2 55 C 150 E r4 ul 100 50 0 40 50 60 70 80 90 10 110 Ty JUNCTION TEMPERATURE C Figure 26 Flash EE Memory Data Retention 37 ADuC816 Using the Flash EE Program Memory The 8 Kbyte Flash EE Program Memory array is mapped into the lower 8 Kbytes of the 64 Kbytes program space addressable by the ADuC816 and is used to hold user code in typical applications The program memory Flash EE memory arrays can be pro grammed in one of two modes namely Serial Downloading In Circuit Programming As part of its factory boot code the ADuC816 facilitates serial code download via the standard UART serial port Serial download mode is automatically entered on power up if the external pin PSEN is pulled low through an external resistor as shown in Figure 27 Once in this mod
87. ied to external interrupt pin INT 1 depend ing on bit IT1 state Cleared by hardware when the when the PC vectors to the interrupt service routine only if the inter rupt was transition activated If level activated the external requesting source controls the request flag rather than the on chip hardware 2 ITI External Interrupt 1 IE1 Trigger Type Set by software to specify edge sensitive detection 1 1 to 0 transition Cleared by software to specify level sensitive detection i e zero level 1 External Interrupt 0 INTO Flag Set by hardware by a falling edge or zero level being applied to external interrupt pin INTO depend ing on bit ITO state Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition activated If level activated the external requesting source controls the request flag rather than the on chip hardware 0 ITO External Interrupt 0 Trigger Type Set by software to specify edge sensitive detection i e 1 to 0 transition Cleared by software to specify level sensitive detection i e zero level Timer Counter 0 and 1 Data Registers Each timer consists of two 8 bit registers These can be used as independent registers or combined to be a single 16 bit register depending on the timer mode configuration THO and TLO Timer 0 high byte and low byte SFR Address 8Chex 8Ahex respectively and TL1 Timer 1 high
88. imum calibration operation 26 REV 0 ADuC816 ADCOCON Primary ADC Control Register Used to configure the Primary ADC for range channel selection external Ref enable and unipolar or bipolar coding SFR Address D2H Power On Default Value 07H Bit Addressable No 1 CH0 UNIO RN2 RNO Table V ADCOCON SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 XREFO Primary ADC External Reference Select Bit Set by user to enable the Primary ADC to use the external reference via REFIN REFIN Cleared by user to enable the Primary ADC to use the internal bandgap reference Vggg 1 25 V 5 CH1 Primary ADC Channel Selection Bits 4 CHO Written by the user to select the differential input pairs used by the Primary ADC as follows CHO Positive Input Negative Input 0 0 AINI AIN2 0 1 AIN3 AIN4 1 0 AIN2 AIN2 Internal Short 1 1 AIN3 AIN2 3 UNIO Primary ADC Unipolar Bit Set by user to enable unipolar coding i e zero differential input will result in 000000 hex output Cleared by user to enable bipolar coding zero differential input will result in 800000 hex output 2 RN2 Primary ADC Range Bits 1 RNI Written by the user to select the Primary ADC input range as follows 0 RNO RN2 RNI RNO Selected Primary ADC Input Range 2 5 V 0 0 0 20 mV 0 0 1 40 mV 0 1 0 80 mV 0 1 1 160 mV 1 0 0 320 mV 1 0 1 640 mV 1 1 0 1 28 1 1 1
89. inverter Port 2 is a bidirectional port with internal pull up resistors Port 2 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state they can be used as inputs As inputs Port 2 pins being pulled externally low will source current because of the internal pull up resistors Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24 bit external data memory space External Access Enable Logic Input When held high this input enables the device to fetch code from internal program memory locations 0000H to 1FFFH When held low this input enables the device to fetch all instructions from external program memory To determine the mode of code execution i e internal or external the EA pin is sampled at the end of an external RESET assertion or as part of a device power cycle EA may also be used as an external emulation I O pin and therefore the voltage level at this pin must not be changed during normal mode operation as it may cause an emulation interrupt that will halt code execution Program Store Enable Logic Output This output is a control signal that enables the external program memory to the bus during external fetch operations It is active every six oscillator periods except during external data memory accesses This pin remains high during internal program execution PSEN can also be used to enab
90. ion it uses strong internal pull ups when emitting 1s I Input Output S Supply NOTES 1 In the following descriptions SET implies a Logic 1 state and CLEARED implies a Logic 0 state unless otherwise stated 2 In the following descriptions SET and CLEARED also imply that the bit is automatically set or cleared by the ADuC816 hardware unless otherwise stated 3 User software should not write 1s to reserved or unimplemented bits as they may be used in future products REV 0 AIN3 yn qma AINS 4 XA ADC BANDGAP REFERENCE REFIN V REFIN 7 DETECT CURRENT SOURCE MUX AVpp AGND DVpp 8 amp DVpp DGND 8 DGND 2 AUXILIARY ADC ca 2 2 5 55525555 soer ug2z222 E8228 lt lt 4 4 455444444 LONGO XO ON v Y qv Y v T ON QN QN QN a aao 1 0a 2000000 Om 7 8 2202329 CS ADC CONTROL AND CALIBRATION PRIMARY ADC 16 BIT ADC 12 BIT ADC CONTROL VOLTAGE AND CALIBRATION 640x8 DATA FLASH EE mm WATCHDOG PROGRAM FLASH EE INTERVAL COUNTER DOWNLOADER DEBUGGER PROG CLOCK DIVIDER SYNCHRONOUS SERIAL INTERFACE SPI OR PC ASYNCHRONOUS S
91. is Software Program WASP 8051 Assembler Metalink C Compiler Keil Evaluation Copy Limited to 2 Kcode Example Code Documentation CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although WARN NG l lt the ADuC816 features proprietary ESD protection circuitry permanent damage may occur Sept 100 devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Windows is a registered trademark of Microsoft Corporation 48 REV 0 ADuC816 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description 00 10 vi 12 13 14 15 16 19 P1 0 T2 P1 1 T2EX P1 2 DAC IEXC1 P1 3 AIN5 IEXC2 AVpp AGND REFIN REFIN P1 4 P1 6 P1 4 AINI P1 5 AIN2 P1 6 AIN3 P1 7 AIN4 DAC SS MISO RESET P3 0 P3 3 P3 0 RXD P3 1 TXD P3 2 INTO IO IO IO IO IO IO IO IO Port 1 0 can function as a digital input or digital output and has a pull up configu ration as described below for Port 3 P1 0 has an increased current drive sink capability of 10 mA and can also be used to provide a clock input to Timer 2 When Enabled Counter 2 is incremented in response to a negative transition
92. it timer counter TLO serves as 5 bit prescaler 0 1 16 Bit Timer Counter THO and are cascaded there is no prescaler 0 8 Bit Auto Reload Timer Counter THO holds a value which is to be reloaded into TLO each time it overflows 1 1 TLO is an 8 bit timer counter controlled by the standard timer 0 control bits THO is an 8 bit timer only controlled by Timer 1 control bits 52 REV 0 ADuC816 TCON Timer Counter 0 and 1 Control Register SFR Address 88H Power On Default Value 00H Bit Addressable Yes TF1 TR1 TFO TRO IE1 IT1 ITO NOTE These bits are not used in the control of timer counter 0 and 1 but are used instead in the control and monitoring of the external INTO and INTI interrupt pins Table XXIV TCON SFR Bit Designations Bit Name Description 7 1 Timer 1 Overflow Flag Set by hardware on a timer counter 1 overflow Cleared by hardware when the Program Counter PC vectors to the interrupt service routine 6 TRI Timer 1 Run Control Bit Set by user to turn on timer counter 1 Cleared by user to turn off timer counter 1 5 TFO Timer 0 Overflow Flag Set by hardware on a timer counter 0 overflow Cleared by hardware when the PC vectors to the interrupt service routine 4 TRO Timer 0 Run Control Bit Set by user to turn on timer counter 0 Cleared by user to turn off timer counter 0 3 1 External Interrupt 1 INT1 Flag Set by hardware by a falling edge or zero level being appl
93. ital Input Voltage to DGND 0 3V to DVpp 0 3 V Not to Scale Digital Output Voltage to DGND 0 3 V to DVpp 0 3 V Operating Temperature Range 40 C to 85 Storage Temperature Range 65 C to 150 Junction Temperature 150 Oja Thermal Impedance 90 C W Lead Temperature Soldering Vapor Phase 60 sec 215 C Infrared 15 SEC ere es 220 C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability AGND and DGND are shorted internally on the ADuC816 to P1 2 to P1 7 pins operating in analog or digital input modes ORDERING GUIDE Model Temperature Range Package Description Package Option ADuC816BS 40 to 85 52 Lead Plastic Quad Flatpack S 52 QuickStart Development System Model Description EVAL ADUC816QS Development System for the ADuC816 MicroConverter Containing Evaluation Board Serial Port Cable Plug In Power Supply Windows Serial Downloader WSD Windows Debugger DeBug Windows ADuC816 Simulator ADSIM Windows ADC Analys
94. l the chip will function equally well at any power supply level between 2 7 V and 5 25 V Separate analog and digital power supply pins AVpp and DVpp respectively allow AVpp to be kept relatively free of noisy digital signals often present on the system DVDD line In this mode the part can also operate with split supplies that is using different voltage supply levels for each supply For example this means that the system can be designed to operate with a DVpp voltage level of 3 V while the AVpp level can be at 5 V or vice versa if required A typical split supply configuration is shown in Figure 49 DIGITAL SUPPLY ANALOG SUPPLY Figure 49 External Dual Supply Connections 63 ADuC816 As an alternative to providing two separate power supplies AVpp quiet by placing a small series resistor and or ferrite bead between it and DVpp and then decoupling AVpp separately to ground An example of this configuration is shown in Figure 50 With this configuration other analog circuitry such as op amps voltage reference etc can be powered from the AVpp supply line as well DIGITAL SUPPLY J dp YQ d BEAD 1 60 10pF 7 Figure 50 External Single Supply Connections Notice that in both Figure 49 and Figure 50 a large value 10 reservoir capacitor sits on DVpp and a separate 10 uF capacitor sits on AVpp Also local small value 0 1 capacitors located at e
95. le Pin Emulation Mode 65 Flash EE Memory Overview 37 Enhanced Hooks Emulation Mode 66 Flash EE Memory and the ADuC816 37 Typical System Configuration 66 ADuC816 Flash EE Memory Reliability 37 QUICKSTART DEVELOPMENT SYSTEM 67 Using the Flash EE Program Memory 38 Download In Circuit Serial Downloader 67 Flash EE Program Memory Security 38 DeBug In Circuit Debugger 67 Using the Flash EE Data Memory 39 ADSIM Windows Simulator 67 ECON Flash EE Memory Control SFR 39 OUTLINE DIMENSIONS sees 68 Flash EE Memory Timing 40 2 REV 0 ADuC816 SPEC 0 NS My 2 7 V to 3 6 Vor 4 75 V to 5 25 V DVpp 2 7 V to 3 6 V or 4 75 V to 5 25 V REFIN 2 5 V REFIN AGND AGND DGND 0 V XTAL1 XTAL2 32 768 kHz Crystal all specifications to Tmax unless otherwise noted Parameter ADuC816BS Unit Test Conditions Comments ADC SPECIFICATIONS Conversion Rate 5 4 Hz min On Both Channels 105 Hz max Programmable in 0 732 ms Increments Primary ADC No Missing Codes 16 Bits min 20 Hz Update Rate Resolution 13 Bits p p typ Range 20 mV
96. le is fed to the difference amplifier along with the output of the feedback DAC The differ ence between these two signals is integrated and fed to the comparator The output of the comparator provides the input to the feedback DAC so the system functions as a negative feedback loop that tries to minimize the difference signal The digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the comparator This duty cycle data can be recovered as a data word using a subsequent digital filter stage The sampling frequency of the modulator loop is many times higher than the bandwidth of the input signal The integrator in the modulator shapes the quantization noise which results from the analog to digital con version so that the noise is pushed toward one half of the modulator frequency Digital Filter The output of the sigma delta modulator feeds directly into the digital filter The digital filter then band limits the response to a frequency significantly lower than one half of the modulator REV 0 frequency In this manner the 1 bit output of the comparator is translated into a band limited low noise output from the ADuC816 ADCs The ADuC816 filter is a low pass Sinc or sinx x filter whose primary function is to remove the quantization noise introduced at the modulator The cutoff frequency and decimated output data rate of the filter are programmable via the
97. le serial download mode when pulled low through a resistor at the end of an external RESET assertion or as part of a device power cycle Address Latch Enable Logic Output This output is used to latch the low byte and page byte for 24 bit data address space accesses of the address to external memory during external code or data memory access cycles It is activated every six oscillator periods except during an external data memory access It can be disabled by setting the PCON 4 bit in the PCON SFR 20 REV 0 ADuC816 Mnemonic Type Description 49 52 P0 0 P0 3 IO AD0 AD3 P0 4 P0 7 Io AD4 AD7 P0 0 PO0 3 these pins are part of PortO which is an 8 bit open drain bidirectional I O port Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs An external pull up resistor will be required on PO out put outputs to force a valid logic high level externally Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this application it uses strong internal pull ups when emitting 1s P0 4 P0 7 these pins are part of PortO which is an 8 bit open drain bidirectional I O port Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this applicat
98. lected trip point 5 PSMI Power Supply Monitor Interrupt Bit This bit will be set high by the MicroConverter if either CMPA or CMPD are low indicating low analog or digital supply The PSMI bit can be used to interrupt the processor Once CMPD and or CMPA return and remain high a 250 ms counter is started When this counter times out the PSMI interrupt is cleared PSMI can also be written by the user However if either com parator output is low it is not possible for the user to clear PSMI 4 TPDI DVDD Trip Point Selection Bits 3 TPDO These bits select the DVDD trip point voltage as follows TPDI TPDO Selected DVDD Trip Point V 0 0 4 63 0 1 3 08 1 0 2 93 1 1 2 63 TPAI AVDD Trip Point Selection Bits 1 TPAO These bits select the AVDD trip point voltage as follows 1 TPAO Selected AVDD Trip Point V 0 0 4 63 0 1 3 08 1 0 2 93 1 1 2 63 0 PSMEN Power Supply Monitor Enable Bit Set to 1 by the user to enable the Power Supply Monitor Circuit Cleared to 0 by the user to disable the Power Supply Monitor Circuit REV 0 47 ADuC816 SERIAL PERIPHERAL INTERFACE The ADuC816 integrates a complete hardware Serial Peripheral Interface SPI interface on chip SPI is an industry standard syn chronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously i e full duplex It should be noted that the SPI physical interface is shared with the in
99. ll start at the next valid baud rate clock The TI flag 18 set as soon as the stop bit appears on TXD Reception for Mode 2 is similar to that of Mode 1 The eight data bytes are input at RXD LSB first and loaded onto the receive shift register When all eight bits have been clocked in the following events occur The eight bits in the receive shift register are latched into SBUF The ninth data bit is latched into RB8 in SCON The Receiver interrupt flag RI is set if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and Either SM2 0 or SM2 1 and the received stop bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set Mode 3 9 Bit UART with Variable Baud Rate Mode 3 is selected by setting both SMO and SM1 In this mode the 8051 UART serial port operates in 9 bit mode with a variable baud rate determined by either Timer 1 or Timer 2 The opera tion of the 9 bit UART is the same as for Mode 2 but the baud rate can be varied as for Mode 1 In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 UART Serial Port Baud Rate Generation Mode 0 Baud Rate Generation The baud rate in Mode 0 is fixed Mode 0 Baud Rate Core C
100. lled low they will source current because of the internal pull ups With 0s written to them both these pins will drive a logic low output voltage VOL and will be capable of sinking 10 mA compared to the standard 1 6 mA sink capa bility on the other port pins These pins also have various secondary functions described in Table XXI Table XXI Port 1 Alternate Pin Functions Pin Alternate Function P1 0 T2 Timer Counter 2 External Input 1 1 T2EX Timer Counter 2 Capture Reload Trigger The remaining Port 1 pins 1 2 1 7 can only be configured as Analog Input ADC Analog Output DAC or Digital Input pins By power on default these pins are configured as Analog Inputs i e 1 written in the corresponding Port 1 register bit To configure any of these pins as digital inputs the user should write a 0 to these port bits to configure the corresponding pin as a high impedance digital input Port 2 is a bidirectional port with internal pull up resistors directly controlled via the P2 SFR SFR address A0 hex Port 2 pins that have 1 written to them are pulled high by the internal pull up resistors and in that state they can be used as inputs As inputs Port 2 pins being pulled externally low will source current because of the internal pull up resistors Port 2 emits the high order REV 0 address bytes during fetches from external program memory and middle and high order address bytes during accesse
101. lock Frequency 12 NOTE In these descriptions Core Clock Frequency refers to the core clock frequency selected via the CD0 2 bits in the PLLCON SFR Mode 2 Baud Rate Generation The baud rate in Mode 2 depends on the value of the SMOD bit in the PCON SFR If SMOD 0 the baud rate is 1 64 of the core clock If SMOD 1 the baud rate is 1 32 of the core clock Mode 2 Baud Rate 2500 64 x Core Clock Frequency Modes 1 and 3 Baud Rate Generation The baud rates in Modes 1 and 3 are determined by the overflow rate in Timer 1 or Timer 2 or both one for transmit and the other for receive REV 0 ADuC816 Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows Modes 1 and 3 Baud Rate 25M0D 32 x Timer 1 Overflow Rate The Timer 1 interrupt should be disabled in this application The Timer itself can be configured for either timer or counter opera tion and in any of its three running modes In the most typical application it is configured for timer operation in the autoreload mode high nibble of TMOD 0100Binary In that case the baud rate is given by the formula Modes 1 and 3 Baud Rate 25 00 32 x Core Clock 12 x 256 TH1 A very low baud rate can also be achieved with Timer 1 by leaving the Timer 1 interrupt enabled and configuring the timer to run as a 16 bit timer hi
102. ly by reading the SPIDAT SFR 6 WCOL Write Collision Error Bit Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress Cleared by user code 5 SPE SPI Interface Enable Bit Set by user to enable the SPI interface Cleared by user to enable the interface 4 SPIM SPI Master Slave Mode Select Bit Set by user to enable Master Mode operation SCLOCK is an output Cleared by user to enable Slave Mode operation SCLOCK is an input 3 CPOL Clock Polarity Select Bit Set by user if SCLOCK idles high Cleared by user if SCLOCK idles low 2 CPHA Clock Phase Select Bit Set by user if leading SCLOCK edge is to transmit data Cleared by user if trailing SCLOCK edge is to transmit data 48 REV 0 ADuC816 Table XIX SPICON SFR Bit Designations continued Bit Name Description 1 SPRI SPI Bit Rate Select Bits SPRO These bits select the SCLOCK rate bit rate in Master Mode as follows SPRI SPRO Selected Bit Rate 0 0 2 0 1 4 1 0 8 1 1 16 In SPI Slave Mode 1 SPIM 0 the logic level on the external SS pin Pin 13 can be read via the SPRO bit NOTE The CPOL and CPHA bits should both contain the same values for master and slave devices SPIDAT SPI Data Register Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface SFR Address F7
103. m the PLL is halted The on chip peripherals con tinue to receive the clock and remain functional The CPU status is preserved with the stack pointer program counter and all other internal registers maintain their data during idle mode Port pins and DAC output pins also retain their states and ALE and PSEN outputs go high in this mode The chip will recover from idle mode upon receiving any enabled interrupt or on receiving a hardware reset 64 In power down mode both the PLL and the clock to the core are stopped The on chip oscillator can be halted or can continue to oscillate depending on the state of the oscillator power down bit OSC PD in the PLLCON SFR The TIC being driven directly from the oscillator can also be enabled during power down All other on chip peripherals however are shut down Port pins retain their logic levels in this mode but the DAC output goes to a high impedance state three state while ALE and PSEN outputs are held low During full power down mode the ADuC816 consumes a total of 5 typically There are five ways of terminating power down mode Asserting the RESET Pin 15 Returns to normal mode all registers are set to their default state and program execution starts at the reset vector once the Reset pin is deasserted Cycling Power registers are set to their default state and program execution starts at the reset vector Time Interval Counter TIC Interrupt Power down mod
104. n by the user to enable individual interrupt sources while the Interrupt Priority registers Source Vector Address allow the user to select one of two priority levels for each interrupt IEO 0003 Hex An interrupt of a high priority may interrupt the service routine TFO 000B Hex of a low priority interrupt and if two interrupts of different priority IE1 0013 Hex occur at the same time the higher level interrupt will be serviced 001 first An interrupt cannot be interrupted by another interrupt of RI TI 0023 Hex the same priority level If two interrupts of the same priority level TF2 EXF2 002B Hex occur simultaneously a polling sequence is observed as shown RDY0 RDY1 ADC 0033 Hex in Table XXXIII ISPI 003B Hex PSMI 0043 Hex Table XXXIII Priority within an Interrupt Level TII 0053 Hex Source Priority Description NOSE 0028 Hex The watchdog can be configured to generate an interrupt instead of a reset when it PSMI 1 Highest Power Supply Monitor Interrupt times out This is used for logging errors or to examine the internal status of the WDS 2 Watchdog Interrupt microcontroller core to understand from a software debug point of view why a 3 External Interrupt 0 dia The a ER x RDYO RDY1 4 ADC Interrupt to disable the interrupt via the global disable bit EA in the IE SFR This is TFO 5 Timer Counter 0 Interrupt done to ensure that the interrupt will always be responded to if
105. ng used to monitor the system it can alternatively be used as a timer The prescaler is used to set the timeout period in which an interrupt will be generated See also Note 1 Table XXXIV in the Interrupt System section 2 WDS Watchdog Status Bit Set by the Watchdog Controller to indicate that a watchdog timeout has occurred Cleared by writing a 0 or by an external hardware reset It is not cleared by a watchdog reset 1 WDE Watchdog Enable Bit Set by user to enable the watchdog and clear its counters If this bit is not set by the user within the watchdog timeout period the watchdog will generate a reset or interrupt depending on WDIR Cleared under the following conditions User writes 0 Watchdog Reset WDIR 0 Hardware Reset PSM Interrupt 0 WDWR Watchdog Write Enable Bit To write data into the WDCON SFR involves a double instruction sequence The WDWR bit must be set and the very next instruction must be a write instruction to the WDCON SER e g CLR EA disable interrupts while writing to WDT SETB WDWR allow write WDCON MOV WDCON 72h enable for 2 05 timeout SET B EA enable interrupts again if 46 REV 0 ADuC816 Power Supply Monitor As its name suggests the Power Supply Monitor once enabled monitors both supplies AVDD or DVDD on the ADuC8106 It will indicate when any of the supply pins drop below one of four user selectable voltage trip points from 2 63 V to 4 63 V F
106. o different input conditions These are zero scale and full scale points These points are derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration The result of the zero scale calibration conversion is stored in the Offset Calibration Registers for the appropri ate ADC The result of the full scale calibration conversion is stored in the Gain Calibration Registers for the appropriate ADC With these readings the calibration logic can calculate the offset and the gain slope for the input to output transfer function of the converter During an internal zero scale or full scale calibration the respective zero input and full scale input are automatically connected to the ADC input pins internally to the device A system calibration however expects the system zero scale and system full scale voltages to be applied to the external ADC pins before the calibration mode is initiated In this way external ADC errors are taken into account and minimized as a result of system calibration It should also be noted that to optimize calibration accuracy all ADuC816 ADC calibrations are carried out auto matically at the slowest update rate Internally in the ADuC816 the coefficients are normalized before being used to scale the words coming out of the digital filter The offset calibration coefficient is subtracted from the result prior to
107. oad capability very low baud rates are still possible Timer 2 is selected as the baud rate generator by setting the TCLK and or RCLK in T2CON The baud rates for transmit and receive can be simultaneously different Setting RCLK and or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 41 In this case the baud rate is given by the formula Modes 1 and 3 Baud Rate Core Clk 32 x 65536 RCAP2H RCAP2L Table XXIX shows some commonly used baud rates and how they might be calculated from a core clock frequency of 1 5728 MHz and 12 5829 MHz Table XXIX Commonly Used Baud Rates Timer 2 Ideal Core RCAP2H RCAP2L Actual Baud CLK Value Value Baud Error 19200 12 58 1 FFh 20 ECh 19661 2 4 9600 12 58 1 FFh 41 D7h 9591 0 1 2400 12 58 l FFh 164 5 2398 0 1 1200 12 58 2 FEh 72 B8h 1199 0 1 9600 1 57 1 FFh 5 FBh 9830 2 4 2400 1 57 1 FFh 20 ECh 2457 2 4 1200 1 57 1 FFh 41 D7h 1199 0 1 TIMER 1 OVERFLOW SMOD TIMER 2 T OVERFLOW Ene CLOCK H2 BIT AM RELOAD 2 TIMER 2 INTERRUPT THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 41 Timer 2 59 REV 0 UART Baud Rates ADuC816 INTERRUPT SYSTEM The ADuC816 provides a total of twelve interrupt sources with two priority levels The control and configuration of the int
108. on the T2 input pin Port 1 1 can function as a digital input or digital output and has a pull up configu ration as described below for Port 3 P1 1 has an increased current drive sink capability of 10 mA and can also be used to provide a control input to Timer 2 When Enabled a negative transition on the T2EX input pin will cause a Timer 2 capture or reload event Port 1 2 This pin has no digital output driver it can function as a digital input for which 0 must be written to the port bit As a digital input P1 2 must be driven high or low externally The voltage output from the DAC can also be configured to appear at this pin If the DAC output is not being used one or both of the excita tion current sources 200 or 2 x 200 uA can be programmed to be sourced at this pin Port 1 3 This pin has no digital output driver it can function as a digital input for which 0 must be written to the port bit As a digital input P1 3 must be driven high or low externally This pin can provide an analog input AIN5 to the auxiliary ADC and one or both of the excitation current sources 200 or 2 x 200 uA can be programmed to be sourced at this pin Analog Supply Voltage 3 V or 5 V Analog Ground Ground reference pin for the analog circuitry Reference input negative terminal Reference input positive terminal Port 1 4 to P1 6 These pins have no digital output drivers they can function as digital inputs for which 0
109. oon as the byte of data has been received 4 REN Serial Port Receive Enable Bit Set by user software to enable serial port reception Cleared by user software to disable serial port reception 3 T B8 Serial Port Transmit Bit 9 The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3 2 RB8 Serial port Receiver Bit 9 The ninth data bit received in Modes 2 and 3 is latched into RB8 For Mode 1 the stop bit is latched RB8 1 TI Serial Port Transmit Interrupt Flag Set by hardware at the end of the eighth bit in Mode 0 or at the beginning of the stop bit in Modes 1 2 and 3 TI must be cleared by user software 0 RI Serial Port Receive Interrupt Flag Set by hardware at the end of the eighth bit in mode 0 or halfway through the stop bit in Modes 1 2 and 3 RI must be cleared by software REV 0 57 ADuC816 Mode 0 8 Bit Shift Register Mode Mode 0 is selected by clearing both the SMO and SM1 bits in the SFR SCON Serial data enters and exits through RXD TXD outputs the shift clock Eight data bits are transmitted or received Transmission is initiated by any instruction that writes to SBUF The data is shifted out of the RXD line The eight bits are trans mitted with the least significant bit LSB first as shown in Figure 39 MACHINE gt lt MACHINE CYCLE 1 CYCLE 2 1 32 3 sa ss se s 2 33 4 MACHINE gt lt MACHINE CYCLE 7 CYCLE 8
110. or correct operation of the Power Supply Monitor function AVpp must be equal to or greater than 2 7 V Monitor function is controlled via the PSMCON SFR If enabled via the IEIP2 PSMCON SER This bit will not be cleared until the failing power supply has returned above the trip point for at least 250 ms This monitor function allows the user to save working registers to avoid possible data loss due to the low supply condi tion and also ensures that normal code execution will not resume until a safe supply level has been well established The supply monitor is also protected against spurious glitches trig gering the interrupt circuit SFR the monitor will interrupt the core using the PSMI bit in the PSMCON Power Supply Monitor Control Register SFR Address DFH Power On Default Value DEH Bit Addressable No CMPD CMPA PSMI TPDO 1 PSMEN Table XVIII PSMCON SFR Bit Designations Bit Name Description 7 CMPD DVDD Comparator Bit This is a read only bit and directly reflects the state of the DVDD comparator Read 1 indicates the DVDD supply is above its selected trip point Read 0 indicates the DVDD supply is below its selected trip point 6 CMPA AVDD Comparator Bit This is a read only bit and directly reflects the state of the AVDD comparator Read 1 indicates the AVDD supply is above its selected trip point Read 0 indicates the AVDD supply is below its se
111. ory Reliability The Flash EE Program and Data Memory arrays on the ADuC816 are fully qualified for two key Flash EE memory characteristics namely Flash EE Memory Cycling Endurance and Flash EE Memory Data Retention Endurance quantifies the ability of the Flash EE memory to be cycled through many Program Read and Erase cycles In real terms a single endurance cycle is composed of four independent sequential events These events are defined as a initial page erase sequence b read verify sequence c byte program sequence d second read verify sequence A single Flash EE Memory Endurance Cycle In reliability qualification every byte in both the program and data Flash EE memory is cycled from 00 hex to FFhex until a first fail is recorded signifying the endurance limit of the on chip Flash EE memory As indicated in the specification pages of this data sheet the ADuC816 Flash EE Memory Endurance qualification has been carried out in accordance with JEDEC Specification 117 over the industrial temperature range of 40 C 25 C and 85 The results allow the specification of a minimum endurance figure over supply and temperature of 100 000 cycles with an endurance figure of 700 000 cycles being typical of operation at 25 C Retention quantifies the ability of the Flash EE memory to retain its programmed data over time Again the ADuC816 has been qualified in accordance with the formal JEDEC Retention Life time Specif
112. program memory fetches Port 0 serves as a multiplexed address data bus It emits the low byte of the program counter PCL as an address and then goes into a float state awaiting the arrival of the code byte from the program memory During the 62 time that the low byte of the program counter is valid on the signal ALE Address Latch Enable clocks this byte into an address latch Meanwhile Port 2 P2 emits the high byte of the program counter PCH then PSEN strobes the EPROM and the code byte is read into the ADuC816 ADuC816 EPROM D0 D7 INSTRUCTION LATCH RU AT Figure 43 External Program Memory Interface Note that program memory addresses are always 16 bits wide even in cases where the actual amount of program memory used is less than 64 Kbytes External program execution sacrifices two of the 8 bit ports PO and P2 to the function of addressing the program memory While executing from external program memory Ports 0 and 2 can be used simultaneously for read write access to exter nal data memory but not for general purpose I O Though both external program memory and external data memory are accessed by some of the same pins the two are completely independent of each other from a software point of view For example the chip can read write external data memory while executing from external program memory Figure 44 shows a hardware configuration for accessing up to 64 Kbytes of external RA
113. pt Bit Set when the 8 bit Interval Counter matches the value in the INTVAL SFR Cleared by user software 1 TIEN Time Interval Enable Bit Set by user to enable the 8 bit time interval counter Cleared by user to disable and clear the contents of the interval counter 0 TCEN Time Clock Enable Bit Set by user to enable the time clock to the time interval counters Cleared by user to disable the clock to the time interval counters and clear the time interval SFRs The time registers HTHSEC SEC MIN and HOUR can be written while TCEN is low 44 REV 0 ADuC816 INTVAL Function SFR Address Power On Default Value Bit Addressable Valid Value HTHSEC Function SFR Address Power On Default Value Bit Addressable Valid Value SEC Function SFR Address Power On Default Value Bit Addressable Valid Value MIN Function SFR Address Power On Default Value Bit Addressable Valid Value HOUR Function SFR Address Power On Default Value Bit Addressable Valid Value REV 0 User Time Interval Select Register User code writes the required time interval to this register When the 8 bit interval counter is equal to the time interval value loaded in the INTVAL SFR the TII bit TIMECON 2 bit is set and generates an interrupt if enabled See IEIP2 SFR description under Interrupt System later in this data sheet A6H 00H No 0 to 255 decimal Hundredths Seconds Time Register This register is inc
114. r analog circuitry which could happen if the user placed a noisy digital chip on the left half of the board in Figure 51c Whenever possible avoid large discontinuities in the ground plane s such as are formed by a long trace on the same layer since they force return signals to travel a longer path And of course make all connections to the ground plane directly with little or no trace separating the pin from its via to ground If the user plans to connect fast logic signals rise fall time lt 5 ns to any of the ADuC816 s digital inputs add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the ADuC816 input pins A value of 100 or 200 Q is usually sufficient to prevent high speed signals from coupling capacitively into the ADuC8106 and affecting the accuracy of ADC conversions ADuC816 System Self Identification In some hardware designs it may be an advantage for the soft ware running on the ADuC816 target to identify the host Micro Converter For example code running on the ADuC816 may be used at future date to run on an ADuC816 MicroConverter host and the code may be required to operate differently The CHIPID SFR is a read only register located at SFR address C2 hex The top nibble of this byte is set to 1 to designate an ADuC824 host For an ADuC824 host the CHIPID SFR will contain the value 0 in the upper nibble REV 0 OTHER HARDWARE CONSIDERATIONS facilitat
115. r and modulator are held in a reset state although the modulator clocks are still provided 0 1 0 Single Conversion Mode In Single Conversion Mode a single conversion is performed on the enabled ADC On completion of the conversion the ADC data regis ters ADCOH M and or ADCIH L are updated the relevant flags in the ADCSTAT SFR are written and power down is re entered with the MD2 MDO accordingly being written to 000 0 1 1 Continuous Conversion In continuous conversion mode the ADC data registers are regularly updated at the selected update rate see SF register 1 0 0 Internal Zero Scale Calibration Internal short automatically connected to the enabled ADC s 1 0 1 Internal Full Scale Calibration Internal or External as determined by XREFO and XREF bits in ADC0 1CON is automatically connected to the ADC input for this calibration 1 1 0 System Zero Scale Calibration User should connect system zero scale input to the ADC input pins as selected by and ACH1 ACHO bits in the ADC0 1 CON register 1 1 1 System Full Scale Calibration User should connect system full scale input to the ADC input pins as selected by and 1 bits in the ADC0 1 CON register NOTES 1 2 3 Any change to the MD bits will immediately reset both ADCs A write to the MD2 0 bits with no change is also treated as reset See exception to this in Note 3 below If ADCOCON is written when ADOEN 1 or if ADOEN is
116. r input voltage ranges Bipolar input ranges do not imply that the part can handle negative voltages with respect to system AGND Unipolar and bipolar signals on the AIN input on the primary ADC are referenced to the voltage on the respective AIN input For example if AIN is 2 5 V and the primary ADC is config ured for an analog input range of 0 mV to 20 mV the input voltage range on the AIN input is 2 5 V to 2 52 V If AIN is 2 5 V and the ADuC816 is configured for an analog input range of 1 28 V the analog input range on the AIN input is 1 22 V to 3 78 V i e 2 5 V 1 28 V As mentioned earlier the auxiliary ADC input is a single ended input with respect to the system AGND In this context a bipolar signal on the auxiliary ADC can only span 30 mV negative with respect to AGND before violating the voltage input limits for this ADC Bipolar or unipolar options are chosen by programming the Primary and Auxiliary Unipolar enable bits in the ADCOCON and ADCICON SFRs respectively This programs the relevant ADC for either unipolar or bipolar operation Programming for either unipolar or bipolar operation does not change any of the input signal conditioning it simply changes the data output coding and the points on the transfer function where calibrations occur When an ADC is configured for unipolar operation the output coding is natural straight binary with a zero differential input voltage resulting in code of
117. ram Status Word which contains several bits reflecting the current status of the CPU as detailed in Table I SFR Address DOH Power ON Default Value 00H Bit Addressable Yes CY AC FO RS1 RSO OV F1 P Table I PSW SFR Bit Designations Bit Name Description 7 Carry Flag 6 AC Auxiliary Carry Flag 5 FO General Purpose Flag 4 RS1 Register Bank Select Bits 3 RSO RS1 RSO Selected Bank 0 0 0 0 1 1 1 0 2 1 1 3 2 OV Overflow Flag 1 Fl General Purpose Flag 0 Power Control SFR The Power Control PCON register contains bits for power saving options and general purpose status flags as shown in Table II SFR Address 87H Power ON Default Value 00H Bit Addressable No SMOD SERIPD INTOPD ALEOFF PD IDL Table II PCON SFR Bit Designations Bit Name Description 7 SMOD Double UART Baud Rate 6 SERIPD 8 Power Down Interrupt Enable 5 INTOPD INTO Power Down Interrupt Enable 4 ALEOFF Disable ALE Output 3 GF1 General Purpose Flag Bit 2 General Purpose Flag Bit 1 PD Power Down Mode Enable 0 IDL Idle Mode Enable 23 ADuC816 SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general purpose register banks reside in the SFR area The SFR registers include control configuration and data registers that provide an interface between the CPU and
118. rated at 25 C with DVpp 5 V yielding this full scale error If user power supply or temperature conditions are signifi cantly different from these an Internal Full Scale Calibration will restore this error to this level Gain Error Drift is a span drift To calculate Full Scale Error Drift add the Offset Error Drift to the Gain Error Drift times the full scale input gt The auxiliary ADC is factory calibrated at 25 with AVpp DVpp 5 V yielding this full scale error of 2 5 LSB A system zero scale and full scale calibration will remove this error altogether linearity and AC Specifications are calculated using reduced code range of 48 to 4095 0 to Vref reduced code range of 48 to 3995 0 to Vpp Gain Error is a measure of the span error of the DAC In general terms the bipolar input voltage range to the primary ADC is given by Range apc 28 125 where Veer REFIN to REFIN voltage and Vggg 1 25 V when internal ADC Vpgr is selected RN decimal equivalent of RN2 RN1 e g 2 5 V and RN2 RN1 1 1 0 the Rangeapc 1 28 V In unipolar mode the effective range is 0 V to 1 28 V in our example 91 25 V is used as the reference voltage to the ADC when internal V is selected via XREFO and XREFI bits in ADCOCON and ADCICON respectively 101 bipolar mode the Auxiliary ADC can only be driven to a minimum of 30 mV as indicated by the Auxiliary ADC absolut
119. re Clock Frequency 1 0 0 0 786432 1 0 1 0 393216 1 1 0 0 196608 1 1 1 0 098304 42 REV 0 ADuC816 Time Interval Counter TIC A time interval counter is provided on chip for counting longer intervals than the standard 8051 compatible timers are capable of The TIC is capable of timeout intervals ranging from 1 128th second to 255 hours Furthermore this counter is clocked by the crystal oscillator rather than the PLL and thus has the ability to remain active in power down mode and time long power down intervals This has obvious applications for remote battery powered sensors where regular widely spaced readings are required Six SFRs are associated with the time interval counter TIMECON being its control register Depending on the configuration of the ITO and IT1 bits in TIMECON the selected time counter register TCEN 32 768kHz EXTERNAL CRYSTAL 8 BIT PRESCALER overflow will clock the interval counter When this counter is equal to the time interval value loaded in the INTVAL SFR the TII bit TIMECON 2 is set and generates an interrupt if enabled See IEIP2 SFR description under Interrupt System later in this data sheet If the ADuC816 is in power down mode again with TIC interrupt enabled the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053 hex The TIC related SFRs are described in Table XVI Note also that the timebas
120. remented in 1 128 second intervals once TCEN in TIMECON is active The HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register A2H 00H No 0 to 127 decimal Seconds Time Register This register is incremented in 1 second intervals once TCEN in TIMECON is active The SEC SFR counts from 0 to 59 before rolling over to increment the MIN time register A3H 00H No 0 to 59 decimal Minutes Time Register This register is incremented in 1 minute intervals once TCEN in TIMECON is active The MIN counts from 0 to 59 before rolling over to increment the HOUR time register AAH 00H No 0 to 59 decimal Hours Time Register This register is incremented in 1 hour intervals once TCEN in TIMECON is active The HOUR SFR counts from 0 to 23 before rolling over to 0 A5H 00H No 0 to 23 decimal 45 ADuC816 Watchdog Timer The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC816 enters an erroneous state possibly due to a programming error electrical noise or RFI The Watchdog function can be disabled by clearing the WDE Watchdog Enable bit in the Watchdog Control WDCON SFR When enabled the watchdog circuit will generate a system reset or interrupt WDS if the user program fails to set the watchdog WDE bit within a predetermined amount of time see PRE3 0 bits in WDCON The watchdog timer itself is a 16 bit counter
121. s to the 16 bit external data memory space Port 3 is a bidirectional port with internal pull ups directly controlled via the P2 SFR SFR address hex Port 3 pins that have 1s written to them are pulled high by the internal pull ups and in that state they can be used as inputs As inputs Port 3 pins being pulled externally low will source current because of the internal pull ups Port 3 pins also have various secondary functions described in Table XXII Table XXII Port 3 Alternate Pin Functions Pin Alternate Function P3 0 RXD UART Input Pin or Serial Data I O in Mode 0 P3 1 TXD UART Output Pin or Serial Clock Output in Mode 0 P3 2 INTO External Interrupt 0 P3 3 INT1 External Interrupt 1 P3 4 TO Timer Counter 0 External Input P3 5 T1 Timer Counter 1 External Input P3 6 WR External Data Memory Write Strobe P3 7 RD External Data Memory Read Strobe The alternate functions of P1 0 P1 1 and Port 3 pins can only be activated if the corresponding bit latch in the P1 and P3 SFRs contains a 1 Otherwise the port pin is stuck at 0 Timers Counters The ADuC816 has three 16 bit Timer Counters Timer 0 Timer 1 and Timer 2 The Timer Counter hardware has been included on chip to relieve the processor core of the overhead inherent in implementing timer counter functionality in soft ware Each Timer Counter consists of two 8 bit registers THx and TLx x 0 1 and 2 All three can be config
122. ser to halt the 32 kHz oscillator in power down mode Cleared by user to enable the 32 kHz oscillator in power down mode This feature allows the TIC to continue counting even in power down mode 6 LOCK PLL Lock Bit This is a read only bit Set automatically at power on to indicate the PLL loop is correctly tracking the crystal clock If the external crystal becomes subsequently disconnected the PLL will rail and the core will halt Cleared automatically at power on to indicate the PLL is not correctly tracking the crystal clock This may be due to the absence of a crystal clock or an external crystal at power on In this mode the PLL output can be 12 58 MHz 20 5 Reserved for future use should be written with 0 4 LTEA Reading this bit returns the state of the external EA pin latched at reset or power on 3 FINT Fast Interrupt Response Bit Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency regardless of the configuration of the CD2 0 bits see below Once user code has returned from an interrupt the core resumes code execution at the core clock selected by the CD2 0 bits Cleared by user to disable the fast interrupt response feature 2 CD2 CPU Core Clock Divider Bits 1 CD1 This number determines the frequency at which the microcontroller core will operate 0 2 CD1 Core Clock Frequency MHz 0 0 0 12 582912 0 0 1 6 291456 0 1 0 3 145728 0 1 1 1 572864 Default Co
123. set and EXF2 like TF2 can generate an interrupt The Capture Mode is illustrated in Figure 38 The baud rate generator mode is selected by RCLK 1 and or TCLK 1 In either case if Timer 2 is being used to generate baud rate the TF2 interrupt flag will not occur Hence Timer 2 interrupts will not occur so they do not have to be disabled In this mode the EXF2 flag however can still cause interrupts and this can be used as a third external interrupt Baud rate generation will be described as part of the UART serial port operation in the following pages TH2 8 BITS TF2 TIMER INTERRUPT T2EX PIN oo 1 a EXEN2 CONTROL THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 37 Timer Counter 2 16 Bit Autoreload Mode CORE CLK CiT2 0 r T2 Cf 1 PIN CONTROL TR2 CAPTURE TRANSITION DETECTOR RCAP2L RCAP2H TIMER INTERRUPT T2EX PIN 46 an EXEN2 CONTROL THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42 Figure 38 Timer Counter 2 16 Bit Capture Mode 56 REV 0 ADuC816 UART SERIAL INTERFACE while the SFR interface to the UART is comprised of the fol The serial port is full duplex meaning it can transmit and receive lowing registers simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from
124. st 10 ms before the RESET signal is deasserted low by which time the power supply must have reached at least a 2 7 V level The external POR circuit must be opera tional down to 1 2 V or less The timing diagram of Figure 46 illustrates this functionality under three separate events power up brownout and power down Notice that when RESET is asserted high it tracks the voltage on DVpp 2 5V MIN DVpp 10ms 1 2V MAX MIN 1 2V MAX RESET J Figure 46 External POR Timing The best way to implement an external POR function to meet the above requirements involves the use of a dedicated POR chip such as the ADM809 ADM810 SOT 23 packaged PORs from Analog Devices Recommended connection diagrams for both active high ADMS10 and active low ADM809 PORs are shown in Figure 47 and Figure 48 respectively REV 0 Figure 47 External Active High POR Circuit Some active low POR chips such as the ADM809 can be used with a manual push button as an additional reset source as illustrated by the dashed line connection in Figure 48 POWER SUPPLY ADuC816 1kQ POR ACTIVE LOW 1 1 1 1 4 OPTIONAL MANUAL RESET PUSH BUTTON Figure 48 External Active Low POR Circuit Power Supplies The ADuC816 s operational power supply voltage range is 2 7 V to 5 25 V Although the guaranteed data sheet specifications are given only for power supplies within 2 7 V to 3 6 V or 5 of the nominal 5 V leve
125. stem at a byte level although it must first be erased the erase being per formed in page blocks Thus Flash memory is often and more correctly referred to as Flash EE memory EPROM TECHNOLOGY EEPROM TECHNOLOGY SPACE EFFICIENT DENSITY IN CIRCUIT REPROGRAMMABLE FLASH EE MEMORY TECHNOLOGY Figure 25 Flash EE Memory Development Overall Flash EE memory represents a step closer to the ideal memory device that includes nonvolatility in circuit program mability high density and low cost Incorporated in the ADuC816 Flash EE memory technology allows the user to update program code space in circuit without the need to replace one time programmable OTP devices at remote operating nodes Flash EE Memory and the ADuC816 The ADuC816 provides two arrays of Flash EE memory for user applications 8K bytes of Flash EE Program space are provided on chip to facilitate code execution without any external discrete ROM device requirements The program memory can be pro grammed using conventional third party memory programmers This array can also be programmed in circuit using the serial download mode provided A 640 Byte Flash EE Data Memory space is also provided on chip This may be used as a general purpose nonvolatile scratchpad area User access to this area is via a group of six SFRs This space can be programmed at a byte level although it must first be erased in 4 byte pages REV 0 ADuC816 Flash EE Mem
126. sup Pulsewidth of Spike Suppressed 50 ns 7 Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns al SDATA SCLK I LPS LLL LS R STOP START i REPEATED CONDITION CONDITION START Figure 7 12 Interface Timing REV 0 13 ADuC816 Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING CPHA 1 181 SCLOCK Low Pulsewidth 630 ns 8 SCLOCK High Pulsewidth 630 ns 8 tpay Data Output Valid after SCLOCK Edge 50 ns 8 tpsu Data Input Setup Time before SCLOCK Edge 100 ns 8 tDHD Data Input Hold Time after SCLOCK Edge 100 ns 8 tpr Data Output Fall Time 10 25 ns 8 Data Output Rise Time 10 25 ns 8 tsp SCLOCK Rise Time 10 25 ns 8 tsp SCLOCK Fall Time 10 25 ns 8 Characterized under the following conditions a Core clock divider bits CD2 CDI and CDO bits in PLLCON SFR set to 0 1 and 1 respectively i e core clock frequency 1 57 MHz and b SPI bit rate selection bits SPR1 and SPRO bits in SPICON SFR set to 0 and 0 respectively SCLOCK CPOL 0 SCLOCK CPOL 1 MOSI ipsu tou 14 BITS 6 1 LSB IN Figure 8 SPI Master Mode Timing CPHA 1 REV 0 ADuC816 Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING CPHA 0 ts SCLOCK Low Pulsewidth 630 ns 9 tsH SCLOCK High Pulsewidth 630 ns 9 tpay Data Output Valid after SCLOCK
127. ted together somewhere else at the system s power supply for example they cannot be con nected again near the ADuC816 since a ground loop would result In these cases tie the ADuC816 s AGND and DGND pins all to the analog ground plane as illustrated in Figure 51b In systems with only one ground plane ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa The ADuC816 can then be placed between the digital and analog sections as illustrated in Figure 51c REV 0 ADuC816 A PLACE DIGITAL COMPONENTS HERE COMPONENTS HERE AGND DGND B PLACE ANALOG puo E PLACE DIGITAL i COMPONENTS COMPONENTS HERE mmm DGND PLACE ANALOG 4 PLACE DIGITAL COMPONENTS COMPONENTS HERE Figure 51 System Grounding Schemes In all of these scenarios and in more complicated real life appli cations keep in mind the flow of current from the supplies and back to ground Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations For example do not power components on the analog side of Figure 51b with DVpp since that would force return currents from DVpp to flow through AGND Also try to avoid digital currents flowing unde
128. tempting to read the op codes from internal memory This mode is deactivated by initiating a code erase command in serial download or parallel programming modes REV 0 ADuC816 Serial Safe Mode This mode disables serial download capability on the device If Serial Safe mode is activated and an attempt is made to reset the part into serial download mode 1 RESET asserted and deasserted with PSEN low the part will interpret the serial download reset as a normal reset only It will therefore not enter serial download mode but only execute a normal reset sequence Serial Safe mode can only be disabled by initiating a code erase command in parallel programming mode Using the Flash EE Data Memory The user Flash EE data memory array consists of 640 bytes that are configured into 160 00H to 9FH 4 byte pages as shown in Figure 29 9FH 1 BYTE1 Figure 29 Flash EE Data Memory Configuration As with other ADuC816 user peripheral circuits the interface to this memory space is via a group of registers mapped in the SFR space A group of four data registers EDATA1 4 are used to hold 4 byte page data just accessed EADRL is used to hold the 8 bit address of the page to be accessed Finally ECON is an 8 bit control register that may be written with one of five Flash EE memory access commands to trigger various read write erase and verify functions These registers can be summarized as follows
129. ter SFR Address Primary ADC Offset Coefficient High Byte E3H Primary ADC Offset Coefficient Middle Byte E2H Power On Default Value 8000H OFOM Respectively Bit Addressable No Both Registers OF1H OFIL Auxiliary ADC Offset Calibration Registers These two 8 bit registers hold the 16 bit offset calibration coefficient for the Auxiliary ADC These registers are configured at power on with a factory default value of 8000Hex However these bytes will be automatically overwritten if an internal or system zero scale calibration is initiated by the user via the MD2 0 bits in the ADCMODE register SFR Address OF1H Auxiliary ADC Offset Coefficient High Byte E5H OFIL Auxiliary ADC Offset Coefficient Low Byte E4H Power On Default Value 8000H 1 and OFIL Respectively Bit Addressable No Both Registers GNOHIGNOM Primary ADC Gain Calibration Registers These two 8 bit registers hold the 16 bit gain calibration coefficient for the Primary ADC These registers are configured at power on with a factory calculated internal full scale calibration coefficient Every device will have an individual coefficient However these bytes will be automatically overwritten if an internal or system full scale calibration is initiated by the user via 2 0 bits in the ADCMODE register SFR Address GNOH Primary ADC Gain Coefficient High Byte EBH GNOM Primary ADC Gain Coefficient Middle Byte EAH Power On Default Value Configured
130. ter banks form a block of directly addressable bit locations at bit addresses 00H through 7FH The stack can be located anywhere in the internal memory address space and the stack depth can be expanded up to 256 bytes GENERAL PURPOSE AREA BANKS SELECTED VIA 1 BITS IN PSW 114 BIT ADDRESSABLE BIT ADDRESSES 10 4 FOUR BANKS OF EIGHT REGISTERS 01 lt RO R7 4 RESET VALUE OF 00 4 STACK POINTER Figure 15 Lower 128 Bytes of Internal Data Memory REV 0 ADuC816 Reset initializes the stack pointer to location 07 hex and increments it once to start from locations 08 hex which is also the first regis ter RO of register bank 1 Thus if one is going to use more than one register bank the stack pointer should be initialized to an area of RAM not used for data storage The SFR space is mapped to the upper 128 bytes of internal data memory space and accessed by direct addressing only It provides an interface between the CPU and all on chip peripherals A block diagram showing the programming model of the ADuC816 via the SFR area is shown in Figure 16 A complete SFR map is shown in Figure 17 640 BYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH EE DATA MEMORY DUAL SIGMA DELTA ADCs OTHER ON CHIP PERIPHERALS TEMPERATURE SENSOR CURRENT SOURCES 12 BIT DAC SERIAL I O WDT PSM TIC 8 KBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH EE PROGRAM MEMORY 128 BYTE
131. terface and therefore the user can only enable one or the other interface at any given time see SPE in SPICON below The system can be configured for Master or Slave opera tion and typically consists of four pins namely MISO Master In Slave Out Data I O Pin Pin 14 The MISO master in slave out pin is configured as an input line in master mode and an output line in slave mode The MISO line on the master data in should be connected to the MISO line in the slave device data out The data is transferred as byte wide 8 bit serial data MSB first MOSI Master Out Slave In Pin Pin 27 The MOSI master out slave in pin is configured as an output line in master mode and an input line in slave mode The MOSI line on the master data out should be connected to the MOSI line in the slave device data in The data is transferred as byte wide 8 bit serial data MSB first SCLOCK Serial Clock I O Pin Pin 26 The master clock SCLOCK is used to synchronize the data being transmitted and received through the MOSI and MISO data lines A single data bit is transmitted and received in each SCLOCK period Therefore a byte is transmitted received after eight SCLOCK periods The SCLOCK pin is configured as an output in master mode and as an input in slave mode In master mode the bit rate polarity and phase of the clock are controlled by the CPOL CPHA SPRO and SPRI bits in the SPICON SFR see Table XIX below In slave mode the
132. that is clocked at 32 768 kHz The watchdog time out interval can be adjusted via the PRE3 0 bits in WDCON Full Control and Status of the watchdog timer function can be controlled via the watchdog timer control SFR WDCON The WDCON SFR can only be written by user software if the double write sequence described in WDWR below is initiated on every write access to the WDCON SFR WDCON Watchdog Timer Control Register SFR Address COH Power On Default Value 10H Bit Addressable Yes PRE3 PRE2 PREO WDIR WDS WDE WDWR Table XVII WDCON SFR Bit Designations Bit Name Description 7 PRE3 Watchdog Timer Prescale Bits 6 PRE2 The Watchdog timeout period is given by the equation typ 2 x 2 fpr1 5 PREI 0 7 32 768 kHz 4 PREO PRE3 PRE2 PREI PREOTimout Period ms Action 0 0 0 0 15 6 Reset or Interrupt 0 0 0 1 31 2 Reset or Interrupt 0 0 1 0 62 5 Reset or Interrupt 0 0 1 1 125 Reset or Interrupt 0 1 0 0 250 Reset or Interrupt 0 1 0 1 500 Reset or Interrupt 0 1 1 0 1000 Reset or Interrupt 0 1 1 1 2000 Reset or Interrupt 1 0 0 0 0 0 Immediate Reset PRE3 0 gt 1001 Reserved 3 WDIR Watchdog Interrupt Response Enable Bit If this bit is set by the user the watchdog will generate an interrupt response instead of a system reset when the watchdog timeout period has expired This interrupt is not disabled by the CLR EA instruction and it is also a fixed high priority interrupt If the watchdog is not bei
133. that it no longer has a valid reference In this case the NOXREF bit of the ADCSTAT SER is set to a 1 If the ADuC816 is performing normal conversions and the NOXREF bit becomes active the conversion results revert to all 1s Therefore it is not necessary to continuously monitor the status of the NOXREF bit when performing conversions It is only necessary to verify its status if the conversion result read from the ADC Data Register is all 1s If the ADuC816 is performing either an offset or gain calibration and the NOXREF bit becomes active the updating of the respec tive calibration registers is inhibited to avoid loading incorrect coefficients to these registers and the appropriate ERRO or ERRI bits in the ADCSTAT SFR are set If the user is concerned about verifying that a valid reference is in place every time a cali bration is performed the status of the ERRO or ERRI bit should be checked at the end of the calibration cycle Sigma Delta Modulator A sigma delta ADC generally consists of two main blocks an analog modulator and a digital filter In the case of the ADuC816 ADCs the analog modulators consist of a difference amplifier an integrator block a comparator and a feedback DAC illus trated in Figure 20 DIFFERENCE ANALOG COMPARATOR INPUT AMP HIGH 0 FREQUENCY INTEGRATOR BITSTREAM TO DIGITAL FILTER Figure 20 Sigma Delta Modulator Simplified Block Diagram In operation the analog signal samp
134. the multiplication by the gain coefficient All ADuC816 ADC specifications will only apply after a zero scale and full scale calibration at the operating point supply voltage temperature of interest From an operational point of view a calibration should be treated like another ADC conversion A zero scale calibration if required should always be carried out before a full scale calibration System software should monitor the relevant ADC RDY0O 1 bit in the ADCSTAT SFR to determine end of calibration via a polling sequence or interrupt driven routine REV 0 ADuC816 NONVOLATILE FLASH EE MEMORY Flash EE Memory Overview The ADuC816 incorporates Flash EE memory technology on chip to provide the user with nonvolatile in circuit reprogrammable code and data memory space Flash EE memory is a relatively recent type of nonvolatile memory technology and is based on a single transistor cell architecture This technology is basically an outgrowth of EPROM technology and was developed through the late 1980s Flash EE memory takes the flexible in circuit reprogrammable features of EEPROM and combines them with the space efficient density features of EPROM see Figure 25 Because Flash EE technology is based on a single transistor cell architecture a Flash memory array like EPROM can be imple mented to achieve the space efficiencies or memory densities required by a given design Like EEPROM Flash memory can be programmed in sy
135. the receive register However if the first byte still has not been read by the time reception of the second byte is complete the first byte will be lost The physical interface SBUF The serial port receive and transmit registers are both accessed through the SBUF SFR SFR address 99 hex Writing to SBUF loads the transmit register and reading SBUF accesses a to the serial data network is via Pins RXD P3 0 and TXD P3 1 physically separate receive register SCON UART Serial Port Control Register SFR Address 98H Power On Default Value 00H Bit Addressable Yes SMO SM1 SM2 REN TB8 RB8 TI RI Table XXVII SCON SFR Bit Designations Bit Name Description T SMO UART Serial Mode Select Bits 6 SMI These bits select the Serial Port operating mode as follows SMO SMI Selected Operating Mode 0 0 Mode 0 Shift Register fixed baud rate Core CIk 2 0 1 Mode 1 8 bit UART variable baud rate 1 0 Mode 2 9 bit UART fixed baud rate Core_Clk 64 or Core_Clk 32 1 1 Mode 3 9 bit UART variable baud rate 5 SM2 Multiprocessor Communication Enable Bit Enables multiprocessor communication in Modes 2 and 3 In Mode 0 SM2 should be cleared In Mode 1 if SM2 is set RI will not be activated if a valid stop bit was not received If SM2 is cleared RI will be set as soon as the byte of data has been received In Modes 2 or 3 if SM2 is set RI will not be activated if the received ninth data bit in RB8 is 0 If SM2 is cleared RI will be set as s
136. tive for two core clock periods of the instruction cycle Port 3 pins also have various secondary functions described below Receiver Data Input asynchronous or Data Input Output synchronous of serial UART port Transmitter Data Output asynchronous or Clock Output synchronous of serial UART port Interrupt 0 programmable edge or level triggered Interrupt input which can be programmed to one of two priority levels This pin can also be used as a gate con trol input to Timer 0 REV 0 19 ADuC816 Mnemonic Type Description 20 34 48 21 35 47 22 25 26 27 28 31 32 33 36 39 40 41 42 P3 0 P3 3 Continued P3 3 INTI DVpp DGND P3 4 P3 7 P3 4 TO 3 5 1_ P3 6 WR P3 7 RD SCLK SDATA MOSI P2 0 P2 3 A8 A11 A16 A19 XTALI XTAL2 P2 4 P2 7 A12 A15 A20 A23 PSEN ALE IO IO IO IO IO IO IO IO IO IO Interrupt 1 programmable edge or level triggered Interrupt input which can be programmed to one of two priority levels This pin can also be used as a gate con trol input to Timerl Digital supply 3 V or 5 V Digital ground ground reference point for the digital circuitry P3 4 P3 7 are bidirectional port pins with internal pull up resistors Port 3 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs Port 3 pins being pulle
137. unter 2 Data Registers 55 Registers ato bte e V s LEURS E 29 TH2 and TL2 55 OFOH OFOM Primary ADC Offset Calibration RCAP2H and RCAP2L ee 55 Registers ias existe d e Un qua 30 Timer Counter 2 Operating Modes 56 OF1H OFIL Auxiliary ADC Offset Calibration 16 Autoreload Mode 56 Registers esset dac te ri eRe eh eR 30 16 Bit Capture 56 GNOH GNOM Primary ADC Gain Calibration UART SERIAL INTERFACE 57 Registers RD ET MR SIC BOIS Ao A RET A MT EEO ERES APER 30 SBUF Bake epo e me ee an gr ele Mer 57 GNIH GNIL Auxiliary ADC Gain Calibration Mode 0 8 Bit Shift Register Mode 58 Registers e ceri eee eT LAETI ae habe be RA 30 Mode 1 8 Bit UART Variable Baud Rate 58 PRIMARY AND AUXILIARY ADC CIRCUIT Mode 2 9 Bit UART with Fixed Baud Rate 58 DESCRIPTION OVERVIEW 31 Mode 3 9 Bit UART with Variable Baud Rate 58 Primary 31 UART Serial Port Baud Rate Generation 58 Auxiliary ADG 32 Timer 1 Generated Baud Rates 59 PRIMARY AND AUXILIARY ADC NOISE Timer 2 Generated Baud Rates 59 PERFORMANCE
138. ured to operate either as timers or event counters In Timer function the TLx register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 12 core clock periods the maximum count rate is 1 12 of the core clock frequency In Counter function the TLx register is incremented by a 1 to 0 transition at its corresponding external input pin or T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes two machine cycles 16 core clock periods to recognize a 1 to 0 transition the maximum count rate is 1 16 of the core clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it must be held for a mini mum of one full machine cycle Remember that the core clock frequency is programmed via the CD0 2 selection bits in the PLLCON SFR 51 ADuC816 User configuration and control of all Timer operating modes is achieved via three SFRs namely TMOD TCON Control and configuration for Timers 0 and 1 T2CON Control and configuration for Timer 2 TMOD Timer Counter 0 and 1 Mode Re
139. xers switch the selected input channel to the on chip buffer amplifier in the case of the primary ADC and directly to the sigma delta modulator input in the case of the auxiliary ADC When the analog input channel is switched the settling time of the part must elapse before a new valid word is available from the ADC REV 0 ADC converting in bipolar mode In unipolar mode peak to peak resolution at 105 Hz is 15 bits Primary and Auxiliary ADC Inputs The output of the primary ADC multiplexer feeds into a high impedance input stage of the buffer amplifier As a result the primary ADC inputs can handle significant source impedances and are tailored for direct connection to external resistive type sensors like strain gauges or Resistance Temperature Detectors RTDs The auxiliary ADC however is unbuffered resulting in higher analog input current on the auxiliary ADC It should be noted that this unbuffered input path provides a dynamic load to the driving source Therefore resistor capacitor combinations on the input pins can cause dc gain errors depending on the output impedance of the source that is driving the ADC inputs Analog Input Ranges The absolute input voltage range on the primary ADC is restricted to between AGND 100 mV to AVDD 100 mV Care must be taken in setting up the common mode voltage and input voltage range so that these limits are not exceeded otherwise there will be a degradation in linearity performance
140. xternal program memory space as described earlier To enable single pin emulation mode however users will need to pull the EA pin high through a 1 kQ resistor as shown in Figure 52 The emulator will then connect to the 2 pin header also shown in Figure 52 To be compatible with the standard connector that 65 ADuC816 DVpp DOWNLOAD DEBUG ENABLE JUMPER NORMALLY OPEN 1 DVpp V V 1kQ 2 PIN HEADER FOR EMULATION ACCESS 49 48 96963 4241 v NORMALLY OPEN a 88 G 36 DVpp 200pA 400pA EXCITATION o Lo 10 P1 5 AIN2 ADuC816 DVpp Gi 32 766kHz 23 24 29 26 X NOT CONNECTED IN THIS EXAMPLE 9 PIN D SUB FEMALE 1 ON Oo OC 5 Q NM Figure 52 Typical System Configuration comes with the single pin emulator available from Accutron Limited www accutron com use a 2 pin 0 1 inch pitch Friction Lock header from Molex www molex com such as their part number 22 27 2021 Be sure to observe the polarity of this header As represented in Figure 52 when the Friction Lock tab is at the right the ground pin should be the lower of the two pins when viewed from the top Enhanced Hooks Emulation Mode ADuC816 also supports enhanced hooks emulation mode An enhanced hooks based emulator is available from Metalink Corpo ration www metaice com No special hardware support for these emulators needs to be designed onto the board since these are pod
141. y been erased To be more specific a byte can only be programmed if it already holds the value FFH Because of the Flash EE architecture this erasure must happen at a page level therefore a minimum of four bytes 1 page will be erased when an erase command is initiated A more specific example of the Program Byte process is shown below In this example the user writes F3H into the second byte on Page 03H of the Flash EE Data Memory space while preserving the other three bytes already in this page As the user is only required to modify one of the page bytes the full page must be first read so that this page can then be erased without the exist ing data being lost This example coded in 8051 assembly would appear as MOV EADRL 03H Set Page Address Pointer MOV ECON 01H Read Page MOV EDATA2 0F3H Write New Byte MOV ECON 05 Erase Page MOV ECON 02H Write Page Program Flash EE REV 0 ADuC816 USER INTERFACE TO OTHER ON CHIP ADuC816 driving 10 kQ 100 pF It has two selectable ranges 0 V to PERIPHERALS the internal bandgap 2 5 V reference and 0 V to AVpp It can The following section gives a brief overview of the various operate in 12 bit or 8 bit mode The DAC has a control regis peripherals also available on chip A summary of the SFRs used ter DACCON and two data registers DACH L The DAC to control and configure these peripherals is also given output can be programmed to appear at Pin 3 or Pin
142. y user to power down the DAC DACHIL DAC Data Registers Function DAC Data Registers written by user to update the DAC output SFR Address DACL DAC Data Low Byte gt FBH DACH DAC Data High Byte gt Power On Default Value 00H gt Both Registers Bit Addressable No gt Both Registers The 12 bit DAC data should be written into DACH L right justified such that DACL contains the lower eight bits and the lower nibble of DACH contains the upper four bits REV 0 41 ADuC816 On Chip PLL required The default core clock is the PLL clock divided by The ADuC816 is intended for use with a 32 768 kHz watch crys 8 or 1 572864 MHz The ADC clocks are also derived from the tal A PLL locks onto a multiple 384 of this to provide a stable PLL clock with the modulator rate being the same as the crystal 12 582912 MHz clock for the system The core can operate at oscillator frequency The above choice of frequencies ensures this frequency or at binary submultiples of it to allow power that the modulators and the core will be synchronous regardless saving in cases where maximum core performance is not of the core clock rate The PLL control register is PLLCON PLLCON PLL Control Register SFR Address D7H Power On Default Value 03H Bit Addressable No OSC PD LOCK LTEA FINT CD2 CD1 CDO0 Table XV PLLCON SFR Bit Designations Bit Name Description 7 OSC_PD Oscillator Power Down Bit Set by u

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