MAXIM MAX2360/MAX2362/MAX2364 handbook
Contents
1. 1 Q BASEBAND FREQUENCY RESPONSE OUTPUT IMPEDANCE INPUT IMPEDANCE MAX2360 2 4 11 MAX2360 2 4 12 x 0 I e 800 40 600 3 35 0 5 i _ 50 a 309 d s lu LL N o 2 2 240 2 N 25 5 S 5 2 S15 Se 20 8 300 x Ki E s 5 S 2 0 5 220 E N E oe ITAN BE E a 35 05 100 q 3 0 0 0 0 5 10 15 20 25 30 35 40 45 50 100 120 140 160 180 200 220 240 260 280 300 100 120 140 160 180 200 220 240 260 280 300 c FREQUENCY MHz FREQUENCY MHz FREQUENCY MHz Q PHASE NOISE LOW BAND OSCILLATOR PHASE NOISE HIGH BAND OSCILLATOR vs FREQUENCY OFFSET 130 38MHz vs FREQUENCY OFFSET 165MHz RFL OUTPUT SPECTRUM 9 S cw z 10 2 DN 60 S 60 3 0 5 e 70 70 10 3 80 80 20 E a E 90 S 90 g 30 IH Lo amp 100 100 B A 110 110 50 120 120 o a 130 130 70 DESIRED MAGE 140 140 80 150 150 i 90 1k Ok 00k OM 1k Ok 00k 1 10M 566 38 766 38 966 38 1166 38 1366 38 FREQUENCY Hz FREQUENCY Hz FREQUENCY MHz RFHO CASCADE ACPR RFHO OUTPUT SPECTRUM vs Pour AND Vgat CASCADE ACPR vs Pour AND VBar 10 g E g 10 E s 20 1 E i E 30 3 3 8 A 101 s E 50 2 2 E 60 70 IMAGE DESIRED 80 90 1350 1550 1750 1950 2150 10 10 FREQUENCY MHz 6 MAALM Typical Operating Characteristics continued MAX2360EVKIT Vcc 2 75V Ta2. PARAMETER CONDITIONS MIN TYP MAX UNITS MODULATOR QUADRATURE MODES CDMA PCS FM_IQ IF_BAND low 120 235 IF Frequency Range MHz IF_BAND high 120 300 I Q Common Mode Input Voltage Vcc 2 7V to 3 0V Notes 2 3 6 1 35 Vec 2 SCH V IF Gain Control Range VGC 0 5V to 2 5V IFG 100 85 dB IF Output Power at IFOUTL and IFOUTH _ _ CDMA Mode VGC 2 5V IFG 100 ACPR 70dBc 10 dBm Gain Variation Over Temperature Relative t0 2570 ne 1 1 dB Note 4 Carrier Suppression VGC 2 5V IFG 100 30 49 dB Sideband Suppression VGC 2 5V IFG 100 30 38 dB MODULATOR FM MODE IF Gain Control Range VGC 0 5V to 2 5V IFG 100 85 dB Output Power at IFOUTL VGC 2 5V IFG 111 I Q modulation 8 5 dBm VGC 2 5V IFG 111 Output Power at IFOUTL direct VCO modulatien 5 5 dBm UPCONVERTER AND PREDRIVER IF_BAND low 120 200 IF Frequency Range IF BAND high 180 300 MHz RFL Frequency Range RFL port 800 1000 MHz RFH Frequency Range RFHO and RFH1 ports 1700 2000 MHz LOL Frequency Range 800 1150 MHz LOH Frequency Range 1400 2300 MHz Cellular f n ti 1300 RFPLL Frequency Range uui uu N on MHz PCS frequency operation 2300 Output Power RFL Port VGC 2 5V ass 7 dB utput Power or 1 FM mode 12 m Output Power RFH1 Port VGC 2 6V ACPR 54dBc 7 5 dBm Output Power RFHO Port VGC 2 6V ACPR 54dBc 6 6 dBm Power Control Range VGC 0 5V to 2 5V 30 dB Gain Variation Over Temperature Relative
3. Typical Operating Characteristics MAX2360EVKIT Vec 2 75V TA 25 C unless otherwise noted IF VCO VOLTAGE vs TIME TANK 1 S11 vs FREQUENCY OUTPUT POWER ACPR Icc vs VGC gt lt MAX2360 2 4 01 20 MAX2360 2 4 03 200 i CELLULAR CDMA RFL N 3 10 182 M LOCK 3 Q E 0 ze 164 o ES M Pour le id so Ba 20 A 128 D E Acer 30 em iss no E cs 40 A g VS ADJACENT P 50 74 4 1 048ms LOCK 3 gt lt TIME a 60 56 70 38 N ALTERNATE LA EQUIVALENT PARALLELR C 3 330MHz 1 58kQ 0 34pF 80 20 TIME 200u1s div 1 200MHz 1 76kQ 0 26pF 4 780MHz 1 21kQ 0 43pF 15 17 319 21 23 25 27 2 260MHz 1 66kQ 0 31pF 5 1GHz 0 94kQ 0 47pF VGC V N OUTPUT POWER ACPR OUTPUT POWER ACPR IF OUTPUT POWER icc vs VGC Jee TOTAL vs VGC vs VGC AND IF DAC SETTING m MAX2360 2 4 04 MAX2360 2 4 05 10 esou RFHO 200 10 PCS CDMA REI a i gt lt 180 8 s Pour s Pour 160 E N E 10 o Ed E E a 120 E E Ice A lt 5 100 5 amp ADJACENT 86 ie gj m e E 60 40 20 0 05 10 15 20 25 30 VGC V SIDEBAND SUPPRESSION AND IF OUTPUT POWER vs VGC LO FEEDTHROUGH IFOUTH DESIRED E 8 5 5 x c 0 05 10 15 20 25 30 0 05 10 15 20 25 30 129 98 13018 130 38 13058 130 78 VGC V VGC V FREQUENCY MHz MAXIM Complete Dual Band Quadrature Transmitters
4. TXGATE 17 P9t cxvHW c9ecxvW O9 EcXVM MAX2360 MAX2362 MAX2364 Complete Dual Band Quadrature Transmitters MAXIM MAX2362 m u a ea E u a ea oz CS XER DUPLE Y Figure 3 MAX2362 Typical Application Circuit 18 AVLAZCLAVI Complete Dual Band Quadrature Transmitters ON i 1cxo NE H HH 1000g MAXIM MAX2364 47pF I 1000pF SE TXGATE Figure 4 MAX2364 Typical Application Circuit MAXIM 19 P9t cxvHW c9ecxvW O9 EcXVM MAX2360 MAX2362 MAX2364 Complete Dual Band Quadrature Transmitters tes gt 50ns tcH gt 10ns tcwH gt 50ns DI iil
5. over specified 3 Charge Pump Source Sink Matching compliance range Note 6 5 76 Charge Pump High Z Leakage Over specified compliance range 10 nA RF PLL RF Main Divide Ratio 4096 262144 RF Reference Divide Ratio 2 8192 Maximum Phase Detector Comparison 10 MHz Frequency RCP 00 Note 6 100 165 225 RCP 01 Note 6 135 230 310 Charge Pump Source Sink Current UA RCP 10 Note 6 210 340 460 RCP 11 Note 6 270 450 630 Turbolock Boost Current Notes 5 6 245 435 630 UA Charge Pump Source Sink Matching Locked all values of RCP over specified 5 compliance range Note 6 Charge Pump High Z Leakage Over specified compliance range 10 nA RFPLL Input Sensitivity 160 mVp p Note 1 See Table 6 for register settings Note 2 ACPR is met over the specified Vcm range Note 3 Vom must be supplied by the I Q baseband source with 6uA capability Note 4 Guaranteed by design and characterization Note 5 When enabled turbolock is active during acquisition and injects boost current in addition to the normal charge pump current Note 6 gt 25 C guaranteed by production test lt 25 C guaranteed by design and characterization AVLAZCLAVI Complete Dual Band Quadrature Transmitters
6. reduc ing high frequency spectral content RC filtering also AVLAZCLAVI provides for transient protection against IEC802 testing by shunting high frequencies to ground while the series resistance attenuates the transients for error free operation The same applies to the override pins SHDN TXGATE IDLE High frequency bypass capacitors are required close to the pins with a dedicated via to ground The 48 pin TQFP EP package provides minimal inductance ground by using an exposed paddle under the part Provide at least five low inductance vias under the paddle to ground to minimize ground inductance Use a solid ground plane wherever possible Any cutout in the ground plane may act as slot radiator and reduce its shield effectiveness Keep the RF LO traces as short as possible to reduce LO radiation and susceptibility to interference 13 P9t cxvHW c9ecxvW O9 EcXVM MAX2360 MAX2362 MAX2364 Complete Dual Band Quadrature Transmitters Table 3 Operation Control Register OPCTRL BIT BIT NAME de ring LOCATION FUNCTION 0 LSB LO SEL 1 15 1 selects LOL input port O selects LOH port 1 keeps RF turbo mode current active even when frequency acquisition is RCP MAX 0 14 achieved This bit has no effect when RF TURBO CHARGE 0 This mode is used when high operating RF charge pump current is needed 1 keeps IF turbo mode current active even when
7. 235 800 to 1150 800 to 1000 MAXIM 21 P9 cXVHW c9 cXVW O9 cXVM MAX2360 MAX2362 MAX2364 Complete Dual Band Quadrature Transmitters 22 TOP VIEW MAXIM MAX2360 BOTTOM SIDE GND Pin Configurations continued N C RFHO LOCK Voc IDLE Voc TXGATE N C N C IFINH IFINH RBIAS MAXIM MAX2364 MAXUM MAX2362 C TANKH TANKH AVLAZCLAVI MAXIM TOP_VIEW BOTTOM VIEW sA RB 30 MAX EXI Complete Dual Band Quadrature Transmitters Package Information 48L TQFP EPS Note 10 POSED PAD CORNER TAB DETAIL SV dl sl ZVI bp PROPRICTARY INFORMATION me PACKAGE OUTLINE 32 48L 7x7x1 0 MM TOFP WITH EP OPTION TOOUMENT CONTROL RO 1 oO Pes Fl VIETXVWN TZIESXVWN OIETXVN MAX2360 MAX2362 MAX2364 Complete Dual Band Quadrature Transmitters Package Information continued NOTES 1 ALL DIMENSIONS AND TOLERANCING CONFORM TO ANSI Y14 5 1982 2 DATUM PLANE H IS LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE 3 DIMENSIONS Di AND Ei DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE MOLD PROTRUSION IS 0 254 MM ON D AND EL DIMENSIONS THE TOP OF PACKAGE IS SMALLER THAN THE BOTTOM OF PACKAGE BY 015 MILLIMETERS 5 DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08 MM TOTAL IN EXCESS OF THE b DIMENSION AT
8. 25 C unless otherwise noted IFOUTH DIFFERENTIAL PORT IFINH DIFFERENTIAL PORT Complete Dual Band Quadrature Transmitters Typical Operating Characteristics continued MAX2360EVKIT Vcc 2 75V TA 25 C unless otherwise noted icc vs RFL OUTPUT POWER 836MHz icc vs RFHO OUTPUT POWER 1880MHz Ice vs RFH1 OUTPUT POWER 1880MHz 180 180 5 180 E 170 J 170 m S E E 160 160 160 _ 150 _ 150 150 3 Z 140 Z 140 Z 140 o 2 O 130 130 130 120 120 120 110 110 no 100 100 E 100 60 50 40 30 20 40 0 10 60 50 40 30 20 10 0 10 60 50 40 30 20 10 0 10 OUTPUT POWER dBm OUTPUT POWER dBm OUTPUT POWER dBm BUFFERED LO OUTPUT LOL PORT S11 LOH PORT S11 0 E g E 20 E 8 E _ 30 E S 40 Ww 3 5 60 2 70 80 90 1 700MHz 720 j51Q 1600MHz TO 2500MHz ii 2 966MHz 602 j46Q 1 1 6GHz 400 j25Q 3 1 22MHz 520 j38
9. MAX2364 come in a 48 pin TQFP EP package and are specified for the extended 40 C to 85 C temperature range Applications Triple Mode Dual Mode or Single Mode Mobile Phones Satellite Phones Wireless Data Links WAN LAN Wireless Local Area Networks LANs High Speed Data Modems High Speed Digital Cordless Phones Wireless Local Loop WLL Pin Configurations appear at end of data sheet Selector Guide appears at end of data sheet SPI and QSPI are trademarks of Motorola Inc MICROWIRE is a trademark of National Semiconductor Corp MAKLA NAKI Complete Dual Band Quadrature Transmitters Features Dual Band Triple Mode Operation 7dBm Output Power with 54dBc ACPR 100dB Power Control Range Supply Current Drops as Output Power Is Reduced Dual Synthesizer for IF and RF LO Dual On Chip IF VCO QSPI SPI MICROWIRE Compatible 3 Wire Bus Digitally Controlled Operational Modes 2 7V to 5 5V Operation Single Sideband Upconverter Eliminates SAW Filters 9 9 9 Ordering Information PART TEMP RANGE PIN PACKAGE MAX2360ECM 40 C to 85 C 48 TQFP EP MAX2362ECM 40 C to 85 C 48 TQFP EP MAX2364ECM 40 C to 85 C 48 TQFP EP Exposed paddle Functional Diagram Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s web
10. frequency acquisition is ICP MAX 0 13 achieved This bit has no effect when IF TURBO CHARGE 0 This mode is used when high operating IF charge pump current is needed Sets operating mode according to the following 00 FM mode MODE 01 12 11 01 Cellular digital mode RFL is selected 10 PCSHIGH mode RFH1 is selected 11 2 PCSLOW mode RFHO is selected 1 selects IFINH and IFOUTH 0 selects IFINL and IFOUTL For FM mode IF_BAND 19 MODE 00 set IF BAND to 0 VCO 0 9 1 selects high band IF VCO O selects low band IF VCO 3 bit IF gain control Alters IF gain by approximately 2dB per LSB 0 to 14dB IFG 100 8 7 6 Provides a means for adjusting balance between RF and IF gain for optimized linearity SIDE BAND 4 5 When this register is 1 the upper sideband is selected LO below RF When this register is O the lower sideband is selected LO above RF BUF_EN 0 4 O turns IFLO buffer off 1 turns IFLO buffer on 4 O selects direct VCO modulation IF VCO is externally modulated and the I Q MOD TYPE 3 modulator is bypassed 1 selects quadrature modulation STBY 1 2 O shuts down everything except registers and serial interface TXSTBY j 1 O shuts down modulator and upconverter leaving PLLs locked and registers active This is the programmable equivalent to the TXGATE pin SHDN_BIT 4 0 O shuts down everything except serial interface and also resets all registers to power up state 14 MAXI Complete Dual Band Quadrature Transmit
11. g TA SA0 10 E8970 1 2 dB Note 4 LO Leakage 17 dBm Image Signal 29 dBc AVLAZCLAVI P9 cxVHW c9e cxvW O9 cXVM MAX2360 MAX2362 MAX2364 Complete Dual Band Quadrature Transmitters ELECTRICAL CHARACTERISTICS continued MAX2360 62 64 evaluation kit 500 system operating modes as defined in Table 6 input voltage at and Q 200mVRms differen tial common mode Vcc 2 300kHz quadrature CW tones RF and IF synthesizers locked with passive lead lag second order loop filter REF 200mVp p at 19 68MHz Vcc SHDN IDLE CS TXGATE 2 75V VBAT 2 75V IF output load 4009 LOH LOL input power 7dBm fi oi 966MHz fi oH 1750MHz IFINH 125mVRms at 130MHz IS 95 CDMA modulation fRFHo fRFH1 1880MHz Top 836MHz TA 25 C unless otherwise noted PARAMETER CONDITIONS MIN TYP MAX UNITS IF_PLL Reference Frequency 5 30 MHz Frequency Reference Signal Level 0 1 0 6 Vp p IF Main Divide Ratio 256 16384 IF Reference Divider Ratio 2 2048 VCO low 240 470 VCO O ting Ran MH ain add VCO high 240 600 E IF LO Output Power BUF EN 1 6 dBm ICP 00 Note 6 115 175 230 ICP 01 Note 6 145 235 315 Charge P S e Sink Current A Nje mp SourceS 2 ICP 10 Note 6 235 350 470 S ICP 11 Note 6 300 465 625 Turbolock Boost Current Notes 5 6 265 450 615 HA X Locked all values of ICP
12. on each of these pins may be used to reduce noise MAXIM Complete Dual Band Quadrature Transmitters Pin Description continued PIN NAME FUNCTION MAX2360 MAX2362 MAX2364 Differential IF Outputs These ports are active when the register bit IF_SEL is high They do not support FM mode These pins must be inductively pulled IFOUTH up to Vcc A differential IF bandpass filter is connected between this port 16 17 16 17 IFOUTH and IFINH or IFINH The pull up inductors can be part of the filter structure The differential output impedance of this port is nominally 600Q The trans mission lines from these pins should be short to minimize the pick up of spu rious signals and noise Differential IF Outputs These ports are active when the register bit IF_SEL is low These pins must be inductively pulled up to Vcc A differential IF band 18 19 m 18 19 IFOUTL pass filter is connected between this port and IFINL and IFINL The pull up IFOUTL inductors can be part of the filter structure The differential output impedance of this port is nominally 600 The transmission lines from these pins should be short to minimize the pick up of spurious signals and noise RF and IF Variable Gain Control Analog Input VGC floats to 1 5V Apply 20 20 20 vGC 0 5V to 2 6V to control the gain of the RF and IF stages An RC filter on this pin may be used to reduce DAC noise or PDM clock
13. spurs from this line Supply Pin for the IF VGA Bypass with a capacitor as close to the pin as 21 21 21 Vec possible The bypass capacitor must not share its ground vias with any other branches Supply for the I Q Modulator Bypass with capacitor as close to the pin as 22 22 22 Voc possible The bypass capacitor must not share its ground vias with any other branches Differential Q Channel Baseband Inputs to the Modulator These pins go 23 24 23 24 23 24 Q Q directly to the bases of a differential pair and require an external common mode bias voltage Differential l Channel Baseband Inputs to the Modulator These pins go 25 26 25 26 25 26 l l directly to the bases of a differential pair and require an external common mode bias voltage of 1 4V 27 27 27 SHDN Shutdown Input A logic low on SHDN shuts down the entire IC An RC low pass filter may be used to reduce digital noise 28 28 28 V Supply Pin to the VCO Section Bypass as close to the pin as possible The ee bypass capacitor should not share its vias with any other branches 29 29 29 IFLO Buffered LO Output Control the output buffer using register bit BUF EV and the divide ratio using the register bit BUF_DIV 30 81 o 30 81 TANKL Differential Tank Pins for the Low Frequency IF VCO These pins are internally TANKL biased to 1 6V MAXIM PJE ZXVM EJ ZXVMN OJEZX VI MAX2360 MAX2362 MAX2364 Complete Dual Band Quadrature Transmitters Pin
14. B18 KA tes gt 50ns Figure 5 3 Wire Interface Diagram IF Tank Design The low band tank TANKL TANKL and high band tank TANKH TANKH are fully differential The exter nal tank components are shown in Figure 6 The fre quency of oscillation is determined by the following equation fosc m 2n Cint CCENT Cvar Cr C _ Cp x Cc WAR 2 Cp Co CINT Internal capacitance of TANK port Cp Capacitance of varactor Cvar Equivalent variable tuning capacitance CPAR Parasitic capacitance due to PCB pads and traces CCENT External capacitor for centering oscillation fre quency Cc External coupling capacitor to the varactor Internal to the IC the charge pump will have a leakage of less than 10nA This is equivalent to a 300MQ shunt resistor The charge pump output must see an extremely high DC resistance of greater than 300MQ This will minimize charge pump spurs at the compari son frequency Make sure there is no solder flux under the varactor or loop filter Layout Issues The MAX2360 MAX2362 MAX2364 EV kit can be used as a starting point for layout For best performance take into consideration power supply issues as well as the RF LO and IF layout 20 tcwL gt 50ns tew 50ns MAXIM MAX2360 MAX2362 MAX2364 Rn Figure 6 Tank Port Oscillator Power Supply Layout To minimize coupling between different sections of the IC the i
15. Description continued PIN NAME FUNCTION MAX2360 MAX2362 MAX2364 32 33 32 33 o TANKH Differential Tank Pins for the High Frequency IF VCO These pins are internally i TANKH biased to 1 6V 34 35 34 35 34 35 N C No Connection Leave these pins floating Reference Frequency Input REF is internally biased to Vcc 0 7V and must 36 36 36 RE be AC coupled to the reference source This is a high impedance port 25kQ 3pF Supply for the IF Charge Pump This supply can differ from the system Vcc 37 37 37 Voc Bypass as close to the pin as possible The bypass capacitor must not share its vias with any other branches High Impedance Output of the IF Charge Pump Connect to the tune input of the IF VCOs through the IF PLL loop filter Keep the line from IFCP to the tune 38 38 38 IFCP i input as short as possible to prevent spurious pick up and connect the loop filter as close to the tune input as possible 39 39 39 V Supply Pin for Digital Circuitry Bypass as close to the pin as possible The Se bypass capacitor must not share its vias with any other branch High Impedance Output of the RF Charge Pump Connect to the tune input of 40 40 40 RFCP the RF VCOs through the RF PLL loop filter Keep the line from this pin to the tune input as short as possible to prevent spurious pick up and connect the loop filter as close to the tune input as possibl
16. MAXIMUM MATERIAL CONDITION 6 CONTROLLING DIMENSIDN MILLIMETER 7 THIS DUTLINE CONFORMS TO JEDEC PUBLICATION 95 REGISTRATION MD 136 VARIATIONS AC AND AE 8 LEADS SHALL BE COPLANAR WITHIN 004 INCH 9 EXPDSED DIE PAD SHALL BE COPLANAR WITH BOTTOM OF PACKAGE WITHIN 2 MILS C05 MM 10 DIMENSIONS X amp Y APPLY TD EXPOSED PAD EP VERSIONS ONLY SEE INDIVIDUAL PRODUCT DATASHEET TO DETERMINE IF A PRODUCT USES EXPOSED PAD PACKAGE me PACKAGE OUTLINE EXPOSED PAD 32 481 7x7x1 0 MM TQFP WITH EP OPTION Note 10 DOCUMENT CONTROL NO e CO Fomos ele SVIAAI VI Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 24 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2000 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products
17. N TYP MAX UNITS Operating Supply Voltage 2 7 3 0 V VGC 0 5V 92 118 PCS mode VGC 2 0V 97 123 VGC 2 5V 132 161 en VGC 0 5V 91 110 TE asians de VGC 20V 95 122 VGC 2 5V 132 164 VGC 0 5V 85 110 mA Operating Supply Current FM mode VGC 20V Bo 114 VGC 2 5V 114 142 Addition for IFLO buffer 6 5 9 5 IDLE 0 6V cell idle 15 20 STBY 0 6V 26 34 TXGATE 0 6V RFPLL off 11 SHDN 0 6V sleep mode 0 5 20 UA Logic High Note 6 2 0 V Logic Low Note 6 0 6 V Logic Input Current Note 6 5 5 MA VGC Input Current Note 6 10 10 MA VGC Input Resistance During Shutdown SHDN 0 6V Note 6 225 280 kO Lock Indicator High 50kQ pull up load Note 6 Voc 0 4 V Lock Indicator Low 50kQ pull up load Note 6 0 4 V 2 MAXIM ELECTRICAL CHARAC TERISTICS Complete Dual Band Quadrature Transmitters MAX2360 62 64 evaluation kit 500 system operating modes as defined in Table 6 input voltage at and Q 200mVRms differen Hz quadrature CW tones RF and IF synthesizers locked with passive lead lag second order loop tial common mode Vcc 2 300k filter REF 200mVp p at 19 68MH z Vcc SHDN IDLE CS TXGATE 2 75V VBAT 2 75V IF output load 4000 LOH LOL input power 7dBm fLoL 966MHz fj oH 1750MHz IFINH 125mVRms at 130MHz IS 95 CDMA modulation fREHo fREH1 1880MHz Top 836MHz TA 25 C unless otherwise noted
18. Output Buffer IFLO provides a buffered LO output when BUF EN is 1 The IFLO output frequency is equal to the VCO fre quency when BUF DIV is 0 and half the VCO frequen cy when BUF DIV is 1 The output power is 6dBm This output is intended for applications where the receive IF is the same frequency as the transmit IF IF RF PLL The IF RF PLL uses a charge pump output to drive a loop filter The loop filter will typically be a passive sec ond order lead lag filter Outside the filter s bandwidth phase noise will be determined by the tank compo nents The two components that contribute most signifi cantly to phase noise are the inductor and varactor Use high Q inductors and varactors to maximize equiv alent parallel resistance The IF TURBO CHARGE and the RF TURBO CHARGE bits in the CONFIG register can be set to 1 to enable turbo mode Turbo mode pro vides maximum charge pump current during frequency acquisition Turbo mode is disabled after the second transition from phase lead to phase lag or from phase lag to phase lead Turbo mode is also disabled after frequency acquisition is achieved When turbo mode is disabled charge pump current will return to the pro grammed levels as set by ICP and RCP bits in the CONFIG register Table 4 IF VGA The IF VGA allows varying an IF output level that is con trolled by the VGC The voltage range on VGC of 0 5V to 2 6V provide a gain control range of 85dB There are two differential IF outpu
19. Q 2 1 75GHz 360 j22Q 12918 129 78 130 38 130 98 131 58 4 1 56Hz 400 j250 3 1 88GHz 34Q j180 FREQUENCY MHz 4 2 01GHz 320 j15Q 5 2 56Hz 290 j0Q MAXIM 7 VIETXVWN TZIESXVW OIETXVN MAX2360 MAX2362 MAX2364 Complete Dual Band Quadrature Transmitters Pin Description PIN MAX2360 MAX2362 MAX2364 NAME FUNCTION RFL Transmitter RF Output for Cellular Band 800MHz to 1000MHz for both FM and digital modes This open collector output requires a pull up inductor to the supply voltage which may be part of the output matching network and may be connected directly to the battery 1 8 9 18 19 30 31 34 85 44 N C No Connection Make no connection to these pins RFHO Transmitter RF Output for PCS Band 1700MHz to 2000MHz This open collector output requires a shunt inductor to the supply voltage The pull up inductor may be part of the output matching network and may be connected directly to the battery Open Collector Output Indicating Lock Status of the IF and or the RF PLLs Requires a pull up resistor Control using configuration register bit LD MODEO LD_MODE1 Power Supply Digital Input A logic low on IDLE shuts down everything except the RF PLL and associated registers A small RC lowpass filter may be used to prevent digital noise Vcc Supply Pin for the Upconverter Stage Vcc must be bypassed to system ground as close to the p
20. RF_TURBO_ 1 2 1 activates turbocharge feature providing an additional 435pA of IF charge CHARGE pump current during frequency acquisition Determines output mode for LOCK detector pin as follows 00 test mode LD MODE cannot be 00 for normal operation LD MODE 11 1 0 01 IF PLL lock detector 10 RF PLL lock detector 11 logical AND of IF PLL and RF PLL lock detectors MAXIM 15 PJE ZXVM EJ ZXVMN OJHEZX VI MAX2360 MAX2362 MAX2364 Complete Dual Band Quadrature Transmitters Table 5 Power Down Modes Se 9 o ES Si Slalk o a POWER DOWN End eS agla ES MODE COMMENTS sez 25 gt 2 2 oa lk 265 sale Eal oO O u u u uc a z0 clo 0O 2 SHDN Pin Ultra low shutdown current X XX IX X X X X XXX IDLE Pin IDLE is low in RX mode X X X X XX TXGATE pin For punctured TX mode X X RF PLL SHDN For external RF PLL use X X IF PLL SHDN For external IF PLL use X X TX STBY TX is OFF but IF and RF LOs stay locked X X REG STBY Shuts down but preserves registers X X x X XX REG SHDN Serial bus is still active X X xI XIX IX X X X X X Off Table 6 Register and Control Pin States for Key Operating Modes CONFIG CONTROL OPCTRL REGISTER REGISTER PINS SIS MODE DESCRIPTION ul Q alu oll gt l QD I 5 u E z nA lt GoGI a E zs 1 a Jal S olg ams 5 Ele 53 Jaj T
21. SE u o Ia a o uu ky PCS High PCS upper half band RFH1 selected O 10 1 1 1 1 1 1 1 1 HIHIH PCS Low PCS lower half band RFHO selected O 11 1 1 1 1 1 1 1 1 H H Cellular Digital RFL selected 1101 070 4 1 1 1 1 1 H H FM Direct VCO modulation RFL selected 1 00 0 0 0 1 1 1 1 1 HIHIH PCS Idle Listen for pages RX ON TX OFF O PIX X X X 1 X1 X 1 L H H Cellular Idle Listen for pages RX ON TX OFF 110X X X X 1 X1 X 1 LIHHH PCS TXGATE Gated transmission PCS O 1X 1 1 1 1 X 1 1 1 HILIH Cellular TXGATE Gated transmission cellular digital 101 010 1 1X1 1 1 HILIH Sleep Everything off X XX XIX IX X X X x x X X L X Don t care 16 AVLAZCLAVI Complete Dual Band Quadrature Transmitters 50Q 33pF 33pF 33pF TX CELL CELL RX CELL DUPLEXER DIPLEXER Figure 2 MAX2360 Typical Application Circuit MAXIM 1000pF
22. ZI9MAX2360fH hv fS 19 1635 Rev 1 10 00 General Description The MAX2360 dual band triple mode complete transmit ter for cellular phones represents the most integrated and architecturally advanced solution to date for this applica tion The device takes a differential UO baseband input and mixes it up to IF through a quadrature modulator and IF variable gain amplifier VGA The signal is then routed to an external bandpass filter and upconverted to RF through an SSB mixer and RF VGA The signal is further amplified with an on board PA driver Dual IF synthesiz ers dual RF synthesizers a local oscillator LO buffer and a 3 wire programmable bus complete the basic func tional blocks of this IC The MAX2362 supports single band single mode PCS operation The MAX2364 supports single band cellular dual mode operation The MAX2360 enables architectural flexibility because its two IF voltage controlled oscillators VCOs two IF ports two RF LO input ports and three PA driver output ports allow the use of a single receive IF frequency and split band PCS filters for optimum out of band noise performance The PA drivers allow up to three RF SAW filters to be eliminated Select a mode of operation by loading data on the SPI QSPI MICROWIRE com patible 3 wire serial bus Charge pump current side band rejection IF RF gain balancing standby and shutdown are also controlled with the serial interface The MAX2360 MAX2362
23. deal power supply layout is a star configuration which has a large decoupling capacitor at a central Vcc node The Vcc traces branch out from this node each going to a separate Vcc node in the MAX2360 MAX2362 MAX2364 circuit At the end of each trace is a bypass capacitor with impedance to ground less than 1Q at the frequency of interest This arrangement pro vides local decoupling at each Vcc pin Use at least one via per bypass capacitor for a low inductance ground connection Matching Network Layout The layout of a matching network can be very sensitive to parasitic circuit elements To minimize parasitic inductance keep all traces short and place compo nents as close to the IC as possible To minimize para sitic capacitance a cutout in the ground plane and AVLAZCLAVI Complete Dual Band Quadrature Transmitters any other planes below the matching network compo Tank Layout nents can be used Keep the traces coming out of the tank short to reduce On the high impedance ports e g IF inputs and out series inductance and shunt capacitance Keep the inductor pads and coupling capacitor pads small to puts keep traces short to minimize shunt capacitance na minimize stray shunt capacitance Selector Guide PART IF RANGE MHz RF LO RANGE MHz urea 120 to 235 800 to 1150 800 to 1000 MAX2360 120 to 300 1400 to 2300 1700 to 2000 MAX2362 120 to 300 1400 to 2300 1700 to 2000 MAX2364 120 to
24. der count OPCTRL 892F hex 0100p Operational control settings CONFIG DOSF hex 0101p Configuration and setup control TEST 0000 hex 0111p Test mode control AVLAZCLAVI Complete Dual Band Quadrature Transmitters 24 BIT REGISTER LSB DATA 20 BITS ADDRESS 4 BITS B11 B10 B9 B8 B6 A3 AO IVIDE RAT B9 EGISTER CONFIGURATION REGISTER TEST REGISTER X X X X DONT CA Figure 1 Register Configuration Electromagnetic Compliance Considerations Two major concepts should be employed to produce a noise free and EMC compliant transmitter minimize cir cular current loop area to reduce H field radiation and minimize voltage drops to reduce E field radiation To minimize circular current loop area bypass as close to the part as possible and use the distributed capaci tance of a ground plane To minimize voltage drops make Vcc traces short and wide and make RF traces short The don t care bits in the registers should be 0 in order to minimize electromagnetic radiation due to unnecessary bit banging RC filtering can also be used to slow the clock edges on the 3 wire interface
25. e Supply for the RF Charge Pump This supply can differ from the system Vcc 41 41 41 Voc Bypass as close to the pin as possible The bypass capacitor must not share its vias with any other branches 42 42 42 RFPLL RF PLL Input AC couple this port to the RF VCO 43 43 LOH High band RF LO Input Port AC couple to this port 44 44 LOL Low band RF LO Input Port AC couple to this port 45 46 48 45 46 48 45 46 48 GND Ground Connect to PCB ground plane Transmitter RF Output for PCS Band 1700MHz to 2000MHz This open col 47 47 o RFH1 lector output requires a shunt inductor to the supply voltage The pull up inductor may be part of the output matching network and may be connected directly to the battery Exposed Exposed Exposed GND DC and AC GND Return for the IC Connect to PC board ground plane using paddle paddle paddle multiple vias 10 MAXI Detailed Description The MAX2360 complete quadrature transmitter accepts differential UO baseband inputs with external common mode bias A modulator upconverts this to IF frequency in the 120MHz to 300MHz range A gain control voltage pin VGC controls the gain of both the IF and RF VGAs simultaneously to achieve best noise and linearity per formance The IF signal is brought off chip for filtering then fed to a single sideband upconverter followed by the RF VGA and PA driver The RF upconverter requires an external VCO for operation The IF PLL RF PLL and operating mode can be pr
26. in as possible The ground vias for the bypass capacitor should not be shared by any other branch TXGATE Digital Input A logic low on TXGATE shuts down everything except the RF PLL IF PLL IF VCO and serial bus and registers This mode is used for gated transmission 8 9 8 9 IFINL IFINL Differential Inputs to the RF Upconverter These pins are internally biased to 1 5V The input impedance for these ports is nominally 4009 differential The F filter should be AC coupled to these ports Keep the differential lines as short as possible to minimize stray pick up and shunt capacitance 10 11 10 11 IFINH IFINH Differential Inputs to the RF Upconverter These pins are internally biased to 1 5V The input impedance for these ports is nominally 4009 differential The F filter should be AC coupled to these ports Keep the differential lines as short as possible to minimize stray pick up and shunt capacitance 12 12 RBIAS Bias Resistor Pin RBIAS is internally biased to a bandgap voltage of 1 18V An external resistor or current source must be connected to this pin to set the bias current for the upconverters and PA driver stages The nominal resistor value is 16kQ This value can be altered to optimize the linearity of the driver stage 13 14 15 13 14 15 13 14 15 CLK DI cs Input Pins from the 3 Wire Serial Bus SPI QSPI MICROWIRE compatible An RC filter
27. ogrammed by an SPI QSPI MICROWIRE compatible 3 wire interface The following sections describe each block in the MAX2360 Functional Diagram LO Modulator Differential in phase and quadrature phase Q input pins are designed to be DC coupled and biased with the baseband output from a digital to analog converter DAC I and Q inputs need a DC bias of Vcc 2 and a current drive capability of 6A Common mode voltage will work within a 1 35V to Vcc 1 25V range Typically and Q will be driven differentially with a 200mVRMS baseband signal Optionally and Q may be programmed for 100mVRMs operation with the IQ LEVEL bit in the configuration register The IF VCO output is fed into a divide by two quadrature generator block to derive quadrature components to drive the IQ modulator The output of the modulator is fed into the VGA IF VCOs There are two VCOs to support high IF and low IF appli cations The VCOs oscillate at twice the desired IF fre quency Oscillation frequency is determined by external tank components see Applications Information Typical phase noise performance for the tank is as shown in Table 1 The high band and low band VCOs can be selected independently of the IF port being used Table 1 Typical VCO Phase Noise IF 130 38MHz OFFSET kHz PHASE NOISE dBc 1 80 12 5 105 30 111 120 121 900 128 AVLAZCLAVI Complete Dual Band Quadrature Transmitters IFLO
28. ower Management Bias control is distributed among several functional sections and can be controlled to accommodate many different power down modes as shown in Table 5 The shutdown control bit is of particular interest since it differs from the SHDN pin When the shutdown control bit is active SHDN_BIT 0 the serial interface is left active so that the part can be turned on with the serial bus while all other functions remain shut off In contrast when the SHDN pin is low it shuts down everything In either case PLL programming and register information is lost To retain the register information use standby mode STBY 0 Signal Flow Control Table 6 shows an example of key registers for triple mode operation assuming half band PCS and IF fre quencies of 130MHz 165MHz Applications Information The MAX2360 is designed for use in dual band triple mode systems It is recommended for triple mode hand sets Figure 2 The MAX2362 is designed for use in CDMA PCS handset or WLL single mode 2 4GHz ISM systems Figure 3 The MAX2364 is designed for use in dual mode cellular systems Figure 4 3 Wire Interface Figure 5 shows the 3 wire interface timing diagram The 3 wire bus is SPI QSPI MICROWIRE compatible REGISTER DEFAULT ADDRESS FUNCTION RFM 172087 dec 0000 RF M divider count RFR 1968 dec 00016 RF R divider count IFM 6519 dec 0010p IF M divider count IFR 0492 dec 0011p IF R divi
29. site at www maxim ic com PJE ZXVM EJ ZXVMN OJHEZX VI MAX2360 MAX2362 MAX2364 Complete Dual Band Quadrature Transmitters ABSOLUTE MAXIMUM RATINGS VGC 10 EI IR 0 3V to 3 6V RFL REHO RERI iiser res 5 5V DI CLK CS VGC SHDN TXGATE IDLE EI nennen 0 3V to Vcc 0 3V AC Input Pins IFINL IFINH Q TANKL TANKH REF RFPLL FOE een 1 0V peak Digital Input Current SHDN TXGATE IDLE CLK DIOS FE ERE 10mA Continuous Power Dissipation TA 70 C EP derate 27mW C above 70 C 2 16W 40 C to 85 C 48 Pin TQFP Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature soldering 10s Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS MAX2360 2 4 test fixture Vcc VBATT 2 75V SHDN IDLE TXGATE 2 0V VGC 2 5V RBiAs 16kQ TA 40 C to 85 C unless otherwise noted Typical values are at TA 25 C and operating modes are defined in Table 6 PARAMETER CONDITIONS MI
30. t ports from the VGA IFOUTL IFOUTL are optimized for low IF operation 120MHz to 235MHz for IFOUTH IFOUTH support high IF operation 120MHz to 300MHz IFOUTL ports support direct VCO FM modulation The differential IF output port has an output impedance of 6000 when pulled up to Vcc through a choke Single Sideband Mixer The RF transmit mixer uses a single sideband architec ture to eliminate an off chip RF filter The single sideband mixer has IF input stages that correspond to IF output ports of the VGA The mixer is followed by the RF VGA The RF VGA is controlled by the same VGC pin as the IF VGA to provide optimum linearity and noise perfor mance The total power control range is gt 100dB PA Driver The MAX2360 includes three power amplifier PA dri vers Each is optimized for the desired operating fre quency RFL is optimized for cellular band operation 11 P9t cxvW c9ecxvW O9 EcXVM MAX2360 MAX2362 MAX2364 Complete Dual Band Quadrature Transmitters RFHO and RFH1 are optimized for split band PCS opera tion The PA drivers have open collector outputs and require pull up inductors The pull up inductors can act as the shunt element in a shunt series match Programmable Registers The MAX2360 MAX2362 MAX2364 include seven pro grammable registers consisting of four divide registers a configuration register an operational control register and a test register Each register consists of 24 bits The 4 leas
31. t significant bits LSBs are the register s address The 20 most significant bits MSBs are used for register data All registers contain some don t care bits These can be either a O or a 1 and will not affect operation Figure 1 Data is shifted in MSB first followed by the 4 bit address When CS is low the clock is active and data is shifted with the rising edge of the clock When CS transitions to high the shift reg ister is latched into the register selected by the con tents of the address bits Power up defaults for the seven registers are shown in Table 2 The dividers and control registers are programmed from the SPI QSPI MICROWIRE compatible serial port The RFM register sets the main frequency divide ratio for the RF PLL The RFR register sets the reference fre quency divide ratio The RF VCO frequency can be determined by the following RF VCO frequency fREF RFM RFR IFM and IFR registers are similar IF VCO frequency fREF IFM IFR where fREF is the external reference frequency for the MAX2360 MAX2362 MAX2364 The operational control register OPCTRL controls the state of the MAX2360 MAX2362 MAX2364 See Table 3 for the function of each bit Table 2 Register Power Up Default States The configuration register CONFIG sets the configura tion for the RF IF PLL and the baseband I Q input lev els See Table 4 for a description of each bit The test register is not needed for normal use P
32. ters Table 4 Configuration Register CONFIG BIT BIT NAME ad LOCATION FUNCTION 0 LSB IF_PLL_SHDN 1 15 O shuts down the IF PLL This mode is used with an external IF VCO and IF PLL RF_PLL_ j SHDN 1 4 O shuts down the BF PLL This mode is used with an external RF PLL RESERVED 0 13 Must be set to 0 for normal operation IQ LEVEL 1 12 1 selects 200mVRms input mode O selects 100mVnys input mode BUF DIV 0 11 1 selects 2 on IFLO port O bypasses the divider VCO BYPASS 0 10 1 bypasses IF VCO and enables a buffered input for external VCO use A 2 bit register sets the IF charge pump current as follows 00 175yA ICP 00 9 8 01 235A 10 350uA 11 465LA A 2 bit register sets the RF charge pump current as follows 00 165yA RCP 00 7 6 01 230uA 10 340uA 11 450uA IF phase detector polarity 1 selects positive polarity increasing tuning voltage IF_PD_POL 1 5 on the VCO produces increasing frequency 0 selects negative polarity increasing tuning voltage on the VCO produces decreasing frequency RF phase detector polarity 1 selects positive polarity increasing tuning voltage RF_PD_POL 1 4 on the VCO produces increasing frequency O selects negative polarity increasing voltage on the VCO produces decreasing frequency IF_TURBO_ 1 3 1 activates turbocharge feature providing an additional 450 4A of IF charge CHARGE PUMP current during frequency acquisition
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MAXIM MAX2360/MAX2362/MAX2364 handbook