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Winbond ISD5216 8 TO 16 MINUTES VOICE RECORD/PLAYBACK DEVICE WITH INTEGRATED CODEC

1. FMcuk FLD FLDO CKD2 CKDV Sample Rate Filter Knee 1 13 824 MHz 0 0 0 0 8 0 kHz 3 7 kHz 20 48 MHz 0 0 0 1 8 0 kHz 3 7 kHz 27 648 MHz 0 0 1 0 8 0 kHz 3 7 kHz 40 96 MHz 0 0 1 1 8 0 kHz 3 7 kHz 13 824 MHz 0 1 0 0 6 4 kHz 2 9 kHz 20 48 MHz 0 1 0 1 6 4 kHz 2 9 kHz 27 648 MHz 0 1 1 0 6 4 kHz 2 9 kHz 40 96 MHz 0 1 1 1 6 4 kHz 2 9 kHz 13 824 MHz 1 0 0 0 5 3 kHz 2 5 kHz 20 48 MHz 1 0 0 1 5 3 kHz 2 5 kHz 27 648 MHz 1 0 1 0 5 3 kHz 2 5 kHz 40 96 MHz 1 0 1 1 5 3 kHz 2 5 kHz 13 824 MHz 1 1 0 0 4 0 kHz 1 8 kHz 20 48 MHz 1 1 0 1 4 0 kHz 1 8 kHz 27 648 MHz 1 1 1 0 4 0 kHz 1 8 kHz 40 96 MHz 1 1 1 1 4 0 kHz 1 8 kHz 14 ISDS216 a Winbond Electronics Corp 7 3 INTERFACE The interface is for bi directional two line communication between different ICs or modules The two lines are a serial data line SDA and a serial clock line SCL Both lines must be connected to a positive supply via a pull up resistor Data transfer may be initiated only when the interface bus is not busy 7 3 1 System configuration A device generating a message is a transmitter a device receiving a message is the receiver device that controls the message is the master and the devices that are controlled by the master are the slaves Example of an configuration using two microcontrollers 7 3 2 Start and stop conditions Both data and clo
2. 35 78 PIN DETAILS mms 36 7 8 1 Power and Ground PINS 37 7 8 2 Digital PINS iiine re ore 37 7 8 3 CODEC interface PCS 39 7 8 4 ANALOG VO PINS nella dake HAN de ted esed ede 39 7 9 AUTO MUTE AND AUTO GAIN FUNCTIONS Nt 41 7 10 PROGRAMMING THE ISD 5216 42 7 10 1 Sending a byte on the I2C 2 42 710 2 POWER UP SEQUENCE alia 42 7 10 3 Read Status ec 42 7 10 4 Load Command Byte Register Single Byte 43 7 10 5 Load Command Byte Register Address 43 1 10 6 Digital Erase m 44 121072 Digital 45 7 10 8 ES 45 1 10 9 Feed Through Mode 45 10 10 SC ER SES da 48 1 10 11 Record EE eade 49 7 10 12 Memo and Playback aa 50 7 11 SAMPLE PC LAYOUT EOR PDIB ae ines 51 8 TIMING DIAGRAMS 52 9 ABSOLUTE MAXIMUM eco eb coena LE B
3. Symbol Parameters Min Typ Units Conditions Vwicr MIC Input Voltage 300 mV Peak to Peak Pl 0TLP input reference 208 mV Peak to Peak 41101 transmission level point OTLP GT MIC Gain Tracking 0 1 dB 1 kHz 3 to 40 dB OTLP Input Microphone input resistance 10 MIC and MIC pins Microphone Amplifier 6 40 dB Over 3 300 mV Range Range VMicBs Microphone Bias Voltage 2 2 V lucas 0 0 mA MICBS Output Resistance 700 Q AUX IN 4 Symbol Parameters Min 2 Max Units Conditions Vaux IN AUX IN Input Voltage 1 0 V Peak to Peak 0 dB gain setting VAUX IN OTLP AUX IN OTLP Input 694 2 mV Peak to Peak 0 dB Voltage gain setting AAUX IN GA AUX IN Gain Accuracy 0 5 0 5 dB 1 IN GT AUX IN Gain Tracking 0 1 dB 1000 Hz 3 to 45 dB OTLP Input 0 dB setting Raux IN AUX IN Input Resistance 10 to 100 Depending AUX IN Gain 64 ISDS216 52555 6 Winbond EHD Electronics Corp SPEAKER OUTPUTS 4 arameters in p ax nits onditions ymbo P t Min Typ 14 Units Conditi SP Output Voltage High 3 6 V Peak to Peak Gain Setting differential load 1500 01 SP Output Load 8 Q OPA1 OPAO 10 Low Gain RsPHG SP Output Load Imp
4. Note Lead coplanarity to be within 0 004 inches 70 1505216 QWinbond Electronics Corp 12 2 PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT SOIC DIMENSIONS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Max A 18 06 B 2 64 7 59 D 0 29 E 0 48 F G 10 41 H 1 02 Note Lead coplanarity to be within 0 004 inches Publication Release Date June 2003 71 Revision B 2 ISDS216 12 3 PLASTIC DUAL INLINE PACKAGE PDIP DIMENSIONS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Plastic Dual Inline Package PDIP P Dimensions INCHES MILLIMETERS Min Nom Max Min Nom Max A 1 445 1 450 1 455 36 70 36 83 36 96 B1 3 81 2 1 65 1 78 1 91 C1 15 24 15 88 C2 13 46 13 72 13 97 D 4 83 D1 0 38 E 3 18 3 43 F 0 38 0 46 0 56 G 1 40 1 52 1 65 H 2 54 J 0 008 0 010 0 012 0 20 0 25 0 30 S 0 070 0 075 0 080 1 78 1 91 2 03 0 0 15 0 15 727 1505216 Winbond 13 ORDERING INFORMATION Winbond Part Number Description 15216 _ Product Family Special Temperature Field ISD5216 Product 8 to 16 minute durations Blank Commercial Packaged 0 to 70 D Extended 20 to 70 Industrial 40 to 85 Package 28 Lead 8x13 4mm Plastic Thin Small Outline Package TSOP Type 1 S 28 Lead 0 300 Inch Plastic Small Outline Package SOIC P 28 Lead 0 600 Inch Plastic Dual Inline Package PDIP When ordering 1505216 s
5. 1SD 5216 6 Winbond Electronics Corp ISD5216 8 TO 16 MINUTES VOICE RECORD PLAYBACK DEVICE WITH INTEGRATED CODEC ISDS216 Electronics Corp 1 GENERAL DESCRIPTION The ChipCorder ISD5216 is an 8 to 16 minute Voice and Data Record and Playback system with integrated Voice band CODEC The device works on a single 2 7V to 3 3V supply and has fully integrated system functions including AGC microphone preamplifier speaker driver memory and CODEC The CODEC meets the PCM conformance specification of the G 714 recommendation Its u Law and A Law compander meets the specification of the ITU T G 711 recommendation 2 FEATURES Single Supply 2 7 to 3 3 Volt operation Voice and digital data record and playback system on a single chip Industry leading sound quality Low voltage operation Message management Fully integrated system functions Flexible architecture Nonvolatile message storage Configurable ChipCorder sampling rates of 4 kHz 5 3kHz 6 4 kHz and 8kHz 8 10 12 and 16 minutes duration External or internal Voice recorder clock serial interface 400kHz Configurable analog paths 2 2N Microphone Bias Pin 100 year message retention typical 100K analog record cycles typical 10K digital record cycles typical Full duplex not in 128 mode single channel speech CODEC with External 13 824 MHz 27 648 MHz 20 48 MHz 40 96 MHz master clock 125 and PCM digital audio inte
6. 0 1 1 12 dB 0 1 IDAC OUT 1 0 0 16 1 0 1 0 1 20 dB 1 1 SUM2 1 1 0 24 dB 1 1 1 28 dB Configuration Register CFG1 and CFG2 The bits described on this page are highlighted 15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 CIG2 CIG1 CIGO AXG1 AXGO AXPD 1460 OSPD AMTO CDM CDIO 0 81 50 OPAO VLPD B CFGO 15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 visi VESO vor vom VOLO 5151 5150 51 1 S1MO 52 1 S2M0 FLSO FLD1 FLDO FLPD AGPD CFGI 15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 X X CKD2 COG2 CKDV MUTE HSRO 1250 LAW1 LAWO DAPD ADPD CFG2 Publication Release Date June 2003 Revision B 2 293 ISDS216 amp Winbond Electronics Corp 7 7 2 Microphone and Auxiliary Inputs r internal to the device AXPD Power up the AUX in input amplifier 0 Power Up Ccour 0 1iF 1 Power Down ANA IN Input oA ANA IN AXG1 Gain dB of the Input Amplifier aux input 0 0 0 0 1 3 1 NOTE fcurrorr 1 0 6 2xRaCccup 1 1 9 2 2V Voltage AGPD Power up the AGC control and the MIC bias voltage 0 Power Up 1 Power Down Select input to the CODEC A D converter 0 0 INP 0 1 SUM2 1 0 MIC 1 1 No Input Co
7. SEHD Electronics Corp 7 8 1 Power and Ground Pins Vccp Voltage Inputs To minimize noise the analog and digital circuits in the Winbond 1505216 device use separate power busses These 3 V busses lead to separate pins Tie the Vccp pins together as close as possible and decouple both supplies as near to the package as possible Vssp Ground Inputs The Winbond ISD5216 series utilizes separate analog and digital ground busses The analog ground Vssa pins should be tied together as close to the package as possible and connected through a low impedance path to power supply ground The digital ground Vssp pin should be connected through separate low impedance path to power supply ground These ground paths should be large enough to ensure that the impedance between the VssA pins and the Vggp pin is less than The backside of the die is connected to Vssp through the substrate resistance In a chip on board design the die attach area must be connected to Vssp NC No Connect These pins should not be connected to the board at any time Connection of these pins to any signal ground or Vcc may result in incorrect device behavior or cause damage to the device 7 8 2 Digital I O Pins SCL SERIAL CLOCK LINE The Serial Clock Line is a bi directional clock line It is an open drain line requiring a pull up resistor to Vcc It is driven by the master chips in a system and controls the timing of the d
8. 0 0 1 1 0 0 1 1 0 O o Publication Release Date June 2003 I9 Revision B 2 1505216 CWinbond 7 4 12 SERIAL INTERFACE As shown in the following figure the bus has three lines e continuous serial clock SCK e word select WS e serial data SDIO and the device generating SCK and WS is the master Simple System Configurations and Basic Interface Timing TRANSMITTER TRANSMITTER MASTER RECEIVER MASTER WORD RO WORD n 1 RIGHT CHANNEL RIGHT CHANNEL SN00119 7 4 1 Serial Data Serial data is transmitted in two s complement with the MSB first The MSB is transmitted first because the transmitter and receiver may have different word lengths It isn t necessary for the transmitter to know how many bits the receiver can handle nor does the receiver need to know how many bits are being transmitted When the system word length is greater than the transmitter word length the word is truncated least significant data bits are set to 0 for data transmission If the receiver is sent more bits than its word length the bits after the LSB are ignored On the other hand if the receiver is sent fewer bits than its word length the missing bits are set to zero internally And so the MSB has a fixed position whereas the position of the LSB depends on the word length The transmitter always sends the MSB of the next word one clock period after the WS changes
9. Veca Vssa Vssa Vsso Vsso Veco Veco SCK 00 SDI Publication Release Date June 2003 2345 Revision B 2 ISDS216 Electronics Corp 4 TABLE OF CONTENTS 1 GENERAL DESCRIPTION notte tete dente n p residet poa Ar nux a Eo se dz boda 2 2 FEATURES unie en etie Mp Med Ae Pl cua de 2 3 BLOCK DIAGRAM H PMET 3 4 TABLE OF CONTENTS 4 5 PIN CONFIGURAT ION cadit rccte rte 7 6 DESCRIPTION 8 FUNCTIONAL DE SE RIP 9 A MEMORY ORGANIZATION 11 1 2 CODEC DER 11 7 2 1 Analog Input to Digital Output 12 7 2 2 Digital Input to Analog Output 13 7 2 3 CODEC External Clock Configuration ea 13 7 2 4 ChipCorder Analog Array Sampling Frequency With External 14 LS G INTERFACE ine napi d PUR n Md brad M cu UE 15 33 1 SYSTEM CONTIQUIATION TEE 15 63 2 Start and stop conditions 15 3 16 1 34 ACKNOWLEDGE 16 7 3 5 Additional 1505216 flow control ettet eeepc rb deae bte e c dg A 17 7 3 6 PG Protocol Addressing ote i eut its an ica el
10. 062 COG1 COGO CKDV MUTE HPFO HSRO 1250 LAW1 Lawo DAPD ADPD CFG2 235 Publication Release Date June 2003 Revision B 2 6 Winbond Electronics Corp LAW1 LAWO Data Format 0 0 Two s Complement 0 1 A Law 1 0 Law 1 1 Signed Magnitude ISD5216 MUTE State DAPD Power up the CODEC DAC 0 Unmuted 0 Power Up 1 muted 1 Power Down CODEC Configuration Second Page DAO coco 2 bits 8 bits or 16 ple frequency gt ANALOG OUT ADPD CODEC ADC Digital High Pass HSRO Sample Rate Inte Filter Mode 0 Power Up 0 PCM Bypassed 0 Low 1 Power Dewn 1 128 1 High Configuration Register CFGO CFG1 and G2 The bits described on thi page are highlighted 15 14 13 12 11 10 9 8 7 1 0 CIG2 CIG1 CIGO AXG1 AXGO AXPD INSO OSPD AMTO CDI1 CDIO OPS1 OPSO OPA1 VLPD CFGO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VLS1 VLSO VOL2 VOL1 VOLO S181 5180 S1M1 S1M0 S2M1 52 0 FLS0 FLD1 FLDO FLPD AGPD B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X CKD2 COG2 COG1 COGO CKDV MUTE HPFO HSRO 1280 LAW1 LAWO DAPD ADPD CFG2 7 8 PIN DETAILS 36 ISDS216 Winbond
11. 70 150 Q 01 High Gain Csp SP Output Load Cap 100 pF VspAG SP Output Bias Voltage 1 2 VDC Analog Ground Vsppco Speaker Output DC Offset 100 mV With CODEC D A IN to DC Speaker PSRR Power Supply Rejection 55 dB Measured with a 1 kHz Ratio 100 ma sine wave input at Vcc and Vcc pins Frequency Response 300 0 25 0 25 dB With OTLP input to AUX 3400 Hz IN 6 dB setting Power Output Low Gain 23 5 mW Differential load at 80 Setting RMS AUX OUT Symbol Parameters Min Typ 114 Units Conditions VAUX OUT AUX OUT Maximum 1 0 V 5kQ Load Output Swing RL Minimum Load Impedance 5 CL Maximum Load 100 pF Capacitance V BIAS AUX OUT 1 2 VDC 65 Publication Release Date June 2003 Revision B 2 ISDS216 Winbond Electronics Corp VOLUME CONTROL 4 Symbol Parameters Min Typ 114 Units Conditions Aout Output Gain 28 to 0 dB 8 steps of 4 dB referenced to output Absolute Gain 0 5 0 5 AUX IN 1 0 kHz 6 dB gain setting measured differentially at SP Typical values T4 25 C and Vcc 3 0V 2 All min max limits are guaranteed by Winbond via electrical testing or characterization Not all specifications are 100 percent tested 3 Low frequency cut off depends upon the value of external capacitors see Pin Descriptions 4 Differential input m
12. SCK to WS WS to SCK SCK to WS WS to SCK 59 ISD5216 Publication Release Date June 2003 Revision B 2 ISDS216 a Winbond Electronics Corp 9 ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS Packaged Parts Condition Value Junction temperature 150 Storage temperature range 65 C to 150 C Voltage Applied to any pin Vss 0 3V to 0 3V Voltage applied to any pin Input current limited to 20 mA Vas 1 0V to Vcc 1 0 Lead temperature soldering 10 seconds 300 C Voc Vss 0 3V to 5 5V 1 Stresses above those listed may cause permanent damage to the device Exposure to the absolute maximum ratings may affect device reliability Functional operation is not implied at these conditions OPERATING CONDITIONS Packaged Parts Condition Value Commercial operating temperature range 0 to 70 Extended operating temperature n 20 C to 70 C Industrial operating temperature 40 C to 85 C Supply voltage Vcc 2 2 7V to 3 3V Ground voltage Vss P ov temperature 2 BI Vss VssA Vssp 60 10 ELECTRICAL CHARACTERISTICS General Parameters ISDS216 617 Publication Release Date June 2003 Revision B 2 Symbol Parameters Min Typ Unit Conditions 5 Vit Input Low Voltage Vcc X V 0
13. Serial data sent by the transmitter may be synchronized with either the trailing HIGH to LOW or the leading LOW to HIGH edge of the clock signal However the serial data must be latched into the receiver on the leading edge of the serial clock signal and so there are some restrictions when 20 1505216 Winbond transmitting data that is synchronized with the leading edge see the timing specifications at the back of this data sheet Note that the specifications are defined by the transmitter speed The specification of the receiver has to be able to match the performance of the transmitter 7 4 2 Word Select The word select line indicates the channel being transmitted WS 0 channel 1 WS 1 channel 2 right WS may change either on a trailing or leading edge of the serial clock but it doesn t need to be symmetrical In the slave this signal is latched on the leading edge of the clock signal The WS line changes one clock period before the MSB is transmitted This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission Furthermore it enables the receiver to store the previous word and clear the input for the next word see figure Timing for PS Transmitter on previous page 7 4 3 Timing In the 125 format any device can act as the system master by providing the necessary clock signals slave will usually derive its internal clock signal from an e
14. to the 51 SUMMING amplifier Bits 51 0 and S1M1 control the state of the SUM1 SUMMING amplifier These are bits D7 and D8 respectively of CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the INPUT SOURCE MUX only path 4 Select the SUM1 SUMMING amplifier path through the FILTER MUX Bit FLSO controls the state of the FILTER MUX This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path 5 Deselect the signal compression Bit AMTO controls the signal compression This is bit D7 of CFGO and it must be set to ZERO 6 Power up the LOW PASS FILTER Bit FLPD controls the power up state of the LOW PASS FILTER stage This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE 7 Select the 5 3 kHz sample rate Bits FLDO and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback These are bits D2 and D3 of CFG1 To enable the 5 3 kHz sample rate D2 must be set to ZERO and D3 set to ONE 8 Select the LOW PASS FILTER input only to the S2 SUMMING amplifier BITS S2MO and S2M1 control the state of the SUM2 SUMMING amplifier These are bits D5 and D6 respectively of CFG1 set D5 to ZERO and D6 to ONE to select the LOW PASS FILTER only path 9 Power up the Internal Oscillator Bit OSPD controls the power up state of the Internal Oscillator This is bit D8 of CFGO and it must be set to ZERO to power
15. 2 Input High Voltage Vcc x 0 8 V VoL SCL SDA SDIO Output Low 0 4 V lou 3 mA Voltage Vout RAC INT Output Low Voltage 0 4 V lo 1 mA Output Voltage 0 4 V lor 10 pA loc Vcc Current Operating Playback amp A D D A 30 50 mA Load P Record amp A D D A 36 56 mA No Load P CODEC A D D A 20 30 mA No Load P Iss Vcc Current Standby 1 10 uA li Input Leakage Current 1 1 Typical values 25 Vcc 3 0 2 min max limits are guaranteed by Winbond electrical testing or characterization Not all specifications are 100 percent tested 3 Vcca and summed together TIMING PARAMETERS ISDS216 Symbol Parameters Min 2 Typ Units Conditions Fs Sampling Frequency 8 0 kHz 6 4 kHz 5 3 kHz 4 0 kHz For Filter Knee 8 0 kHz sample rate 3 7 kHz Knee Point PT 6 4 kHz sample rate 2 9 kHz Knee Point PII 5 3 kHz sample rate 2 5 kHz Knee Point PII 4 0 kHz sample rate 1 8 kHz Knee Point PII Trec Record Duration 8 0 kHz sample rate 8 05 min 6 4 kHz sample rate 10 06 min 5 3 kHz sample rate 12 15 min 4 0 kHz sample rate 16 1 min Playback Duration 8 0 kHz sample rate 8 05 min 6 4 kHz sample rate 10 06 min 5 3 kHz sample rate 12 15 min 4 0 kHz sample rate 16 1 min f Delay 8 0 kHz sample rate 1 m
16. and ZERO 2 Power up the ADC Bit ADPD controls the power up state of ADC This is bit DO of CFG2 and it should be a ZERO to power up the ADC 3 Set the CODEC input gain The input gain setting will depend on the input level at the MIC pins and can be set by the CODEC INPUT GAIN Bits CIG2 CIG1 and CIG0 These are the D15 D14 and D13 bits respectively of Configuration Register 0 CFG0 4 Set audio interface Set the interface mode to PCM interface by setting bit 1750 bit D4 of CFG2 to ZERO This will also enable full duplex mode 5 Set data format Set the digital data format through bits LAW1 and LAWO These are bits D3 and D2 of CFG2 respectively 6 Set Master Clock Division Set the Master Clock division ratios as described in Set Master Clock Division Ratio on page 25 7 Power up the DAC Bit DAPD controls the power up state of the DAC This is bit D1 of CFG2 and should be a ZERO to power up the DAC 8 Send DAC output to speaker Select the DAC path through the OUTPUT MUX Bits OPSO and OPS1 control the state of the OUTPUT MUX These are bits D3 and D4 respectively of CFGO and they should be set to the state where D3 is ONE and D4 is ZERO to select the DAC path 9 Power up the Speaker Amplifier Bits OPAO and control the state of the Speaker and AUX amplifiers These are bits D1 and D2 respectively of CFGO They should be set to the state where D1 is ONE and D2 is ZERO This powers up the Spea
17. form providing superior quality voice and music reproduction SPEECH SOUND QUALITY The ISD5216 ChipCorder product can be software configured to operate at 4 0 5 3 6 4 and 8 0 kHz sampling frequencies allowing the user a choice of speech quality options Increasing the duration decreases the sampling frequency and bandwidth which affects sound quality The Sample Duration table below compares filter pass band and product durations DURATION To meet end system requirements the 1505216 device is a single chip solution which provides 8 to 16 minutes of voice record and playback depending on the sample rates defined by the customer s software Input Sample Rate to Duration Input Sample Rate kHz Duration Minutes Typical Filter Pass Band kHz 8 0 8 min 3 sec 3 7 6 4 10 min 4 sec 2 9 5 3 12 min 9 sec 2 5 4 0 16 min 6 sec 1 8 Publication Release Date June 2003 2 Revision B 2 1505216 Winbond l Minus any pages selected for digital storage FLASH STORAGE One of the benefits of Winbond s ChipCorder technology is the use of on chip nonvolatile memory which provides zero power message storage A message is retained for up to 100 years typically without power In addition the device can be re recorded over 10 000 times typically for digital messages and over 100 000 times typically for analog messages Memory space can be allocated to either digital or analog storage when rec
18. half description on page 32 If an external clock is not used this input should be connected to Vssp 7 8 3 CODEC linterface Pincs SCK Bit clock for PCM or 125 audio data WS The Word Sync Frame Sync signal is used to differentiate between data for left and right channel in lS For PCM it signals the beginning of the word SDIO For PCM this is the output signal from the CODEC it should be connected to the input pin of the receiving device In S mode this is a bi directional pin that should be connected to the bi directional lS data pin on the other device connected to the 125 bus SDI This pin is only used when the CODEC is in PCM mode this signal provides digital audio input to the CODEC it should be connected to the output pin of the transmitting device 7 8 4 ANALOG I O PINS MIC MIC Microphone Input The microphone inputs transfer the voice signal to the on chip AGC preamplifier or directly to the CODEC INPUT MUX depending on the selected path The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p p into the storage array from a typical electret microphone output of 2 to 20 mV The input impedance is typically 20 differential and 13 3 differential when the CODEC INPUT MUX MICIN path is selected The MICBS pin provides a 2 2V bias voltage for the external microphone only when the AGC is powered up Using this regulated bias voltage results in less supply noise coupling in
19. noise using the D A power down bit DAPD The analog output amplifier gain is controlled from configuration registers bits COG2 COGO from 8 dB to 6 dB 7 2 3 CODEC External Clock Configuration The ISD5216 has two Master Clock configuration bits that allow four possible Master Clock frequencies Bits CKD2 and CKDV set the Master Clock Division ratios These are bits D12 and D8 of CFG2 respectively The combination of these bits with the sample rate bit HSRO also set the CODEC sample frequency as shown in the following table Master Clock Possible Settings HSRO 05 012 08 Faconec CFG2 CFG2 CFG2 13 824 MHz 0 0 0 8 kHz 20 48 MHz 0 0 1 11 852 kHz 27 648 MHz 0 1 0 8 kHz 40 96 MHz 0 1 1 11 852 kHz 13 824 MHz 1 0 0 32 kHz 20 48 MHz 1 0 1 44 1 48 kHz 27 648 MHz 1 1 0 32 kHz 40 96 MHz 1 1 1 44 1 48 kHz hot tested Publication Release Date June 2003 13 Revision 2 ISDS216 7 2 4 ChipCorder Analog Array Sampling Frequency With External Clock If an external master clock is used the clock dividers must be set according to the following table to get the filter cut off frequency and sample rate setup correctly The duty cycle on the input clock is not critical when CKD2 is set to ONE as the clock is immediately divided by two internally See the Analog Structure Right Half description on page 32
20. test 17 19 14 25 SERIAL INTERFACE de Ee E e EM patet e HE etta de 20 TAA Sonal Data EA 20 7 4 2 Word Selegt aae dde M e 21 Y 21 5 CONTROL REGIS TERS 22 COA Command Byle rt ep heo 22 23 7 5 8 Register BINS ae 23 7 5 4 OPCODE Command Byte 24 FESTUM UT 25 09 6 Read Status iie 25 7 5 7 Attaching an Address to a Command 25 9 8 Playback a et eee hedera 26 7 5 9 26 ISDS216 11122 Electronics Corp 17 59 10 Message CU 26 H A 26 1 621 Writing Data dieere den 26 7 6 2 26 7 6 3 Erasing 27 7 6 4 Load Configuration Registers ener nene 27 7 7 1505216 ANALOG STRUCTURE Left Half description 31 7 7 1 Speaker AUX OUT and Volume Control Description 33 7 7 2 Microphone and Auxiliary Inputs pp 34 7 7 3 CODEC Configuration First
21. the Internal Oscillator Bit OSPD controls the power up state of the Internal Oscillator This is bit D8 of CFGO and it must be set to ZERO to power up the Internal Oscillator To set up the chip for Memo or Call Playback the configuration registers are set up as follows CFGO 0010 0100 0010 0010 hex 2422 CFG1 0101 1001 1101 0001 hex 59D1 CFG2 0000 0000 0000 0011 hex 0003 50 1505216 Winbond 7 11 SAMPLE PC LAYOUT FOR PDIP The PDIP package is illustrated from the top PC board traces and the three chip capacitors are on the bottom side of the board Note 2 gt ofc MCLK Note 1 V i lt Note 3 Digital Ground C1 C2 C3 0 1 uF chip Capacitors Note 1 Va traces should be kept separated back to the V supply feed point Note 2 Vocp traces should be kept separated back to the V4 supply feed 0 0 0 0 0 0 0 0 0 0 0 0 0 c c point To gt Note 3 The Digital and Analog grounds Voca tie together at the power supply The Veca and supplies will also need filter capacitors typ 50 to 100uF Analog Ground Note 3 Publication Release Date June 2003 51 Revision B 2 ISDS216 PC TIMING DIAGRAM PLAY AT ADDR DATA CLOCK PULSES AUX OUT 52s ISDS216 Example of power up command ON THE 12 BUS Wiite to Slave 80 Hex Acknowledge Clock S
22. the MLS playback signal or the output of the CODEC DAC to the summing amp Set to OFF to disable the signal 0 0 DAC OUT DAO 0 1 ARRAY 1 0 FILTO 1 1 OFF CIG2 CIG1 CIGO AXG1 AXGO AXPD INSO OSPD AMTO CDI1 CDIO OPS1 OPSO OPA1 OPAO VLPD CFGO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VLS1 VLSO VOL2 VOL1 VOLO 8181 5150 S1M1 S1M0 S2M1 S2M0 FLSO FLD1 FLDO FLPD AGPD N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X CKD2 COG2 COG1 COGO CKDV MUTE HPFO HSRO 1280 LAW1 LAWO DAPD ADPD N CFG2 Publication Release Date June 2003 sol Revision B 2 ISDS216 Electronics Corp ISD5216 ANALOG STRUCTURE Right Half description FLSO Select input MLS Switch on or off the auto gain FLPD Control power to the array or sum 1 amp circuit low pass filter 0 SUM1 0 Uncompressed 0 Power Up 1 ARRAY 1 Compressed 1 Power Down Multilevel Storage Array 52 1 52 0 SOURCE FLD1 FLDO SAMPLE PASS 0 0 BOTH RATE BAND 0 1 AUX IN ONLY 0 0 8 KHz 3 7 KHz 1 0 FILTO ONLY 0 1 6 4 KHz 2 9 KHz 1 1 Power Down 1 0 5 3 KHz 2 5 KHz 1 1 4 0 KHz 1 8 KHz CKD2 Divide Master Clock CKDV Divide Master Clock OSPD Power Up Internal by 1 or 2 by 1728 or 2560 Oscillator 0 Divide by 1 0 Divide by 1728 0 Pow
23. the event any inconsistencies exist between the information in this and other product documentation or in the event that other product documentation contains information in addition to the information in this the information contained herein supersedes and governs such other information in its entirety Copyright 2003 Winbond Electronics Corporation All rights reserved ISD a registered trademark of Winbond ChipCorder is a trademark of Winbond All other trademarks are properties of their respective owners 6 Winbond Electronics Corp Headquarters No 4 Creation Rd 111 Science Based Industrial Park Hsinchu Taiwan TEL 886 3 5770066 FAX 886 3 5665577 Winbond Electronics Corporation America 2727 North First Street San Jose CA 95134 U S A TEL 1 408 9436666 FAX 1 408 5441797 Winbond Electronics Shanghai Ltd 27F 299 Yan An W Rd Shanghai 200336 China TEL 86 21 62365999 FAX 86 21 62356998 http www winbond com tw Taipei Office 9F No 480 Pueiguang Rd Neihu District Taipei 114 Taiwan TEL 886 2 81777168 FAX 886 2 87153579 http www winbond usa com Winbond Electronics Corporation Japan 7F Daini ueno BLDG 3 7 18 Shinyokohama Kohokuku Yokohama 222 0033 TEL 81 45 4781881 FAX 81 45 4781800 Please note that all data and specifications are subject to change without notice All the trademarks of products and companies mentioned in this datasheet belong to their resp
24. up the Internal Oscillator To set up the chip for Memo Record the configuration registers are set up as follows 0 0000 0100 0000 0001 hex 0401 CFG1 0000 0001 0100 1000 hex 0148 CFG2 0000 0000 0000 0011 hex 0003 Publication Release Date June 2003 49 Revision B 2 ISDS216 Winbond 12222 Electronics Corp 7 10 12 Memo and Call Playback This mode sets the chip up for local playback of recorded messages The playback path is from the MULTILEVEL STORAGE ARRAY to the FILTER MUX then to the LOW PASS FILTER stage From there the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX through the VOLUME CONTROL then to the SPEAKER output stage We will assume that we are driving a piezo speaker element and that this audio was recorded at 8 kHz All unnecessary stages will be powered down 1 Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX Bit FLSO the state of the FILTER MUX This is bit D4 of CFG1 and must be set to ONE 2 Power up the LOW PASS FILTER Bit FLPD controls the power up state of the LOW PASS FILTER stage This is bit D1 of CFG1 and it must be set to ZERO 3 Select the 8 0 kHz sample rate Bits FLDO and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback These are bits D2 and D3 of CFG1 To enable 8 0 kHz sample rate D2 and D3 must be set to ZERO 4 Select the LOW PASS FILTER input only to the S2 SUMMING ampli
25. 216 7 1 MEMORY ORGANIZATION The ISD5216 memory array is arranged as 1888 rows or pages of 2048 bits for a total memory of 3 866 624 bits The primary addressing for the 2048 pages is handled by 11 bits of address data in the analog mode At the 8 kHz sample rate each page contains 256 milliseconds of audio Thus at 8 kHz there is actually room for 8 minutes and 3 seconds of audio A memory page is 2048 bits organized as thirty two 64 bit blocks when used for digital storage The contents of a page are either analog or digital This is determined by instruction op code at the time the data is written A record of what is analog and what is digital and where is stored by the system microcontroller in the message address table MAT The MAT is a table kept in the microcontroller memory that defines the status of each message block It can be stored back into the ISD5216 if the power fails or the system is turned off Use of this table allows for efficient message management Segments of messages can be stored wherever there is available space in the memory array When a page is used for analog storage the same 32 blocks are present but there are 8 EOM End of Message markers This means that for each 4 blocks there is an EOM marker at the end Thus when recording the analog recording will stop at any one of eight positions At 8 kHz this results in a resolution of 32 msec when ENDING an analog recording Beginning an analog rec
26. AME FUNCTION 7 EOM Indicates whether an EOM interrupt has occurred 6 OVF Indicates whether an overflow interrupt has occurred 5 READY Indicates the internal status of the device if READY is LOW no new commands should be sent to device 4 PD Device is powered down if PD is HIGH 3 PRB Play Record mode indicator HIGH Play LOW Record 2 1 DEVICE ID An internal device ID This is 001 for the 1505216 0 The lower address byte will always return the block address bits as zero either in digital or analog mode It is good practice to read the status register after a Write or Record operation to ensure that the device is ready to accept new commands Depending upon the design and the number of pins available on the controller the polling overhead can be reduced If INT and RAC are tied to the microcontroller the controller does not have to poll as frequently to determine the status of the ISD5216 7 5 7 Attaching an Address to a Command In the write mode the device can accept data sent after the command byte If a register load option is selected the next two bytes are loaded into the selected register The format of the data is MSB first as specified by the standard Thus to load DATA 15 0 into the device DATA lt 15 8 gt is sent first the byte is acknowledged and DATA lt 7 0 gt is sent next The address register consists of two bytes The format of the address is as follows ADDRESS lt 15 0 gt PAGE ADDRE
27. HIGH for 500 usec and stays LOW for 15 6 usec under the Message Cueing mode See the Timing Parameters table on page 63 for RAC timing information at other sample rates When a record command is first initiated the RAC pin remains HIGH for an extra Tracto period order to load sample and hold circuits internal to the device The RAC pin can be used for message management techniques ZEN 1 ROW BEEN RAC Waveform During Message Cueing 500 usec 15 6 us Tracto T RAC RAC Waveform During Digital Erase 1 25 hsec 25 usec 38 ISDS216 Winbond Electronics Corp INT Interrupt INT is an open drain output pin The Winbond 1505216 Interrupt pin goes LOW and stays LOW when an Overflow OVF or End of Message EOM marker is detected Each operation that ends in an EOM or OVF generates an interrupt including the message cueing cycles The interrupt is cleared by a READ STATUS instruction that gives a status byte on the SDA line MCLK Master Clock Input The Master clock input for the Winbond 1505216 product has an internal pull down device Normally the Winbond ISD5216 ChipCorder section is operated at one of four internal rates selected for its internal oscillator by the Sample Rate Select bits If the internal oscillator is powered down configuration bit OSPD set to ONE the device is clocked through the MCLK pin as shown in the section SD5216 Analog Structure right
28. No Ops ISDS216 Command Bits Function C6 C5 C4 C3 DAB FN2 FN1 FNO 0 0 0 0 STOP or do nothing 0 1 0 1 Analog Play 0 0 1 0 Analog Record 0 1 1 1 Analog MC 1 1 0 0 Digital Read 1 0 0 1 Digital Write 1 0 1 0 Erase row RG2 RG1 RGO Function C2 C1 C0 0 0 0 No action 0 0 1 Load Address 0 1 0 Load 0 1 1 Load CFG1 1 0 1 Load CFG2 Publication Release Date June 2003 23 Revision 2 ISDS216 CWinbon lectronics Corp 7 5 4 OPCODE Command Byte Table Function Bits Register Bits 1 1 EF 8 STOP DONOTHING STAVON eo E STOP DO NOTHING STAY OFF E Em KE p EN E E RECORD ANALOG ADOR 1 EON MSG CUE ANALOG ADDR 89 ERASE DIGITALPAGE 00 EN N A 24 ISDS216 a Winbond 122 Nd Electronics Corp 7 5 5 Power up The ISD5216 must be powered up before sending any other commands Wait for Tpud time before sending the next command 7 5 6 Read Status When the device is polled with the Read Status command it will return three bytes of data The first byte is the status byte the next is the upper address byte and the last is the lower address byte The status register is one byte long and its bit function is BIT N
29. SS 10 0 BLOCK ADDRESS 4 0 If an analog function is selected the block address bits must be set to 00000 Digital Read and Write are block addressable Publication Release Date June 2003 25 Revision 2 ISDS216 7 5 8 Playback Mode The command sequence for an analog playback operation from a given address is the Slave Address 80h the Command Byte A9h for Play Analog Address and the two address bytes If The Play Analog A8h is sent playback starts from the current address pointer The current address pointer is returned when the three status bytes are read 7 5 9 Record Mode The command sequence for an Analog Record is a four byte sequence consisting of the Slave Address 80h the Command Byte 91h for Record Analog Address and the two address bytes The Record Analog 90h is sent recording starts from the current address pointer 7 5 10 Message Cueing Message cueing allows the user to skip through messages without having to know the actual physical location of each message This operation is used during playback In this mode the messages are skipped 512 times faster than in normal playback mode This operation will stop when an EOM marker is reached Then the internal address counter will be pointing to the next message 7 6 DIGITAL MODE 7 6 1 Writing Data The Digital Write function allows the user to select a portion of the array to be used as digital memory The partition between a
30. Slave Address with W bit 0 Write 3 Send Digital Write command c9h 4 Send high address byte 00h 5 Send low address byte a0h erase row 5 in this example 6 Write all bytes that needs to be written 7 Send 12 STOP 8 Read status byte see example above until ready bit is set 7 10 8 Digital Read 1 Send START 2 Send Slave Address with W bit 0 Write 3 Send Digital Read command eh 4 Send high address byte 00h 5 Send low address byte a0h erase row 5 in this example 6 START 7 Send Slave Address with W bit 1 Read 8 Send Read commands until all bytes have been read 9 After the last byte has been read send 10 Send I2C STOP 7 10 9 Feed Through Mode To set up the device for the various paths requires loading the three 16 bit Configuration Registers with the correct data For example in the Feed Through Mode the device only needs to be powered up and a few paths selected This mode enables the ISD5216 to connect to a cellular or cordless baseband phone chip set without affecting the audio source or destination There are two paths involved the transmit path and the receive path The transmit path connects the Winbond chip s microphone source through to the digital audio input on the baseband chip set The receive path connects the baseband chip set s digital output through to the speaker driver on the Winbond chip This allows the Winbond
31. UX OUT 25 18 20 Auxiliary Output This is one the analog outputs for the device When this output is in use the SP and SP outputs are disabled SDI 2 23 22 Serial Digital Audio PCM Input SDIO 3 24 24 Serial Digital Audio PCM Output or 25 Input Output WS 28 21 18 Digital audio PCM Frame sync FS or 2 Word Sync WS SCK 27 20 19 Digital audio PCM or 125 Serial Clock 7 8 1 28 1 28 Positive Digital Supply pins These pins carry noise generated by internal clocks in the chip They must be carefully bypassed to Digital Ground to ensure correct device operation Vesp 13 14 6 7 5 6 Digital Ground pins 1 15 21 8 14 22 11 14 23 Analog Ground pins VccA 23 16 16 Positive Analog Supply pin This pin supplies the low level audio sections for the device It should be carefully bypassed to Analog Ground to ensure correct device operation NC 26 19 21 No Connection See parameters section of datasheet ISDS216 a Winbond UT 122 Nd Electronics Corp 7 FUNCTIONAL DESCRIPTION The ISD5216 ChipCorder Product provides high quality fully integrated single chip Record Playback solutions for 8 to 16 minute messaging applications that are ideal for use in PBX systems cellular phones automotive communications GPS navigation systems and other portable products The 1505216 product is an enhancement to the 1505116 architecture providing 1 A full duplex Voice CODEC with u Law and A Law compander using
32. ad A single byte may be written to the Command Byte Register in order to power up the device start or stop Analog Record if no address information is needed or perform a Message Cueing function The Command Byte Register is loaded as follows SLAVE ADDRESS wa DATA Send Slave Address with R W bit 0 Write 8 Command Byte Host executes START 1 2 3 Host sends command byte to Slave 4 Host executes STOP 7 10 5 Load Command Byte Register Address Load For the normal addressed mode the Registers are loaded as follows 1 Host executes START 2 Send Slave Address with R W bit 0 Write 3 Host sends byte to Slave Command Byte 4 Host sends a byte to Slave High Address Byte 5 Host sends byte to Slave Low Address Byte 6 Host executes STOP 5 SLAVE ADDRESS DATA DATA DATA Publication Release Date June 2003 43 Revision 2 ISDS216 a Winbond 122 Nd Electronics Corp 7 10 6 Digital Erase 1 Hostexecutes START 2 Send Slave Address with W bit 0 Write 3 Send Digital Erase command d1h 4 Send high address byte 00h 5 Send low address byte a0h erase row 5 in this example Erase operations must be addressed on a page boundary The 5 LSB bits of the Low Address Byte will be ignored 6 Host executes STOP 7 Wait until the desired number of pages have be
33. ails the transfer explained in the section on page 22 of this datasheet Master Reads from the Slave after setting data address in Slave Write data address READ Data acknowledgement acknowledgement acknowledgement acknowledgement from slave from slave from slave from slave SLAVE ADDRESS ER COMMAND BYTE High ADDR BYTE Low ADDR BYTE Start Bit RW From From Master acknowledgement from slave a From Slave 8 BITS of DATA a From Slave a From Slave SLAVE ADDRESS 8 BITS of DATA 8 BITS of DATA X From Master 7 Start Bit RW acknowledgement acknowledgement Stop Bit From From from Master from Master From Master Master Master not acknowled from Master 18 1505216 Winbond 7 3 7 Slave Address The 1505216 has a 7 bit slave address of lt 100 OOxy gt where x and y are equal to the state respectively of the external address pins A1 and AO Because all data bytes are required to be 8 bits the LSB of the address byte is the Read Write selection bit that tells the slave whether to transmit or receive data Therefore there are eight possible slave addresses for the ISD5216 To use more than four ISD5216 devices in an application requires some external switching of the PC link Slave R W Bit HEX Value Address lt 100 00 00 gt lt 100 00 01 gt lt 100 00 10 gt lt 100 00 11 gt lt 100 00 00 gt lt 100 00 01 gt lt 100 00 10 gt lt 100 00 11 gt
34. are not used in Feed Through Mode Their bits may be set to either level In this example we will set all the Don t Care bits to a ZERO This setup should result in the following configuration register values 0 0010 0101 0100 1011 hex 254B 1 0000 0001 1110 0011 hex 01E3 CFG2 0000 0000 0100 0000 hex 0040 The three registers must be loaded with CFGO first followed by CFG1 and CFG2 The internal set up for these registers will take effect synchronously with the rising edge of SCL Publication Release Date June 2003 47 Revision B 2 ISDS216 Winbond Electronics Corp 7 10 10 Call Record The call record mode adds the ability to record the incoming phone call In most applications the ISD5216 would first be set up for Feed Through Mode as described above When the user wishes to record the incoming call the set up of the chip is modified to add that ability For the purpose of this explanation we will use the 6 4 kHz ChipCorder sample rate during recording The block diagram of the ISD5216 shows that the Multilevel Storage array is always driven from the SUM2 SUMMING amplifier The path traces back from there through the LOW PASS Filter the FILTER MUX the SUM1 SUMMING amplifier the SUM1 MUX back to the origin CODEC Feed Through Mode has already powered up the CODEC so we only need to power up and enable the path to the Multilevel Storage array from that point 1 Setup the feed th
35. ata exchanged over the Serial Data Line SDA SERIAL DATA LINE The Serial Data Line carries the data between devices on the interface Data must be valid on this line when the SCL is HIGH State changes can only take place when the SCL is LOW This is a bi directional line requiring a pull up resistor to Vcc A1 Address Pins These two pins are normally strapped for the desired address that the Winbond ISD5216 will have on the serial interface If there are four of these devices on the bus then each must be strapped differently in order to allow the master device to address them individually The possible addresses range from 80h to 87h depending upon whether the device is being written to or read from by the host The Winbond 1505216 has a 7 bit slave address of which only 0 A1 are pin programmable The eighth bit LSB is the R W bit Thus the address will be 1000 OxyO or 1000 Oxy1 RAC ROW ADDRESS CLOCK Publication Release Date June 2003 37 Revision 2 1505216 is an open drain output pin that normally marks the end of a row the 8 kHz sample frequency the duration of this period is 256 ms there are 1888 pages of memory in the Winbond ISD5216 device RAC stays HIGH for 248 ms and goes LOW for the remaining 8 ms before it reaches the end of the page 1 ROW i RAC Waveform During 8 KHz Operation 256 lt 2 msec RAC 8 msec Tracto RAC pin remains
36. ation to follow and waits for the Tpud time before sending the next command sequence ACK Acknowledge No ACK Send Start Send one byte 10000000 Slave Address R W 0 80h 7 bit SI Send one byte 10000000 Command Byte Power Up 80h niu ud Stop DEZ FE TE Power up 80h PONS The Box color indicates the direction of data flow E Host to Slave Gray E Slave to Host White 7 10 3 Read Status command The read status command is a read request from the Host processor to the ISD5216 without delivering a Command Byte The Host supplies all of the clocks SCL The 1505216 drives the data line SDA During the read commands to read status send the following sequence Host executes START Send Slave Address with R W bit 1 Read 81h Read one byte of data and send ACK the read data is the status byte Read one byte of data and send ACK the read data is the upper address byte Read one byte of data and send NACK the read data is the lower address byte Host sends STOP Note processor could have sent STOP after the Status Word data transfer and thus aborted the transfer of the Address bytes 42 ISDS216 A graphical representation of this operation is found below See the caption box above for more explanation E SLAVE ADDRESS DATA DATA E DATA High Addr 7 10 4 Load Command Byte Register Single Byte Lo
37. chip to substitute for Analog to Digital and Digital to Analog conversion and incidentally gain access to the audio both to and from the baseband chip set To setup the environment described above a series of commands need to be sent to the ISD5216 First the chip needs to be powered up as described in Power Up Sequence on page 25 Then the Configuration Registers need to be filled with the specific data to connect the desired paths In the case of the Feed Through Mode most of the chip can remain powered down The Feed Through Mode diagram illustrates the affected paths The following example shows the setup for a full duplex feed through path at 8 kHz sampling rate The twos complement data format is enabled The High Pass filter is also enabled The Master Clock input is running at 13 824MHz To select the Feed Through mode the following control bits must be configured in the ISD5216 configuration register Publication Release Date June 2003 45 Revision 2 ISDS216 Winbond Electronics Corp FILTO SPEAKER lt SDI SP 1 ws 5 LAWI LAWO OPS1 0PS0 SCK gt O A Law SDIO s5b5555555 Compressor 2 1 Connect the microphone to the CODEC input Bits and CDIO control state of the CODEC INPUT MUX These are the D6 and D5 bits respectively of Configuration Register 0 CFGO and they should set to ONE
38. ck lines remain HIGH when the interface bus is not busy A HIGH to LOW transition of the data line while the clock is HIGH is defined as the start condition S A LOW to HIGH transition of the data line while the clock is HIGH is defined as the stop condition P Publication Release Date June 2003 15 Revision B 2 ISDS216 a Winbond UT 122 Nd Electronics Corp 7 3 3 Bit transfer One data bit is transferred during each clock pulse The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal The same timing applies to both read and write data line changed stable of data data valid allowed Bit transfer the 7 3 4 ACKNOWLEDGE The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited Each byte of eight bits is followed by an acknowledge bit The acknowledge bit is a HIGH level signal put on the interface bus by the transmitter during which time the master generates an extra acknowledge related clock pulse A slave receiver which is addressed must generate an acknowledge after the reception of each byte In addition a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter The device that acknowledges must pull down the SDA line during the acknowled
39. d is sent If an active command is sent before the internal cycle is finished the 1505216 will hold SCL LOW until the current command is finished 7 6 2 Reading Data The Digital Read command utilizes the combined command format That is command is sent to the chip using the write data direction Then the data direction is reversed by sending a repeated start condition and the slave address with R W set to one After this the slave device 1505216 begins to send data to the master until the master generates a Not Acknowledge If the part encounters an overflow condition the INT pin is pulled LOW No other communication with the master is possible due to the master generating ACK signals 26 ISDS216 Winbond Electronics Corp As with Digital Write Digital Read can be done block at a time Thus only 64 bits need to be read in each Digital Read command sequence 7 6 3 Erasing Data The Digital Erase command can only erase an entire page at a time This means that the DO or D1 command only needs to include the 11 bit page address the 5 bit for block address are left at 00000 Once a page has been erased each block may be written separately 64 bits at a time But if a block has been previously written then the entire page of 2048 bits must be erased in order to re write or change a block While erasing data the RAC pin will have a pulse at the end of each erased page when the stop erase command is sen
40. ded low level input signals If the configuration bit 0 lt 7 gt is set to ZERO all input levels are recorded with the same gain setting The attack and release time of the Auto Gain and Auto Mute functions is set by the capacitor on the ACAP pin The AGC cannot be used if the Auto Gain or Auto Mute function is enabled Tattack 0 1504 x Vpeak Trelease 6 58 x Vpeak Cattcap 4 7 uF Expand Compress Gain 0 Gain 12 dB dB 12 0 0 Vpp 0 Vpp Publication Release Date June 2003 41 Revision B 2 ISDS216 Winbond Electronics Corp 7 10 PROGRAMMING THE ISD 5216 7 10 1 Sending byte 12 interface Conventions used Data When reading or writing byte of data on the bus two different Transfer Diagrams mechanisms for flow control are used the first is the standard ACK that the slave or master sends after reading or writing a byte but the 1505216 also uses flow control by holding the clock line SCL low until the chip is ready to transmit data START Condition For example the sequence of sending the slave address will be as STOP Condition follows 1 Send one byte 10000000 Slave Address R W 0 80h 2 Slave 3 Next time the clock is pulled high by the master for SCL 1 in the R W bit to actually go high 0 in the R W bit 7 10 2 POWER UP SEQUENCE This sequence prepares the SD5216 for an oper
41. e Address consists of 7 bits followed by a single bit that indicates the direction of data flow This single bit is 1 for a Write cycle which indicates the data is being sent from the current bus master to the device being addressed This single bit is a 0 for a Read cycle which indicates that the data is being sent from the device being addressed to the current bus master Before any data is transmitted on the interface the current bus master must address the slave it wishes to transfer data to or from The Slave Address is always sent out as the 1 byte following the Start Condition sequence An example of a Master transmitting an address to a ISD5216 slave is shown below In this case the Master is writing data to the slave and the R W bit is 0 i e a Write cycle All the bits transferred are from the Master to the Slave except for the indicated Acknowledge bits Master Transmits to Slave Receiver Write Mode acknowledgement acknowledgement acknowledgement acknowledgement from slave from slave from slave from slave SLAVE ADDRESS COMMAND BYTE High ADDR BYTE Low ADDR BYTE Start Bit R Stop Bit common procedure in 1505216 is reading of the Status Bytes The Read Status condition in the ISD5216 is triggered when the Master addresses the chip with its proper Slave Address immediately followed by the R W bit set to 0 and without the Command Byte being sent This is example of
42. e e eod dc Ea ou 60 10 ELECTRICAL CHARACTERISTIGS uite Uds dete Ee 61 11 TYPICAL APPLICATION CIRCUIT ei rele eroe tede cet pere A A 67 12 PACKAGE SPECIFICATIONG deine aera 70 Publication Release Date June 2003 B5 Revision B 2 1505216 12 1 PLASTIC THIN SMALL OUTLINE PACKAGE TSOP TYPE DIMENSIONS 70 12 2 Plastic Small Outline Integrated Circuit SOIC DIMENSIONS sesser 71 12 3 Plastic Dual Inline Package PDIP Dimensions pp 72 13 ORDERING INFORMATION e 73 14 VERSION HISTORY 74 1505216 QWinbond Electronics Corp 5 PIN CONFIGURATION ISD5216 Pin Layout AUX OUT AUX IN Veca SP 0000000000000 28 PIN TSOP AN DA FW M o N s A m Please note that the pin assignments are different for the PDIP and the SOIC packages zu Revision B 2 6 PIN DESCRIPTION ISDS216 Pin Name Pin No Pin No Pin No Functionality 28 pin 28 pin 28 pin TSOP PDIP SOIC RAC 4 25 25 Row Address Clock an
43. ective owners This product incorporates SuperFlash technology licensed From SST 275 Winbond Electronics H K Ltd Unit 9 15 22F Millennium City No 378 Kwun Tong Rd Kowloon Hong Kong TEL 852 27513100 FAX 852 27552064 Publication Release Date June 2003 Revision B 2
44. ed authorized or warranted for use as components in systems or equipments intended for surgical implantation atomic energy control instruments airplane or spaceship instruments transportation instruments traffic signal instruments combustion control instruments or for other applications intended to support or sustain life Furthermore Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury death or severe property or environmental injury could occur Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and Winbond makes no representation or warranty that such applications shall be suitable for the use specified ISD and ChipCorder are trademarks of Winbond Electronics Corporation SuperFlash is the trademark of Silicon Storage Technology Inc The 100 year retention and 10K record cycle projections are based upon accelerated reliability tests as published in the Winbond Reliability Report and are neither warranted nor guaranteed by Winbond This product incorporates SuperFlash technology Information contained in this ISD ChipCorder data sheet supersedes all data for the ISD ChipCorder products published by ISD prior to August 1998 This data sheet and any future addendum to this data sheet is are the complete and controlling IsD ChipCorder product specifications In
45. en erased There will be a pulse on the RAC pin for each page that is erased After the stop command described below has been received erasing will stop at the end of the page currently being erased To erase one page only issue the stop command immediately after the start erase command 8 Host executes START 9 Send Slave Address with W bit 0 Write 10 Send the Stop command cOh 11 Host executes STOP Erase starts on falling edge of Slave acknowledge Command Byte Low Addr Byte High Addr Byte Command Byte Notes 1 bus is released while erase proceeds Other devices may use the bus until it is time to execute the STOP command that causes the end of the Erase operation 2 Host processor must count RAC cycles to determine where the chip is in the erase process one row per RAC cycle RAC pulses LOW for 0 25 microsecond at the end of each erased row erase of the row begins with the rising edge of See the Digital Erase RAC timing diagram on page 46 3 4 When the erase of the last desired row begins the following STOP command Command Byte 80 hex must be issued This command must be completely given including receiving the ACK from the Slave before the RAC pin goes HIGH 25 microseconds before the end of the row 44 ISDS216 Winbond SED Electronics Corp 7 10 7 Digital Write 1 Send 12 START 2 Send
46. er up 1 Divide by 2 1 Divide by 2560 1 Power Down Configuration Register CFG1 and CFG2 The bits described on this page are highlighted CIG2 CIG1 CIGO AXG1 AXGO AXPD INSO OSPD AMTO CDM 0 81 OPSO VLPD CFGO 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 VLS1 VLSO VOL2 voL1 VOLO 5151 150 S1M1 81 0 S2M1 S2MO FLSO FEDI FIDO FEPD AGPD N 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 X X X 2 COG1 COGO MUTE HSRO 1250 LAW1 DAPD ADPD CFG2 2324 Winbond Electronics Corp 7 7 1 Speaker AUX OUT and Volume Control Description VOLO ISD5216 AUX OUT SPEAKER VOL 1 fb VOL2 ex State the State of aux out VLPD Switch volume speaker output control on or off 0 0 Power Down Power Down Power Up 0 1 13 6 Voer Q 1500 Power Down Power Down 1 0 23 5 980 Power Down 1 1 Power Down 1 Vp p 5 VEST input VOL2 VOLT VOL Attenuation source to the 0 volume mux i OPS1 OPSO Select input source 0 0 DACOUT to the gt analog 0 1 SUM2 0 0 1 4dB output mux 1 0 SUMI 2 1 0 8 dB 0 0
47. eries devices please refer to the following valid part numbers Part Number Part Number 15216E 152165 15216ED 15216P 15216EI 1521631 Chip scale package is available upon customer s request For the latest product information access Winbond s worldwide website at http www winbond usa com Publication Release Date June 2003 73 Revision B 2 Electronics Corp 14 VERSION HISTORY ISDS216 VERSION DATE DESCRIPTION A1 Nov 2001 Initial issue B 1 Aug 2002 Overall updates not available in die form B 2 Jun 2003 Update cover page Replace all 15216 by ISD5216 74 1505216 CWinbond The contents of this document are provided only as a guide for the applications of Winbond products Winbond makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice No license whether express or implied to any intellectual property or other right of Winbond or others is granted by this publication Except as set forth in Winbond s Standard Terms and Conditions of Sale Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability fitness for a particular purpose or infringement of any Intellectual property Winbond products are not designed intend
48. fier Bits S2MO and 52 1 control the state of the SUM2 SUMMING amplifier These are bits D5 and D6 respectively of CFG1 Set D5 to ZERO and D6 to ONE to select the LOW PASS FILTER only path 5 Select the SUM2 SUMMING amplifier path through the VOLUME MUX Bits VLSO and VLS1 control the VOLUME MUX stage These bits are D14 and D15 respectively of CFG1 Set D14 to ONE and D15 to ZERO to select the SUM2 SUMMING amplifier 6 Power up the VOLUME CONTROL LEVEL Bit VLPD controls the power up state of the VOLUME CONTROL attenuator This is Bit DO of CFGO Set this bit to a ZERO 7 Select a VOLUME CONTROL LEVEL Bits VOLO VOL1 and VOL2 control the state of the VOL UME CONTROL LEVEL These are bits D11 D12 and D13 respectively of CFG1 A binary count of 000 through 111 controls the amount of attenuation through that stage To set an attenuation of 12 dB D11 should be set to ONE D12 should be set to ONE and D13 should be set to a ZERO 8 Select the VOLUME CONTROL path through the OUTPUT MUX These bits and D4 respectively of CFGO Set D3 to ZERO and D4 is a ZERO to select the VOLUME CONTROL 9 Power the SPEAKER amplifier and select the HIGH GAIN mode Bits and control the state of the speaker SP and SP and AUX OUT outputs These are bits D1 and D2 of CFGO Set D1 to ONE and D2 to ZERO to power up the speaker outputs in the HIGH GAIN mode and to power down the AUX OUT 10 Power up
49. figuring the device Looking at the block diagram on the following page one can see that the ISD5216 may be very easily designed into a cellular phone Placing the device between the microphone and the existing baseband chip takes care of the transmit path The SDI SDIO of the baseband chip is connected to the SDIO SDI of the ISD5216 Two pins are needed for the digital control and digital information for storage 15216 BasebandSection K Earpiece Display Starting at the MICROPHONE inputs the input signal at the MICROPHONE inputs can be routed in the following ways e directly through the Voice band CODEC of the ISD5216 chip then through the SDIO pin to output the digital PCM signal e through the AGC amplifier before it is routed to the voice band CODEC e through the AGC amplifier to the storage array e through the AGC amplifier and mixed with an analog voice band CODEC signal coming from the digital SDI pin In addition if the phone is inserted into a hands free car kit then the signal from the pickup microphone in the car can be passed through to the same places from the AUX IN pin and the phone s microphone is switched off In this scenario the other party s voice from the phone would be played into the PCM IN input and passed through to the AUX OUT pin that would drive the car kit s loudspeaker Publication Release Date June 2003 67 Revision B 2 1505216 Winbond Depending upon
50. filter signal 08 OSPD Power down the internal ChipCorder oscillator D9 INSO Select Microphone input or Auxiliary input D10 AXPD Power down Auxiliary input amplifier D11 AXGO Auxiliary input amplifier gain setting D12 AXG1 Auxiliary input amplifier gain setting D13 CIGO Input gain setting for the Analog to digital converter D14 CIG1 Input gain setting for the Analog to digital converter 015 MSB CIG2 Input gain setting for the Analog to digital converter 28 ISDS216 QWinbond Electronics Corp CFG1 Bit no Signal Description DO LSB AGPD Power down the Microphone AGC D1 FLPD Power down the Filter D2 FLDO Set the duration and sample rate of the ChipCorder D3 FLD1 Set the duration and sample rate of the ChipCorder D4 FLSO Select the filter input signal D5 S2M0 Select Sum Amplifier 2 input D6 S2M1 Select Sum Amplifier 2 input D7 S1M0 Select Sum Amplifier 1 input D8 S1M1 Select Sum Amplifier 1 input D9 5150 Select Sum Amplifier 1 multiplexer D10 S1S1 Select Sum Amplifier 1 multiplexer D11 VOLO Volume Control Setting D12 VOL1 Volume Control Setting D13 VOL2 Volume Control Setting D14 VLSO Select Volume Control input D15 MSB VLS1 Select Volume Control input Publication Release Date June 2003 29 Revision 2 ISDS216 QWinbond Electronics C
51. ge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse set up and hold times must be taken into consideration A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition BY TRANSMITTER not acknowledge DATA OUTPUT BY acknowledge SCL FROM 1 2 MASTER Ls 1 dock pulse for START acknowledgement condition Acknowledge the I C bus 16 ISDS216 7 3 5 Additional ISD5216 flow control The Interface in the ISD5216 differs from the standard implementation in the way the SCL line is also used for flow control The ISD5216 will hold the clock line low until it is ready to accept another command data SCL line must be implemented as bi directional line like the SDA line For example the sequence of sending the slave address will be as follows 1 Send one byte 10000000 Slave Address R W 0 80h 2 Wait for slave to acknowledge ACK 3 Next time the clock is pulled high by the master wait for SCL to actually go high 7 3 6 Protocol Addressing Since the protocol allows multiple devices on the bus each device must have an address This address is known as a Slave Address A Slav
52. iasing filter which can be muted to suppress noise the mute bit controls both the A D and D A filter simultaneously The following high pass filter is enabled by bit HPFO in the configuration register The High Sampling Rate bit HSRO needs to be set to enable operation at 44 1kHz 48 kHz The digital audio signal can be companded using Law and A Law companding or go to the output uncompressed using 2 s complement or signed magnitude output selected with bits LAW1 LAWO in the configuration registers Finally the digital output interface is selected to be either full duplex PCM or half duplex 175 using the interface selector bit 260 in the configuration register The PCM interface uses the SDIO and SDI pins the half duplex 155 format uses the SDIO pin as both input and output 2 ISDS216 amp Winbond Electronics Corp 7 2 2 Digital Input to Analog Output Path The digital input interface must be selected to either PCM or 29 using interface selector bit 250 in the configuration register The compression format must also selected with bits LAW1 LAWO in the configuration registers The external clock input signal on pin MCLK and the internal clock dividers must be set to values supporting the selected digital input signal The digital smoothing and interpolation filter runs at 3 4 kHz and feeds the XA D A converter that can be switched off to conserve power and reduce
53. ion Its u Law and A Law compander meets the specification of the ITU T G 711 recommendation The CODEC operates in full duplex in PCM mode and half duplex 1275 mode Operating the CODEC requires an external master clock running at 13 824 MHz 20 48 MHz 27 648 MHz or 40 96 MHz This provides a sampling frequency ranging from 8kHz to 48kHz Publication Release Date June 2003 11 Revision 2 1505216 Winbond The following diagram shows the functional blocks in the CODEC piA Law Mbit Digital 14 bit Digital as 2 mure m DAO ANALOG OUT 1 bit D A ANALOG IN 8 bits or 16 bits 21 ws SCK 5010 501 MCLK 7 2 1 Analog Input to Digital Output Path A 200 kHz anti aliasing filter processes the analog input signal before entering the amplifier for the A D converter The gain of this amplifier is adjustable through the configuration registers bits CIG2 CIGO for a gain from 0 80 to 2 00 The Sigma Delta modulator is a Linear 14 bit ZA modulator running at a sampling frequency determined by the external clock input and the internal clock dividers CKD2 CKDV The standard telecom frequency of 8kHz and digital audio of 44 1kHz and 48 kHz as well as intermediate frequencies as shown in the table on the next page are supported The A D converter can be turned off to save power and reduce noise by setting the A D power down bit ADPD The A D converter feeds a 3 4 kHz digital anti al
54. ive the speaker circuit in a car kit It drives a minimum load of 5 and up to a maximum of 1 V p p The AC signal is superimposed on approximately 1 2 VDC bias and must be capacitively coupled to the load AUX IN Auxiliary Input The AUX IN is an additional audio input to the Winbond SD5216 such as from the microphone circuit in a mobile phone car kit This input has a nominal 694 mV p p level at its minimum gain setting 0 dB See Aux In Amplifier Gain Settings Table below Additional gain is available in 3 dB steps controlled by the interface up to 9 dB OTLP Input Gain Setting Gain dB Gain Array In Out Vp p Speaker Out Vp P 0 694 00 0 1 00 0 694 0 694 0 491 01 3 141 0 694 0 694 0 347 10 6 2 00 0 694 0 694 0 245 11 9 2 82 0 694 0 694 Gain from AUX IN to ARRAY IN 2 OTLP Input is the reference Transmission Level Point that is used for testing This level is typically 3 dB below clipping 3 Differential 40 1505216 Winbond 7 9 AUTO MUTE AND AUTO GAIN FUNCTIONS During playback the signal passes through the Automatic Attenuator before it is filtered The Automatic Attenuator will attenuate all signals at the noise level in order to reduce the noise during quiet pauses During record low level input signals are brought up by the Auto Gain function if the configuration bit D7 of CFGO is set This improves the signal to noise ratio of recor
55. ker Amplifier and configures it for a higher gain setting for use with a piezo speaker element and also powers down the AUX output stage 46 10 11 12 13 14 15 16 ISDS216 Electronics Corp Power down the Volume Control Element Bit VLPD controls the power up state of the Volume Control This is bit DO of CFGO and it should be set to a ONE to power down this stage Power down the internal oscillator Bit PDOS controls the power up state of the internal ChipCorder oscillator This is bit D8 of CFGO and it should be set to ONE to power down this oscillator Power down the AUX IN amplifier Bit AXPD controls the power up state of the AUX IN input amplifier This is bit D10 of CFGO and it should be set to a ONE to power down this stage Power down SUM1 and SUM2 Mixer amplifiers Bits S1MO and S1M1 control the SUM 1 mixer and bits 52 0 and S2M1 control the SUM2 mixer These are bits D7 and 08 in CFG1 and bits D5 and D6 in CFG1 respectively All four bits should be set to a ONE in order to power down these two amplifiers Power down the FILTER stage Bit FLPD controls the power up state of the FILTER stage in the device This is bit D1 in CFG1 and should be set to a ONE to power down the stage Power down the AGC amplifier Bit AGPD controls the power up state of the AGC amplifier This is bit DO in CFG1 and should be set to a ONE to power down this stage Don t Care bits All other bits
56. nalog and digital memory is left up to the user A page can only be either Digital or Analog but not both The minimum addressable block of memory in the digital mode is 1 block or 64 bits when reading or writing The address sent to the device is the 11 bit row or page address with the 5 bit scan or block address However one must send a Digital Erase before attempting to change digital data on a page This means that even when changing only one of the 32 blocks all 32 will need to be rewritten to the page After the address is entered the data is sent in one byte packets followed by acknowledge generated by the chip Data for each block is sent MSB first The data transfer is ended when the master generates STOP condition If only partial block of data is sent before the STOP condition zero is written in the remaining bytes that is they are left at the erase level An erased page row will be read as all zeros The device can buffer up to two blocks of data If device is unable to accept more data due to the internal write process the SCL line will be held LOW indicating to the master to halt data transfer If the device encounters an overflow condition it will respond by generating an interrupt condition and an Not Acknowledge signal after the last valid byte of data Once data transfer is terminated the device needs up to two cycles 64 us to complete its internal write cycle before another comman
57. nfiguration Register CFG1 and CFG2 The bits described this page are highlighted 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CIG2 CIG1 CIGO AXG1 AXGO AXPD INSO OSPD AMTO CDI1 CDIO OPS1 OPSO OPA1 OPAO VLPD CFG0 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 VLS1 VLSO VOL2 VOL1 VOLO S181 5180 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLDO FLPD AGPD 0 X X X CKD2 COG2 COG1 COGO CKDV MUTE HPFO HSRO 1280 LAW1 LAWO DAPD ADPD CFG2 34 e Vinbond Electronics Corp 7 7 3 CODEC Configuration First Page SCK 00 SDI ISDS216 ANALOG OUT coco 2 Sample frequency CIG2 CIG1 CIGO ADC GAIN COG2 COG1 COG0 DAC GAIN dB 0 0 0 0 80 0 0 0 0 0 0 1 1 00 0 0 1 2 0 1 0 1 20 0 1 0 4 0 1 1 1 25 0 1 1 6 1 0 0 1 40 1 0 0 8 1 0 1 1 60 1 0 1 6 1 1 0 1 80 1 1 0 4 1 1 1 2 00 1 1 1 2 Configuration Register CFG0 CFG1 and CFG2 The bits described on this page are highlighted 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CIG2 CIG1 CIGO AXG1 AXPD INSO OSPD AMTO CDI 0 81 0 80 VLPD CFGO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VLS1 VOL2 VOLO S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLSO FLD1 FLDO FLPD AGPD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X CKD2
58. ode Nominal differential input is 208 mV p p OTLP 5 Sampling frequency can vary as much as 6 4 percent over the industrial temperature and voltage ranges For greater stability an external clock can be utilized see Pin Descriptions 6 Playback and Record Duration can vary as much as 6 4 percent over the industrial temperature and voltage ranges For greater stability an external clock can be utilized see Pin Descriptions 7 Filter specification applies to the low pass filter 8 For optimal signal quality this maximum limit is recommended 9 When a record command is sent Trac Trac on the first page addressed 10 The maximum signal level at any input is defined as 3 17 dB higher than the reference transmission level point OTLP This is the point where signal clipping may begin 11 Measured at OTLP point for each gain setting See AUX IN table 12 OTLP is the reference test level through inputs and outputs See AUX IN table 13 Referenced to OTLP input at 1 kHz measured over 300 to 3 400 Hz bandwidth 14 For die only typical values are applicable 66 ISDS216 Winbond 11122 Electronics Corp 11 TYPICAL APPLICATION CIRCUIT APPLICATIONS The 1505216 single chip solution for voice and analog storage that also includes the capability to store digital information in the memory array The array may be divided between analog and digital storage as the user chooses when con
59. open drain output The RAC pin goes LOW Tracie before the end of each row of memory and returns HIGH at exactly the end of each row of memory INT 5 26 26 Interrupt Output an open drain output indicating that a set EOM bit has been found during Playback or that the chip is in an Overflow OVF condition This pin remains LOW until a Read Status command is executed MCLK 6 27 27 This pin allows the internal clock of the Voice record playback system to be externally driven for enhanced timing precision This pin is grounded for most applications It is required for the CODEC operation SCL 9 2 2 Serial Clock Line is part of the serial bus It is used to clock the data into and out of the interface SDA 11 4 4 Serial Data Line is part of the serial bus Data is passed between devices on the bus over this line AO 12 5 7 Input pin that supplies the LSB for the Slave Address 1 10 3 3 Input that supplies the LSB 1 bit for the Slave Address MIC 16 9 10 Differential positive Input to the microphone amplifier MIC 17 10 9 Differential negative Input to the microphone amplifier MICBS 18 11 8 Microphone Bias Voltage ACAP 19 12 12 AGC Capacitor connection Required for the on chip AGC amplifier SP 22 15 15 Differential Positive Speaker Driver Output SP 20 13 13 Differential Negative Speaker Driver Output When the speaker outputs are in use the AUX OUT output is disabled AUX IN 24 17 17 Auxiliary Input A
60. ording The system micro controller stores this information in the Message Address Table MICROCONTROLLER INTERFACE The 1505216 is controlled through an 2 wire interface This synchronous serial port allows commands configurations address data and digital data to be loaded to the device while allowing status digital data and current address information to be read back from the device In addition to the serial interface two other pins can be connected to the microcontroller for enhanced interface the RAC timing pin and the INT for interrupts to the controller Communications with all of the internal registers is through the serial bus as well as digital memory Read and Write operations PROGRAMMING The ISD5216 series is also ideal for playback only applications whereas single or multiple messages may be played back when desired Playback is controlled through the port Once the desired message configuration is created duplicates can easily be generated via a Winbond or third party programmer For more information on available application tools and programmers please see the Winbond web site at http Awww winbond usa com AUDIO PATHS The 1505216 has extremely powerful audio routing functionality where all audio signals can be routed and multiplexed to multiple destinations A few examples are Simultaneous recording of microphone input and CODEC DAC output for recording both parties of a phone call 10 ISDS
61. ording is limited to the 256 msec resolution provided by the 11 bit address A recording does not immediately stop when the Stop command is issued but continues until the 32 millisecond block is filled Then a bit is placed into the EOM memory to develop the interrupt that signals a message is finished playing in the Playback mode Digital data is sent and received serially over the interface The data is serial to parallel converted and stored in one of two alternating commutating 64 bit shift registers When an input register is full it becomes the register that is parallel written into the array The prior write register becomes the new serial input register A mechanism is built in to ensure there is always a register available for storing new data Storing data in the memory is accomplished by accepting data one byte at a time and issuing an acknowledgement If data is coming in faster than it can be written then the chip will not issue an acknowledgement to the host microcontroller until it is ready The read mode is the opposite of the write mode Data is read into one of two 64 bit registers from the array and serially sent to the PC port See Digital Mode on page 26 for details 7 2 CODEC The CODEC built into the ISD5216 supports both the IS and PCM digital interface using u Law and A Law companding as well as 2 s complement and signed magnitude data The CODEC meets the PCM conformance specification of the G 714 recommendat
62. orp CFG2 Bit no Signal Description DO LSB ADPD Power down the Analog to Digital converter D1 DAPD Power down the Digital to Analog converter D2 LAWO Select digital u Law or A Law input output format D3 LAW1 Select digital u Law or A Law input output format D4 1250 Select the 125 interface D5 HSRO Enable the high sample rate mode D6 HPFO Enable High Pass Filter 07 MUTE Mute the CODEC A D and D A path D8 CKDV Divide by 2560 or 1728 for 8 kHz ChipCorder sample rate D9 0 Output gain setting for the Digital to Analog converter D10 COG1 Output gain setting for the Digital to Analog converter D11 COG2 Output gain setting for the Digital to Analog converter D12 CKD2 Divide frequency by 2 1 D13 Reserved D14 Reserved D15 MSB Reserved 30 iinbond Electronics Corp 7 7 1SD5216 ANALOG STRUCTURE LEFT HALF description INSO Select whether send the AUX input or the microphone signal to the summing amp to AGC AMP AUX IN AMP Configuration Register CFG1 and CFG2 The bits described this page are highlighted ISDS216 S1M0 This summing amp allows the signal from the input mux or sum 1 mux to be selected or added together Set the amp to OFF to switch off completely 0 BOTH 1 SUM1 MUX ONLY 0 INP Only 1 POWER DOWN 5181 5150 Select whether to send the signal
63. quency MCLK 20 48MHz Master clock frequency 500 0 500 ppm accuracy Master Clock Duty Cycle 48 50 52 25 PARAMETERS all values in nano seconds Parameter Transmitter Receiver NOTE Lower Limit Upper Limit Lower Limit Upper Limit 5 MIN MIN MIN MIN Bit Clock period 325 325 High time thc 114 114 Low time tic 114 114 Rise time tRc 49 Delay tar 260 Hold time thir 100 Set up time tsr 65 Hold time 0 56 1505216 QWinbond Electronics Corp SDI dee 213121669 68 07 JD6 JOS 04 02 Long Frame Sync PCM Timing for 14 bits example Short Frame Sync PCM Timing Publication Release Date June 2003 57 Revision B 2 1505216 QWinbond Electronics Corp ur eA rl RR RR HI WIS SDIO Short Frame Sync Transmit PCM Timing Parameters o Qe ls SE L soi 52 51 55 LSB Short Frame Sync Receive PCM Timing Parameters Tasa T NA LI A RON WS SCK SDIO Long Frame Sync Transmit PCM Timing Parameters BM 1 NNNM WS T SCK Tarsi t HD7 De os 53 o2 D700 MSB LSB Long Frame Sync Receive PCM Timing Parameters 52555 6 Winbond Electronics Corp PCM PARAMETERS Hold Time for 2 cycle of Bit clock
64. rface ports o Serial transfer data rate from 64 to 3072 Kbps o Short and Long frame sync formats o 2s complement and signed magnitude data format o Complete p Law and A Law companding o Linear 14 bit AZ PCM CODEC filter for A D and D A converter o 8 kHz or 44 1 kHz 48 kHz digital audio sampling rate options o Analog receive and transmit gain adjust o Configurable setup through the 12 interface ISDS216 3 BLOCK DIAGRAM 15216 Block Diagram 2 2V Voltage i MICROPHONE Auto mute Low Pass Auto gain Filter 7 150 4 FLPD 52 0 2 SM AGCCAPo lndul Internal Multilevel Clock Storage Array OSPD FLDO a s E CSDL 265 5 SUM2 Array Mu OO il SSNs CTRL ram Read Control MIC ickpy DIGITAL Progrem sad Control MIC ARRAY OUT 1 DIGITAL 82 02 V LIO AUX OUT SPEAKER SP xnwindino INP o SP pomo OPA1 Control 4 VOL2 VLSO VLS1 A Law Linear 14 bit CODEC Power Conditioning Device Control 7222220
65. riod of the SCL signal it must output the next data bit to the SDA line tsu nar 1000 250 1250 ns according to the Standard mode PC interface specification before the SCL line is released 2 C total capacitance of one bus line in pF If mixed with HS mode devices faster fall times are allowed 54 1505216 QWinbond Electronics Corp 5 TIMING DIAGRAMS tyc 0 35T Timing 125 Transmitter tyc 0 35T Timing 1 S Receiver Clock rise time definition with respect to the voltage levels Publication Release Date June 2003 55 Revision B 2 QWinbond Electronics Corp CODEC Parameters The internal CODEC meets the specification of the ITU T G 714 recommendation in 8 kHz sampling mode This specification is verified using the MIC and SPEAKER pins as analog input and output ISD5216 The CODEC MA Law Compander meets the specification of the ITU T G 711 u A Law companding recommendation Symbol Parameters Min Typ Max Units Conditions LABS Absolute level Vrms 0 2 50 600 Q Tyxmax Max Transmit level 2 Vpp Mic Mic differential foni High pass filter gt cut off 300 Hz WS 8kHz frequency MCLK 13 824MHz Low pass filter cut off 3400 Hz WS 8kHz frequency MCLK 13 824MHz foo Low pass filter cut off 4686 5037 5100 Hz WS 44 1kHz 48kHz fre
66. rough mode described in the previous section 2 Select the CODEC path through the SUM1 MUX Bits S1S0 and S1S1 control the state of the SUM1 MUX These are bits D9 D10 respectively of CFG1 and they should set to the state where both D9 and D10 are ZERO to select the CODEC path 3 Select the SUM1 MUX input only to the 1 SUMMING amplifier Bits 51 0 and S1M1 control the state of the SUM1 SUMMING amplifier These are bits D7 and D8 respectively of CFG1 and they should be set to the state where D7 is ONE and D8 is ZERO to select the SUM1 MUX only path 4 Select the SUM1 SUMMING amplifier path through the FILTER MUX Bit FLSO controls the state of the FILTER MUX This is bit DA of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path 5 Deselect the signal compression Bit AMTO controls the signal compression This is bit D7 of CFGO and it must be set to ZERO 6 Power up the LOW PASS FILTER Bit FLPD controls the power up state of the LOW PASS FILTER stage This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE 7 Select the 6 4 kHz sample rate Bits FLDO and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback These are bits D2 and D3 of CFG1 To enable the 6 4 kHz sample rate D2 must be set to ONE and D3 set to ZERO 8 Select the LOW PASS FILTER input only to the 52 SUMMING amplifier Bits 52 0 and S2M1 control
67. rs The Command byte sent is used to start and stop recording write or read digital data and perform other functions necessary for the operation of the device 7 5 1 Command Byte Control of the ISD5216 is implemented through an 8 bit command byte that is sent after the 7 bit device address and the 1 bit Read Write selection bit The 8 bits are power up bit PU bit determines whether device is performing analog digital function 3 function bits these determine which function the device is to perform conjunction with the DAB bit 3 register address bits these determine if and when data is to loaded to register maner Reuss 27 Electronics Corp 7 5 2 Function Bits The command byte function bits are detailed in the table to the right C6 the DAB bit determines whether the device is performing an analog or digital function The other bits are decoded to produce the individual commands Note that not all decode combinations are currently used they are reserved for future use Out of 16 possible codes the ISD5216 uses 7 for normal operation The other 9 are No Ops 7 5 3 Register Bits The register load may be used to modify a command sequence such as load an address or used with the null command sequence to load a configuration or test register Not all registers are accessible to the user The remaining three codes are
68. sec 6 4 kHz sample rate 1 msec 5 3 kHz sample rate 1 msec 4 0 kHz sample rate 1 msec Tstop OR pause Stop or Pause Record or Play 8 0 kHz sample rate 32 msec 6 4 kHz sample rate 40 msec 5 3 kHz sample rate 48 msec 4 0 kHz sample rate 64 msec 62 Winbond Electronics Corp ISDS216 Symbol Parameters Min Typ Units Conditions Trac RAC Clock Period 8 0 kHz sample rate 256 msec P 6 4 kHz sample rate 320 msec Pl 5 3 kHz sample rate 386 msec Pl 4 0 kHz sample rate 512 msec TRACLO RAC Clock Low Time 8 0 kHz sample rate 8 msec 6 4 kHz sample rate 10 msec 5 3 kHz sample rate 12 1 msec 4 0 kHz sample rate 16 msec TRACM Clock Period Message Cueing Mode 8 0 kHz sample rate 500 6 4 kHz sample rate 625 met 5 3 kHz sample rate 750 mseg 4 0 kHz sample rate 1000 msec TRACML RAC Clock Low Time in Message Cueing Mode 8 0 kHz sample rate 156 mide 6 4 kHz sample rate 19 5 Mene 5 3 kHz sample rate 23 4 Edd 4 0 kHz sample rate 312 THD Total Harmonic Distortion 1 KHz at AUX IN to ARRAY 1 sample rate 5 3 ARRAY to SPKR 1 ane 63 Publication Release Date June 2003 Revision B 2 iinbond Electronics Corp ANALOG PARAMETERS MICROPHONE INPUT 41 1505216
69. t the device will stop erasing at the end of the current page To erase a single page the stop command should be sent immediately after the start erase command To erase multiple pages count pulses on the RAC pin and send the stop command after n 1 RAC pulses have been detected where n is the number of pages to erase A sequence might look like read the entire page store it in RAM change the desired bit s erase the page write the new data from RAM to the entire page 7 6 4 Load Configuration Registers To load the configuration registers send the LOAD CFG command followed by the two configuration bytes with the most significant byte first The following tables provide a summary of the bits There are three configuration registers CFGO CFG1 and CFG2 Thus there are six 8 bit bytes to be loaded during the set up of the device Publication Release Date June 2003 27 Revision 2 ISDS216 QWinbond Electronics Corp CFGO Bit no Signal Description DO LSB VLPD Power down the Volume Control D1 OPAO Power down Speaker driver and or Auxiliary output D2 Power down Speaker driver and or Auxiliary output D3 50 Select speaker output multiplexer D4 OPS1 Select speaker output multiplexer D5 CDIO Analog to digital converter input selector D6 CDI1 Analog to digital converter input selector D7 Compress
70. tart Sequence Publication Release Date June 2003 53 Revision B 2 PC INTERFACE TIMING ISDS216 STANDARD MODE FAST MODE PARAMETER SYMBOL MIN MAX MIN MAX UNIT SCL clock frequency fscu 0 100 0 400 kHz Hold time repeated START condition typ sta 4 0 0 6 ns After this period the first clock pulse is generated LOW period of the SCL clock 47 1 3 ns HIGH period of the SCL clock THIGH 4 0 0 6 ns Setup time for a repeated START 4 7 0 6 ns condition Data set up time tsu DAT 250 100 ns Rise time of both SDA and SCL signals 1000 20 0 10 300 ns Fall time of both SDA and SCL signals t 300 20 0 1 300 ns Set up time for STOP condition tsu sTo 4 0 0 6 ns Bus free time between a STOP and 4 7 1 3 ns START condition Capacitive load for each bus line 400 400 Noise margin at the LOW level for each VaL 0 1 Vpp 0 1 Vpp V connected device including hysteresis Noise margin at the HIGH level for each 0 2 0 2 V connected device including hysteresis 1 Fast mode device be used Standard mode l C interface system but the requirement gt 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW pe
71. the Master sending to the Slave immediately followed by the Slave sending data back to the Master The N not acknowledge cycle from the Master ends the transfer of data from the Slave Publication Release Date June 2003 I7 Revision B 2 ISDS216 Master Reads from Slave immediately after first byte Read Mode acknowledgement from slave Slave a4 From Slave a4 From Slave SLAVE ADDRESS STATUS WORD High ADDR BYTE Low ADDR BYTE x From Master Start Bit RW acknowledgement acknowledgement Stop Bit From From from Master from Master From Master Master Master not acknowledged from Master Another common operation in the ISD5216 is the reading of digital data from the chip s memory array at a specific address This requires the interface Master to first send an address to the ISD5216 Slave device and then receive data from the Slave in a single operation accomplish this the data direction R W bit must be changed in the middle of the command The following example shows the Master sending the Slave address then sending a Command Byte and 2 bytes of address data to the ISD5216 and then immediately changing the data direction and reading some number of bytes from the chip s digital array An unlimited number of bytes can be read in this operation The N not acknowledge cycle from the Master forces the end of the data transfer from the Slave The following example det
72. the l S and PCM interface ports 2 A 2 2V microphone bias supply for reduced noise coupling This supply can also be used to power down the external microphone with the system Analog functions and audio gating have also been integrated into the 1505216 product to allow for easy interfacing with integrated chip sets on the market Audio paths have been designed to enable full duplex conversation record voice memo and answering machine including outgoing message playback Logic Interface Options of 2 0V and 3 0V are supported by the 1505216 to accommodate both portable communication 2 0 and 3 0 volt required and automotive product customers 5 0 volt required Like other ChipCorder products the 1505216 integrates the sampling clock anti aliasing and smoothing filters and multi level storage array on a single chip For enhanced voice features the 1505216 eliminates external circuitry by integrating automatic gain control AGC a power amplifier speaker driver volume control summing amplifiers analog switches and a Voice CODEC Input level adjustable amplifiers are also included providing a flexible interface for multiple applications Recordings are stored in on chip nonvolatile memory cells providing zero power message storage This unique single chip solution is made possible through Winbond s patented multilevel storage technology Voice and audio signals are stored directly into solid state memory in their natural uncompressed
73. the state of the SUM2 SUMMING amplifier These are bits D5 and D6 respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER only path The configuration settings in the call record mode are 0 0100 0100 0000 1011 hex 4408 1 0000 0000 1100 0101 hex 00C5 2 0000 0000 0100 0000 hex 0040 48 ISDS216 a Winbond Electronics Corp 7 10 11 Memo Record The Memo Record mode sets the chip up to record from the local microphone into the chip s Multilevel Storage Array A connected cellular telephone or cordless phone chip set may remain powered down since they are not active in this mode The path to be used is microphone input to AGC amplifier then through to the INPUT SOURCE MUX to the SUM1 SUMMING amplifier From there the path goes through the FILTER MUX the LOW PASS FILTER the SUM2 SUMMING amplifier then to the MULTILEVEL STORAGE ARRAY In this example we will select the 5 3 kHz sample rate The rest of the chip may be powered down 1 Power up amplifier Bit AGPD controls the power up state of the amplifier This 1 bit DO of CFG1 and must be set to ZERO to power up this stage 2 Select the AGC amplifier through the INPUT SOURCE Bit INSO controls the state of the INPUT SOURCE MUX This is bit D9 of CFGO and must be set to a ZERO to select the AGC am plifier 3 Select the INPUT SOURCE MUX only
74. to the MIC and Publication Release Date June 2003 39 Revision B 2 ISDS216 MIC pins compared to the situation in which the external microphone is powered up through the power supply It also saves current during power down ACAP AGC Capacitor This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit It should have a 4 7 HF capacitor connected to ground It cannot be left floating This is because the capacitor is also used in the playback mode for the AutoMute circuit or when signal compression is chosen AMTO is set to ONE This circuit reduces the amount of noise present in the output during quiet pauses Tying this to ground gives maximum Tying it to Veca gives minimum gain for the AGC amplifier but cancels the AutoMute function Connect the capacitor to low noise ground as ground noise directly affects the microphone performance SP SP Speaker This is the speaker differential output circuit It is designed to drive an 80 speaker connected across the speaker pins up to a maximum of 23 5 mW RMS power This stage has two selectable gains 1 32 and 1 6 which can be chosen through the configuration registers These pins are biased to ap proximately 1 2 VDC and if used single ended must be capacitively coupled to their load Do NOT ground the unused pin AUX OUT Auxiliary Output The AUX OUT is an additional audio output pin to be used for example to dr
75. whether one desires recording one side simplex or both sides duplex of a conversation the various paths will also be switched through to the low pass filter for antialiasing and into the storage array Later the cell phone owner can play back the messages from the array When this happens the Array Output MUX is connected to the volume control through the Output MUX to the Speaker Amplifier For applications other than a cell phone the audio paths can be switched into many different and flexible configurations Some examples follow TRANSFORMER APPLICATION To Microcontroller interface and Address setting O 13 824 MHz 1 5kQ PCM OUT Mean PCM IN Vssp Vesa 8 KHz MiC 2 048 MHz Electret Microphone E WM 54B Panasonic MICBS TO AUXILIARY INPUT ACAP 1 5 68 ISDS216 Electronics Corp HANDSET APPLICATION To Microcontroller interface and Address setting O 1uF 13 824 MHz oO cc 1 5kQ PCM OUT 6 PCM IN AF 1505216 Vss a 8 kHz 9 SCK Electret Microphone WM 54B Panasonic AUX OUT TO RINGER AUX IN AUXILIARY INPUT VccA 1 5 SP RECEIVE Publication Release Date June 2003 69 Revision B 2 1505216 QWinbond Electronics Corp 12 PACKAGE SPECIFICATIONG 12 1 PLASTIC THIN SMALL OUTLINE PACKAGE TSOP TYPE E DIMENSIONS Post 3 4 5 6 7 8 9 1 1 1 1 1
76. xternal clock input This means taking into account the propagation delays between master clock and the data and or word select signals the total delay is simply the sum of the delay between the external master clock and the slave s internal clock and the delay between the internal clock and the data and or word select signals For data and word select inputs the external to internal clock delay is of no consequence because it only lengthens the effective set up time see figure Timing for 125 Transmitter on previous page The major part of the time margin is to accommodate the difference between the propagation delay of the transmitter and the time required to set up the receiver All timing requirements are specified relative to the clock period or to the minimum allowed clock period of a device This means that higher data rates can be used in the future Timing for 125 Receiver tar 0 2T ta 2 0 SD and minimum allowed clock period for transmitter T clock period T gt Note that the specifications are defined by the transmitter speed The specification of the receiver has to be able to match the performance of the transmitter Publication Release Date June 2003 21 Revision B 2 ISDS216 Winbond Electronics Corp 7 5 CONTROL REGISTERS The 1505216 15 controlled by loading commands to or reading commands from the internal command configuration and address registe

Winbond ISD5216 8 TO 16 MINUTES VOICE RECORD/PLAYBACK DEVICE WITH INTEGRATED CODEC

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