intersil HI5741 handbook
Contents
1. 90 90 85 85 80 80 2 75 8 75 8 5 70 70 65 65 four 10 fcLk four 1 5 fcu 60 10 20 30 40 50 60 70 8090100 60 10 20 30 40 50 60 70 8090100 MSPS MSPS FIGURE 10 SFDR vs CLOCK FREQUENCY FIGURE 11 SFDR vs CLOCK FREQUENCY 82 82 80 80 76 18 74 76 74 m 72 8 72 5 70 B 70 68 68 66 66 64 50 MSPS 64 L 75 MSPS 62 62 1 5 t MSPS 10 1 5 10 15 nid four MHz FIGURE 12 SFDR vs foyt FIGURE 13 SFDR vs foyt 80 72 fouT 2 08MHz 78 74 76 76 SRD HARMONIC 74 72 78 o 5 70 5 80 68 2ND HARMONIC 82 66 64 100 MSPS 4 62 86 1 5 10 15 20 10 20 30 40 50 60 70 8090100 four MHz MSPS FIGURE 14 SFDR vs fout FIGURE 15 HARMONIC DISTORTION vs CLOCK FREQUENCY 7 intersil HI5741 Typical Performance Curves continued2. 10dB 10dB ae qmm qmm M14 1 ao epe TE 1 20 MSPS MTPR 75 17dBc 100 MSPS E CUm eee TY ECT four 26 6MHz pe 7 me L SFDR 77 5dBc 5 o _ _ 1 _ bud AM Lie LT A E CTRL a CENTER 26 637MHz SPAN 2 000MHz FIGURE 16 TYPICAL MTPR PERFORMANCE FIGURE 17 SFDR WITHIN A WINDOW 57 sif A 300 240 30 96mV 124 1mV c SETTLING TIME ie 10ns a 1 gt HEHEHE EEE HEHEHE HEE HHH CH1 1 00mV 5 0ns CH1 16 9mV CH1 1 00mV 5 0ns CH1 109mV FIGURE 18 TYPICAL SETTLING TIME PERFORMANCE FIGURE 19 TYPICAL GLITCH ENERGY Pin Descriptions PIN NO PIN NAME PIN DESCRIPTION 1 14 D13 MSB thru DO Digital Data Bit 13 the Most Significant Bit through Digital Data Bit 0 the Least Significant Bit LSB 15 CLK Data Clock Pin 100kHz to 100 MSPS 16 DVcc Digital Logic Supply 5V 17 28 DGND Digital Ground 18 DVEE 5 2V Logic Supply 23 RSET External Resistor to set the full scale output current Ips 16 x VagrouT RsrrT Typically 9760 27 AGND Analog Groun
3. 150 C Maximum Storage Temperature Range 65 C to 150 C Maximum Lead Temperature Soldering 105 300 C SOIC Lead Tips Only CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 Oja is measured with the component mounted on a low effective thermal conductivity test board in free air See Tech Brief TB379 for details Electrical Specifications AVgg DVgg 4 94 to 5 46V Vcc 44 75 to 5 25V Vpef Internal TA 25 5741 TA 40 C TO 85 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SYSTEM PERFORMANCE Resolution 14 Bits Integral Linearity Error INL Best Fit Straight Line 25 C 5 1 0 1 5 LSB Notes 5 Best Fit Straight Line TA 40 C to 85 C 175 LSB Differential Linearity Error DNL Note 5 Ta 25 C 5 0 5 1 0 LSB Offset Error los Note 5 8 75 Full Scale Gain Error FSE Notes 3 5 3 2 10 Full Scale Gain Drift With Internal Reference 150 ppm FSR C Offset Drift Coefficient Note 4 0 05 Full Scale Output Current Irs 20 48 mA Output Voltage Compliance Range Note 4 1 25 0 V DYNAMIC
4. 6 D7 7 D6 8 21 lour D5 9 D4 10 D3 11 D2 12 D1 13 DO LSB 14 19 ARTN CLK 15 27 AGND DGND 17 28 DVge 18 0 1 uF J uF T n uF 5 2V DVgg 5 2V AVgg 26 REF OUT Functional Block Diagram LSB DO D1 D2 D3 D4 10 LSBs R2R D5 CURRENT NETWORK D6 BUFFER SLAVE LEVEL REGISTER MASTER D7 REGISTER D8 D9 D10 D11 SWITCHED 4 BIT CURRENT D12 DECODER CELLS MSB D13 REF CELL CLK CTRL AMP OVERDRIVEABLE e E o CTRL AMP VOLTAGE OUT REFERENCE AVge AGND DGND DVcc REF OUT Reset 2 intersil HI5741 Absolute Maximum ratings T4 25 Digital Supply Voltage Vcc to DGND 45 5V Negative Digital Supply Voltage DVgg to DGND 5 5V Negative Analog Supply Voltage AVgg to AGND ARTN 5 5V Digital Input Voltages D13 D0 CLK to DGND DVcc to 0 5V Internal Reference Output 2 5mA Voltage from CTRL AMP IN 2 5V to OV Control Amplifier Output 2 5mA Reference Input Voltage Range 3 7V to AVEE Analog Output Current 30mA Operating Conditions Temperature 40 C to 85 C Thermal Information Thermal Resistance Typical Note 1 C W SOIC Package 70 Maximum Junction Temperature
5. 50uV 9C of temperature drift typical The internal reference is connected to the Control Amplifier which in turn drives the segmented current cells Reference Out REF OUT is internally connected to the Control Amplifier The Control Amplifier Output CTRL OUT should be used to drive the Control Amplifier Input CTRL IN and a 0 1uF capacitor to analog This improves settling time by providing an AC ground at the current source base node The Full Scale Output Current is controlled by the REF OUT and the set resistor The ratio is lout Full Scale VREF oUT RseET 16 The internal reference REF OUT can be overdriven with a more precise external reference to provide better performance over temperature Figure 21 illustrates a typical external reference configuration HI5741 26 REF OUT 5 2V FIGURE 21 EXTERNAL REFERENCE CONFIGURATION 9 intersil HI5741 Multiplying Capability The HI5741 can operate in two different multiplying configurations For frequencies from DC to 100kHz a signal of up to 0 6Vp p can be applied directly to the REF OUT pin as shown in Figure 22 CTRL OUT CTRL IN 5741 REF OUT RSET Vin CIN OPTIONAL FIGURE 22 LOW FREQUENCY MULTIPLYING BANDWIDTH CIRCUIT The signal must have a DC value such that the peak negative voltage equals 1 25V Alternately a capacitor can be placed in series with REF OUT if a DC multiplying is not require
6. CHARACTERISTICS Throughput Rate Note 4 100 MSPS Output Voltage Settling Time 640 Note 4 Settling to 0 024 11 ns 4eth Scale Step Across Segment 640 Note 4 Settling to 0 012 5 20 3 ns Singlet Glitch Area GE Peak RL 640 Note 4 1 Output Slew Rate 640 DAC Operating in Latched Mode Note 4 1 000 V us Output Rise Time 640 DAC Operating in Latched Mode Note 4 675 ps Output Fall Time 640 DAC Operating in Latched Mode Note 4 470 ps Spurious Free Dynamic Range within a Window 10 MSPS four 1 23MHz 2MHz Span 87 s dBc Note 4 20 MSPS four 5 055MHz 2MHz Span 77 2 dBc 40 MSPS four 16MHz 10MHz Span 75 50 MSPS fouT 10 1 MHz 2MHz Span E 80 gt dBc 80 MSPS four 5 1 MHz 2MHz Span 78 dBc 100 MSPS four 10 1MHz 2MHz Span 79 dBc 3 intersil HI5741 Electrical Specifications AVgg DVgg 4 94 to 5 46V Voc 4 75 to 5 25V Vref Internal 25 Continued 5741 40 C TO 85 C PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Spurious Free Dynamic Range to Nyquist 10 MSPS fourt 1 023 2 5MHz Span 86 dBc Notes 4 10 MSPS four 2 02MHz 5MHz Span 85 dBc 25 MSPS
7. Performance Curves 670 660 650 640 mW 630 620 NOTE CLOCK FREQUENCY DOES 610 ALTER POWER DISSIPATION 00 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE C FIGURE 4 TYPICAL POWER DISSIPATION OVER TEMPERATURE 1 5 m LSB FIGURE 6 TYPICAL INL PERFORMANCE uA 0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE C FIGURE 8 TYPICAL OFFSET CURRENT OVER TEMPERATURE V 1 17 1 18 1 19 1 20 1 21 1 22 1 23 1 24 1 25 1 26 27 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE C FIGURE 5 TYPICAL REFERENCE VOLTAGE OVER TEMPERATURE 0 25 0 25 albi 0 81 i i i 0 5000 10 000 15 000 FIGURE 7 TYPICAL DNL PERFORMANCE 4 2 4 0 3 8 3 6 3 4 3 2 a 3 0 2 8 2 6 2 4 2 2 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE C FIGURE 9 TYPICAL GAIN ERROR OVER TEMPERATURE 6 intersil 5741 Typical Performance Curves continued
8. Rout is achieved due to the 2270 11596 parallel resistance seen looking back into the output This is the nominal value of the R2R ladder of the DAC The 500 output is needed for matching the output with a 500 line The load resistor should be chosen so that the effective output resistance RouT matches the line resistance The output voltage is lout x Rout lour is defined in the reference section 0 is not trimmed to 14 bits so it is not recommended that it be used in conjunction with differential to single ended application The compliance range of the output is from 1 25V to OV with a 1Vp p voltage swing allowed within this range TABLE 2 INPUT CODING vs CURRENT OUTPUT INPUT CODE D13 D0 lout mA lout mA 1111111111 1111 20 48 0 10 0000 0000 0000 10 24 10 24 00 0000 0000 0000 0 20 48 Settling Time The settling time of the HI5741 is measured as the time it takes for the output of the DAC to settle to within a defined error band of its final value during a 1 4gth code 0000 to 0001 0000 or 1111 to 1110 1111 scale transition In defining settling time specifications for the HI5741 two levels of accuracy are considered The accuracy levels defined for the HI5741 are 12 or 0 024 and 13 0 012 bits Glitch The output glitch of the HI5741 is measured by summing the area under the switching transients after an update of the DAC Glitch is c
9. internally translated from TTL to ECL The internal latch and switching current source controls are implemented in ECL technology to maintain high switching speeds and low noise characteristics Decoder Driver The architecture employs a split R 2R ladder and segmented current source arrangement Bits DO LSB through D9 directly drive a typical R 2R network to create the binary weighted current sources Bits D10 through D13 MSB pass through a thermometer decoder that converts the incoming data into 15 individual segmented current source enables This split architecture helps to improve glitch thus resulting in a more constant glitch characteristic across the entire output transfer function Clocks and Termination The internal 14 bit register is updated on the rising edge of the clock Since the HI5741 clock rate can run to 100 MSPS to minimize reflections and clock noise into the part proper termination should be used In PCB layout clock runs should be kept short and have a minimum of loads To guarantee consistent results from board to board controlled impedance PCBs should be used with a characteristic line impedance Zo 04500 To terminate the clock line shunt terminator to ground is the most effective type at a 100 MSPS clock rate A typical value for termination can be determined by the equation Zo for the termination resistor For a controlled impedance board with a Zo of 509 the RT 500 Shunt termination
10. 4 0 5 0 25 ns Propagation Delay Time tpp See Figure 1 Note 4 4 5 ns CLK Pulse Width tpw1 tpwe See Figure 1 Note 4 1 0 0 85 ns POWER SUPPLY CHARACTERISTICS IVEEA Note 5 42 50 mA IVEED Note 5 75 95 mA IVccp Note 5 13 20 mA Power Dissipation Note 5 650 mW Power Supply Rejection Ratio Voc 5 Vgg 5 5 uA V NOTES 2 Dissipation rating assumes device is mounted with all leads soldered to printed circuit board 3 Gain Error measured as the error in the ratio between the full scale output current and the current through Rsgr typically 1 28mA Ideally the ratio should be 16 All devices are 10096 tested at 259C the region of removed tones Parameter guaranteed by design or characterization and not production tested Dynamic Range must be limited to a 1V swing within the compliance range Intesting MTPR tone frequencies ranged from 1 95MHz to 3 05 2 The ratio is measured as the range from peak power to peak distortion in 4 intersil HI5741 Timing Diagrams eo Y dM D Z ERROR BAND VA w 5 H WIDTH W t tipp tseTT 4 w ps FIGURE 1 FULL SCALE SETTLING TIME DIAGRAM FIGURE 2 PEAK GLITCH AREA SINGLET MEASUREMENT METHOD FIGURE 3 PROPAGATION DELAY SETUP TIME HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 5 intersil 5741 Typical
11. 41BIBZ Note 40 85 28 Ld SOIC M28 3 Test Equipment Pb free High Resolution Imaging Systems HI5741BIBZ T 28 Ld SOIC Tape and Reel M28 3 Note Pb free Arbitrary Waveform Generators HI5741 EVS 25 Evaluation Board SOIC Pinout NOTE Intersil Pb free products employ special Pb free material HI5741 sets molding compounds die attach materials and 100 matte tin SOIC plate termination finish which is compatible with both SnPb and TOP VIEW Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J Std 020B D13 MSB 1 28 DGND D12 12 11 3 26 REF OUT D10 4 25 CTRL AMP OUT D9 5 24 CTRL AMP IN 6 23 D7 22 D6 8 21 lout 05 9 20 tour 10 119 ARTN D3 18 DVee D2 DGND D1 13 116 LSB 14 15 CLOCK 1 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 321 724 7143 Intersil and design is a registered trademark of Intersil Americas Inc Copyright Intersil Americas Inc 2000 2001 2003 2004 All Rights Reserved All other trademarks mentioned are the property of their respective owners 5741 Typical Application Circuit 5V 5741 DVcc 16 D13 MSB 1 D12 2 011 3 24 CTRL AMP IN 010 4 25 CTRL AMP OUT D9 5 D8
12. D HSP45106 16 BIT NCO 12 intersil HI5741 Small Outline Plastic Packages SOIC NOTES 1 10 M28 3 JEDEC MS 013 AE ISSUE 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE ppano OO H SEATING PLANE Symbols are defined in the MO Series Symbol List in Section 2 2 of Publication Number 95 Dimensioning and tolerancing per ANSI Y14 5M 1982 Dimension D does not include mold flash protrusions or gate burrs Mold flash protrusion and gate burrs shall not exceed 0 15mm 0 006 inch per side Dimension E does not include interlead flash or protrusions In terlead flash and protrusions shall not exceed 0 25mm 0 010 inch per side The chamfer on the body is optional If it is not present a visual index feature must be located within the crosshatched area L is the length of terminal for soldering to a substrate N is the number of terminal positions Terminal numbers are shown for reference only The lead width B as measured 0 36mm 0 014 inch or greater above the seating plane shall not exceed a maximum value of 0 61mm 0 024 inch Controlling dimension MILLIMETER Converted inch dimen sions are not necessarily exact All Intersil U S products are manufactured assembled and tested utilizing ISO9000 quality systems Intersil Corporation s quality cert
13. aused by the time skew between bits of the incoming digital data Typically the switching time of digital inputs are asymmetrical meaning that the turn off time is faster than the turn on time TTL designs Unequal delay 10 intersil HI5741 paths through the device can also cause one current source to change before another In order to minimize this the Intersil HI5741 employs an internal register just prior to the current sources which is updated on the clock edge Lastly the worst case glitch on traditional D A converters usually occurs at the major transition i e code 8191 to 8192 However due to the split architecture of the HI5741 the glitch is moved to the 1023 to 1024 transition and every subsequent 1024 code transitions thereafter This split R 2R segmented current source architecture which decreases the amount of current switching at any one time makes the glitch practically constant over the entire output range By making the glitch a constant size over the entire output range this effectively integrates this error out of the end application In measuring the output glitch of the HI5741 the output is terminated into 640 load The glitch is measured at any one of the current cell carry code 1023 to 1024 transition or any multiple thereof throughout the DACs output range The glitch energy is calculated by measuring the area under the voltage time curve Figure 25 shows the area considered as glitch whe
14. d The lower input bandwidth can be calculated using the following formula Cin IN For multiplying frequencies above 100kHz the CTRL IN pin can be driven directly as seen in Figure 23 5741 500 FIGURE 23 HIGH FREQUENCY MULTIPLYING BANDWIDTH CIRCUIT The nominal input output relationship is defined as Alout 800 In order to prevent the scale output current from exceeding 20 48mA the resistor must be adjusted according to the following equation 16V REF Rset V IN PEAK lour Full scale 800 The circuit in Figure 23 can be tuned to adjust the lower cutoff frequency by adjusting capacitor values Table 1 below illustrates the relationship TABLE 1 CAPACITOR SELECTION fin Cy Co 100kHz 0 01uF 1uF gt 1MHz 0 001 LF 0 1uF Also the input signal must be limited to 1Vp p to avoid distortion in the DAC output current caused by excessive modulation of the internal current sources Outputs The outputs and lout are complementary current outputs Current is steered to either or IOUT in proportion to the digital input code The sum of the two currents is always equal to the full scale current minus one LSB The current output can be converted to a voltage by using a load resistor Both current outputs should have the same load resistor 640 typically By using 64Q load on the output a 500 effective output resistance
15. d Supply current return pin 19 ARTN Analog Signal Return for the R 2R ladder 21 IOUT Current Output Pin 20 IOUT Complementary Current Output pin 22 AVEE 5 2V Analog Supply 24 CTRL AMP IN Input to the current source base rail Typically connected to CTRL AMP OUT and a 0 1uF capacitor to AVgg Allows external control of the current sources 25 CTRL OUT Control amplifier out Provides precision control of the current sources when connected to CTRL AMP IN such that IFs 16 x VREFOUT RseET 26 REF OUT 1 23V typical bandgap reference voltage output Can sink up to 500uA or be overdriven by an external reference capable of delivering up to 2mA 8 intersil HI5741 Detailed Description The HI5741 is a 14 bit current out D A converter The DAC can convert at 100 MSPS and runs on 5 and 5 2V supplies The architecture is an R 2R and segmented switching current cell arrangement to reduce glitch Laser trimming is employed to tune linearity to true 14 bit levels HI5741 achieves its low power and high speed performance from an advanced BiCMOS process The HI5741 consumes 650mW typical and has an improved hold time of only 0 25ns typical The HI5741 is an excellent converter for use in communications applications and high performance video systems Digital Inputs The HI5741 is a TTL CMOS compatible D A Data is latched by a Master register Once latched data inputs DO LSB through D13 MSB are
16. four 2 02MHz 12 5MHz Span 77 dBc fci 50 MSPS four 5 055MHz 25MHz Span 74 dBc fcLk 75 MSPS four 7 52MHz 37 5MHz Span 73 dBc 100 MSPS four 10 1 MHz 50MHz Span 71 dBc Multi Tone Power Ratio 8 Tones no Clipping 110kHz Spacing 220kHz 76 p dBc MTPR spacing between tones 4 and 5 20 MSPS Note 7 REFERENCE CONTROL AMPLIFIER Internal Reference Voltage VREF Notes 5 1 27 1 23 1 17 V Internal Reference Voltage Drift Note 4 50 uV PC Internal Reference Output Current Sink Source Note 4 500 50 Capability Internal Reference Load Regulation IREF 0 to IREF 500 5 100 uV Amplifier Input Impedance Note 4 3 E MO Amplifier Large Signal Bandwidth 4 0Vp p Sine Wave Input to Slew Rate Limited Note 1 gt MHz 4 Amplifier Small Signal Bandwidth 1 0Vp p Sine Wave Input to 3dB Loss Note 4 5 MHz Reference Input Impedance CTL IN Note 4 12 kQ Reference Input Multiplying Bandwidth CTL IN 500 100mV Sine Wave to 3dB Loss at IoyT 75 MHz Note 4 DIGITAL INPUTS 09 00 CLK INVERT Input Logic High Voltage Vu Note 5 2 0 V Input Logic Low Voltage Vi Note 5 0 8 V Input Logic Current Note 5 400 Input Logic Current Note 5 700 Digital Input Capacitance Note 4 3 0 pF TIMING CHARACTERISTICS Data Setup Time tsu See Figure 1 Note 4 3 2 0 ns Data Hold Time See Figure 1 Note
17. ifications can be viewed at www intersil com design quality INCHES MILLIMETERS MIN MAX MIN MAX NOTES 0 0926 0 1043 2 35 2 65 5 1 0 0040 0 0118 0 10 0 30 z B 0 013 0 0200 0 38 0 51 9 0 0091 0 0125 0 23 0 32 D 0 6969 0 7125 17 70 18 10 3 E 0 2914 0 2992 7 40 7 60 4 e 0 05 BSC 1 27 BSC H 0 394 0 419 10 00 10 65 2 h 0 01 0 029 0 25 0 75 5 L 0 016 0 050 0 40 1 27 6 N 28 28 7 a 0 8 0 8 Rev 0 12 93 Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com 13 intersil
18. is best used at the receiving end of the transmission line or as close to the HI5741 CLK pin as possible HI5741 DAC FIGURE 20 HI5741 CLOCK LINE TERMINATION Rise and Fall times and propagation delay of the line will be affected by the shunt terminator The terminator should be connected to DGND Noise Reduction To reduce power supply noise separate analog and digital power supplies should be used with and 0 01 uF ceramic capacitors placed as close to the body of the HI5741 as possible on the analog AV gg and digital DVgg supplies The analog and digital ground returns should be connected together back at the device to ensure proper operation on power up The Vcc power pin should also be decoupled with a 0 1uF capacitor Reduction of digital noise caused by high slew rates on the bit inputs to the HI5741 can be accomplished through the use of series termination resistors The use of serial resistors which combine with the input capacitance of the HI5741 to induce a low pass filter characteristic keeps the noise generated by high slew rate digital signals from corrupting the high accuracy analog data Refer to Application Note AN9619 Optimizing setup conditions for high accuracy measurements of the HI5741 for further details on selecting the proper value of series termination to meet application specific needs Reference The internal reference of the HI5741 is a 1 23V typical bandgap voltage reference with
19. n changing the DAC output Units are typically specified in picoVolt seconds pV s 5741 100 2 LOW PASS 21 lout FILTER 500 FIGURE 24 GLITCH TEST CIRCUIT i GLITCH ENERGY a x t 2 FIGURE 25 MEASURING GLITCH ENERGY Applications Bipolar Applications To convert the output of the HI5741 to a bipolar 4V swing the following applications circuit is recommended The reference can only provide 125 of drive so it must be buffered to create the bipolar offset current needed to generate the 2V output with all bits off The output current must be converted to a voltage and then gained up and offset to produce the proper swing Care must be taken to compensate for the voltage swing and error 1 2904 HI5741 louT 21 HFA1100 FIGURE 26 BIPOLAR OUTPUT CONFIGURATION Interfacing to the HSP45106 NCO 16 The HSP45106 is a 16 bit Numerically Controlled Oscillator NCO The HSP45106 can be used to generate various modulation schemes for Direct Digital Synthesis DDS applications Figure 27 shows how to interface an HI5741 to the HSP45106 Definition of Specifications Integral Linearity Error INL is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve Differential Linearity Error DNL is the measure of the error in step size between adjacent codes along the converter s transfer c
20. tal to the RMS sum of the harmonics The through 4 and 5 through 8 are spaced equally with tones 4 first 5 harmonics are included and an output filter of 15 the and 5 spaced at 2Af MTPR is measured as the dynamic clock frequency is used to eliminate alias products range from peak power to peak distortion in the 2Af gap Spurious Free Dynamic Range SFDR is the amplitude Intermodulation Distortion IMD is the measure of the difference from a fundamental to the largest harmonically or sum and difference products produced when a two tone non harmonically related spur A sine wave is loaded into the input is driven into the D A The distortion products created D A and the output filtered at 15 the clock frequency to will arise at sum and difference frequencies of the two tones eliminate noise from clocking alias terms IMD can be calculated using the following equation Multi Tone Power Ratio MTPR is the amplitude difference 20Log RMS of Sum and Difference Distortion Products from peak amplitude to peak distortion either harmonic or K ndamental non harmonic An 8 tone pattern is loaded into the D A The 33 MSPS en TO RF BASEBAND MOD2 BIT ENCODER Bi MOD1 FILTER UP CONVERT STREAM STAGE R4 louT 64 R 2 V 64 gt 92 AMP OUT 6 52 C4 0 01uF CONTROLLER R3 RSET 976 ARET AVss AVEE 2 5 2V A V HSP45106 FIGURE 27 PSK MODULATOR USING THE HI5741 AN
21. urve Ideally the step size is 1 LSB from one code to the next and the deviation from 1 LSB is known as DNL A DNL specification of greater than 1 LSB guarantees monotonicity Feedthru is the measure of the undesirable switching noise coupled to the output Output Voltage Full Scale Settling Time is the time required from the 50 point on the clock input for a full scale step to settle within an l LSB error band Output Voltage Small Scale Settling Time is the time required from the 50 point on the clock input for a 100mV step to settle within an 1 LSB error band This is used by applications reconstructing highly correlated signals such as sine waves with more than 5 points per cycle Glitch Area GE is the switching transient appearing on the output during a code transition It is measured as the area under the curve and expressed as a volt time specification typically pV s Differential Gain Ay is the gain error from an ideal sine wave with a normalized amplitude Differential Phase is the phase error from an ideal sine wave Signal to Noise Ratio SNR is the ratio of a fundamental to the noise floor of the analog output The first 5 harmonics are ignored and an output filter of Ts the clock frequency is used to eliminate alias products 11 intersil HI5741 Total Harmonic Distortion THD is the ratio of the DAC tone spacing of this pattern Af is created such that tones 1 output fundamen
22. zr 184115 31BI B T HMA e Data Sheet 14 Bit 100 5 5 High Speed D A Converter The HI5741 is a 14 bit 100MSPS D A converter which is implemented in the Intersil BICMOS 10V HBC 10 process Operating from 5V and 5 2V the converter provides 20 48mA of full scale output current and includes an input data register and bandgap voltage reference Low glitch energy and excellent frequency domain performance are achieved using a segmented architecture The digital inputs are TTL CMOS compatible and translated internally to ECL All internal logic is implemented in ECL to achieve high switching speed with low noise The addition of laser trimming assures 14 bit linearity is maintained along the entire transfer curve 5741 4071 11 July 2004 Features e Throughput Rate 100MSPS LOW IPOWGN tee eet nolo 650mW Integral Linearity 1LSB e Low Glitch Energy 1pV s TTL CMOS Compatible Inputs Improved Hold 0 25ns Excellent Spurious Free Dynamic Range Pb free Available Applications Cellular Base Stations Ordering Information Wireless Communications TEMP PKG u PART NUMBER RANGE PACKAGE DWG Direct Digital Frequency Synthesis HI5741BIB 40 85 28 Ld SOIC M28 3 Signal Reconstruction HI57
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