PHILIPS HEF4085B gates Dual 2-wide 2-input AND-OR-invert gate handbook
Contents
1. INTEGRATED CIRCUITS DATA SHEET For a complete data sheet please also download e The IC04 LOCMOS HE4000B Logic Family Specifications HEF HEC e The IC04 LOCMOS HE4000B Logic Package Outlines Information HEF HEC HEF4085B gates Dual 2 wide 2 input AND OR invert gate Product specification January 1995 File under Integrated Circuits IC04 Philips PHILIP sS Semiconductors DH LI p Philips Semiconductors Product specification HEF4085B gates Dual 2 wide 2 input AND OR invert gate DESCRIPTION The HEF4085B is a dual 2 wide 2 input AND OR invert gate each with an additional input A or B4 which can be used as either an expander input or an inhibit input A HIGH on Ag or Bg forces the output O4 or Og LOW Voo A3 Az Bg Ay B3 Bo independent of the other inputs Ag to Ag or Bo to B3 The HEF4085B outputs Oa and Og are fully buffered for highest noise immunity and pattern insensitivity of output impedance 7274258 Fig 2 Pinning diagram HEF4085BP N 14 lead DIL plastic SOT27 1 HEF4085BD F 14 lead DIL ceramic cerdip SOT73 HEF4085BT D 14 lead SO plastic SOT108 1 Package Designator North America 7Z74257 1 Fig 1 Functional diagram LOGIC FUNCTION Ag On Ag Ay Ag Ag Ay Ay Op B B B B B Ay o Oa A3 FAMILY DATA Ipp LIMITS category GATES A4 7275425 1 See Family Specifications Fig 3 Logic diagram one gate Januar2. y 1995 2 Philips Semiconductors Dual 2 wide 2 input AND OR invert gate AC CHARACTERISTICS Vss 0 V Tamb 25 C C 50 pF input transition times lt 20 ns Product specification HEF4085B gates V TYPICAL EXTRAPOLATION lt SYMBOL TYP MAX PORMULA Propagation delays An Bn gt On 5 75 155 ns 48ns 0 55 ns pF CL HIGH to LOW 10 tPHL 30 60 ns 19ns 0 23 ns pF CL 15 20 40 ns 12ns 0 16 ns pF CL 5 65 135 ns 38 ns 0 55 ns pF CL LOW to HIGH 10 tPLH 30 55 ns 19ns 0 23 ns pF CL 15 20 40 ns 12ns 0 16 ns pF CL Output transition times 5 60 120 ns 10ns 1 0 ns pF Ci HIGH to LOW 10 tTHL 30 60 ns 9ns 0 42 ns pF CL 15 20 40 ns 6ns 0 28 ns pF CL 5 60 120 ns 10ns 1 0 ns pF Ci LOW to HIGH 10 tTLH 30 60 ns 9ns 0 42 ns pF CL 15 20 40 ns 6ns 0 28 ns pF CL bii TYPICAL FORMULA FOR P uW Dynamic power 5 750 fi foC x Vpp where dissipation per 10 3200 fi foCL x Vpop fi input freq MHz package P 15 9200 fi foC1 x Vpp fo output freq MHz C load capacitance pF foCL sum of outputs Vpp supply voltage V January 1995
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