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ANALOG DEVICES ADM1170 handbook

1. This reduces current surges at insertion After the initial timing cycle the GATE is then pulled high During an overcurrent condition the ADM1170 servos the GATE pin in an attempt to maintain a constant current to the load until the circuit breaker timeout completes In the event of a timeout the GATE pin abruptly shuts down using the 4 mA pull down device Care must be taken not to load the GATE pin resistively because this reduces the gate drive capability CURRENT LIMIT FUNCTION The ADMIT2O features a fastjresponse current control loop that aetively Itmitsthe c rrent by reducing the gate voltage of the external FET This current is measured by monitoring the voltage drop across an external sense resistor The ADM1170 tries to regulate the gate of the FET to achieve a 50 mV voltage drop across the sense resistor CALCULATING THE CURRENT LIMIT The sense resistor connected between SENSE and the SENSE pin is used to determine the nominal fault current limit This is given by the following equation ILIMITyom VCBnom RSENSEnom 1 The minimum load current is given by Equation 2 ILIMITum VCBum RSENSEvAx 2 The maximum load current is given by Equation 3 ILIMITmax VCBmax RSENSEmin 3 For proper operation the minimum current limit must exceed the circuit maximum operating load current with margin The sense resistor power rating must exceed VCBmax RSENSEmw CIRCUIT BREAKER FUNCTION When the supply experience
2. 0 2 0 25 V TIMER falling SS PIN Soft Start Pull Up Current 10 pA Current Setting Gain 20 V V Vss VseNse Soft Start Completion Voltage 1 V Pull Down Current 50 yA During fault torr Turn Off Time TIMER Rise to GATE Fall 2 us Vimer 0 V to 2 V step Vcc Von 5 V Turn Off Time ON Fall to GATE Fall 40 us Von 5 V to OV step Vc 5V Turn Off Time Vcc Fall to IC Reset 40 us Vcc 5 V to 2 V step Von 5 V Rev 0 Page 3 of 16 ADM1170 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating Vcc Pin 0 3V to 20V SENSE Pin SENSE Pin 0 3V to 20 V SENSE Pin SENSE Pin 5V TIMER Pin 0 3 V to Vcc 0 3 V ON ON CLR Pin 0 3V to 20 V SS Pin 0 3 V to Vcc 0 3 V GATE Pin 0 3 V to Vcc 11 V Storage Temperature Range 65 C to 125 C Operating Temperature Range 40 C to 85 C Lead Temperature 10 sec 300 C Junction Temperature 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL CHARACTERISTICS Oya is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 3 Thermal Resis
3. 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V Figure 4 Supply Current vs Supply Voltage GATE off SUPPLY VOLTAGE V Figure 5 Supply Current vs Supply Voltage GATE on 1 0 0 9 07 Vcc 12V Voc 15V Vcc 5V Vec 3V 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 6 Supply Current vs Temperature 05124 023 05124 024 05124 033 Rev 0 Page6 of 16 UVLO THRESHOLD V GATE VOLTAGE V GATE VOLTAGE V TEMPERATURE C Figure 7 UVLO Threshold vs Temperature 25 20 15 10 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V Figure 8 GATE Voltage vs Supply Voltage 25 Vcc 15V 20 Vcc 12V 15 Vec 5V 10 Voc 3V 5 0 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 9 GATE Voltage vs Temperature 05124 046 05124 013 05124 015 DELTA GATE VOLTAGE V DELTA GATE VOLTAGE V Itimerup HA 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V Figure 10 Delta GATE Voltage vs Supply Voltage 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 11 Delta GATE Voltage vs Temperature 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V Figure 12 Irmerue in Initial Cycle vs Supp
4. reference Input Pin The ON ON CLR pin is an input to a comparator that has a low to high threshold of 1 3 V with 80 mV hysteresis and a glitch filter The ADM1170 is reset when the ON ON CLR pin is low When the ON ON CLR pin is high the ADM1170 is enabled A rising edge on this pin has the added function of clearing a fault and restarting the device on the latched off model the ADM1170 2 Gate Output Pin An internal charge pump provides a 12 pA pull up current to drive the gate of an N channel MOSFET In an overcurrent condition the ADM1170 controls the external FET to maintain a constant load current amp urrent Limit Sense Input Pins The current limitis setwviavaysemse resistor between the SENSE and SENSE pins Inan overcurrent condition the gate of the FET is controlled t maintain the SENSE voltage at 50 mV When this limit is reached the TIMER circuit breaker mode is activated The circuit breaker limit can be disabled by connecting the SENSE and SENSE pins together Positive Supply Input Pin The ADM1170 operates between 2 7 V to 16 5 V An undervoltage lockout UVLO circuit with a glitch filter resets the ADM1170 when the supply voltage drops below the specified UVLO limit Rev 0 Page 5 of 16 ADM1170 TYPICAL PERFORMANCE CHARACTERISTICS SUPPLY CURRENT mA SUPPLY CURRENT mA SUPPLY CURRENT mA 0 50 0 45 0 40 0 35 0 30 0 25 0 20 0 15 0 10 0 0
5. 021 ADM1170 o Figu 8 GATE CURRENT mA 2 e o N A o eo o N 05124 008 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V re 28 GATE Current Down vs Supply Voltage GATE CURRENT pA i ih B 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V Figure 29 GATE Current up vs Supply Voltage pA GATE CURRENT 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 30 GATE Current up vs Temperature 05124 009 05124 017 10 4 10 5 10 6 10 7 10 8 SOFT START CURRENT pA 10 9 Voc 3V i Voc 5V e S Voc 12V LM Voc 15V 50 25 0 25 50 75 100 125 CCT BREAKER VOLTAGE mV Rev 0 Page 10 of 16 TEMPERATURE C Figure 31 Soft Start Current vs Temperature SOFT START VOLTAGE V Figure 32 Circuit Breaker Voltage vs Soft Start Voltage 05124 018 05124 020 ADM1170 THEORY OF OPERATION Many systems require the insertion or removal of circuit boards to live backplanes During this event the supply bypass and hold up capacitors can require substantial transient currents from the backplane power supply as they charge These currents can cause permanent damage to connector pins or undesirable glitches and resets to the system The ADM1170 is intended to control the powering of a system on and off in
6. 19 TIMER High Threshold vs Temperature TA 25 c 1 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V Figure 20 TIMER Low Threshold vs Supply Voltage 05124 043 05124 045 TEMPERATURE C Figure 21 TIMER Low Threshold vs Temperature ON ON CLR PIN THRESHOLD V ON ON CLR PIN THRESHOLD V torr oNLow HS 1 45 1 40 1 35 HIGH THRES 1 30 THRES 1 25 1 20 SUPPLY VOLTAGE V Figure 22 ON ON CLR Pin Threshold vs Supply Voltage 1 45 1 40 1 35 THRESHOLD 1 30 1 25 THRESHOLD 1 20 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 23 ON ON CLR Pin Threshold vs Temperature SUPPLY VOLTAGE V Figure 24 torr ontow vs Supply Voltage 05124 040 05124 041 05124 047 Rev 0 Page 9 of 16 torr oLow HS Vcg mV Vcg mV ADM1170 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 25 torriontow vs Temperature 50 47 5 E 42 41 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V Figure 26 Cct Breaker Voltage vs Supply Voltage 50 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 27 Cct Breaker Voltage vs Temperature 05124 048 05124 049 05124
7. 4700 www analog com Fax 781 461 3113 2006 Analog Devices Inc All rights reserved ADM1170 TABLE OF CONTENTS Features 1 UVEO m TM G 11 S EISE ION NN 1 ONTONECEISEPHI uU NOn 11 General Descriptio nsss a E eene 1 GAT Efe cscs cron tation toad ME ce oecet saat 11 Functional Block Diagram eerte 1 Current Limit Function eeseseeeseeeeeete tette 11 REVISION ISL ORY s eoe IN SEN E 2 Calculating the Current Limit ee 11 Specifications ee p ta er OR E 3 Circuit Breaker Function sesenta 11 Absolute Maximum Ratings sese 4 Timer Function ee ep pt a a ais 12 Thermal Characteristics eerte 4 Power Up Timing Cycle eene 12 BSD Caution RR REED ES e 4 Circuit Breaker Timing Cycdle eee 12 Pin Configurations and Function Descriptions 5 Automatic Retry or Latched Off sss 13 Typical Performance Characteristics sss 6 SOft Startrsive code ed aede ned e noU RED PERUANO 13 Theory of Operation sessseeeseeeeentennnt tenentes 11 O tline Dimensions nissin ite IR RR inta 14 deua ERN 11 Ordering Guides eue eH RERO HER 14 REVISION HISTORY 7 06 Revision 0 Initial Version rj Rev 0 Page 2 of 16 SPECIFICATIONS ADM1170 Vcc 2 7 V to 16 5 V Ta 40 C to 85 C typical values at Ta 25 C unless otherwis
8. ANALOG DEVICES 1 6 V to 16 5 V Hot Swap Controller with Soft Start FEATURES Controls supply rails from 1 6 V to 16 5 V Supply voltage range from 2 7 V to 16 5 V Allows protected board removal and insertion to a live backplane External sense resistor provides adjustable analog current limit with circuit breaker Soft start controls inrush current profile Peak fault current limited with fast response Charge pumped gate drive for external N FET switch Automatic retry or latch off during current fault Undervoltage lockout 8 lead TSOT package APPLICATIONS Hot swap board insertion line cards raid systems Industrial high side switches circuit breakers Electronic circuit breakers ADM1170 GENERAL DESCRIPTION The ADM1170 is a hot swap controller that safely enables a printed circuit board to be removed and inserted to a live backplane This is achieved using an external N channel power MOSFET with a current control loop that monitors the load current through a sense resistor An internal charge pump is used to enhance the gate of the N channel FET When an overcurrent condition is detected the gate voltage of the FET is reduced to limit the current flowing through the sense resistor The ADM1170 operates with a supply voltage ranging from 2 7 V to 16 5 V By using independent SENSE pins from Vcc the ADM1170 allows for the hot swap of supplies ranging down to 1 6 V During an overcurrent condition the TIMER pin capacito
9. EPTION OF PACKAGE HEIGHT AND THICKNESS Figure 37 8 Lead Thin Small Outline Transistor Package TSOT UJ 8 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ADM1170 1AUJZ RL7 40 C to 85 C 8 Lead TSOT UJ 8 M1H ADM1170 2AUJZ RL7 40 C to 85 C 8sLead SOT UJ 8 M1J Z Pb free part UM Rev 0 Page 14 of 16 M ADM1170 NOTES waw BDTI C com AD ADM1170 NOTES 2006 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D05124 0 7 06 0 DEVICES www analog com Rev 0 Page 16 of 16
10. R LATCHED OFF reaches 1 V the current limit reaches the normal operating j i condition of Vsense 50 mV The voltage on the SS pin The ADM1170 is available in two models The ADM1170 1 continues to rise past the 1 V level with no effect on the current has an automatic retry system whereby when a current fault is i f limit The reference voltage for the GATE linear control detected the FET is shut down after a time determined by the amplifier is derived from the soft start voltage such that the timer capacitor and it is switched on again in a controlled con inrush linear current limit is defined as tinuous cycle to determine if the fault remains see Figure 35 for details The period of this cycle is determined by the timer Iuurr Vssl 20 x Rsense capacitor at a duty cycle of 3 8 on and 96 2 off This provides a limit of 50 mV across Rsense when Vss is at 1 V Therefore the value for the SS capacitor is chosen as follows Css Iss X t where Iss 10 uA and t is the time required for the current limit to ramp up Rev 0 Page 13 of 16 ADM1170 OUTLINE DIMENSIONS SER 2 80 BSC E 8 7 6 5 1 60 BSC l1 2 PIN 1 INDICATOR ay 0 65 BSC k 1 95 0 90 BSC oes 1 00MAX 0 20 Y HH 0 08 0 60 oaomaxt 0 38 gt gt e 0 45 0 22 SEATING i 0 30 PLANE 0 COMPLIANT TO JEDEC STANDARDS MO 193 BA WITH THE EXC
11. a controlled manner allowing the board to be removed from or inserted into a live backplane by protecting it from excess currents The ADM1170 can reside either on the backplane or on the removable board OVERVIEW The ADM1170 operates over a supply range of 2 7 V to 16 5 V As the supply voltage is coming up an undervoltage lockout circuit checks if sufficient supply voltage is present for proper operation During this period the FET is held off by the GATE pin being held to GND When the supply voltage reaches a level above UVLO and the ON ON CLR pin is high an initial timing cycle ensures that the board is fully inserted in the backplane before turning on the FET The TIMER pin capacitor sets the periods for all of the TIMER pin functions After the initial timing cycle the ADM1170 monitors the inrush eurrent through an external sense TAM Oyercurrent c uditioris ate actively limited to 50 mV RStsEfor the cifcuit br akef timer limit The ADM1170 1 automatically retries after a current limit fault and the ADM1170 2 latches off The retry duty cycle on the ADM1170 1 timer function is limited to 3 8 for FET cooling UVLO If the Vcc supply is too low for normal operation an under voltage lockout circuit holds the ADM1170 in reset The GATE pin is held to GND during this period When the supply reaches this UVLO voltage the ADM1170 starts when the ON ON CLR pin condition is satisfied ON ON CLR PIN The ON ON CLR pin is
12. and the TIMER pin is pulled high with 5 uA At Time Point 3 the TIMER reaches the COMP2 threshold When the voltage across the sense resistor exceeds the circuit breaker trip voltage the 60 uA timer pull up current is activated If the sense voltage falls below this level before the TIMER pin This is the end of the first section of the initial cycle The 100 uA reaches 1 3 V the 60 uA pull up is disabled and the 2 uA pull current source then pulls down the TIMER pin until it reaches down is enabled This is likely to happen if the overcurrent fault 0 2 V at Time Point 4 The initial cycle delay Time Point 2 to is only transient such as an inrush current This is shown in Time Point 4 relates to Crimer by equation Figure 34 However if the overcurrent condition is continuous bare 135 Cial quA 4 and the sense voltage remains above the circuit breaker trip voltage the 60 uA pull up remains active This allows the TIMER pin to reach the high trip point of 1 3 V and initiate the GATE shutdown On the ADM1170 2 the TIMER pin continues pulling up but switches to the 5 uA pull up when it reaches the 1 3 V Rev 0 Page 12 of 16 ADM1170 threshold The device can be reset by toggling the ON CLR pin The ADM1170 2 model has a latch off system whereby when a or by manually pulling the TIMER pin low On the ADM1170 1 current fault is detected the GATE is switched off after a time the TIMER pin activates the 2 uA pull down once the 1 3 V determine
13. d by the timer capacitor see Figure 36 for details threshold is reached and continues to pull down until it reaches Toggling the ON CLR pin or pulling the TIMER pin to GND the 0 2 V threshold At this point the 100 uA pull down is activated and the GATE pin is enabled The device keeps retrying in the manner as shown in Figure 35 for a brief period resets this condition The duty cycle of this automatic retry cycle is set to the ratio of 2 uA 60 uA which approximates 3 8 on The value of the timer capacitor determines the on time of this cycle This time is calculated as follows ton 1 3 x Crmer 60 pA torr 1 1 x Crmer 2 yA IRSENSE 05124 005 V TMER Figure 36 ADM1170 2 Latch Off After Overcurrent Fault Vasrer L 4 A SOFT START I The inrush current profile is controlled using an external l l l I l l l l I I l l l l I l l l SHORT l i rr CIRCUIT capacitor on the soft starf S j pin During power on reset the vour NAN i i SS pin is heldjat GND When p pass FET begins to conduct c rfentza pullwup currentSource is initiated on the SS pin and a charges the voltage on the soft start capacitor in a linear fashion The current limit of the device is porportional to the voltage on the SS pin until it reaches 1 V When the voltage on the SS pin 004 FAULT l FAULT CYCLE CYCLE 05124 Figure 35 ADM1170 1 Automatic Retry During Overcurrent Fault AUTOMATIC RETRY O
14. e noted Table 1 Parameter Symbol Min Typ Max Unit Conditions Vcc PIN Operating Voltage Range Vcc 2 7 16 5 V Supply Current lec 0 65 0 8 mA Undervoltage Lockout Vuvio 2 4 2 525 2 65 V Vcc rising Undervoltage Lockout Hysteresis Vuvionys 40 mV ON ON CLR PIN Input Current linon 1 0 1 yA Threshold Von 122 1 3 1 38 V ON rising Threshold Hysteresis Vonuyst 50 mV SENSE PINS SENSE SENSE Hot Swap Operating Range 1 6 16 5 V Input Current IiNsENsE 160 65 13 yA Vsense 1 6 V Input Current IiNsENsE 5 10 15 uA Vsense 2 2 2 V Circuit Breaker Limit Voltage Vc 26 50 77 mV Vcs Vsense Vsense Vsense 1 6 V Circuit Breaker Limit Voltage Vc 44 50 56 mV Vcs Vsense Vsense Vsense 2 2 V GATE PIN Drive Voltage Vaate 4 6 7 5 10 V Vaate Vcc Vcc 3 0 V 6 0 8 12 V Veate Vcc Vcc 3 3 V 8 75 10 12 V Vaart Vcc Vcc 5 V 7 5 9 12 V MontP VEc Vcc 12V i 5 56 8 12 V f Veate Vec Vec 15 V Pull Up Current 16 5 42 145 BA Verre OV Pull Down Current 4 mA Vaate 3 V Vcc 5 V ON ON CLR low Pull Down Current 25 mA Vaate 3 V Vcc lt UVLO TIMER PIN Pull Up Current IrimeruP 2 5 8 5 uA Initial cycle Vrimer 1 V 25 60 100 uA During current fault Vrmer 1 V Pull Down Current ITIMERDN 2 3 5 yA After Cct breaker tip Vrimer 1 V 100 pA Normal operation Vrimer 1 V Threshold High VTIMERH 1 22 13 1 38 V TIMER rising Threshold Low VTIMERL 0 15
15. ly Voltage 05124 014 05124 016 05124 035 Rev 0 Page 7 of 16 himerup HA Itimerup HA ItimeRup HA ADM1170 Voc 5V 3 4 Ems 50 25 0 25 50 75 100 125 1 TEMPERATURE C a 0 Figure 13 Inmerue in Initial Cycle vs Temperature 20 Ta 25 C 30 40 50 60 70 80 90 100 2 4 6 8 10 12 14 16 0 18 SUPPLY VOLTAGE V Figure 14 Immerup During Cct Breaker Delay vs Supply Voltage TEMPERATURE C Figure 15 Imerue During Cct Breaker Delay vs Temperature 05124 038 05124 036 05124 039 ADM1170 ItimeRDN HA ItimeRDN HA TIMER HIGH THRESHOLD V 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE V Figure 16 Irmeron in Cool Off Cycle vs Supply Voltage TEMPERATURE C Figure 17 ITmeron in Cool Off Cycle vs Temperature SUPPLY VOLTAGE V Figure 18 TIMER High Threshold vs Supply Voltage 05124 034 05124 037 05124 042 Rev 0 Page 8 of 16 TIMER LOW THRESHOLD V TIMER HIGH THRESHOLD V TIMER LOW THRESHOLD V 1 38 1 36 1 34 1 32 1 30 1 28 0 24 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 24 0 23 0 22 0 21 0 20 0 19 TEMPERATURE C 3 Figure
16. r determines the amount of time the FET remains at a current limiting mode of operation until it is shut down The ON ON CLR pin is the enable input for the device and can be used to monitor the input supply voltage The ADM1170 also features soft start to provide the user with a capacitor program mable ramping reference to the internal current sense comparator This provides alinearly increasing current limit at startup at a rate set by Css This helps to Y and limit large inrush currents This device is available in two options the ADM1170 1 with automatic retry for overcurrent fault and the ADM1170 2 with latch off for an overcurrent fault Toggling the ON ON CLR pin resets a latched fault The ADM1170 is packaged in an 8 lead TSOT FUNCTIONAL BLOCK DIAGRAM Vin 1 8V LONG Vin 3 3VAUX Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners RsENsE Qi SENSE SENSE GATE ADM1170 1 05124 001 Figure 1 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329
17. s a sudden current surge such as a low impedance fault on load the bus supply voltage can drop significantly to a point where the power to an adjacent card is affected potentially causing system malfunctions The ADM1170 limits the current drawn by the fault by reducing the Rev 0 Page 11 of 16 ADM1170 gate voltage of the external FET This minimizes the bus supply When the initial cycle ends a start up cycle activates and the voltage drop caused by the fault and protects neighboring cards GATE pin is pulled high the TIMER pin continues to pull down As the voltage across the sense resistor approaches the current limit a timer activates This timer resets again if the sense Vin voltage returns below this level If the sense voltage is any 1 voltage below 44 mV the timer is guaranteed to be off Should T Eg r the current continue to increase the ADM1170 tries to regulate the gate of the FET to achieve a limit of 50 mV across the sense Ii o dg Ig og EE Io l l I I I i piae i l Vaid l l I resistor However if the device is unable to regulate the fault Vrimer Na i I I current and the sense voltage further increases a larger pull P EV l l l 1 fi L1 d Lg I iif I Ie np d i l than 56 mV this pull down is guaranteed to be on When the l l l l I l down in the order of milliamperes is enabled to compensate for fast current surges If the sense
18. tance ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection Although this product features Package Type Osa Unit 8 Lead TSOT 152 9 C W WARNING CS proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Sprit 4 electrostatic discharges Therefore proper ESD pregautions are recommended to avoid performance degradation or loss of functionality i i ESD SENSITIVE DEVICE Rev 0 Page 4 of 16 ADM1170 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADM1170 1AUJ ADM1170 2AUJ TIMER 8 Voc GND 2 rop view SENSE ss 3 Not to Scale 6 SENSE ON CLR 4 s GATE 05124 006 05124 007 Figure 2 Pin Configuration 1AUJ Model Figure 3 Pin Configuration 2AUJ Model Table 4 Pin Function Descriptions Pin No Mnemonic Description 1 6 7 TIMER GND SS ON ON CLR GATE SENSE SENSE Vcc Timer Input Pin The initial and circuit breaker timing cycles are set by this external capacitor The initial timing delay is 272 9 ms pF and 21 7 ms uF for a circuit breaker delay When the TIMER pin is pulled beyond the upper threshold the GATE turns off Chip Ground Pin Soft Start Pin An external capacitor between the SS pin and GND sets the ramp rate of the current limit
19. the enable pin It is connected to a comparator that has a low to high threshold of 1 3 V with 80 mV hysteresis and a glitch filter The ADM1170 is reset when the ON ON CLR pin is low When the ON ON CLR pin is high the ADM1170 is enabled A rising edge on this pin has the added function of clearing a fault and restarting the device on the latched off model the ADM1170 2 A low input on the ON ON CLR pin turns off the external FET by pulling the GATE pin to ground and resets the timer An external resistor divider at the ON ON CLR pin can be used to program an undervoltage lockout value higher than the internal UVLO circuit There is a glitch filter delay of approximately 3 us on rising allowing the addition of an RC filter at the ON ON CLR pin to increase the delay time at card insertion If using a short pin system to enable the device a pull down resistor should be used to hold the device prior to insertion GATE Gate drive for the external N channel MOSFET is achieved using an internal charge pump The gate driver consists of a 12 uA pull up from the internal charge pump There are various pull down devices on this pin At a hotswap condition the board is hot inserted to the supply bus During this event it is possible for the external FET GATE capacitance to be charged up by the sudden presence of the supply voltage This can cause uncontrolled inrush currents An internal strong pull down circuit holds GATE low while in UVLO
20. voltage is any voltage greater Voare I l I l timer expires the GATE pin shuts down T OUT I l TIMER FUNCTION Lg lg ee MI The TIMER pin is responsible for several key functions on the MODE CYCLE N E YE ADM1170 A capacitor controls the initial power on reset time STARTUP E and the amount of time an overcurrent condition lasts before NCE 8 the FET shuts down On the ADM1170 1 the timer pin also Figures tower timing controls the time between auto retry pulses There are pull up l I and pull down currents internally available to control the timer Vin MUS ae 4 functions The voltage on the TIMER pin is compared with two threshold voltages COMPI 0 2 V and COMP2 1 3 V The four timing currents are listed in Table 5 Table 5 FAN Timing Current Level pA Pull up 5 Pull up 60 Pull down 2 Pull down 100 POWER UP TIMING CYCLE The ADM1170 is in reset when the ON ON CLR pin is held low The GATE pin is pulled low and the TIMER pin is pulled low with a 100 uA pull down At Time Point 2 in Figure 33 the RESET INITIAL START UP NORMAL ON ON CLR pin is pulled high For the device to startup MODE uem ORNs 08 CENCE Figure 34 Power Up into Capacitor 05124 003 correctly the supply voltage must be above UVLO the ON ON CLR pin must be above 1 3 V and the TIMER pin voltage CIRCUIT BREAKER TIMING CYCLE must be less than 0 2 V The initial timing cycle begins when these three conditions are met

ANALOG DEVICES ADM1170 handbook

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