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ANALOG DEVICES ADM1041 handbook

1. G OHS3HHL 135 dAO 13S A yopu6 Q IOHS3HHL aNva 3SN3S Q IOHS3HHL dWV19 An 13S dV 1o AN AS WA ASZT A 39VIlOAH3AO 145 39VL10A avol 1435 vyse z 5 0 0 25 0 SHalsio3H ATIVLIOIG 3 SUYALAWOILNALOd TIY c Nid 15 Nid 39V L10A SHLON 3sNas Figure 4 Chip Diagram Part 2 Re un o a lt gt a S www dzsc o ADM1041 SPECIFICATIONS Ta 40 to 85 C Vpp 5 10 unless otherwise noted Table 1 Parameter Min Typ Max Unit Test Conditions Comments SUPPLIES Voo 4 5 5 0 5 5 lop Current Consumption 6 10 mA Peak during EEPROM Erase Cycle 40 mA UNDERVOLTAGE LOCKOUT Voo See Figure 9 Start Up Threshold 4 4 3 4 5 Stop Threshold 3 7 4 4 2 V Hysteresis 0 3 V Vnrr 2 5 Vrerout Reg OFh 4 2 111 See Table 24 Output Voltage 2 49 2 50 2 51 V Inge 1 MA Ta 25 C Line Regulation 5 0 45 mV 4 5 V lt Voo lt 5 5 V Load Regulation 5 0 45 mV mA lt Ine lt 2 mA Temperature Stability 100 ppm C Inge 1 mA Long Term Stability 5 Over 1 000 hr T 125 C Current Limit 10 20 mA Veer 24 V Output Resistance 0 5 Load Capacitance 1 nF Recommended for stabilit
2. essent 34 SMBus Protocols for RAM and 36 SMBus Read Operations 38 SMBus Alert Response Address 39 Support for Bus 1 tetris pen 39 Layout Considerations sees 39 Power Up Auto Configuration 39 Extended SMBus Addressing sss 40 Backdoor ACCESS 40 Register Listing 41 Detailed Register Descriptions 42 Manufacturing Data sss 51 Microprocessor Support esee teet 52 Trim tete ir de Ree EHE 54 Appendix A Configuration Table 55 Appendix B Test Name Table ses 61 Outline Dimensions tentent tenens 64 Ordering 64 REVISION HISTORY 3 04 Revision Sp0 Initial Version 5 04 Changed from Rev Sp0 to Rev A Rev A Page 2 of 64 GENERAL DESCRIPTION The ADM1041 is a secondary side and management IC specifi cally designed to minimize external component counts and to eliminate the need for manual calibration or adjustment on the secondary side controller The principle application of this IC is to provide voltage control current share and housekeeping functions for single
3. 0 Normal SMBus microprocessor 1 SCL AC_OK Link SDA PSon Link Configure ACsense to be 6 up_AC_OK_m b6 Mode hardware derived or from 0 Hardware ACsense an SMBus command 1 Microprocessor support via SMBus Configure PSON to be 7 up_pson_m b7 Mode hardware derived or from 0 Hardware PS_ON an SMBus command 1 Micorporcessor support via SMBus Configure UV blanking to 4 uvbm b4 Mode be internally derived or 0 UVB follows AC_OKLink from AC_OKLink Set 1 UVB follows ACsense opposite to i2cmb Build FAULT or SMBAlert signal Allows a composite interrupt to be constructed 7 0 selcbd1 bn signal by ORing up to 15 different 7 ovfault signals 6 uvfault 5 ocptO ridethough timed out 4 acsnsb 3 ocpf This uses the CBD pin 2 otp mov5 1 orfetokb m cbd wis a uP writable 0 Share OKb bit 7 1 selcbd2 7 b 6 mfgl 5 mfg2 4 mfg3 3 mfg4 2 m cbd w 1 mfg5 0 Not used 1g E www dzsc Rev A Page 55 of 64 ADM1041 Description Trim registers locking bit Current Sense Mode Chopper Mode Current sense dc offset adjustment with respect to the input Compensates for the amplifier input offset voltage Current sense external divider error correction range with respect to the input Compensates for the mismatch error of the external resistor dividers at Pins 2 and 3 Set differential current sense gain Set current transformer input gain OCP mode Disa
4. 1 V Input Offset Voltage 40 50 60 mV Master slave arbitration Share OK Window Comparator Threshold SHRS 2 V SHRrunesh Share Drive Error 100 Reg 04h 1 0 00 See Table 13 200 mV Reg 04h 1 0 01 See Table 13 300 mV Reg 04h 1 0 10 See Table 13 400 mV Reg 04h 1 0 11 See Table 13 CURRENT LIMIT Figure 10 Current Limit Control Lower Threshold 1 3 0 7 V Vs 1 5 Current Limit Control Upper Threshold 3 5 V Vst 0 V Vscme OV CURRENT SHARE CAPTURE Vscwp 3 5 V Current Share Capture Range 0 7 1 1 3 90 Reg 10h 5 4 00 See Table 25 1 4 2 2 6 Reg 10h 5 4 01 See Table 25 2 1 3 3 9 96 Reg 10h 5 4 10 See Table 25 2 8 4 5 2 Reg 10h 5 4 11 See Table 25 Capture Threshold 0 6 1 0 14 V FET OR GATE DRIVE Open drain N channel FET Output Low Level On 0 4 V lio 5 mA 0 8 V lo 10 mA Output Leakage Current 5 45 REVERSE VOLTAGE COMPARATOR FS FD Vcs FS Common Mode Range 0 25 2 0 Voo 2 V Voltage set by Cs resistor divider Voltage on Cs pin Ta 25 C Rev A Page 9 of 64 1g E www dzsc ADM1041 Parameter Min Typ Max Unit Test Conditions Comments Reverse Voltage Detector Turn Off Threshold Vcs_ 2 V for threshold specs 100 mV Reg 03h 7 6 00 See Table 12 150 mV Reg 03h 7 6 01 See Table 12 200 mV Reg 03h 7 6 10 See Table 12 250 Reg 03h 7 6 11 See Table 12 Reverse Voltage Detector Turn
5. 1041A RQ ERY FS ANALOG Secondary Side Controller with DEVICES Current Share and Housekeeping ADM1041 PRODUCT FEATURES INTERFACE AND INTERNAL FEATURES Digital calibration via internal EEPROM SMBus interface compatible Supports SSI specification Low drift precision 2 5 V reference Comprehensive fault detection Voltage error amplifier Reduced component count on secondary side Differential current sense Standal n or microcontroller coritrol Sense resistor or current transformer option Overvoltage protection Undervoltage protection SECONDARY SIDE FEATURES Overcurrent protection Generates error signal for primary side PWM Overtemperature protection Output voltage adjustment and margining Start up undervoltage blanking Current sharing Programmable digital debounce and delays Current limit adjustment 352 byte EEPROM available for field data OrFET control 160 byte EEPROM for calibration Programmable soft start slew rate Ground continuity monitoring Standalone or microcontroller operation APPLICATIONS Differential load voltage sense Network servers AC mains undervoltage detection ac sense Web servers Overvoltage protection Power supply control ar 0 Vour gt 2 GND Vpp PWM CONTROLLER ADM1041 SHARE BUS CBD 5 Fp Cs SHRO our i aes Vst OVs OVs ee PEN s
6. www dzsc ADM1041 Description To set DC_OK polarity see polDC OK Option Vrer AC_OK MON5 To set AC_OK polarity see polDC AC sense source PSON delay debounce time DC OK on delay Delay time from dc outputs being enabled to DC OK being asserted DC OK off delay Delay time from PSON forcingDC OK to be deasserted to PEN being deasserted Bit No 4 2 Name mn5s2 mn5s1 mn5s0 acss psonts1 psontsO pokts1 50 potsO Bit Bit Bit 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 b4 b3 b2 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 b2 0 1 b1 b2 0 0 0 1 1 0 1 1 b1 bo 0 0 0 1 1 1 1 b7 56 0 0 0 1 1 0 1 1 Option ve ov iopin 1 15 ov gt 1 25 V ve uv iopin 1 25 V uv gt 1 35 V ve ov iopin 1 25 V ve ov gt 1 35 V ve uv lt 1 15 ve uv gt 1 25 V flag iopin 1 15 V flag iopin 1 25 V flag iopin 1 15 V flag iopin 1 25 V iopin AC OK iopin AC OK iopin AC OK ov lt ve ov iopin gt ve uv iopin lt ve uv iopin gt ve ov iopin vdac ve ov iopin gt ve uv iopin vdac ve uv gt flag iopin vdac flag iopin vdac 2 5 V ref out Source from ACsense1 OK from ACsense2 Period 80 ms 0 ms 40 ms 16
7. BitNo Name R W Description 7 4 Major Revision Code These 4 bits denote the generation of the device 3 0 Minor Revision Code R These 4 bits contain the manufacturer s code for minor revisions to the device Rev 0 Oh Rev 1 1h and soon This register is used by the manufacturer for test purposes It should not be read from or written to in normal operation Table 39 Register 2Ah Status Mirror Power On Default 00h These flags are cleared by a register read provided the fault no longer persists BitNo Name R W Description 7 ovfault L R Overvoltage fault has occurred 6 uvfault L R Undervoltage fault has occurred 5 ocpto L R Overcurrent has occured and timed out ocpf is in Status3 4 mfg1_L R MONT flag 3 mfg2_L R MON flag 2 mfg3 L R flag 1 mfg4 L R MONA flag 0 mfg5 L R MONS flag Note that latched bits are clocked on a low to high transmission only Also note that these register bits are cleared when read via the SMBus except if the fault is still present It is recommended to read the register again after the faults disappear to ensure reset Rev A Page 50 of 64 HE www dzsc ADM1041 Table 40 Register 2Bh Status2 Mirror Power On Default 00h These flags are cleared by a register read provided the fault no longer persists BitNo Name R W Description 7 Share_OKb_L R share fault 6 orfetokb_L R ORFET fault 5 r
8. Vos Dc RANGE Fe True Operate Time from Load OV to TLOADOV_TRUE Fc False LOCAL VOLTAGE SENSE Vis AND FALSE UV CLAMP Input Voltage Range Vis RANGE Stage Gain False UV Clamp Vis Input Voltage Clamp Trim Step DC Offset Trim Step Size with Vos_pc_sTEP respect to input Total Offset Temperature Drift Gain Range Isense range range Gain Setting 1 16h B2 0 000 Gesx Gain Setting 2 16h B2 0 001 Gain Setting 3 16h 2 0 010 G110x Gain Setting 4 16h B2 0 100 Gissx Gain Setting 5 16h B2 0 101 Gizsx Gain Setting 6 16h B2 0 110 Go30x CURRENT SENSE CALIBRATION Full Scale No Offset Attenuation Range Current Share Trim Step At SHRO VsunsreP Current Sense Accuracy 40 mV Cal Accuracy 20 mV at Cs Cs Tolcsua Cal Accuracy 40 mV at Cs Cs Tolcsur Cal Accuracy 40 mV at Cs Cs Tolcsua www dzsc Rev A Page 61 of 64 ADM1041 Specification SHARE BUS OFFSET Test Name Specification REVERSE VOLTAGE COMPARATOR FS FD Common Mode Range Input Impedance Reverse Voltage Detector Turn Off Threshold Reverse Voltage Detector Turn On Threshold Test Name Rrs THRES OFF THRES ON ACsense1 ACsense2 COMPARATOR AC or Bulk Sense Threshold Voltage Thr
9. 08 w UT ANOJ 2 9 4 5 dure 10119 O AST 05155 151455 xu D SV os uosd Ts uosd 33 i dure 2 aseyso jas nos susse 4 9 ur 2 sur 1544 susse 39V L10 5 i 5 tue o susoe 8528 X C z SMBus SERIAL PORT The programming and microprocessor interface for the ADM1041 is a standard SMBus serial port which consists of a clock line and a data line The more rigorous requirements of the SMBus standard are specified in order to give the greatest noise immunity The ADM1041 operates in slave mode only If a microprocessor is not used these pins can be configured to perform the PSonLINK and AC_OKLink functions Note that this port is not intended to be connected to the customer s SMBus or bus Continuous SMBus activity or an external bus fault interferes with the inter ASIC communication possibly preventing proper operation and proper fault reporting If the customer needs status and control functions via the SMBus it is recommended that a microprocessor with a hardware SMBus PC port be used for this interface The microprocessor should access the ASICs via a second SMBus port which may be emu lated in software subset of the full protocol SDA PSonLINK The SDA pin normally carries data in and out of the ASIC
10. Input Voltage High 2 2 V Output Voltage Low 0 4 V Voo 5 V Isnk 4 mA Pull Up Current 100 350 Leakage Current 5 45 ADDO HARDWIRED ADDRESS ADDO Low Level 0 4 ADDO Floating 2 V Floating ADDO High Voo 0 5 SERIAL BUS TIMING See Figure 5 Clock Frequency 400 kHz Glitch Immunity tsw 50 ns Bus Free Time 4 7 us Start Setup Time tsusrA 4 7 us Start Hold Time tup srA 4 Us SCL Low Time 4 7 us SCL High Time 4 Us SCL SDA Rise Time tr 1000 ns SCL SDA Fall Time te 300 ns Data Setup Time tsupar 250 ns Data Hold Time 300 ns EEPROM RELIABILITY Endurance 100 250 k cycles Data Retention 100 Years Rev A Page 11 of 64 1g E www dzsc ADM1041 1 This specification is a measure of during an EEPROM page erase cycle The current is a dynamic Refer to Figure 29 for a typical Ibo plot during an EEPROM page erase Specification is not production tested but is supported by characterization data at initial product release 3 Four external divider resistors are the same ration which is selected to produce 2 0 V nominal at Pin 21 while at zero load current Recommended values are 3 3V 5 0V 12V Rrop 680R 1 5 5 1 1 1 1K 4 Chopper off 5 The maximum specification here is the maximum source current of Pin 8 as specified by the Absolute Maximum Ratings 6 All internal amplifiers acc
11. 2 m shr clmp W Allow the microprocessor to directly control the share clamp 0 normal share clamp operation i e not clamped 1 assert share clamp i e clamped 1 m cbd w R W Allow the microprocessor to write directly to CBD as a possible way of adding an additional port This might be a blinking led or a fail signal to the system 0 cbd R W Microprocessor clear of CBD latch if configured as latching folowing an SMBAlert Table 29 Register 14h Current Sense Divider Error Trim 1 Power On Default from EEPROM Register 8114h during Power Up BitNo Name R W Description 7 0 OS div R W Trim out offset due to external resistor divider tolerances for common mode correction Table 30 Register 15h Current Sense Amp Offset Trim 2 Power On Default from EEPROM Register 8115h during Power Up Bit No Name R W Description 7 0 os dc R W Trim out current sense amplifier offset dc offset correction Table 31 Register 16h Current Sense Options 1 Power On Default from EEPROM Register 8116h during Power Up BitNo Name R W Description 7 6 isense3 R W Unused 5 3 OS div range R W External Divider Tolerance Trim Range Common Mode Trim Range b5 b4 b3 Range External Resistor Tolerance 0 0 0 5 mV 0 2596 0 0 1 10 mV 0 5096 0 1 0 20 1 0096 1 0 0 5 mV 0 25 1 0 1 10 mV 0 50 1 1 0 20 mV 1 00 2 0 isense_range R W Gain Selector b2 b1 Gain Range
12. 5 9 3sNas S 5 5 oor 5 9 1 3uvHs S oyaa A a 39V110A 135 A LOUSUI 5 1 A amp 8 2 1 MalaridWv 3HVHS 1 OL 0 1 01 SHVHSA Ll 135440 0 3uvHs 01 AN AN AN 29 93H d3HA 13 10 1 31V9 13 50 dzsc WWW ADM1041 CURRENT SHARE The current share method is the master slave type which means that the power supply with the highest output current automatically becomes the master and controls the share bus signal All other power supplies become slaves and the share bus signal causes them to increase their output voltages slightly until their output currents are almost equal to that of the master This scheme has two major advantages A failed master power supply simply allows one of the slaves to become the new master A short circuited share signal disables current sharing but all power supplies default to their normal voltage setting allowing a certain degree of passive sharing Because this chip uses a low voltage process an external bidirectional amplifier is needed for most existing share bus signal levels The voltage between Pins 20 and 23 is always controlled to 2 0 V full scale ignoring any offset By connecting Pins 20 and 23 together the chip can produce a
13. Figure 17 OrFET Turn Off Time Default Polarity Tek Stop 506ns 1 00 Ch2 2 00 100 5 Chi 7 1 86 1117 60 56 Figure 18 OrFET Turn On Time Default Polarity 04521 0 042 04521 0 013 ADM1041 Tek Prevu Hic I Tek Prevu I3 506ns 04521 0 043 04521 0 044 ch TUA ChT X 1544 100 Ch2 200 1005 A Chl f 1 84 V 02174 40 13 00 Figure 19 OrFET Turn Off Time Inverse Polarity Figure 20 OrFET Turn On Time Inverse Polarity CURRENT Vout SOURCE DRAIN GATE V Vout 10V PULSEOK LOADOK PENOK REVERSEOK OrFET OK RESET VOLTAGE DETECTOR POLARITY V V Figure 21 OrFET Gate Drive Circuit 04521 0 036 Rev A Page 29 of 64 ADM1041 OSCILLATOR AND TIMING GENERATORS An on board oscillator is used to generate timing signals Some trimming of the oscillator is provided to adjust for variations in processing All timing generated from the oscillator is expected to meet the same tolerances as the oscillator Since individual delay counters are generally two to three bits the worst error is one clock period into these counters which is 25 of the nominal delay period None of these tolerances are extremely critical LOGIC I O AND MONITOR PINS Apart from pins required for t
14. a DC_OK MON4 PULSE ACgeysel MON1 9 PSONIMON3 ACsense2 MON2 ADDO CBD ALERT SDAIPSoyLINK SCL AC OKLink 04521 0 030 Figure 7 Pin Configuration Pin No Mnemonic Description 1 2 Vis Cs FS 3 4 5 7 GND 8 ICT 9 PULSE ACsense1 MON1 Positive Supply for the ASIC Normal range is 4 5 V to 5 5 V Absolute maximum rating is 6 5 V Inverting Differential Current Sense Input Local Voltage Sense Pin and OrFET Source These three functions are served by a common divider The local voltage sense input is used for local overvoltage and undervoltage sensing This pin also provides an input to the false UV clamp that prevents shutdown during an external load overvoltage condition When supporting an OrFET circuit this pin represents the FET source and is the inverting input of a differential amplifier looking for the presence of a reverse voltage across the FET which might indicate a failure mode Noninverting Differential Current Sense Input The differential sensitivity of Cs and Cs is normally around 10 mV to 40 mV at the input to the ASIC Nulling any external divider offset is achieved by injecting a trimmable amount of current into either the inverting or noninverting input of the second stage of the current sense amplifier A compensation circuit is used to ensure the amount of current for zero offset tracks the common mode voltage Nulling of any amplifier offset is d
15. DC_OK 0 1 0 ve ov iopin 1 15 V 0 0 0 iopin 1 25 V 1 1 0 0 1 1 ve uv lt 1 25 V 0 0 1 gt 1 35 V 1 0 0 1 0 0 iopin 1 25 V 0 1 0 iopin 1 35 V 1 0 0 1 0 1 uv iopin 1 15 V 0 0 0 iopin 1 25 V 1 0 1 1 1 0 flag iopin 1 15 V 0 0 0 iopin 1 25 V 1 0 0 1 1 1 flag iopin 1 15 V 0 0 0 iopin 1 25 V 0 0 0 4 2 mn5s2 mn5s1 R W b4 b3 b2 option mfg5 ov uv Refer to the mn5s0 Configuration table Table 45 0 0 0 iopin AC_OK 0 1 iopin AC_OK 0 ve ov iopin lt vdac 0 0 0 iopin gt vdac 1 1 0 0 1 1 ve uv iopin lt vdac 0 0 1 gt 1 0 0 1 0 0 lt 0 1 0 gt 1 0 0 1 0 1 uv iopin lt vdac 0 0 0 gt 1 0 1 1 1 0 flag iopin lt vdac 0 0 0 iopin gt vdac 1 0 0 1 1 1 vref out e g 2 5 V VreF 1 0 psonts1 psontsO R W PSON debounce time b1 0 option 0 0 80 ms 1 0 0 ms no debounce 1 0 40 ms 1 1 160 ms Table 25 Register 10h Config4 Power On Default from EEPROM Register 8110h during Power Up BitNo Name R W Description 7 6 DC_OKoff_delay R W DC_OKoff delay Power Off Warn Delay b7 b6 option 0 0 2ms 0 1 Oms 1 0 1 5 1 1 4ms 5 4 ISHARE_capture R W b5 b4 option 0 0 196 Rev A Page 46 of 64 HE www dzsc ADM1041 BitNo Name R W Description 0 1 296 1 0 396 1 1 496 3 2 55151 ssrsO R W Soft Start Step b3 b2 R
16. m cbd clr Allows the microprocessor to clear the CBD latch following an SMBalert If CBD is 13h 0 Write only configured to be latching there may be circumstances that lead to CBD SMBAlert being set by for example one of the MON flags but does not lead to PSON being cycled and CBD being reset In this case the microprocessor needs to write directly to CBD to reset the latch mfg5 This flag indicates the status of the MONS pin 00h 0 Read only mfg4 This flag indicates the status of the MONA pin 00h 1 Read only mfg3 This flag indicates the status of the MONS pin 00h 2 Read only mfg2 This flag indicates the status of the MON2 pin 00h 3 Read only mfg1 This flag indicates the status of the MON pin 00h 4 Read only ocpto If this flag is high an overcurrent has occurred and timed out 00h 5 Read only uvfault If this flag is high an undervoltage has been sensed 00h 6 Read only ovfault If this flag is high an overvoltage has been sensed 00h 7 Read only vddov If this flag is high a overvoltage has been sensed Oth 0 read only extrefok If this flag is low the externally available reference on Pin 18 is overloaded 01h 1 Read only intrefok If this flag is low the internal reference has no integrity 01h 2 Read only gndok If this flag is low the ASIC ground Pin 7 is open either pin to PCB or bond wires Oth 3 Read only If this flag is low Vop is below its UVL or the power mangement block has a Oth 4 Read only problem a referen
17. slave asserts ACK on SDA 6 The master asserts a stop condition on SDA and the transaction ends Rev A Page 36 of 64 In the ADM1041 the send byte protocol is used to write register address to RAM for a subsequent single byte read from the same address or block read or write starting at that address This is illustrated in Figure 30 1 2 3 5 6 RAM XDDRERE A ADDRESS 00h TO 7Fh Figure 30 Setting a RAM Address for Subsequent Read 04521 0 021 If it is required to read data from the RAM immediately after setting up the address the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read block read or block write operation without asserting an intermediate stop condition Write Byte Word In this operation the master device sends a command byte and one or two data bytes to the slave device as follows 1 master device asserts a start condition SDA 2 The master sends the 7 bit slave address followed by the write bit low 3 The addressed slave device asserts ACK on SDA 4 The master sends a command code 5 The slave asserts ACK on SDA 6 The master sends a data byte 7 slave asserts ACK on SDA 8 The master sends a data byte or may assert stop at this point 9 slave asserts ACK on SDA 10 The master asserts a stop condition on SDA to end the transaction In the ADM1041 the write byte word protocol is use
18. Current Share Capture Range Capture Threshold THRES MIN THRES MAX 5 RANGE VsHR THRES FET OR GATE DRIVE Output Low Level On Output Leakage Current Polarity Select Vgateon Vio rer rer Noise Filter Tnesns PULSE IN Threshold Voltage VeuLSEMIN Pulseok on delay TpUuLSEON Pulseok off delay TPULSEOFF OSCILLATOR AND TIMING General Tolerance on Time Delays OCP Threshold Voltage Vocp_tHRES OCP Shutdown Delay Time Toce s ow Continuous Period in Current Limit OCP Fast Shutdown Delay Time Toc rasr MON1 MON2 MON3 MONA Sense Voltage Hysteresis OVP Noise Filter Tnrove_Mon1 UVP Noise Filter Turuve woN1 OTP MON5 Sense Voltage Range RANGE OTP Trim Step 5 Hysteresis lore OVP Noise Filter UVP Noise Filter Turuve ore PSON Input Low Level Input High Level Debounce TNF_PSON PEN DC_OK CBD AC_OK Open Drain N Channel Option Output Low Level On Vo Open Drain P Channel Output High Level On Leakage Current fg e www dzsc Rev A Page 62 of 64 Specification DC_OK Test Name ADM1041 DC_OK On Delay Power On and OK Delay DC_OK Off Delay Power Off Early Warning SMBus SDL SCL Input Voltage Low Vit Input Voltage H
19. Page 42 of 64 ww dzsc ADM1041 Bit No 1 0 Name loadov recover R W R W Description b1 O Function Add 100 us delay Add 200 us delay Add 300 us delay Add 400 us delay Table 13 Register 04h Current Sense CC Power On Default from EEPROM Register 8104h during Power Up BitNo Name R W Description 7 3 curr_limit R W This register contains current sense trim level setting at which current limiting starts 2 Share_OK_Window Share_OK Window Comparator Thresholds 1 0 Share_OK_thresh R W b1 bo Function 0 0 100 mV 0 1 200 mV 1 0 300 mV 1 1 400 mV Table 14 Register 05h Current Share Offset Power On Default from EEPROM Register 8105h during Power Up BitNo Name R W Description 7 0 IsHare_Offset R W This register contains current share offset trim level Writing 00h corresponds to the min offset FFh corresponds to maximum offset See the Current Limit Error Amplifier section in the Specifications for more information Table 15 Register 06h Current Share Slope Power On Default from EEPROM Register 8106h during Power Up BitNo Name Description 7 1 ISHARE_slope R W This register contains current share slope trim level 0 Reserved X Don t Care Table 16 Register 07h EEPROM lock Power On Default from EEPROM Register 8107h during Power Up BitNo Name R W Description 7 Reser
20. during programming configuration or while reading writing by a microprocessor If a microprocessor is not used this pin can be configured as PSonLINK and can be connected to the same pin on other ADM1041s in the power supply If a fault is detected in any ADM1041 causing it to shut down it uses this pin to signal the other ADM1041s to also shut down If an auto restart has been configured it also causes all ADM1041s to turn on together SCL AC_OKLink The SCL pin normally provides a clock signal into the ASIC during programming configuration or while reading writing by a microprocessor If a microprocessor is not used this pin can be configured as AC_OKLink and can be connected to the same pin on other ADM1041s in the power supply This allows a single ADM1041 to be used for ac sensing and helps to synchronize the start up of multiple ADM1041s ADDO This pin configures two bits of the chip address for the SMBus It is three level and can be pulled high to Vp pulled low to ground or left floating internally biased to 2 5 V An additional bit may be set during configuration which allows up to six ADM1041s to be used in a single power supply The state of ADDO is continuously sampled after power up After the first time the ADM1041 is successfully addressed the internal bias is released and ADDO becomes high impedance www dzsc ADM1041 MICROPROCESSOR SUPPORT The ADM1041 has many features that allo
21. mn2s0 b7 b6 b5 option mfg2 Ov uv 0 0 0 iopin ACsense2 true high 0 0 1 iopin ACsense2 true high 0 1 0 ve ov 1 15 0 0 0 iopin gt 1 25 V 1 1 0 0 1 1 uv iopin 1 25 V 0 0 1 iopin 1 35 V 1 0 0 1 0 0 lt 1 25 V 0 1 0 iopin 1 35 V 1 0 0 1 0 1 uv iopin lt 1 15 V 0 0 0 iopin 1 25 V 1 0 1 1 1 0 flag lt 1 15V 0 0 0 iopin 1 25 V 1 0 0 1 1 1 flag iopin 1 25 V 1 0 0 iopin gt 1 25V 0 0 0 4 2 mn3s2 mn3s1 R W b4 b3 b2 option mfg3 ov uv mn3s0 0 0 0 iopin PSON true low 0 0 1 iopin PSON true high 0 1 0 ve ov iopin 1 15 V 0 0 0 iopin 1 25 V 1 1 0 0 1 1 ve uv iopin lt 1 25 V 0 0 1 iopin gt 1 35 V 1 0 0 1 0 0 lt 1 25 V 0 1 0 iopin gt 1 35 1 0 0 1 0 1 iopin lt 1 15 0 0 0 iopin gt 1 25 1 0 1 1 1 0 flag lt 1 15V 0 0 0 gt 1 25 V 1 0 0 1 1 1 flag iopin 1 15 V 1 0 0 iopin 1 25 V 0 0 0 1 0 pokts1 poktsO R W DC OKon delay b1 0 option 0 0 400 ms 0 1 200 ms 1 0 800 ms 1 1 1600 ms www dzsc Rev A Page 45 of 64 ADM1041 Table 24 Register OFh Config3 Power On Default from EEPROM Register 810Fh during Power Up BitNo Name R W Description 7 5 mn4s2 mn4s1 R W b7 b6 b5 option mfg4 ov uv 111450 0 0 0 Refer to the Configuration table Table 45 0 0 1 iopin
22. 0 12V DEVICE 0 Figure 38 Extended SMBus Addressing and Backdoor Access 04521 0 029 40 64 REGISTER LISTING ADM1041 Table 8 Register Address Name Power On Value Factory EEPROM Value 00h 2Ah Status1 Status1 Mirror Latched XXh Depends on status of ADM1041 at power up 01h 2Bh Status2 Status2 Mirror Latched XXh Depends on status of ADM1041 at power up 02h 2Ch Status3 Status3 Mirror Latched XXh Depends on status of ADM1041 at power up 03h Calibration Bits From EEPROM Register 8103h 00h 04h Current Sense CC From EEPROM Register 8104h 00h 05h Current Share Offset From EEPROM Register 8105h 00h 06h Current Share Slope From EEPROM Register 8106h FEh 07h EEPROM_lock From EEPROM Register 8107h 20h 08h Load OV Fine From EEPROM Register 8108h 00h 09h Local UVP Trim From EEPROM Register 8109h 00h OAh Local OVP Trim From EEPROM Register 810Ah 00h OBh OTP Trim From EEPROM Register 810Bh 00h OCh ACSNS Trim From EEPROM Register 810Ch 00h ODh Config1 From EEPROM Register 810Dh 00h OEh Config2 From EEPROM Register 810Eh 00h OFh Config3 From EEPROM Register 810Fh 00h 10h Config4 From EEPROM Register 8110h 00h 11h Config5 From EEPROM Register 8111h 00h 12h Config6 From EEPROM Register 8112h 00h 13h Config7 From EEPROM Register 8113h 00h 14h Current Sense Divider Error Trim From EEPROM Register 8114h XXh Factory Cal Values 15h Current Sense Amplifer Offset From EEPROM Registe
23. 2 0 V share signal directly without any exter nal circuits To improve accuracy the share signal is referenced to remote voltage sense negative CURRENT SHARE OFFSET To satisfy some customer specifications the current share signal can be offset by a fixed amount by using a trimmable current generator and a series resistor The offset is added on top of the 2 0 V full scale current share output signal See Figure 14 IsHare DRIVE AMPLIFIER This amplifier is a buffer with enough current source capability to drive the current share circuits of several slave power supplies It has negligible current sink capability Refer to the Differential Sense Amplifier section that follows DIFFERENTIAL SENSE AMPLIFIER This amplifier has unity gain and senses the difference between the share bus voltage and the remote voltage sense negative pin When the power supply is the master it forms a closed loop with the drive amplifier described above and therefore it causes the share bus voltage between Pins 20 and 23 to equal the current share signal at the noninverting input of the drive amplifier When the power supply is a slave the output of the differential sense amplifier exceeds the internal current share signal which causes the Isuare drive amplifier to be driven into cutoff Because it is not possible to trim out negative offsets in the op amps in the current share chain a 50 mV voltage source is used to provide a kno
24. 25 Writing a Register Address to the Address Pointer Register then Writing Data to the Selected Register 5 SDATA START BY MASTER SDATA 5 START BY FRAME 1 SERIAL BUS ADDRESS BYTE 0 RW ACK BY ADM1041 FRAME 2 ACK BY ADM1041 ADDRESS POINTER REGISTER BYTE Figure 26 Writing to the Address Pointer Register Only FRAME 1 SERIAL BUS ADDRESS BYTE 1 1 1 1 1 RW ACK BY ADM1041 FRAME 2 DATA BYTE FROM ADM1041 Figure 27 Reading Data from a Previously Selected Register Table 6 Device SMBus Addresses ACK BY ADM1041 ADM1041 1 1 1 1 C 04521 0 045 5 MASTER 04521 0 046 STOP BY MASTER 04521 0 047 ADD1 ADDO Target Device OOO GND NC 1 0 O0 5 Note ADD1 is low by default To access the additional three addresses it is necessary to set Config 4 lt 1 gt high and then perform a power cycle to allow the new address to be latched after the EEPROM download Refer to the section on Extended SMBUS Addressing for more details www dzsc Rev A Page 35 of 64 ADM1041 SMBus PROTOCOLS FOR RAM AND EEPROM The ADM1041 contains volatile registers RAM and nonvola tile EEPROM RAM occupies the address locations from 00h to 7Fh while EEPROM o
25. 300 600 us OTP MONS Reg OFh 4 2 01x or 10x Table 24 Sense Voltage Range 2 2 2 45 V OTP Trim Step 24 mV 2 1 lt Vm lt 2 45 V 4 bits 15 steps Reg OBh 7 4 See Table 20 Hysteresis 100 130 160 2 fg e www dzsc Rev A Page 10 of 64 ADM1041 Parameter Min Typ Max Unit Test Conditions Comments OVP Noise Filter 5 25 us Reg OFh 4 2 010 or 100 See Table 24 UVP Noise Filter 300 600 us Reg OFh 4 2 011 or 101 See Table 24 5 Reg OEh 4 2 00x See Table 23 Input Low Level 0 8 V Input High Level 2 0 V Debounce 80 ms Reg OFh 1 0 00 See Table 24 0 ms Reg OFh 1 0 01 See Table 24 40 ms Reg OFh 1 0 10 See Table 24 160 ms Reg OFh 1 0 11 See Table 24 DC OK CBD AC OK Open Drain N Channel Option Output Low Level 0 4 V Isink 4 mA Open Drain P Channel Von PEN Output High Level On 2 4 V lsource 4 mA Leakage Current 5 45 DC_OK Reg OFh 7 5 00x See Table 24 DC_OK On Delay Power On and OK Delay 400 ms Reg OEh 1 0 00 See Table 23 200 ms Reg OEh 1 0 01 See Table 23 800 ms Reg OEh 1 0 10 See Table 23 1600 ms Reg OEh 1 0 11 See Table 23 DC_OK Off Delay Power Off Early Warning 2 ms Reg 10h 7 6 00 See Table 25 0 ms Reg 10h 7 6 01 See Table 25 1 ms Reg 10h 7 6 10 See Table 25 4 ms Reg 10h 7 6 11 See Table 25 SMBus SDL SCL Input Voltage Low 0 8
26. 5 b4 b1 Option FET option Polarity N Polarity True low N FET on True high N FET off FET option Polarity N Soft start threshold 75 88 Mode MONS OV causes shutdown MONS OV turns off and then restarts when temperature falls Mode cbdlm nonlatching cbdlm latching FET Option Polarity N N Locks EEPROM range 8140h 817Fh 8120h 813Fh 8100h 811Fh 80COh 80FFh 8080h 80BFh 8040h 807Fh 8000h 803Fh gnd offset ISHARE amp offset 100 mV 50 mV 0 mV 0 mV GND monitoring enabled GND monitoring disabled that is always OK fg e www dzsc Rev A Page 60 of 64 APPENDIX B TEST NAME TABLE This table is included for ADI s internal reference use This is a cross reference for the ADI test program ADM1041 Table 46 Specification Test Name Supplies Vop lop Current Consumption Peak during EEPROM Erase Cycle UNDERVOLTAGE LOCKOUT Start Up Threshold Stop Threshold Hysteresis 2 5 Ref Out VREF Output Voltage VREF Line Regulation Load Regulation Temperature Stability TCrer Long Term Stability VREF_STAB Current Limit Imax Output Resistance Ro Load Capacitance Ripple Due to Autozero VREF_RIPPLE POWER BLOCK PROTECTION Voo Overvoltage Vove Overvoltage Deb
27. 5 Veer This is a 2 5 V precision reference voltage capable of sourcing 2 mA This function is continuously monitored and if the voltage falls below 2 0 V PEN is disabled Forcing this pin s voltage does not affect the integrity of the internal reference AC OK This option be configured as N channel or P channel and as normal or inverted polarity At system level a true AC OK is used to indicate that the primary bulk voltage is high enough to support the system and when false that dc output is about to fail 5 A further option is to configure this as an analog input MONS with a flexible hysteresis and trimmable 2 5 V reference that makes this pin particularly suitable for overtemperature protection OTP sensing Since hysteresis uses a switched 100 pA current source hysteresis can be adjusted via the source impedance of the external circuit It can also be used for overvoltage and undervoltage functions FET Gate Enable When supporting an OrFET circuit this is the gate drive pin Since the open drain voltage on the chip is limited to an external level shifter is required to drive the higher gate voltages suitable for the OrFET This pin is configured as an open drain N channel Either output polarity low on or low off may be selected This pin is used as the ground input reference for the current share and load voltage sense circuits It should be tied to ground at the common remote sense location The input
28. Set by external resistor divider Stage Gain 1 3 AtVis 1 8V False UV Clamp Vis Input Voltage Nominal 1 3 1 85 2 1 Clamp Trim Step 0 2 VRANGE Clamp Trim Step 3 1 8 bits 255 steps Reg 18h 7 0 See Table 33 Local Overvoltage 1 9 2 4 2 85 V Nominal and Trim Range OV Trim Step 0 15 96 VRANGE OV Trim Step 3 7 mV 8 bits 255 steps Reg OAh 7 0 See Table 33 Noise Filter for OVP Function Only 5 25 us Local Undervoltage 1 3 1 7 2 1 V Nominal and Trim Range UV Trim Step 0 18 90 VRANGE UV Trim Step 3 1 mV 8 bits 255 steps Reg 09h 7 0 See Table 18 Noise Filter for UVP Function Only 300 600 us VOLTAGE ERROR AMPLIFIER See Figure 14 Reference Voltage sorr sranT 1 49 1 51 V Ta 25 C Temperature Stability 100 40 lt Ta lt 85 C Long Term Voltage Stability 0 2 Over 1 000 hr 125 C Soft start Period Range 0 40 ms Ramp is 7 bit 127 steps Set Soft start Period 300 us Reg 10h 3 2 00 See Table 25 10 ms Reg 10h 3 2 01 See Table 25 20 ms Reg 10h 3 2 10 See Table 25 40 ms Reg 10h 3 2 11 See Table 25 Unity Gain Bandwidth GBW 1 MHz See Figure 11 Transconductance 1 9 2 7 3 5 mA V At lvcme 180 pA Source Current 250 At gt 1 V Sink Current 250 At Vvcwe lt 1 V DIFFERENTIAL CURRENT SENSE INPUT Reg 17h 7 0 See Table 18 Cs Cs Isense mode See Figure 13 Common Mode Range 0 2 V Set by external divide
29. This 1 5 V reference is the output voltage of the soft start circuit Under closed loop conditions the voltage at the noninverting input is also controlled to 1 5 V During start up the output voltage should be ramped up ina linear fashion at a rate that is independent of the load current This is achieved by digitally ramping up the reference voltage by using a counter and a DAC The ramp rate is configurable via the SMBus See Figure 14 CURRENT SENSE AMPLIFIER This is a two stage differential amplifier that achieves low offset and accuracy The amplifier has the option to be chopped to reduce offset or left as a linear amplifier without chopping Refer to the Register Listing for more details Its gain may be selected from three ranges It is followed by a trim stage and then by a low gain buffer stage that can be configured with a gain of 1 0 or 2 1 The result is a total of six overlapping gain ranges 65 to 230 one of which must be selected via the SMBus This gives ample adjustment to compensate for the poor initial tolerance of the resistance wires typically used for current sensing It also allows selecting a higher sensitivity for better efficiency or a lower sensitivity for better accuracy lower offset The amplifier offset voltage is trimmed to zero in a once off operation via the SMBus and uses a voltage controlled current source at the output of the first gain stage A second controlled current source is used to trim out the ad
30. an OVP condition in an N 1 redundant power system This occurs only after a load OV event The local OVP threshold may be trimmed via the SMBus See Figure 9 LOCAL UNDERVOLTAGE PROTECTION UVP This is the main undervoltage detection for the power supply It is also detected locally so that a faulty power supply can be detected in an N 1 redundant power system The local UVP threshold may be trimmed via the SMBus See Figure 9 FALSE UV CLAMP If a faulty power supply causes an OVP condition on the system bus the control loops in the good power supplies is driven to zero output Therefore a means is required to prevent the good power supplies from indicating an undervoltage and they must recover quickly after the faulty power supply has shut down The false UV clamp achieves this by clamping the output voltage just above the local UVP threshold It may be trimmed via the SMBus The OCPF signal disables the clamp during overcurrent faults See Figure 9 __ VOLTAGE 1 3V ERROR AMP START RAMP UP TO GENERAL LOGIC TO GENERAL LOGIC 04521 0 032 ALL POTENTIOMETERS 3 ARE DIGITALLY PROGRAMMABLE THROUGH REGISTERS Figure 9 Block Diagram of Voltage Sense Amplifier fg e www dzsc Rev A Page 20 of 64 CURRENT GM ww dzsc 70 2 00 1 75 140 04521 0 039 0 1 2
31. logic schematic Figure 24 BitNo Name R W Description 7 Share OK R Current share is within limits 6 OrFET OK R ORing MOSFET is on 5 REVERSE OK R reverseok No reverse voltage has occured across the ORing MOSFET 4 R Vpp is within limits 3 GND OK R Connection of GND pin is good 2 intrefok R Internal voltage reference is within limits 1 extrefok R External voltage reference is within limits 0 vddov R Voo is above its OV threshold Table 11 Register 02h Status3 Power On Default Refer to the logic schematic Figure 24 BitNo Name R W Description 7 m acsns r R Reflects the status on ACsense1 ACsense2 6 m_pson_r R Reflects the status of PSON 5 m_penok_r R Reflects the status of PEN 4 m_psonok_r R Status of PSonLINK 3 m_DC_OK_r R Status of DC_OK 2 ocpf R An overcurrent has occured direct from comparator 1 PULSE_OK R Pulses are present at the PULSE pin 0 fault R Fault latch Table 12 Register 03h Calibration Bits Power On Default from EEPROM Register 8103h during Power Up BitNo Name R W Description 7 6 rev_volt_off R W Reverse Voltage Detector Turn Off Threshold b7 56 Function 0 0 100 mV 0 1 150 mV 1 0 200 mV 1 1 250 mV 5 4 rev_volt_on R W Reverse Voltage Detector Turn On Threshold b5 Function 0 0 20 mV 0 1 30 mV 1 0 40 mV 1 1 50 mV gatepen R W Gatepen Option When set PEN is gated by acsok gateramp R W Gateramp Option When set soft start is gated by acsok e Da Rev A
32. of one of these FETs is typically 6 V to 10 V above the output voltage Since the output voltage of the ADM1041 is limited an external transistor needs to be used The block diagram shows an example of this approach See Figure 21 The output is an open drain N channel MOSFET and 18 normally high which holds the OrFET off When all the start up conditions are correct Pin 19 is pulled low which allows the OrFET to turn on The logic can also be configured as inverted if a noninverting drive circuit is used A differential amplifier monitors the voltage across the OrFET and has two major functions First during start up it allows the OrFET to turn on with almost 0 V across it to avoid voltage glitches on the bus This applies to a hot bus or a cold bus The internal threshold can be configured from 20 mV to 50 mV negative which is scaled up by the external voltage dividers Second if a rectifier or filter capacitor fails during steady state operation it detects the resulting reverse voltage across the OrFET 5 on resistance and turns off the OrFET before a voltage dip appears on the bus The internal threshold can be configured from 100 mV to 250 mV negative which is also scaled up by the external voltage dividers A slightly larger filter capacitor may be used on the voltage divider at Pin 6 to speed up this function Figure 17 shows the typical response time of the ADM1041 to such an event In the plot Vro is ramped down a
33. other ADM1041 ASICs in the power supply When the AC_OK pin is not used as such it can be configured as an analog input MONS or as a voltage reference 5 This is the alternative analog comparator function for the pin Pin 18 The threshold is 2 5 V and it has a Figure 22 Example of MON Pin Configuration 100 current source that allows hysteresis to be controlled by adjusting the external source resistance It is ideal for an OTP sensing circuit using a thermistor as part of a voltage divider The OTP condition can be configured to latch off the power supply similar to OVP or to allow an auto restart soft OTP 04521 0 016 In the preceding example MON2 and MON3 are configured to monitor a negative 12 V rail MON2 is configured as negative going OVP and is configured as positive going UVP The 5 V power rail is used for bias voltage See Figure 22 2 5 MON1 LE GENERAL LOGIC 5 ken MONA MONA SHAREOK PSON ores J RESET VREF VppOV CBD CBD ALERT PENOK CONTROL REGISTERS PEN PWRON CONFIGURE 105 CONFIGURE WRITE REGISTERS CONTROL LINES SERIAL INTERFACE PEN SDAI PSoyLINK SCLI AC_OKLink ADDO 04521 0 014 Figure 23 Block Diagram of Protection and General Logic Rev A Page 31 of 64 1g E www dzsc ADM10
34. selected Prior to shutting down the DC OK output goes false warning the system that output will be lost The latch is the same one used for OVP For auto restart the OCP time out period is configurable Overtemperature Protection If the temperature being sensed is detected as going over the selected limit the OTP function sends out a fault signal that triggers a shutdown that can be latched or allowed to auto restart depending on the mode selected Prior to shutting down the DC OK output goes false warning the system that output will be lost The latch is the same one used for OVP Undervoltage Blanking The UVP function is blanked disabled during power up or if the ACsense function is false ac line voltage is low When in constant current mode UVB is disabled The status of ACsense must be known to the IC either by virtue of the on board ACsense or communicated by the SMBus with the help of an external microprocessor or by using AC OKLink When in constant current mode due to an overload UVB is applied for the overcurrent ride through period The DC OK function advises the system on the status of the power supply When it is false the system is assured of at least 1 ms of operation if ac power is lost for any reason Other turn off modes provide more warning time This pin is an open drain output It can be configured as a P channel pull up or an N channel pull down It may also be configured as positive or negative inverted logic
35. that could be used for monitoring a post regulated output includes overvoltage undervoltage and overtemperature conditions CBD The crowbar drive pin allows implementation of a fast shutdown in case of a load overvoltage fault The pin can be configured as an open drain N channel or P channel and is suitable for driving a sensitive gate SCR crowbar An external transistor is required if a high gate current is needed Either polarity may be selected ALERT This pin can be configured to provide an ALERT function in microprocessor supported applications whereby any of several ICs in a redundant system that detects a problem can interrupt and shut down the power supply An alternative use is as a general purpose logic output signal Power Enable This pin can be configured as an open drain N channel or P channel that typically drives the PEN optocoupler Providing that the PSON pin has been asserted to turn the output on and that there are no faults this pin drives an optocoupler on enabling the primary PWM circuit Either polarity may be selected SCL SMBus Serial Clock Input AC OkKLink In non microprocessor applications this pin can be programmed to give the status of ACsense to all the ICs on the same bus The main effect is to turn on undervoltage blanking whenever the sense circuit monitoring ac or bulk dc detects a low voltage SDA SMBus Serial Data Input and Output PSonLINK In non microprocessor applications this pin can be
36. when the flag is read except when the fault is still present It is advisable to continue reading the flag s until the fault s have cleared HE www dzsc Rev A Page 53 of 64 ADM1041 TRIM TABLE This table shows all of the trims that can be set in the ADM1041 Table 44 Description Name Range Steps Step Size Reg Bit No Set Load Voltage Trim output from load_v 1 7 V 2 3 V 255 1 74 mV 3 18 mV 19h 7 0 differential amplifier to set voltage at load at input pins Set Load OV Trim calibrated output from load_ov 105 120 255 1 6 mV 08h 7 0 remote sense amplifier to set load OV Offset input threshold Set False UV Clamp Threshold Fine trim uv clamp 1 3 V 2 1 V 255 1 94 mV 5 07 mV 18h 7 0 output to set voltage before OR FET in case of load OV at input pins Set Local UVP Threshold Fine trim output local_uvp 1 3 V 2 1V 255 1 94 mV 5 07 mV 09h 7 0 from local sense buffer to set UVP threshold at input pins Set Local OVP Threshold Fine trim output local_ovp 1 9 V 2 85 V 255 2 48 mV 5 59 mV OAh 7 0 from sense buffer to set OVP threshold at input pins External Divider Offset Trim Range 05 div_range 5 mV 20 uV 16h 5 3 10 39 20 78 uV External Divider Offset Trim Trim out offset os_div 255 14h 7 0 due to resistor divider tolerances DC Offset Trim Range os_dc_range 8 mV 30 uV 17h 3 0 15 mV 60 uV 30 mV 120 pV Current Sense DC Offset Trim Trim out os dc 255 15h 7 0 amplifier dc o
37. 0 0 0 65x 34 0 mV to 44 5 mV 0 0 1 85x 26 0 mV to 34 0 mV 0 1 0 110x 20 0 mV to 26 0 mV 1 0 0 135x 16 0 mV to 20 0 mV 1 0 1 175x 12 0 mV to 16 0 mV 1 1 0 230x 9 5 mV to 12 0 mV ww dzsc Rev A Page 48 of 64 ADM1041 Table 32 Register 17h Current Sense Option 2 Power On Default from EEPROM Register 8117h during Power Up BitNo Name R W Description 7 csense_mode R W 0 DIFFsense current sense with external resistor 1 CTsense current transformer 6 chopper R W When chopper 1 current sense amplifier is configured as a chopper Otherwise current sense amplifier is continuous time 5 ct range R W Gain Range 0 4 5 0 45 0 68 122 57 0 79 V 1 20 V 4 select gnd offset R W 0 ground offset 100 mV Ishare error amp offset 50 mV 1 ground offset 0 IsHare error amp offset 0 3 Reserved Don t Care 2 0 os dc range R W Internal Sense Amp Offset Trim Range for Differential Current Sense b2 b1 0 Gain 0 0 0 8 mV 1 0 0 1 15 mV 2 0 1 0 30 4 1 0 0 8 mV 1 1 0 1 15 mV 2 1 1 0 30 mV 4 Table 33 Register 18h UV Clamp Trim Power On Default from EEPROM Register 8118h during Power Up Bit No Name R W Description 7 0 uv_clamp R W This register contains the false UV clamp settings Table 34 Register 19h Load Voltage Trim Power On Default from EEPROM Register 8119h during Power Up Bit No
38. 0 ms Period 400 ms 200 ms 800 ms 1600 ms period 2ms 0 ms 1ms 4 ms orf ofr 0 flag o o O ee ee e gt oo o fg e www dzsc Rev A Page 58 of 64 ADM1041 Description Current share capture range Maximum output voltage control range due to the current share action Soft start mode provides option for soft startramp to be gated by acsnsok Soft start step rise time output rise time PEN start up mode Provides option for PEN to be gated by acsnsok Load overvoltage debounce OrFET Reverse Voltage Threshold Reverse voltage at which the ORFET turns off OrFET Forward Voltage Threshold Reverse voltage at which the OrFET turns on Share_OK Window Threshold Restart Mode Provides an option to auto restart after approximately 1 sec This applies only to UVP and OCP faults not to OVP faults Set PEN Output Polarity Also selects open drain N channel or P channel Bit No 5 4 3 2 5 4 1 0 Name IsHare_Capture gateramp ssrsl ssrsO gatepen loadov_recover rev_volt_off rev_volt_on Share_OK_thresh rsm polpenO polpen1 Bit Bit Bit b5 b4 0 0 0 1 1 0 1 1 0 1 b3 b2 0 0 0 1 1 0 1 1 1 b1 0 0 0 1 1 0 1 1 b7 b6 0 0 0 1 1 0 1 1 b5 b4 0 0 0 1 1 0 1 1 b1 0 0 0 1 1 0 1 1 1 b7 b6 0 0 0 1 1 0 1 1 Option R
39. 1041 ASICs in the power supply The alternative function is an SMBus alert output that can be used as an interrupt to a microprocessor If a fault occurs the microprocessor can then query the ADM1041 s about the fault status This is intended to avoid continuously polling the ADM1041 s Generally the microprocessor needs to routinely gather other data from the ADM1041 s which can include the fault status so the ALERT function may not be used Also the simplest microprocessors may not have an interrupt function This allows the CBD ALERT pin to be used for other functions www dzsc 1 This is the alternative analog comparator function for the Pulse ACsensel pin Pin 9 The threshold is 1 25 V When MONI is selected ACsense1 defaults to true MON2 This is the alternative analog comparator function for the ACsense2 pin Pin 10 The threshold is 1 25 V When MON2 is selected ACsrnsr2 defaults to true PEN This is the power enable pin that turns the PWM converter on and can be configured as active high or low This might drive an opto isolator back to the primary side or connect to the enable pin of a secondary side post regulator PSON This pin is usually connected to the customer s PSON signal and when asserted causes the ADM1041 to turn on the power output It can be configured as active high or low Alternatively a microprocessor can communicate the PSON function to the ADM1041 using th
40. 2 101 A ISNS 5 H3WHOJSNVHL 0 1001 AUVHS a 135440 4 SYVHS 1 934 07 3SN3S 5159 915 WIL 2v UAE S ZASNAS Sy 98ST A SIN 5 59 n A A 2 A A 4 Figure 3 Chip Diagram Part 1 Re o o a gt a S www dzsc o ADM1041 9 05 xuriNO2V nos NOSd NON ZNOW TNOW SNOW 0149 21901 E Nad 8 suaisiozy suaisio3u snivis 38n9ldNo2 500 SHalsiodu Nad 7OHINOO 3OVJH3INI 791435 san 1 F 2a OV 9 NOSd 21901 MON3d 39V ILT1OA dn 43915 1405 AGT FOVLIOA dunidvo 5 1 3SN3S 39V L1OA 1 gt MO3uVHS 3013430 2v 15 TT IN3W3OVNVM MOASYLNI YOLINOW
41. 3 4 VOLTAGE Figure 10 Current Limit 04521 0 040 0 100 1k 10k 100k 1M 10M 100 BANDWIDTH Figure 11 Vcwe Transconductance 04521 0 041 1 10 100 1k 10k 100k 1M 10M 100M BANDWIDTH Figure 12 Ccwe and Scup Transconductance ADM1041 VOLTAGE ERROR AMPLIFIER This is a high gain transconductance amplifier that takes its input from the load voltage trim stage described previously The amplifier requires only the output pin for loop compensation which typically consists of a series RC network to common A parallel resistor may be added to common to reduce the open loop gain and thereby provide some output voltage droop as output current increases The output of the amplifier is typically connected to an emitter follower that drives an optocoupler which in turn controls the duty of the primary side PWM The emitter follower should have a high gain to minimize loading effects on the amplifier Alternatively an op amp voltage follower may be used See Figure 9 Figure 10 and Figure 11 MAIN VOLTAGE REFERENCE 1 5 V reference is connected to the inverting input of the voltage error amplifier
42. 41 lt 4 gt 2 42195 810 0 128 0 4 yoppa 820 E 9 zpqoies lt 9 gt Tpqojes AOppA ynezan lt 9 gt 2 C 0420 5 5 1 50528 g zpqojas d g Ipqojes L lt dioyos 4 39 0 A lt 2 gt 2 921 5 5 2357 Z T YO Tupa UA O pqojod C er zpqajes lt gt Tpqops lt lt um C lt SIp un una C lt 0 gt zpqojas lt 0 gt 5 LON lt yoareys 053920 51420 zsidoo aavsia nee 0 v NS HOHNH3 1 dO 1 Wows An 5 009 008 007 002 061 04 TSLHOd C 1 402p ui 05 yoopjod sup z T o 440 Re o o m lt gt Figure 24 General Logic Nad youad C uedjod C ww Hou pL PE duo aus ur dioyos ur lt nts d Ros X 1 02 SWOT 57005 uosd 88 94 ur uosd dn ur duis zt ava 94 Tavis 9
43. 6 7 8 9 10 11 12 SLAVE COMMAND Ath SLAVE BYTE ADDRESS wla BLOCK READ s ADDRESS COUNT DATAE DATAN se o 04521 0 025 Block Read In this operation the master device reads a block of data from a slave device The start address for a block read must previously have been set In the case of the ADM1041 this is done a send byte operation to set a RAM address or by a write byte word operation to set an EEPROM address The block read operation itself consists of a send byte operation that sends a block read command to the slave immediately followed by a repeat start and a read operation that reads out multiple data bytes as follows 1 master device asserts a start condition on SDA 2 The master sends the 7 bit slave address followed by the write bit low 3 The addressed slave device asserts on SDA 4 The master sends a command code that tells the slave device to expect a block read The ADM1041 command code for a block read is 1 10100001 5 slave asserts ACK on SDA 6 The master asserts a repeat start condition on SDA 7 The master sends the 7 bit slave address followed by the read bit high 8 The slave asserts on SDA 9 The master receives a byte count data byte that tells it how many data bytes will be received The SMBus specification allows a maximum of 32 data bytes to be received in a block read 10 The master asserts ACK on SDA 11 The master rece
44. AC Bulk Sense 1 or Monitor 1 Input PULSE This tells the OrFET circuit that the voltage from the power transformer is normal A peak hold allows the OrFET circuit to pass through the pulse skipping that occurs with very light loads but turns off the circuit about one second after the last pulse is recognized ACsense1 This sense function also uses the peak voltage on this pin to measure the bulk capacitor voltage If too low AC_OK and DC_OK can warn of an imminent loss of power Threshold level and hysteresis can be trimmed When not selected ACsense1 defaults to true When MONT is selected for this pin its input is compared against 1 25 V comparator that could be used for monitoring a post regulated output includes overvoltage undervoltage and overtemperature conditions HE www dzsc Rev A Page 14 of 64 ADM1041 Pin No 10 11 12 13 14 15 16 17 18 19 20 Mnemonic ACsense2 MON2 CBD ALERT PEN SCL AC_OKLink SDA PSonLINK ADDO PSON MON3 DC_OK MON4 Vrer AC_OK OTP MON5 Fe Vs SHRS Description AC Bulk Sense Input 2 or Monitor 2 Input ACsense2 This alternative ACsense input can be used when the ACsense source must be different from that used for the OrFET It also allows dc and opto coupled signals that are not suitable for the OrFET control MON2 When MON2 is selected for this pin its input is compared against a 1 25 V comparator
45. DM1041 1i PATE E ADM1041 are needed to maintain a stable output To maintain a stable loop the ADM1041 uses three main inputs Remote voltage sense e Load current sense e Current sharing information In this example a resistor divider senses the output current as a voltage drop across a sense resistor RS and feeds a portion into the ADM1041 Remote local voltage sense is monitored via Vs and Vs pins Finally current sharing information is fed back via the share bus These three elements are summed together to generate a control signal which closes the loop via an optocoupler to the primary side PWM controller Another key feature of the ADM1041 is its control of an OrFET The OrFET causes lower power dissipation across the ORing diode The main function of the OrFET is to disconnect the power supply from the load in the event of a fault occurring during steady state operation for example if a filter capacitor or rectifier fails and causes a short This eliminates the risk of bringing down the load voltage that is supplied by the redun dant configuration of other power supplies In the case of a short a reverse voltage is generated across the OrFET This reverse voltage is detected by the ADM1041 and the OrFET is shut down via the Fc pin This intervention prevents any interruption on the power supply bus The ADM1041 can then be interrogated via the
46. EEPROM SLAVE ADDRESS ADDRESS DATA ADDRESS HIGH BYTE LOW BYTE 80h OR 81h 00h TO FFh Figure 33 Single Byte Write to EEPROM 04521 0 024 If it is required to read data from the ASIC immediately after setting up the address the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read block read or block write operation without asserting an intermediate stop condition Block Write In this operation the master device writes a block of data to a slave device Programming an EEPROM byte takes approximately 300 us which limits the SMBus clock for repeated or block write operations The start address for a block write must have been set previously In the case of the ADM1041 this is done by a send byte operation to set a RAM address or by a write byte word operation to set an EEPROM address 1 master device asserts a start condition on SDA 2 The master sends the 7 bit slave address followed by the write bit low 3 The addressed slave device asserts on SDA 4 The master sends a command code that tells the slave device to expect a block write The ADM1041 command code for a block read is AOh 10100000 5 slave asserts on SDA Rev A Page 37 of 64 ADM1041 6 The master sends a data byte that tells the slave device how many data bytes will be sent The SMBus specification allows a maximum of 32 data bytes to be sent in a bloc
47. MO3HVHS TIVLLN3H3HIIG 508 3HVHS MalaridWv 338VHS 0 1noi AYVHS 135550 4 J3HVHS 1 dHHA MaldrdWv HHVHS OL 7 0 0 2570 9 3 1 start Figure 14 Current Share Circuit and Soft o m a lt gt dzsc WWW ADM1041 0 20 40 60 80 100 04521 0 010 lout Figure 15 Load Share Characteristic Rev A Page 26 of 64 www dzsc PULSE ACsense2 When configured PULSE and ACsensz monitor the output of the power main transformer See Figure 16 PULSE Providing the output of the pulse function PULSE_OK is high the FET in the ORing circuit can be turned on If the pulses stop for any reason about 1 second later the PULSE_OK goes low and the OrFET drive is disabled This delay allows passage of all expected pulse skipping modes that might occur in no load or very light load situations See Figure 16 ACsense This is rarely used to measure directly the ac input to the supply ACsensel or 2 are usually used to indirectly measure the voltage across the bulk capacitor so that the system can be signaled that power is normal Also if power is actually lost ACsensz represents when just enough energy is left for an orderly shutdown of the power supply See Figure 16 ADM1041 The ac sense function m
48. Name R W Description 7 0 load_v R W This register contains the set load voltage trim settings Table 35 Register 1Ah Sel CBD SMBAlert1 Power On Default From EEPROM Register 811Ah during Power Up BitNo Name R W Description 7 selcbd1 7 R W ovfault 6 selcbd1 6 R W uvfault 5 selcbd1 5 R W ocpto ridethrough timed out ocpf flag 4 selcbd1 4 R W acsnsb inverted 3 selcbd1 3 R W ocpf 2 selcbd1 lt 2 gt otp MONS OV 1 selcbd1 1 R W orfetokb inverted 0 Selcbd1 R W Share_OKb inverted HE www dzsc Rev A Page 49 of 64 ADM1041 Table 36 Register 1Bh Sel CBD SMBAlert2 Power On Default from EEPROM Register 811Bh during Power Up BitNo Name R W Description 7 selcbd2 lt 7 gt R W b inverted 6 selcbd2 6 R W mfg1 5 selcbd2 5 R W mfg2 4 selcbd2 4 R W mfg3 3 selcbd2 3 R W mfg4 2 selcbd2 lt 2 gt R W m_cbd_w Microprocessor Control of CBD 1 selcbd2 lt 1 gt R W mfg5 0 selcbd2 0 R W Not used Table 37 Register 1Ch Manufacturer s ID Power On Default 41h BitNo Name R W Description 7 0 Manufacturer s ID R This register contains the manufacturer s ID code for the device It is used by the manufacturer Code for test purposes and should not be read from or written to in normal operation Table 38 Register 1Dh Revision Register Power On Default 01h
49. On Threshold Vcs 2 for threshold specs 20 mV Reg 03h 5 4 00 See Table 12 30 mV Reg 03h 5 4 01 See Table 12 40 mV Reg 03h 5 4 10 See Table 12 50 Reg 03h 5 4 11 See Table 12 FD Input Impedance 500 kQ FS Input Impedance 20 kQ ACsense1 ACsense2 COMPARATOR Reg 12h 2 0 ODh 3 2 00 See Table 22 AC or Bulk Sense Reg 12h 2 1 Reg OEh 7 6 00 See Table 23 Threshold Voltage 1 25 V Threshold Adjust Range 1 10 1 40 V Min DAC 0 Max DAC Full Scale Threshold Trim Step 0 8 96 1 10 lt lt 1 4 V 10 mV 5 bits 31 steps Reg OCh 7 3 See Table 21 Hysteresis Adjust Range 200 550 mV Vacsense gt 1 V 909R Hysteresis Trim Step 50 mV 200 lt lt 550 mV 7 steps Reg OCh 2 0 See Table 21 Noise Filter 0 6 1 1 2 ms PULSE IN Threshold Voltage 0 525 V PULSE OK On Delay 1 us PULSE_OK Off Delay 0 8 1 1 2 5 5 5 5 Unless otherwise specified OCP Threshold Voltage 0 3 0 5 0 7 V Force for drop in Reg 11h 2 0 See Table 26 OCP Shutdown Delay Time Continuous 1 5 Reg 12h 4 3 00 See Table 27 Period in Current Limit 2 5 Reg 12h 4 3 01 See Table 27 3 5 Reg 12h 4 3 10 See Table 27 4 5 Reg 12h 4 3 11 See Table 27 OCP Fast Shutdown Delay Time 0 100 ms Reg 11h 2 1 See Table 26 VCaye 1 5 MON1 MON2 MON3 MON4 Sense Voltage 1 21 1 25 1 29 V Hysteresis 0 1 V OVP Noise Filter 5 25 us UVP Noise Filter
50. The AC OK function advises the system whether or not sufficient bulk voltage is present to allow reliable operation The system may choose to shut down if this pin is false The power supply normally tries to maintain normal operation as long as possible although DC OK goes false when only millisecond or so of operation time is left This pin is an open drain output It can be configured as a P channel pull up or an N channel pull down It may also be configured as positive or negative inverted logic The OK output is kept false for typically 100 ms to 900 ms during power up When the system is to be shut down in response to PSON going low or in response to an OCP or OTP event a signal is first sent to the DC OK output to go false as a warning that power is about to be lost PEN is signaled false typically 2 ms later configurable All of the inputs to the logic core are first debounced or digitally filtered to improve noise immunity The debounce period for OV events is the order of 16 us for UV events it is 450 us and for PSON it is typically 80 ms configurable A voltage from the secondary of the power transformer which can provide an analog of the bulk supply is rectified and lightly filtered and measured by the ac sense function At start up if this voltage is adequate this function signals the end user system that it is okay to start If a brown out occurs or ac power is removed this function can provide early warning
51. UM FT_CHKSUM QUAL_PART_ID Probe 1 cell current data integer Probe 1 cell current data two decimal places Probe 2 cell current data integer Probe 2 cell current data two decimal places Final test cell current data integer Final test cell current data two decimal places Probe X coordinate Probe Y coordinate Wafer number 1g E www dzsc Rev A Page 51 of 64 ADM1041 MICROPROCESSOR SUPPORT Table 43 Mnemonic Description Register Bit Read Write m_pson_r Allows the microprocessor to read the state of PSON This allows only one 02h 6 Read only ADM1041 to be configured as the PSON interface to the host system m_pson_w Allow the microprocessor to write to control the PSON function of each ASIC 12h 1 Write only When in microprocessor support mode the principle configuration for controlling power on power off will be as follows One ADM1041 would be configured to be the interface to the host system through the standard PSON pin This pin would be configured not to write through to the PSON debounce block The microprocessor would poll the status of this ADM1041 by reading m_pson_r Debouncing would be done by the microprocessor If m_pson_r changed state the microprocessor would write the new state to m_pson_w in all ADM1041s on the SMBus If a fault were to occur on any output the SMBAlert interrupt would request microprocessor attention If this means turning all ADM1041s off this wou
52. V 0 0 1 ve uv iopin gt 1 35 V 1 0 0 ve ov iopin 1 25 V 0 1 0 ve ov gt 1 35 V 1 0 0 1 0 1 ve uv lt 1 15 V 0 0 0 ve uv gt 1 25 V 1 0 1 1 1 0 flag iopin 1 15 V 0 0 0 flag iopin 1 25 V 1 0 0 1 1 1 flag iopin 1 15 V 1 0 0 flag iopin 1 25 V Option ACsense2 MON 7 5 mn2s2 b7 b6 b5 flag uv mn2s1 0 0 0 iopin ACsense2 mn2s0 0 0 1 iopin ACsense2 0 1 0 ve ov lt 1 15 0 0 0 ve ov gt 1 25 1 1 0 0 1 1 ve uv iopin 1 25 V 0 0 1 ve uv iopin gt 1 35 V 1 0 0 1 0 0 ve ov iopin 1 25 V 0 1 0 ve gt 1 35 V 1 0 0 1 0 1 uv iopin 1 15 0 0 0 ve uv iopin 1 25 V 1 0 1 1 1 0 flag iopin 1 15 V 0 0 0 flag iopin 1 25V 1 0 0 1 1 1 flag iopin 1 15V 1 0 0 flag iopin 1 25 V 0 0 0 Option PSON MON3 4 2 mn3s2 b4 b3 b2 flag uv mn3s1 0 0 0 iopin PSON on low mn3s0 0 0 1 PSON high 0 1 0 ov lt 1 15 0 0 0 ve ov iopin gt 1 25 V 1 1 0 0 1 1 ve uv iopin 1 25 V 0 0 1 ve uv iopin gt 1 35 V 1 0 0 1 0 0 ve ov iopin 1 25 V 0 1 0 ve ov gt 1 35 V 1 0 0 1 0 1 ve uv lt 1 15 V 0 0 0 ve uv iopin 1 25 V 1 0 1 1 1 0 flag iopin 1 15 V 0 0 0 flag iopin 1 25 V 1 0 0 1 1 1 flag iopin 1 15 V 1 0 0 flag iopin 1 25 V 0 0 0 Option DC_OK MON4 7 5 mn4s2 b7 b6 b5 flag uv mn4s1 0 0 0 iopin DC_OK mn4sO 0 0 1 iopin DC OK Rev A Page 57 of 64
53. Vrer does not come up until Vpp exceeds the upper UVL threshold Housekeeping functions in this block include reference voltage monitors overvoltage and ground fault detector The ground fault detector monitors ADM1041 ground with respect to the remote sense pin Vs If GND becomes positive Veer 18 GROUND MONITOR gndok_dis REFERENCE AUXILIARY ADM1041 with respect to Vs an on chip signal VopOK goes false is true only when all the following conditions are met ground is negative with respect to Vs INTREF and EXTREF are operating normally Vo gt UVLHL and lt Vp OVP threshold GAIN TRIMMING AND CONFIGURATION The various gain settings and configurations throughout the ADMI041 are digitally set up via the SMBus after it has been loaded onto its printed circuit board There is no need for external trim potentiometers An initial adjustment process should be carried out in a test system Other adjustments such as current sense and voltage calibration should be carried out in the completed power supply INTERNAL REFERENCE 2 5 EXTREFOK INTREFOK 04521 0 006 Figure 8 Block Diagram of Power Management Section 1g E www dzsc Rev A Page 19 of 64 ADM1041 DIFFERENTIAL REMOTE SENSE AMPLIFIER This amplifier senses the load voltage and is the main voltage feedback input A differential input is used to compensate for the voltage dro
54. age Protection 20 Local UnderVoltage Protection UVP 20 False UV 20 Voltage Error Amplifier 21 Main Voltage Reference 21 Current Sense Amplifier serene 21 Current Sensing iati eint e Ie EIER 22 Current Transformer Input eere 22 Current Sense Calibration sse 22 Current Limit Error 22 Overcurrent Protection ect tee e PH eed 22 Current Share 24 Current Share Offset 24 Drive Amplifier rennene 24 Differential Sense Amplifier 24 Error Amplifiers 24 Isis 24 Share ok Detector 24 Pulse A cierre o DHT ERN HE e epe 27 E wWwW dzsc Jj E 27 27 OFEET Gate Drive 28 Oscillator and Timing Generators 30 Logic and Monitor 30 SMBus Serial 33 Microprocessor Support eese 33 D 34 SMBus Serial Interface serene 34 General SMBus Timing
55. ange 1 2 3 4 Mode Soft start gated by pen only Soft start gated by acsnsok and pen Rise time 300 us 10 ms 20 ms 40 ms Mode PEN not gated PEN gated by acsnsok Period 100 us 200 us 300 us 400 us Threshold 100 mV 150 mV 200 mV 250 mV Threshold 20 mV 30mV 40 mV 50 mV Threshold voltage 5 100 mV 10 200 mV 15 300 mV 20 400 mV Mode OV UV OC faults latch Auto restarts after OCP or undervoltage FET option Polarity N N ee www dzsc Rev A Page 59 of 64 ADM1041 Description Set CBD Output Polarity Set OrFET Gate Drive Polarity This is an open drain N FET Set DC_OK Output Polarity Also selects open drain N channel or P channel Set Clamp Release threshold Percent of nominal output voltage Configure Soft OTP Option Select CBD Latch Mode Set AC_OK Output Polarity Also selects open drain N channel or P channel Lock EEPROM Contents Eliminate offset correction Shorts 2 x 50 mV sources in current share circuit Disable groundOK monitor An open circuit GND pin does not affect VppOK Bit No 7 0 Name polcbdo polcbd1 polfg mn4sO polDC OK clamp softotp cbdim mn5s0 polAC_OK eeprom_locks lock7 lock6 lock5 lock4 lock3 lock2 lock1 lockO selects_gnd_ offset gndok_dis Bit Bit Bit 0 b4 b2 O O o
56. ansformer Input Section Source Current Step Size 170 nA 15 steps Reg 15h 3 0 See Table 30 Reverse Current for Extended SMBus 3 5 5 7 mA See Figure 38 See Absolute Addressing Source Current Maximum Ratings Rev A Page 8 of 64 www dzsc ADM1041 Parameter Min Typ Max Unit Test Conditions Comments CURRENT LIMIT ERROR AMPLIFIER See Figure 13 Current Limit Trim Range 105 130 After calibration Current Limit Trim Step 1 1 Current Limit Trim Step 26 5 mV 2 0 lt lt 2 8 V typ 5 bits 31 steps Reg 04h 7 3 See Table 13 Transconductance 100 200 300 20 See Figure 12 Output Source Current 40 gt 1 Output Sink Current 40 lt 1 V CURRENT SHARE DRIVER See Figure 14 Output Voltage Voo 0 4 V Ri 1 Voo 2 V Short Circuit Source Current 55 mA Source Current 15 mA Current at which Vour does not drop by more than 596 Sink Current 60 100 Vsare 2 0 V CURRENT SHARE DIFFERENTIAL SENSE See Figure 14 AMPLIFIER Vs Input Voltage 0 5 V Voltage on Pin 20 Vsues Input Voltage Vo 2 V Voltage on Pin 23 Input Impedance 65 100 kQ Vsugs 0 5 V Vs 0 5 V Gain 1 0 V V CURRENT SHARE ERROR AMPLIFIER Transconductance SHRS to SCMP 100 200 300 20 Output Source Current 40 pA gt 1 V Output Sink Current 40 Vscme lt
57. bles OCP shutdown OCP Ride Through Sets the OCP timer duration before OCP shutdown occurs Bit No 2 0 2 0 Name trim_lock csense_mode chopper os_dc_range os_div_range diff_gain ct_range curr_lim_dis ocpts1 Reg12h ocptsO Reg12h ocpts2 Bit Bit Bit bo 0 1 b7 0 1 b6 0 1 b5 b4 b3 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 b5 b4 b3 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 i i 0 0 x x Option Mode Trimming mode All trim registers locked out Mode Differential sense CT Sense Mode Differential current sense amplifier is continuous recomended Differential sense amplifier is chopper Trim 8 mV 15V 30V 8 mV 15 mV 30 mV Trim 5 mV 10 mV 20 mV 5 mV 10 mV 20 mV Gain Range 65 85 110 135 175 230 Gain 4 5 2 57 Mode 34 0 44 5 mV 26 0 mV 34 0 mV 20 0 mV 26 mV 16 0 mV 20 0 mV 12 0 mV 16 0 mV 9 8 mV 12 0 mV Range 0 45 V 0 68 V 0 79 V 1 20 V OCP timer starts when gt 0 5 V No OCP shutdown Period 1s 2s 3s 4s 100 ms www dzsc Rev A Page 56 of 64 ADM1041 Description Bit No Name Bit Bit Bit Option Option Pulse ACsense1 MON1 3 1 mn1s2 b3 b2 b1 flag uv mn1s1 0 0 0 iopin ACsense1 mnlsO 0 0 1 iopin ACsense1 0 1 0 ve ov lt 1 15 0 0 0 ve ov iopin gt 1 25 V 1 1 0 0 1 1 ve uv iopin 1 25
58. ccupies the address locations from 8000h to 813Fh The SMBus specification defines several protocols for different types of read and write operations The ones used in the ADM1041 are discussed in the next sections The following abbreviations are used in the diagrams S START P STOP R READ W WRITE A ACKNOWLEDGE A NO ACKNOWLEDGE The ADM1041 uses the following SMBus write protocols SMBus Erase EEPROM Page Operations EEPROM memory can be written to only if it is effectively unprogrammed Before writing to one or more locations that are already programmed the page containing those locations must be erased EEPROM ERASE is performed by sending a page erase command byte A2h followed by the page location of what you want to erase There is no need to set an erase bit in an EEPROM control status register The EEPROM consists of 16 pages of 32 bytes each the register default EEPROM consists of 1 page of 32 bytes starting at 8100h Table 7 EEPROM Page Layout Page EEPROM Location Description 1 8000h to 801Fh Available FRU 2 8020h to 803Fh Available FRU 3 8040h to 8050h Available FRU 4 8060h to 8070h Available FRU 5 8080h to 8090h Available FRU 6 80A0h to 80BFh Available FRU 7 80 to 80DFh Available FRU 8 80EOh to 80FFh Available FRU 9 8100h to 811Fh Configuration Boot Registers 10 8120h to 813Fh ADI Registers 11 8140h to 815Fh Available FRU 12 8160h to 817Fh Available FRU 13 8180h to 819Fh Avai
59. ce voltage ground fault or Voo overvoltage fault reverseok If this flag is low the OrFET has an excessive reverse voltage Oth 5 Read only orfetok If this flag is low either PULSE_OK penok loadvok or reverseok is false 01 6 Read only Share_OK If this flag is low the current share accuracy is out of limits 011 7 Read only fault Fault latch If this flag is high either an ovfault uvfault or ocp has occured 02h 0 Read only PULSE_OK Pulses are present at ACsense 1 02h 1 Read only www dzsc Rev A Page 52 of 64 ADM1041 Mnemonic ocpf m_DC_OK_r m_psonok_r m_penok_r m_pson_r m_acsns_r mfg5_L mfg4_L mfg3_L mfg2_L mfgl_L ocpto_L uvfault_L ovfault_L vddov_L extrefokb_L intrefokb_L gndokb_L VopOK b_L reverseokb_L orfetokb_L Share_OKb_L fault_L PULSE_OKb_L ocpf_L m_DC_OK_rb_L m_psonok_rb_L m_penok_rb_L m_pson_rb_L m_acsns_rb_L Description If this flag is high an overcurrent has been sensed and the ocp timer has started This flag indicates the status of the DC_OK pin This flag indicates the status of the PSonLINK pin This flag indicates the status of the PEN pin This flag indicates the status of the PSON pin This flag indicates the status of the ACsense1 ACsense2 pin Latched status of MONS flag Latched status of MON4 flag Latched status of MON3 flag Latched status of MON2 flag Latched status of MON1 flag Latched ocpto Latched uvfault Latched ov
60. d for the following three purposes The ADM1041 knows how to respond by the value of the command byte e Write a single byte of data to RAM In this case the command byte is the RAM address from 00h to 7Fh and the only data byte is the actual data This is illustrated in Figure 31 1 2 3 5 6 7 8 5 ADDRESS DATA 00h TO 7Fh Figure 31 Single Byte Write to RAM 04521 0 022 fg e wWwW dzsc ADM1041 e Setupa2 byte EEPROM address for a subsequent read or block read In this case the command byte is the high byte of the EEPROM address 80h The only data byte is the low byte of the EEPROM address This is illustrated in Figure 32 1 2 3 5 7 8 EEPROM EEPROM SLAVE ADDRESS ADDRESS ADDRESS HIGH BYTE LOW BYTE 80h OR 81h 00h TO FFh Figure 32 Setting an EEPROM Address 04521 0 023 If it is required to read data from the EEPROM immedi ately after setting up the address the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read or a block read without asserting an intermediate stop condition e Write a single byte of data to EEPROM In this case the command byte is the high byte of the EEPROM address 80h or 81h The first data byte is the low byte of the EEPROM address and the second data byte is the actual data Bit 1 of EEPROM Register 3 must be set This is illustrated in Figure 33 4 1 2 3 5 7 8 9 10 EEPROM
61. ditional offset due to the mismatch of the external divider resistors This offset trim is dynamically adjusted according to the common mode voltage present at the top of the voltage dividers Six ranges are selectable according to the magnitude and polarity of this offset component Because the offset compensation circuit itself has some inaccu racies the best overall current sense accuracy is obtained by using more closely matched external dividers and then selecting a low compensation range See Figure 14 Rev A Page 21 of 64 ADM1041 CURRENT SENSING Current is typically sensed by a low value resistor in series with the positive output of the power supply just before the OrFET or diode For high voltages 12 V and higher this resistor is usually placed in the negative load A pair of closely matched voltage dividers connected to Pins 2 and 3 divide the common mode voltage down to approximately 2 0 V The divider ratio must be the same as used in the local and remote voltage sense circuits Alternatively current may be sensed by a current transformer CT connected to Pin 8 The ADM1041 must be configured via the SMBus to select one or the other See Figure 13 CURRENT TRANSFORMER INPUT The ADM1041 can also be configured to sense current by using a current transformer CT connected to Pin 8 In this case the resistive current sense is disabled A separate single ended amplifier has two possible sensitivities that are select
62. e wWwW dzsc ADM1041 If more than one device is asserting an alert all alerting devices try to respond with their slave addresses but an arbitration process ensures that only the lowest slave address is received by the master If the slave device has its alert configured as latching it sends a command via the SMBus to clear the latch The master should then check if the alert line is still asserted and if so repeat the ARA call to service the next alert Note that an alerting slave does not respond to an ARA call unless it is configured in SMBus mode not OKLink PSoxLINK and pson m is set The ADM1041 supports the SMBus ARA function SUPPORT FOR SMBus 1 1 SMBus 1 1 optionally adds a CRC8 frame check sequence to check if transmissions are received correctly This is particularly useful for long block read write EEPROM operations when the SMBus is heavily loaded or in a noisy environment The CRC8 frame can be used to guarantee reliability of the EEPROM LAYOUT CONSIDERATIONS Noise coupling into the digital lines greater than 150 mV overshoot greater than Vcc and undershoot less than GND may prevent successful SMBus communication with the ADM1041 SMBus No Acknowledge is the most common symptom causing unnecessary traffic on the bus Although the SMBus maximum frequency of communication is rather low 400 kHz max care still needs to be taken to ensure proper termination within a system with multiple parts o
63. e SMBus Or the PSonLINK signal may be used When the PSON pin is not used as such it can be configured as an analog input MON3 MON3 This is the alternative analog comparator function for the PSON pin Pin 16 The threshold is 1 25 V When MONS is selected PS ON defaults to off DC_OK PW OK PWR Good Etc This output is true when all dc output voltages are within toler ance and goes false to signify an imminent loss of power Timing is discussed later It can be configured as an open drain N channel or P channel MOSFET and as positive or negative inverted logic A pull up or pull down resistor is required This pin may be wire ORed with the same pin on other ADM1041 ASICs in the power supply When the DC_OK pin is not used as such it can be configured as an analog input MON4 MON4 This is the alternative analog comparator function for the DC_OK pin Pin 17 The threshold is 1 25 V Vrer This pin normally provides a precision 2 5 V voltage reference Alternatively it can be configured as the AC_OK output or as an analog input MONS A load capacitance of 1 nF typ is recommended on Vu Rev A Page 30 of 64 ADM1041 AC_OK This output is true when either ACsensel or ACsense2 is true configurable It can be configured as an open drain N channel or P channel MOSFET and as positive or negative inverted logic A pull up or pull down resistor is required This pin can be wire ORed with the same pin on
64. e amplifier requires only the output pin for loop compensation which typically consists of a series RC network to common trimmable reference provides a wide range of adjustment for the current limit When the current signal reaches the reference voltage the output of the error amplifier comes out of saturation and begins to drive a controlled current source The control threshold is nominally 1 0 V This current flows through a resistor in series with the trimmed voltage loop signal and thereby attempts to increase the voltage signal above the 1 5 V reference for that loop The closed voltage loop reacts by reducing the power supply s output voltage and this results in constant current operation See Figure 13 OVERCURRENT PROTECTION When the current limit threshold is reached the OCP comparator detects when the current error amplifier comes out of saturation Its threshold is nominally 0 5 V This starts a timer that when it times out causes an OCP condition to occur and the power supply to shut down If the current limit disappears before the time has expired the timer is reset The time period is configurable via the SMBus Undervoltage blanking is applied during the timer operation See Figure 14 Rev A Page 22 of 64 ADM1041 860 0 12890 ASO a anog M3WHOJSNVHL 1N3HH02 NIV9 13S AA T3A31 AT AN 1 135 8
65. ed via the SMBus If the CT option is selected the gain of the 1 0 2 1 buffer that follows the gain trim stage is no longer configurable and is fixed at 1 0 The share driver amplifier has a total of 100 mV positive offset built into it In order to use the ADM1041 in CT mode it is necessary to compensate for this additional 100 mV offset This is achieved by adding in a positive offset on the CT input This also allows any negative amplifier offsets in the CT chain to be nulled out This offset cancellation is achieved by sourcing a current through a resistance on the ICT pin The resistor value is 40 and so for 100 mV of offset cancellation a current of 2 5 uA is required It is possible to fine trim this current via Register 15h Bits 4 0 step size 170 nA For example 2 5 uA 15 170 nA so the code for Register 15h is decimal 15 or OFh Refer to the Current Transformer parameter in the Specifications table for more details See Figure 13 1 wWwW dzsc CURRENT SENSE CALIBRATION Regardless of which means is used to sense the current the end result of the calibration process should produce the standard current share signal between Pins 20 and 23 that is 2 0 V at 10096 load excluding any additional share signal offset that might be configured CURRENT LIMIT ERROR AMPLIFIER This is a low gain transconductance amplifier that takes its input from one of the calibrated current stages described previously Th
66. eme micro GND CONTROLLER 5 ISOLATION BARRIER 8 Figure 1 Typical Application Circuit Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use RR Rm die notice No license is granted by implication One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A itent rights of Analog Devices Trademarks and Tel 781 329 4700 www analog com rty of their respective owners Fax 781 326 8703 2004 Analog Devices Inc All rights reserved HE www dzsc ADM1041 TABLE OF CONTENTS 6 Absolute Maximum 2 13 PES 13 Pin Configuration and Function 14 17 Theory of Operation 19 Power Management ecrit esee teniente trees 19 Gain Trimming and Configuration 19 Differential Remote Sense 20 Set Load Voltage i obiicit ierit ite EE 20 Load Overvoltage OV serene 20 Local Voltage Sense 20 Local OverVolt
67. ept inputs with common range from GND to Voo 2 V The output is rail to rail but the input is limited to GND to 2 V See Figure 6 7 These pins can be configured as open drain N channel or P channel except PSON and as normal or inverted logic polarity Refer to Table 45 8 A logic true or false is defined strictly according to the signal name Low and high refer to the pin or signal voltages Endurance is qualified to 100 000 cycles as per JEDEC std 22 method A117 and measured at 40 C 25 C and 85 C Typical endurance at 25 C is 250 000 cycles 10 Retention lifetime equivalent at junction temperature 55 C as std 22 method A117 Retention lifetime based an activation energy of 0 6 V Derates with junction temperature SCL La 5 SDA 04521 0 005 Figure 5 Serial Bus Timing Diagram VA Vpp 04V R1 VB VB Vpp 2V R1 R1 R2 gt 1kQ 04521 0 004 Figure 6 Amplifier Inputs and Outputs Rev A Page 12 of 64 f s www dzsc ADM1041 ABSOLUTE MAXIMUM RATINGS Table 2 Thermal Characteristics Parameter Rating 24 Lead QSOP Package Supply Voltage Continuous 6 5V Qj 150 C W Data Pins SDA SCL Voo 0 5 V GND 0 3 V Stresses above those listed under Absolute Maximum Ratings Continuous Power at 25 C lt 4 450 mW may cause permanent damage to the device This is a stress Operating Temperat
68. equired an external amplifier is necessary The current share output from the supply which when bused with the share output of other power supplies working in parallel allows each of the supplies to contribute essentially equal currents to the load Table 4 Default Pin States during EEPROM Download State Pin No Mnemonic 11 CBD 12 PEN 17 DC_OK 18 AC_OK 19 Fe High impedance Hi Z at power up and until the end of the EEPROM download approximately 20 ms This pin is reconfigured at the end of the EEPROM download High impedance Hi Z at power up and until the end of the EEPROM download approximately 20 ms This pin is reconfigured at the end of the EEPROM download Active low low if DC_OK true at power up This pin is reconfigured during the EEPROM download Active low low if DC_OK true at power up This pin is reconfigured during the EEPROM download High impedance Hi Z at power up and until the end of the EEPROM download approximately 20 ms This pin is reconfigured at the end of the EEPROM download HE www dzsc Rev A Page 16 of 64 TERMINOLOGY Table 5 ADM1041 Mnemonic Description POR UVL CVMode CCMode UVP OVP OCP OTP UVB DC_OK AC_OK DC_OKondelay DC_OKoffdelay Debounce Digital Noise Filter ACsense1 Power On Reset When initially applied to the ASIC the POR function clears all latches and puts the logic i
69. eshold Adjust Range Threshold Trim Step Hysteresis Voltage Hysteresis Adjust Range Hysteresis Trim Step VsNSADJ_THRES VsNSADJ_RANGE VsNsADJ STEP VsNsHsT VsNSHYS_RANGE VsNsHYS_STEP Current Share Offset Range Vzo Zero Current Offset Trim Step VzosrEP CURRENT TRANSFORMER SENSE INPUT Gain Setting 0 Gcr Gain Setting 1 Gcr x2 CT Input Sensitivity Gain Set 0 Vcr CT Input Sensitivity Gain Set 1 Input Impedance cr Source Current Isounct Source Current Step Size lsree Reverse Current for Extended Irev SMBus Addressing CURRENT LIMIT ERROR AMPLIFIER Current Limit Trim Range Current Limit Trim Step Custer Current Limit Trim Step Custer Transconductance Gmccmp Output Source Current Isource_ccme Output Sink Current Isink_ccmP CURRENT SHARE DRIVER Output Voltage VsHRO_1k Short Circuit Source Current IsHRO_SHORT Source Current IsHRo_sOURCE Sink Current IsHRO_SINK CURRENT SHARE DIFFERENTIAL SENSE AMPLIFIER Vs Input Voltage Vsues Input Voltage Input Impedance Gsur_DIFF CURRENT SHARE ERROR AMPLIFIER Transconductance SHRS to SCM Gmscmp Output Source Current 5 Output Sink Current Isink_scme Input Offset Voltage ViN_SHR_OFF Share OK Window Comparator Vsun THRES Threshold Share Drive Error CURRENT LIMIT Current Limit Control Lower Threshold Current Limit Control Upper Threshold CURRENT SHARE CAPTURE
70. everseokb_L R reverse fault 4 VppOK b_L R vdd fault 3 gndokb_L R gnd fault 2 intrefokb_L R intref fault 1 extrefokb_L R extref fault 0 vddov_L R vddov Note that latched bits are clocked on a low to high transmission only Also note that these register bits are cleared when read via the SMBus except if the fault is still present It is recommended to read the register again after faults disappear to ensure reset Table 41 Register 2Ch Status3 Mirror Power On Default 00h These flags are cleared by a register read provided the fault no longer persists BitNo Name R W Description 7 m_acsns_rb_L R AC_OK fault 6 m_pson_rb_L R PSON fault 5 m_penok_rb_L R PEN fault 4 m_psonok_rb_L R PSonLINK fault 3 m_DC_OK_rb_L R DC_OK fault 2 ocpf R ocpf fault 1 PULSE_OKb_L R pulse fault 0 fault R fault latch Note that latched bits are clocked on a low to high transmission only Also note that these register bits are cleared when read via the SMBus except if the fault is still present It is recommended to read the register again after the faults disappear to ensure reset MANUFACTURING DATA Table 42 Register 81 PROBE1_BIN Register 81F1h PROBE2_BIN Register 81F2h FT_BIN Register 81F3h Register 81F4h Register 81F5h Register 81F6h Register 81F7h Register 81F8h Register 81F9h Register 81FAh Register 81FBh Register 81FCh Register 81FDh Register 81FEh Register 81FFh PROBE1_CHKSUM PROBE2_CHKS
71. fault Latched vddov fault Latched extref fault Latched intref fault Latched gnd fault Latched Vo fault Latched reverse voltage fault Latched orfet fault Latched share fault Latched fault Latched pulse fault Latched ocpf fault Latched DC OK fault Latched PSonLINKfault Latched PEN fault Latched PSON fault Latched ACsense fault Register 02h 02h 02h 02h 02h 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah 2Bh 2Bh 2Bh 2Bh 2Bh 2Bh 2Bh 2Bh 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch Bit Read Write Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only NaOnP WN HON KON DU KON Notes to Microprocessor uP support 1 Possible ways to turn the ADM1041 on or off in response to a system request or a fault include e Daisy chaining other ADM1041 PSON pins to the PEN pin which is controlled by PSON on one ADM1041 The microprocessor looks after the PSON system interface and any shutdowns due to faults Connect all AC_OKLink pins together and connect all PSonLINK pins together These pins must be configured appropriately 2 Flags appended with _L are latched Registers 2Ah 2Bh 2Ch The latch is reset
72. ffset Calibrate Current Sense Range Differential lsewse range 9 5 to 12 0 mV 16h 2 0 sense input six ranges configurable 120 to 16 0 mV 16 0 to 20 0 mV 20 0 to 26 0 mV 26 0 to 34 0 mV 34 0 to 44 5 mV Current Transformer Gain Range ct range 0 45 to 0 68 V 17h 5 0 79 to 1 2 V Calibrate Current Sense 2 0 V slope 127 8 mV at SHRO 06h 7 1 Current Share Offset Trim offset to be offset Oto 1 25 V at SHRO 255 5 5 mV 05h 7 0 added to output Current Limit Trim Current sense level curr limit 10596 13096 SHRO 31 26 mV at SHRO 04h 7 3 where current limiting will start 2 1 V 2 6 V OTP Sense Threshold otp trim at 2 1 V 2 5 V 15 27 OBh 7 4 input pins Set AC Sense Threshold acsns thresh 1 10 V 1 45 V 31 14 OCh 7 3 Set AC Sense Hysteresis acsns hyst 200 mV 550 mV 7 50 mV OCh 2 0 1g E www dzsc Rev A Page 54 of 64 APPENDIX A CONFIGURATION TABLE ADM1041 This table is included for users to program the part by function rather than by register Table 45 Description Bit No Name Bit Bit Bit Option Chip address is 1010xxx Second address bit Target EEPROM programmable 1 add1 b1 ADDO XXX device 0 L 000 0 0 001 1 0 2 100 4 First address bit ADDO L pin to ground 1 L 010 2 ADDO pin to 1 H 011 3 ADDO 7 pin open 1 Z 101 5 Broadcast address 111 ALL Config AC_OKLink and PSONLink 0 i2cmb
73. hare circuit and is called the capture range The capture range may be set via the SMBus to one of four values from 1 to 4 nominal See Figure 14 IsHare CLAMP This clamp keeps the current share loop compensation capacitor discharged when the current share is not required to operate The clamp is released during power up when the voltage refer ence and therefore the output voltage of the power supply has risen to either 75 or 88 of its final value This is configurable via the SMBus When the clamp is released the current share loop slowly walks in the current share and helps to avoid output voltage spikes during hot swapping See Figure 14 Share_OK DETECTOR Incorrect current sharing is a useful early indicator that there is some sort of non catastrophic problem with one of the power supplies in a parallel system Two comparators are used to detect an excessive positive or negative error voltage at the input of the Isuare error amplifier which indicates that the current share loop has lost control One of four possible error levels must be configured via the SMBus See Figure 14 Rev A Page 24 of 64 ADM1041 zul za NIVO diva 1 4 16 1405 ASVLIOA 3HVHS 1 3SN3S 39V IOA LN3H380D 73447 135 3SN3S 3A 31033 SA 58 5 HOHMN3 SHHS
74. he various key analog functions a number of pins are used for logic level I O signals If the logic function is not required the pins may be reconfigured as general purpose comparators for analog level monitoring MON and may be additionally configured to have typical OVP and UVP properties either positive going or negative going depending on whether a positive supply output or a negative supply output is being monitored When monitoring negative outputs a positive bias must be applied via a resistor to Vrer The status of all protection and monitoring comparators are held in registers that can be read by a microprocessor via the SMBus Certain control bits may be written to via the SMBus CBD ALERT This pin can be used either as a crowbar driver or as an SMBus alert signal to indicate that a fault has occurred It is typically configured to respond to a variety of status flags as detailed in Registers 1Ah and 1Bh The primary function of this pin is as a crowbar driver and as such it should be configured to respond to the OV fault status flag It can be configured to respond to any or all of a variety of fault status flags including a micro processor writable flag and can be configured as latching or nonlatching It may also be configured as an open drain N channel or P channel MOSFET and as positive or negative inverted logic A pull up or pull down resistor is required This pin may be wire ORed with the same pin on other ADM
75. igh Vin Output Voltage Low VoL Pull Up Current Leakage Current lPurLuP ADDO HARDWIRED ADDRESS ADDO Low Level ADDO Floating ADDO High Specification SERIAL BUS TIMING Clock Frequency Glitch Immunity Bus Free Time Start Setup Time Start Hold Time SCL Low Time SCL High Time SCL SDA Rise Time SCL SDA Fall Time Data Setup Time Data Hold Time Test Name tsw teur tsu sTa THIGH t tr tsu DaT www dzsc EEPROM RELIABILITY Endurance Data Retention Rev A Page 63 of 64 ADM1041 OUTLINE DIMENSIONS 0004 Po m Some 0 010 e 509 COPLANARITY TU PLANE 0006 0 016 0 004 COMPLIANT TO JEDEC STANDARDS MO 137AE Figure 39 24 Lead QSOP RQ 24 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADM1041ARQ 40 C to 85 C 24 Lead QSOP RQ 24 ADM1041ARQ REEL 40 C to 85 C 24 Lead QSOP RQ 24 ADM1041ARQ REEL7 40 C to 85 C 24 Lead QSOP RQ 24 Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components in an system provided that the system conforms to the Standard Specification as defined by Philips 2004 Analog Devices Inc Al
76. impedance is about 35 kO to ground www dzsc Rev A Page 15 of 64 ADM1041 Pin No Mnemonic 21 Vs 22 SCMP 23 SHRS 24 SHRO Description This pin is the positive remote load voltage sense input and is normally divided down from the power supply output voltage to 2 0 V at no load using an external voltage divider The input impedance is high Output of the Current Share Transconductance Error Amplifier Compensation is a series capacitor and resistor to ground While is normal and PEN is false this pin is clamped to ground When the converter is enabled PEN true and the clamp is released the compensation capacitor charges providing a slow walk in The error amplifier input has a built in bias so that all slaves in a parallel supply system do not compete with the master for control of the share bus Current Share Sense This is the noninverting input of a differential sense amplifier looking at the voltage on the share bus For testing purposes this pin is normally connected to SHRO Calibration always expects this pin to be at 2 0 V with respect to SHRS Vs If a higher share voltage is required a resistor divider from SHRO or an additional gain stage as shown in the application notes must be used Current Share Output This output is capable of driving the share bus of several power supplies between 0 V and Voo 0 4 V 10 bus pull down in each supply Where a higher share bus voltage is r
77. ise Time 0 0 300 us 0 1 10 ms 1 0 20 ms 1 1 40 ms add1 R W EEPROM programmable second address bit 0 trim lock RW When this bit is set the trim registers including this register are not writable via SMBus To make registers writable again the trim lock bit in the EEPROM must first be erased and the value downloaded using either power up or test download Table 26 Register 11h Config5 Power On Default from EEPROM Register 8111h 8110h during Power Up Bit No Name R W Description 7 curr_lim_dis R W Mask effect of OCP to general logic status flag still gets asserted when curr_lim_dis 1 6 polpenO R W Sets polarity of PEN output Refer to the Configuration table Table 45 5 polcbdo R W Sets polarity of CBD output Refer to the Configuration table Table 45 4 3 Reserved X Don t Care 2 ocpts2 R W Set this bit to 1 when 0 OCP ridethrough is required A small delay still exists Refer to Reg 12h and the Configuration table Table 45 gndok dis R W Disable gndok input to power management debounce logic 0 R W Select CBD latch mode 0 nonlatching 1 latching Table 27 Register 12h Config6 Power On Default from EEPROM Register 8112h 8110h during Power Up BitNo Name R W Description 7 rsm R W Restart Mode When rsm 1 the circuit attempts to restart the supply after an undervoltage or overcurrent at about 1 second intervals Latch Mode When rsm 0 UV and OC faults latch the o
78. ives data bytes 12 The master asserts ACK on SDA after each data byte 13 The slave does not acknowledge after the Nth data byte 14 The master asserts a stop condition on SDA to end the transaction 13 14 04521 0 027 Figure 36 Block Read from EEPROM or RAM fg e wWwW dzsc Rev A Page 38 of 64 Notes on SMBus Read Operations The SMBus interface of the ASIC cannot load the SMBUS if no power is applied to the ASIC This requirement allows a power supply to be disconnected from the ac supply while still installed in a power subsystem When using the SMBus interface a write always consists of the ADM1041 SMBus interface address byte followed by the internal address register byte and then the data byte There are two cases for a read e If the internal address register is known to be at the desired address simply read the ASIC with the SMBus interface address byte followed by the data byte read from the ASIC The internal address pointer increments if a block mode operation is in progress data values of 0 are returned if the register address limit of 7Fh is exceeded or if unused registers in the address range 00h to 7Fh are accessed If the address register is pointing at EEPROM memory that is 8000h and the address reaches its limit of 80FFh it does not roll over to Address 8100h on the next access Additional accesses do not increment the address pointer all reads return 00h and all writes com
79. k write 7 slave asserts on SDA 8 The master sends N data bytes 9 The slave asserts ACK on SDA after each data byte 10 The master asserts a stop condition on SDA to end the transaction SLAVE COMMAND Aoh BYTE ADDRESS i BLOCK WRITE COUNT m DATAS n DATAS DATAN Figure 34 Block Write to EEPROM or RAM When performing a block write to EEPROM the page that contains the location to be written should not be write protected Register 03h prior to sending the above SMBus packet Block writes are limited to within a 32 byte page boundary and cannot cross into the next page SMBus READ OPERATIONS The ADM1041 uses the following SMBus read protocols Receive Byte In this operation the master device receives a single byte from a slave device as follows 1 The master device asserts a start condition on SDA 2 The master sends the 7 bit slave address followed by the read bit high 3 addressed slave device asserts on SDA 4 The master receives a data byte 5 The master asserts NO ACK on SDA 6 The master asserts a stop condition on SDA and the transaction ends In the ADM1041 the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has been set previously by a send byte or write byte word operation This is illustrated in Figure 35 SLAVE Figure 35 Single Byte Read from EEPROM or RAM 04521 0 026 1 2 3 4 5
80. l rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www analo g com La DEVICES Rev A Page 64 of 64 HE www dzsc
81. lable FRU 14 81A0h to 81BFh Available FRU 15 81COh to 81DFh Available FRU 16 81EOh to 81FFh ADI Registers ww dzsc The EEPROM page address consists of the EEPROM address high Byte 80h for FRU or 81h for register default and the three MSBs of the low byte The lower five bits of the EEPROM address of the low byte are ignored during an erase operation 1 7 8 9 10 11 12 2 3 4 5 6 EEPROM EEPROM SLAVE COMMAND A2h ADDRESS ADDRESS ARBITRARY ADDRESS PAGE ERASE HIGH BYTE LOW BYTE DATA 80h OR 81h 00h TO FFh Figure 28 EEPROM Page Erase Operation 04521 0 019 Page erasure takes approximately 20 ms If the EEPROM is accessed before erasure is complete the SMBus responds with No Acknowledge Figure 29 shows the peak Ip supply current during an EEPORM page erase operation Decoupling capacitors of 10 uF and 100 nF are recommended Tek Stop 1 04521 0 020 Mi4 00ms Chi f 21 6 10 0 25 40 20 Figure 29 EEPROM Page Erase Peak Ipp Current SMBus Write Operations Send Byte In this operation the master device sends a single command byte to a slave device as follows 1 The master device asserts a start condition on SDA 2 The master sends the 7 bit slave address followed by the write bit low 3 addressed slave device asserts on SDA 4 The master sends a command code 5
82. ld be done by writing a zero to the m_pson_w bit m_acsns_r Allows the microprocessor to read the state of ACsense1 ACsense2 This allows one 02h 7 Read only ADM1041 to be configured as the interface to the host power supply m acsns w Allow the microprocessor to write to control the ACSOK function of each ADM1041 12h 5 Write only When in microprocessor support mode the principle configuration for controlling AC OK undervoltage blanking PEN gating and RAMP SS gating will be as follows One ADM1041 will be configured to be the interface with the host power supply AC monitoring circuitry This ADM1041 might be configured so that the acsns signal would be written through or would not be written through Regardless the microprocessor would monitor m acsns r and write to m acsns w as appropriate Since it is possible to sense but not to write through it is possible to configure a second ADM1041 to monitor a second ac or bulk voltage m_shr_clmp Allow the pP to write directly to m_shr_clmp to control when the ISHARE clamp is 13h 2 Write only released During a hot swap insertion there may be a need to delay the release of the ISHARE clamp This allows the designer an option over the default release at 7590 or 8896 of the reference ramp soft start m cbd w Allow the microprocessor to write directly to CBD as a possible way of adding an 1Bh 1 Write only additional output port This might be for blinking LEDs or as a FAIL signal to the system
83. n 110x Gain Setting 4 Reg 16h 2 0 100 135 V V 16 0 mV 20 0 mV Gain 135x Gain Setting 5 Reg 16h 2 0 101 175 VN 12 0 mV 16 0 mV Gain 175x Gain Setting 6 Reg 16h 2 0 110 230 V V 9 5 mV 12 0 mV Gain 230x Full Scale No Offset 2 0 V Vzo 0 Attenuation Range 65 to 99 96 Reg 06h 7 1 See Table 15 Current Share Trim Step at SHRO 0 4 96 SHRS SHRO 1 8 7 bits 127 steps Gain Accuracy 40 mV at Cs Cs 5 5 OV lt Vesem lt 0 3 V Gain 65x Vcscm Input Common Mode Gain Accuracy 20 mV at Cs Cs 5 1 5 2 0V 0 C lt Ta lt 85 C Gain 135x Gain Accuracy 40 mV at Cs Cs 2 5 0 5 42 5 96 Vcscu 2 0 V 0 C lt Ta lt 85 C Gain 65x SHARE BUS OFFSET See Figure 13 Current Share Offset Range 1 25 V Reg 17h 7 1 See Table 32 Reg 17h 5 1 See Table 32 Zero Current Offset Trim Step 0 lt lt 1 25 V 0 4 96 8 bits 255 steps Vcr 1 0 V 5 5 mV Reg 05h 7 0 See Table 14 CURRENT TRANSFORMER SENSE INPUT lcr Reg 17h 7 1 See Table 32 Reg 06h FEh See Table 15 Gain Setting 0 4 5 V V Reg 17h 5 0 2 V Table 31 Gain Setting 1 2 57 V V Reg 17h 5 1 See Table 32 Reg 15h 05h approx 1 pA See Table 30 2 V CT Input Sensitivity 0 45 0 5 0 68 V Gain setting 4 5 CT Input Sensitivity 0 79 1 0 1 20 V Gain setting 2 57 Input Impedance 20 50 kQ Source Current 2 0 pA See Current Tr
84. n a system two or more of them will have duplicate addresses See Figure 38 To overcome this problem the ICT pin has additional function ality Taking ICT below GND temporarily disables the SMBus function of the device Thus if the ICT pin of all devices in which ADD1 is to remain 0 are taken negative the ADDI bits of all other devices can be set to 1 via the SMBus Each device then has a unique address Internal diodes clamp the negative voltage to about 0 6 V and care should be taken to limit the current to less than approximately 5 mA on each ICT input to prevent the possibility of damage or latch up The suggested current is 3 mA One example of a suitable circuit is given in Figure 38 The ADM1041s can then be configured and trimmed If required AC OKLink and PSonLINK must be configured last If ICT is used for its intended purpose as a current transformer input care must be taken with the circuit design to allow the extended SMBus addressing to work BACKDOOR ACCESS After SCL and SDA have been configured as OKLink and PSonLINK it may be desired to recover the SMBus access to the ADM1041 Changes may be necessary to the internal configura tion or trim bits This is achieved by holding the SCL and SDA pins at 0 V ground while cycling SCL and SDA then revert to SMBus operation See Figure 38 HE www dzsc AC_OKLink PSoyLink DEVICE 5 ADD1 1 9 EXTENDED SMBus ADDRESSING ADD1
85. n hardware but this may be more expensive An alternative is to emulate the bus in software and to use two general purpose logic I O pins Only a simple subset of the SMBus protocol need be emulated because the ADM1041 always operates as a slave device Configuring for a Microprocessor Except during initial configuration all ADM1041 registers that need to be accessed are high speed CMOS devices that do not involve EEPROM The Microprocessor Support table Table 43 details the various registers bits and flags that can be read and written to including explanations Note that for the microprocessor to gain control of the PSON and ACsensz functions the normal signal path in the ADM1041 must be configured to be broken A separate configuration bit is allocated to each signal The microprocessor can then write to the signal after the break as though the signal originated within the ADM1041 itself The original signals can still be read prior to the break Rev A Page 33 of 64 ADM1041 BROADCASTING In a power supply with multiple outputs it is recommended that all outputs rise together Because the SMBus is relatively slow simply writing sequentially to the PSON signal in each ADM1041 for instance causes a significant delay in the output rise of the last chip to be written The ADM1041 avoids this problem by allocating a common broadcast address that all chips can respond to To avoid data collisions this feature should be used o
86. n the bus and long printed circuit board traces 5 1 resistor can be added in series with the SDA and SCL lines to help filter noise and ringing Minimize noise coupling by keeping digital traces out of switching power supply areas and ensure that digital lines containing high speed data communications cross at right angles to the SDA and SCL lines POWER UP AUTO CONFIGURATION After power up or reset the ADM1041 automatically reads the content of a 32 byte block of EEPROM memory that starts at 8100h and transfers the contents into the appropriate trim level and control registers 00h to 1Bh In this way the ADM1041 can be preconfigured with the desired operating characteristics without the host system having to download the data over the SMBus This does not preclude the possibility of modifying the configuration during normal operation Figure 37 shows a block diagram of the EEPROM download at power up or power on reset RAM CONFIGURATION REGISTERS DIGITAL TRIM POTS DIGITAL TIMING CONTROL POWER UP 04521 0 028 Figure 37 EEPROM Download Rev A Page 39 of 64 ADM1041 EXTENDED SMBus ADDRESSING A potential problem exists when using more than three ADM1041s in a single power supply The first time the device is powered up Bit 1 of Configuration Register 1 ADD1 is 0 This means that only three device addresses are initially available defined by ADDO if there are more than three devices i
87. nd the response time of the pin to a reverse voltage event on the Fp pin is seen This simulates the rectifier or filter capacitor failure during steady state operation When the F voltage is below 1 9 V 2 V minus 100 mV threshold the Fc pin reacts As can be seen the response time is approx 330 nsecs This extremely fast turn off is vital in an n 1 power supply system configuration It ensures that the damaged power supply removes itself from the system quickly Figure 18 is the equivalent response time to turn on the OrFET As can be seen there is a delay of approxi mately 500 ns before the FG pin ramps down to turn on the OrFET and therefore allow the power supply to contribute to the system This propagation delay is due mainly to internal amplifier response limitations The circuit in Figure 21 is used to generate these plots In this case the resistor to VDD from the FG pin is 2 Figure 19 and Figure 20 show the OrFET turn off time and turn on time when the pin polarity is inverted As can be seen to turn off the OrFET the Vre pin now transitions from high to low Also its corresponding turn on event occurs from a low to high transition The circuit in Figure 21 is used to generate these plots wwwW dzsc Rev A Page 28 of 64 Tek Prevu 1 TpELAv 218ns 112 5 1 007 ch2 2 00v 10068 Chi X 2 123 ii 22 00
88. nly for commands that do not initiate a reply SMBus SERIAL INTERFACE Control of the ADM1041 is carried out via the SMBus The ADM1041 is connected to this bus as a slave device under the control of a master device The ADM1041 has a 7 bit serial bus slave address When the device is powered up it does so with a default serial bus address The default power on SMBus address for the device is 1010XXX binary the three lowest address bits 2 to 0 being defined by the state of the address pin ADDO and Bit 1 of Configuration Register 4 ADD1 Because ADDO has three possible states tied to tied to GND or floating and Config4 lt 1 gt can be high or low there are a total of six possible addresses as shown in Table 6 GENERAL SMBus TIMING The SMBus specification defines specific conditions for different types of read and write operation General SMBus read and write operations are shown in the timing diagrams of Figure 25 Figure 26 and Figure 27 and described in the following sections The general SMBus protocol operates as follows 1 master initiates data transfer by establishing a start condition defined as a high to low transition on the serial data line SDA while the serial clock line SCL remains high This indicates that a data stream will follow All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits consisting of a 7 bit slave address MSB fir
89. nto a state that allows a clean start up Undervoltage Lockout This is used on to prevent spurious modes of operation that might occur if Von is below a specific voltage Constant Voltage Mode This is the normal mode of operation of the power supply main output The output voltage remains constant over the whole range of current specified Constant Current Mode This mode of operation occurs when the output is overloaded until or unless a shutdown event is triggered The output current control level remains constant down to 0 V Undervoltage Protection If the output being monitored is detected as going under voltage the UVP function sends a fault signal After a delay PEN goes false the output is disabled and either latch off or an auto restart occurs depending on the mode selected The DC OK output also goes false immediately to show that the output is out of tolerance Overvoltage Protection If the output being monitored is detected as going over voltage the OVP function latches and sends a fault signal PEN goes false and CBD goes true The DC OK output also goes false immediately OVP faults are always latching and require the cycling of PSON or Vop or SMBus command to reset the latch Overcurrent Protection If the output being monitored is detected as going over current for a certain time the OCP function sends out a fault signal that triggers a shutdown that can be latched or allowed to auto restart depending on the mode
90. one in a similar manner except that it does not track the common mode voltage Current Error Amplifier Compensation This pin is the output of the current limit transconductance error amplifier A series resistor and a capacitor to ground are required for loop compensation Voltage Error Amplifier Compensation This is the output of a voltage error transconductance amplifier Compensate with a series capacitor and resistor to ground An external emitter follower or buffer is typically used to drive an optocoupler Output voltage positioning may be obtained by placing a second resistor directly to ground Refer to Analog Devices applications notes on voltage positioning A divider from the OrFET drain is connected here A differential amplifier is then used to detect the presence of a reverse voltage across the FET which indicates a fault condition and causes the OrFET gate to be pulled low Ground This pin is double bonded for extra reliability If the ground pin goes positive with respect to the remote sense return Vs for a sustained period indicating that the negative remote sense line is disconnected PEN will be disabled Input for Current Transformer The sensitivity of this pin is suitable for the typical 0 5 V to 1 V signal that is normally available If this function is enabled the Cs amplifier is disabled This pin is also used for extended SMBus addressing i e pulled below ground to allow additional SMBus addresses Pulse Present
91. onitors the amplitude of the incoming pulse and if sufficiently high generates a flag to indicate ac or strictly speaking the voltage on the bulk capacitor is okay Since the envelope of the pulse has a considerable amount of 100 Hz ripple hysteresis is available on this input pin Internally there is a 20 A to 80 uA current sink With 909R external thevenin resistance this current range translates to a voltage hysteresis of 200 mV to 500 mV The internal hysteresis current is turned off when the voltage exceeds the reference on the comparator This form of hysteresis allows simple scaling to be implemented by changing the source impedance of the pulse conditioning circuit Some trimming of hysteresis and threshold voltage is provided The ac sense function can be configured to be derived from ACsense2 rather than ACsensel This allows a separate dc input from various locations to be used to generate AC_OK for better flexibility or accuracy TO OrFET SOURCE AE 0 525V V PULSE L ACsenset 5 3kQ SELECT 1 ACsense2 16 15 5 3kO TO CURRENT SENSE RESISTOR AND OrFET GATE b PULSEOK Q ES R TRIM HYSTERESIS 04521 0 035 Figure 16 Pulse In and AC Sense Circuit fg e wWwW dzsc Rev A Page 27 of 64 ADM1041 OrFET GATE DRIVE When configured this block provides a signal to turn on off an OrFET used in the output of paralleled power supplies The gate drive voltage
92. ounce Veer Overvoltage Veerout Undervoltage Vnouve Open Ground Vano Debounce POWER ON RESET DC Level DIFFERENTIAL LOAD VOLTAGE SENSE INPUT 5 Vs Vs Input Voltage Vovem Vs Input Voltage Vs Input Resistance Vovinen Vs Input Resistance Vovinre Adjustment Range Set Load Voltage Trim Step Vovrrim Minimum Set Load Overvoltage Trim Vovov Range Set Load Overvoltage Trim Step Recover from Load OV False to TLOADOV_FALSE External Divider Tolerance Trim Range with respect to input External Divider Tolerance Trim Step Size with respect to input DC Offset Trim Range os_dc_range with respect to input Specification Test Name Local Overvoltage Visov Nominal and Trim Range OV Trim Step VisovsrEP OV Trim Step VisovsrEP Noise Filter for OVP Function Only Tnrove Local Undervoltage Visuv Nominal and Trim Range UV Trim Step Visuvstep UV Trim Step Visuvstep Noise Filter for UVP Function Only Tneuve VOLTAGE ERROR AMPLIFIER Vem Reference Voltage Temperature Coefficient Long Term Voltage Stability Soft start Period Range TssRANGE Set Soft start Period Tss Unity Gain Bandwidth GBW Transconductance Source Current Isource_vcmP Sink Current DIFFERENTIAL CURRENT SENSE INPUT Cs Cs Common Mode Range RANGE Vos piv RANGE Vos piv 5
93. output in N 1 server power supplies The ADM1041 is manufactured with a 5 V CMOS process and combines digital and analog circuitry An internal EEPROM provides added flexibility in the trimming of timing and voltage and selection of various functions Programming is done via an SMBus serial port that also allows communication capability with a microprocessor or microcontroller The usual configuration using this IC is on a one per output basis Outputs from the IC can be wire ORed together or bused in parallel and read by a microprocessor A key feature on this IC is support for an OrFET circuit when higher efficiency or power density is required SAMPLE APPLICATION CIRCUIT DESCRIPTION Figure 1 shows a sample application circuit using the ADM1041 The primary side is not detailed and the focus is on the secon dary side of the power supply The ADM1041 controls the output voltage from the power supply to the designed programmed value This programmed value is determined during power supply design and is digitally adjusted via the serial interface Digital adjustment of the current sense and current limit is also calibrated via the serial interface as are all of the internal timing specifications The control loop consists of a number of elements notably the inputs to the loop and the output of the loop The ADM1041 takes the loop inputs and determines what if any adjustments PRIMARY DRIVER OPTO COUPLER EEPROM AND m A
94. p on the negative output cable of the power supply An external voltage divider should be designed to set the Vs pin to approximately 2 0 with respect to Vs The amplifier gain is 1 0 See Figure 9 SET LOAD VOLTAGE The load voltage may be trimmed via the SMBus by a trim stage at the output of the differential remote sense amplifier The voltage at the output of the trimmer is 1 50 V when the voltage loop is closed See Figure 9 LOAD OVERVOLTAGE OV A comparator at the output of the load voltage trim stage detects load overvoltage The load OV threshold can be trimmed via the SMBus The main purpose is to turn off the OrFET when the load voltage rises to an intermediate over voltage level that is below the local OVP level This circuit is not latching See Figure 9 LOCAL VOLTAGE SENSE This amplifier senses the output voltage of the power supply just before the OrFET Its input is derived from one of the pins used for current sensing and is set to 2 0 V by an external voltage divider The amplifier gain is 1 3 See Figure 9 REMOTE SENSE FROM LOAD SET LOAD VOLTAGE SET LOAD OVERVOLTAGE Vis 2 SET UV CLAMP THRESHOLD SET OVP THRESHOLD SET UVP THRESHOLD NOTE FALSE UV E CLAMP LOCAL OVERVOLTAGE PROTECTION OVP This is the main overvoltage detection for the power supply It is detected locally so that only the faulty power supply shuts down in the event of
95. plete normally but do not change any internal register or EEPROM location If the address register is pointing at EEPROM memory that is 81xxh and the address reaches its limit of 813Fh it does not roll over to Address 8140h on the next access Additional accesses do not increment the address pointer all reads return 00h and all writes complete normally but not change any internal register or EEPROM location Note that for byte reads the internal address does not auto increment e the internal address register value is unknown write to the ADM1041 with the SMBus interface address byte followed by the internal address register byte Then restart the serial communication with a read consisting of the SMBus interface address byte followed by the data byte read from the ADM1041 SMBus ALERT RESPONSE ADDRESS ARA The ADM1041 s CBD ALERT pin can be configured to respond to a variety of fault signals and can be used as an interrupt to a microprocessor The pins from several ADM1041s may be wire ORed When the SMBus master microprocessor detects an alert request it normally needs to read the alert status of each device to identify the source of the alert The SMBus ARA provides an easier method to locate the source of a such an alert When the master receives an alert it can send a general call address 0001100 over the bus The device assert ing the alert responds by returning its own slave address to the master fg
96. plifier is brought up slowly in approximately 127 steps to provide a controlled rate of rise of the output voltage An OVP fault on the auxiliary supply to the ASIC causes a standard OVP operation see the OVP function A UVL fault on the auxiliary supply to the IC causes a standard UVP operation see the UVP function In this mode the housekeeping circuit attempts to restart the supply after an undervoltage event at about 1 second intervals No other fault can initiate auto restart The internal precision reference is monitored by a separate reference for overvoltage and allows truly redundant OVP The externally available reference is also monitored for an undervoltage that would indicate a short on the pin The internal ASIC ground is constantly monitored against the remote sense negative pin If the chip ground goes positive with respect to this pin it indicates that the chip ground is open circuit either inside the ASIC or the external wiring The ASIC would be latched off similar to an OV event www dzsc Rev A Page 18 of 64 THEORY OF OPERATION POWER MANAGEMENT This block contains undervoltage lockout circuitry and a power on reset function It also provides precision references for internal use and a buffered reference voltage Vrer If Vrer is configured to an output pin overloading shorting to ground or shorting to do not effect the internal references See Figure 8 During power on
97. programmed to provide the PSON status to other ICs This allows just IC to be the PSON interface to the host system or the PSonLINK itself can be the PSON interface Chip Address Pin There are three addresses possible using this pin which are achieved by tying ADDO to ground tying to or being left to float One address bit is available via programming at the device daughter card level so the total number of addressable ICs can be increased to six PSON In non microprocessor configurations this is power supply on As a standard I O this pin is rugged enough for direct interface with a customer s system Either polarity may be selected MON3 When MON3 is selected for this pin its input is compared against a 1 25 V comparator that could be used for monitoring a post regulated output includes overvoltage undervoltage and overtemperature conditions DC_OK This pin is the output of a general purpose digital I O that can be configured as open drain N channel or open drain P channel suitable for wire ORing with other ICs and direct interfacing with a customer s system Either polarity may be selected MON4 When is selected for this pin its input is compared against a 1 25 V comparator that could be used for overtemperature protection and for monitoring a post regulated output includes overvoltage undervoltage and overtemperature conditions Voltage Reference Buffered Output Overtemperature Protection or Monitor
98. r External Divider Tolerance Trim Range 5 mV Reg 16h 5 3 000 See Table 31 with respect to input 10 mV Reg 16h 5 3 001 See Table 31 20 mV Reg 16h 5 3 010 See Table 31 5 mV Reg 16h 5 3 100 See Table 31 10 mV Reg 16h 5 3 101 See Table 31 20 mV Reg 16h 5 3 110 See Table 31 External Divider Tolerance Trim Step Size 20 uV 2 0 V with respect to input 39 uV 8 bits 255 steps 78 uV Reg 14h 7 0 See Table 29 fg e www dzsc Rev A Page 7 of 64 ADM1041 Parameter Min Typ Max Unit Test Conditions Comments DC Offset Trim Range with respect to input 8 Reg 17h 2 0 000 See Table 32 15 mV Reg 17h 2 0 001 See Table 32 30 mV Reg 17h 2 0 010 See Table 32 8 mV Reg 17h 2 0 100 See Table 32 15 mV Reg 17h 2 0 101 See Table 32 30 mV Reg 17h 2 0 110 See Table 32 DC Offset Trim Step Size 30 uV Vem 2 0 V Voirr 0 V with respect to input 50 uV 8 bits 255 steps 120 uV Reg 15h 7 0 See Table 30 CURRENT SENSE CALIBRATION Total Current Sense Error 2 0V 0 C lt Ta lt 85 C SHRS Gain and Offset SHRO 2 V Gain 230x 3 Chopper ON 6 Chopper OFF Gain Range Isense Input voltage range at Cs Cs Gain Setting 1 Reg 16h 2 0 000 65 V V 34 0 mV 44 5 mV Gain 65x Gain Setting 2 Reg 16h 2 0 001 85 V V 26 0 mV 34 0 mV Gain 85x Gain Setting 3 Reg 16h 2 0 010 110 V V 20 0 mV 26 0 mV Gai
99. r 8115h XXh Factory Cal Values Trim 16h Current Sense Config 1 From EEPROM Register 8116h XXh Factory Cal Values 17h Current Sense Config 2 From EEPROM Register 8117h XXh Factory Cal Values 18h UV Clamp Trim From EEPROM Register 8118h 00h 19h Diff Sense Trim From EEPROM Register 8119h 00h 1Ah Sel CBD SMBAlert1 From EEPROM Register 811Ah 00h 1Bh Sel CBD SMBAlert2 From EEPROM Register 811Bh 00h 1Ch Manufacturer s ID 41h Hardwired by manufacturer 1Dh Revision Register Xh Hardwired by Manufacturer 20h 29h Reserved for Manufacturer 2Ah Status1 Mirror Latched XXh Depends on status of 1041 at power up 2Bh Status2 Mirror Latched XXh Depends on status of ADM1041 at power up 2Ch Status3 Mirror Latched XXh Depends on status of ADM1041 at power up 2Dh 2Eh Reserved for Manufacturer 8000h 81FFh EEPROM fg e www dzsc Rev A Page 41 of 64 ADM1041 DETAILED REGISTER DESCRIPTIONS Table 9 Register 00h Status1 Power On Default XXh Refer to the logic schematic Figure 24 BitNo Name R W Description 7 ovfault R Overvoltage fault has occurred 6 uvfault R Undervoltage fault has occurred 5 ocpto R Overcurrent has occured and timed out ocpf is in Status3 4 mfg1 R MONT flag 3 mfg2 R MON flag 2 mfg3 R MONS flag 1 mfg4 R MONA flag 0 mfg5 R MONS flag Table 10 Register 01h Status2 Power On Default XXh Refer to the
100. serial interface to determine why the power supply has shut down This application circuit also demonstrates how temperature can be monitored within a power supply A thermistor is connected between the Vp and 2 pins The thermistor s voltage varies with temperature The MON2 input can be programmed to trip a flag at a voltage corresponding to an overheating power supply The resulting action may be to turn on an additional cooling fan to help regulate the temperature within the power supply 1 1 uC OR STANDALONE 1 1 04521 0 002 Figure 2 Application Block Diagram www dzsc Rev A Page 3 of 64 ADM1041 3uVvHS 1 L 5 35 zul zu Ta NIVO awos 15308 oos 2 GHO SuHSI 5A 23 SUHS 12 oaauvHs dSN3s Ez sna auvHs MWalaridwv anya YS 5 dWos uoa 3 5 gt AOVLIOA OL 7OH1NOO 13440 a a A gt 40193130 SSH3AdH 7572 13410 100 alvo AOT AEN gounos 1nd 0 N 4 0 0 12890 3SN3S LNIYYNO 3 A M3WHOJSNVHL A 13A DESEE 135 HOMH3
101. st plus a R W bit which determines the direction of the data transfer that is whether data is written to or read from the slave device 0 write 1 read i www dzsc The peripheral whose address corresponds to the transmit ted address responds by pulling the data line low during the low period before the ninth clock pulse known as the Acknowledge bit and holding it low during the high period of this clock pulse All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it If the R W bit is 0 then the master writes to the slave device If the R W bit is a 1 the master reads from the slave device 2 Data is sent over the serial bus in sequences of nine clock pulses eight bits of data followed by an Acknowledge bit from the slave device Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low to high transition when the clock is high may be interpreted as a stop signal If the operation is a write operation the first data byte after the slave address is a command byte This tells the slave device what to expect next It may be an instruction such as telling the slave device to expect a block write or it may simply be a register address that tells the slave where subse quent data is to be written Because data can flow in only one direction as defined by the R W bi
102. t it is not possible to send a command to a slave device during a read operation Before doing a read opera tion it might be necessary to first do a write operation to tell the slave what sort of read operation to expect and or the address from which data is to be read 3 When all data bytes have been read or written stop conditions are established In write mode the master pulls the data line high during the tenth clock pulse to assert a stop condition In read mode the master device releases the SDA line during the low period before the ninth clock pulse but the slave device does not pull it low This is known as No Acknowledge The master then takes the data line low during the low period before the tenth clock pulse then high during the tenth clock pulse to assert a stop condition Note If it is required to perform several read or write operations in succession the master can send a repeat start condition instead of a stop condition to begin a new operation Rev A Page 34 of 64 SDATA AGN 5 4 2 1 START BY MASTER a 1 FRAME 1 ACK BY ADM1041 FRAME 2 SERIAL BUS ADDRESS BYTE 4 1 ADM1041 ADDRESS POINTER REGISTER BYTE 9 SCLK CONTINUED 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 sonra or X Ke STOP ADM1041 MASTER FRAME 3 DATA BYTE Figure
103. tNo Name R W Description 7 3 acsns thresh R W ACsense Threshold Trim Settings 2 0 acsns hyst R W ACsense Hysteresis Trim Settings Table 22 Register Config1 Power On Default from EEPROM Register 810Dh during Power Up BitNo Name R W Description 7 up_pson_m R W 0 internal PSON 1 support via SMBus Selects PSON from config6 lt 1 gt 2m pson w 6 reserved Don t Care 5 reserved X Don t Care 4 uvbm R W Undervoltage Blanking Mode uvbm 1 blanking hold period starts from recovery of AC OK uvbm 0 blanking hold period starts following SCL 0 while i2cm 1 3 1 mn1s2 mn1s1 R W b3 b2 bi option mfg1 ov uv mn1s0 0 0 0 ACSNS1 true high 0 0 1 iopin ACSNS1 true high 0 1 0 lt 1 15 V 0 0 0 iopin 1 25 V 1 1 0 0 1 1 ve uv iopin 1 25 V 0 0 1 iopin 1 35 V 1 0 0 1 0 0 ve ov iopin 1 25 V 0 1 0 iopin 1 35 V 1 0 0 1 0 1 ve uv iopin 1 15 V 0 0 0 iopin 1 25 V 1 0 1 1 1 0 flag lt 1 15 0 0 0 gt 1 25 1 0 0 1 1 1 flag lt 1 15 V 1 0 0 iopin gt 1 25 0 0 0 0 i2cmb R W 0 pins are configured as SDA SCL default 1 SCL pin is configured as AC_OKLink output SDA pin is configured as PSonLINK output ww dzsc Rev A Page 44 of 64 Table 23 Register OEh Config2 Power On Default from EEPROM Register 810Eh during Power Up ADM1041 BitNo Name R W Description 7 5 mn2s2 mn2s1 2
104. that power is about to be lost and allow the system to shut down in an orderly manner While ACsense is low UVB is enabled which means undervoltage protection is not initiated If ac power is so low that the converter cannot continue to operate other protection circuits on the primary side normally shut down the converter When an adequate voltage level is resumed a power up cycle is initiated www dzsc Rev A Page 17 of 64 ADM1041 Mnemonic Pulse OK AC Hysteresis ACsense2 Soft start Vop UVL AutoRestart Mode Vrer MON GND MON Description As well as providing ac sense the preceding connection to the transformer is used to gate the operation of the OrFET circuit If the output of the transformer is good and has no problems the OrFET circuit allows gate drive to the OrFET AC Sense Hysteresis Configurable voltage on the ac sense input allows the ac sense upper and lower threshold to be adjusted to suit different amounts of low frequency ripple present on the bulk capacitor An alternate form of ac sense can be accepted by the ASIC This may in the form of an opto coupled signal from the primary side where the actual level sensing might be done As with the above while ac is low and UVB is disabled AC_OK is false and DC_OK is true Any brownout protection that might be required on the primary is done on the primary side At start up the voltage reference to the voltage error am
105. ure 40 to 85 C rating only functional operation of the device at these or any Junction Temperature 150 C other conditions above those indicated in the operational Storage Temperature 60 C to 150 C section of this specification is not implied Exposure to absolute Lead Temperature 300 C maximum rating conditions for extended periods may affect Soldering 10 Seconds T device reliability ESD Protection on All Pins Vesp 2kV Thermal Resistance Junction to Air 150 C W Source Current 7mA This is the maximum current that can be sourced out from Pin 8 pin ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features WARNING lt proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions recommended to avoid performance ESD SENSITIVE DEVICE degradation or loss of functionality Rev Page 13 of 64 HE www dzsc ADM1041 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 3 Pin Function Descriptions 24 SHRO VisICs IFS 2 Cyt 22 5 Comp 4 Vs Vcwe Vg ISHRS Fo ADM1041 GND there Seale Veer AC_OKIOTP MONS
106. utput off Cycling PSON or removing the supply to the IC is then required to reset the latch and permit a restart 6 up AC OK m R W Configure microprocessor to control gate signal from acinok to acsok 0 standalone 1 microprocessor support mode 5 m acsns w W Microcessor control of acsok ACsense 4 3 ocpts1 ocptsO R W OCP Ridethrough Reg 11h 2 0 OCP Ridethrough Reg11h 2 1 b4 b3 Period b4 b3 Period 0 0 1 second 0 0 128 us 0 1 2 seconds 0 1 256 us 1 0 3 seconds 1 0 384 us 1 1 4 seconds 1 1 512 us 2 acss W AC Sense Mode 0 means AC_OK is derived from ACsense1 whereas 1 means AC_OK is derived from ACsense2 1 m_pson_w W Microprocessor control of pson 0 IsHare_clamp R W 0 75 Set current share clamp release threshold 1 88 Table 28 Register 13h Config7 Power On Default from EEPROM Register 8113h during Power Up Bit No Name R W Description 1g E www dzsc Rev A Page 47 of 64 ADM1041 BitNo Name R W Description 7 polpen1 R W Sets polarity of PEN output Refer to the Configuration table Table 45 6 polcbd1 R W Sets polarity of CBD output Refer to the Configuration table Table 45 5 polDC OK1 R W Sets polarity of DC OK output Refer to the Configuration table Table 45 4 polAC OK1 R W Sets polarity of AC OK output Refer to the Configuration table Table 45 3 polfg R W Sets polarity of OrFET gate control 0 inverted low on
107. ved X Don t Care 6 lock6 R W Locks 8140h 817Fh Available FRU 5 lock5 R W Locks 8120h 813Fh ADI cal registers Locked by manufacturer 4 lock4 R W Locks 8100h 811Fh ADM1041 Config Boot registers 3 lock3 R W Locks 80COh 80FFh Available FRU 2 lock2 R W Locks 8080h 80BFh Available FRU 1 lock1 R W Locks 8040h 807Fh Available FRU 0 lockO R W Locks 8000h 803Fh Available FRU Table 17 Register 08h Load OV Trim Power On Default from EEPROM Register 8108h during Power Up Bit No Name R W 7 0 load ov R W Description Load OV trim Table 18 Register 09h Local UVP Trim Power On Default from EEPROM Register 8109h during Power Up Bit No Name R W Description 7 0 local uvp R W Local UVP trim www dzsc Rev A Page 43 of 64 ADM1041 Table 19 Register OAh Local OVP Trim Power On Default from EEPROM Register 810Ah during Power Up BitNo Name Description 7 0 local_ovp R W Local OVP Trim Table 20 Register OBh OTP Trim Power On Default from EEPROM Register 810Bh during Power Up BitNo Name R W Description 7 4 otp_trim R W OTP Threshold 3 1 reserved Don t Care 0 softotp R W Configure Soft OTP Option 0 mon5 ov ov 1 mon5 ov softotp Table 21 Register 0Ch ACsense Trim Power On Default from EEPROM Register 810Ch during Power Up Bi
108. w it to operate with the aid of a microprocessor There are several reasons why a microprocessor might be used To provide unusual logic and or timing requirements particularly for fault conditions e drive or more LEDs including flashing according to the status of the power supply e replace other discrete circuits such as multiple OTP extra output monitoring fan speed control and failure detection and combine the status of these circuits with the status of the ADM1041s Tofree up some pins on the ADM1041s This could reduce the number of ASICs and therefore the cost interface to an external SMBus or for more detailed status reporting The SMBus port in the ADM1041 is not intended for this purpose e To allow EEPROM space in ADM1041 s or in the microprocessor to be used for FRU VPD data A simple or complex microprocessor can be used according to the amount of additional functionality required Note that the microprocessor is not intended to access or modify the EEPROM address space that is used for the configuration of the ADM1041 s Interfacing The microprocessor must access the ADM1041 s via their on board SMBus port Since this port is also used for configuration of the ADM1041 s the software must include a routine that avoids SMBus activity during the configuration process The simplest interface is for the microprocessor to have an SMBus port implemented i
109. wn fixed positive offset The share bus offset controlled current source must be trimmed via the SMBus to take out the resulting overall offset See Figure 14 www dzsc IsHare ERROR AMPLIFIER This is a low gain transconductance amplifier that measures the difference between the internal current share voltage and the signal voltage on the external share bus If two power supplies have almost identical current share signals a 50 mV voltage source on the inverting input helps arbitrate which power supply becomes the master and prevents hunting between master and slave roles The amplifier requires only the output pin for loop compensation which typically consists of a series RC network to common When the power supply is a slave the output of the error amplifier comes out of saturation and begins to drive a controlled current sink The control threshold is nominally 1 0 V This current flows from a resistor in series with the trimmed voltage loop signal and thereby attempts to decrease the voltage signal below the 1 5 V reference for that loop The closed voltage loop reacts by increasing the power supply s output voltage until current share is achieved The maximum current sink is limited so that the power supply voltage can be increased only a small amount which is usually limited to be within the customer s specified voltage regulation limit This small voltage increase also limits the control range of the current s
110. y Ripple Due to Autozero 5 mV Veer refreshed at 30 kHz POWER BLOCK PROTECTION Overvoltage 5 8 6 2 6 5 V Overvoltage Debounce 10 20 us Latching Vrer Overvoltage 2 9 V Internal Vaerour Undervoltage 2 1 V External Open Ground 0 1 0 2 0 35 V Vann positive with respect to Vs Debounce 100 200 Hs VooOK POWER ON RESET DC Level 1 5 22 2 75 V Voo rising DIFFERENTIAL LOAD VOLTAGE SENSE INPUT See Figure 6 Vnom Vs 5 Vs Vnom is typically 2 V Vs Input Voltage 0 5 V Voltage on Pin 20 Vs Input Voltage Vop 2 V Voltage on Pin 21 Vs Input Resistance 35 Vs Input Resistance 500 Adjustment Range 1 7 to 2 3 V Set Load Voltage Trim Step 0 10 to 0 14 96 1 7 V Vnom lt 2 3 V typ 1 74 3 18 mV 8 bits 255 steps Reg 19h 7 0 See Table 34 Set Load Overvoltage Trim Range 105 to 120 96 1 7 V lt Vnom 2 3 V min Set Load Overvoltage Trim Step 0 09 96 8 bits 255 step s 1 6 mV Reg 08h 7 0 See Table 17 Vst 2 24 V Recover from Load OV False to True 100 Hs Reg 03h 1 0 00 See Table 12 200 Us Reg 03h 1 0 01 See Table 12 300 Us Reg 03h 1 0 10 See Table 12 400 Us Reg 03h 1 0 11 See Table 12 Operate Time from Load OV to False 2 us 1g E www dzsc Rev A Page 6 of 64 ADM1041 Parameter Min Typ Max Unit Test Conditions Comments LOCAL VOLTAGE SENSE Vis See Figure 9 AND FALSE UV CLAMP Input Voltage Range 2 3 2 V

ANALOG DEVICES ADM1041 handbook

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