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ANALOG DEVICES ADG431/ADG432/ADG433 handbook

1. 900 mW Analog Digital Inputs CAUTION Oja Thermal Impedance Lead Temperature Soldering 10 sec 300 C Plastic Package Power Dissipation 470 mW Oja Thermal Impedance 44 117 C W Lead Temperature Soldering 10 sec 260 C SOIC Package Power Dissipation 600 mW Oja Thermal Impedance sess 77 C W Lead Temperature Soldering Vapor Phase 60 sec 2 ce eee eee eee 215 C Infrared 15 sec uere TRI EE X 220 C NOTES IStresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Only one absolute maximum rating may be applied at any one time Overvoltages at IN S or D will be clamped by internal diodes Current should be limited to the maximum ratings given ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the ADG431 ADG432 ADG433 features proprietary ESD protection circuitry perma nent damage may occur on devices subjected to high energy electrostat
2. 20 10 Vpp 15V Vss 15V 0 20 10 0 10 20 0 5 10 15 20 Vp OR Vs DRAIN OR SOURCE VOLTAGE V Vp OR Vs DRAIN OR SOURCE VOLTAGE V Figure 1 On Resistance as a Function of Vp Vs Dual Figure 4 On Resistance as a Function of Vp Vs Single Supplies Supply 50 100mA Vpp 15V Vpp 15V 4 SW Vss 15V Vss 15V 1 SW 40 Vp 45V 10mA y 45V 1mA 30 l l S z 100pA e 125 C E 20 85 C 10pA 25 C IL 10 T 0 100nA 20 10 0 10 20 10 100 1k 10k 100k 1M 10M Vp OR Vs DRAIN OR SOURCE VOLTAGE V FREQUENCY Hz Figure 2 On Resistance as a Function of Figure 5 Supply Current vs Input Switching Frequency Vp V3 for Different Temperatures 10 x 1 T Is OFF T E E En a tc tc 5 5 o Ot 3 o o N Ip OFF D g Ip OFF lt 0 01 Ip ON 4 0 001 20 40 60 80 100 120 140 20 10 0 10 20 TEMPERATURE C Vp OR Vs DRAIN OR SOURCE VOLTAGE V Figure 3 Leakage Currents as a Function of Temperature Figure 6 Leakage Currents as a Function of Vp Vs REV B b ADG431 AD6432 ADG433 120 100 S z 2 d 9 EEE BURIED OXIDE LAYER KIYAT 2 o 60 Figure 9 Trench Isolation APPLICATION 40 Figure 10 illustrates a precise fast sample and hold circuit An 100 1k 10k 100k 1M 10M FREQUENCY Hz AD845 is used as the input buffer while the output operational amplifier is an AD711 During the track mode
3. Cy Digital Input Capacitance 9 9 pF typ DYNAMIC CHARACTERISTICS Vpp 15 V Vg 15 V ton 90 90 ns typ R 300 Q Cy 35 pF 165 175 ns max Vs 10 V Test Circuit 4 torr 60 60 ns typ Ry 300 Q C 35 pF 130 145 ns max Vs 10 V Test Circuit 4 Break Before Make Time Delay tp 25 25 ns typ Ry 300 Q Cy 35 pF ADG433 Only Vs Vso 10 V Test Circuit 5 Charge Injection 5 5 pC typ Vs 0 V Rs 0 Q Cy 10 nF Test Circuit 6 OFF Isolation 68 68 dB typ R 50 Q Cy 5 pF f 1 MHz Test Circuit 7 Channel to Channel Crosstalk 85 85 dB typ R 50 Q Cy 5 pF f 1 MHz Test Circuit 8 Cs OFF 9 9 pF typ f 1 MHz Cp OFF 9 9 pF typ f 1 MHz Cp Cs ON 35 35 pF typ f 1 MHz POWER REQUIREMENTS Vpp 16 5 V Vss 16 5 V Digital Inputs 0 V or 5 V Ipp 0 0001 0 0001 pA typ 0 1 0 2 0 1 0 2 uA max Iss 0 0001 0 0001 uA typ 0 1 0 2 0 1 0 2 uA max Ir 0 0001 0 0001 LA typ 0 1 0 2 0 1 0 2 uA max Power Dissipation 7 7 7 7 uW max NOTES Temperature ranges are as follows B Versions 40 C to 85 C T Versions 55 C to 125 C Guaranteed by design not subject to production test Specifications subject to change without notice REV B ADG431 ADG432 AD6433 Single Supply Vo 12 v 10 Vss 0 V V 5 V 10 GND 0 V unless otherwise noted B Versions 40 C to T Versions 55 C to Parameter 25 C 485C 25 C 125 C Units Test Conditions Comments ANALOG SWITC
4. SW1 is closed Figure 7 Off Isolation vs Frequency and the output Vour follows the input signal Vw In the hold mode SW1 is opened and the signal is held by the hold capaci tor Cy Due to switch and capacitor leakage the voltage on the hold capacitor will decrease with time The ADG431 ADG432 ADG433 minimizes this droop due to its low leakage specifica tions The droop rate is further minimized by the use of a poly styrene hold capacitor The droop rate for the circuit shown is typically 30 uV us A second switch SW2 which operates in parallel with SW1 is included in this circuit to reduce pedestal error Since both switches will be at the same potential they will have a differen tial effect on the op amp AD711 which will minimize charge injection effects Pedestal error is also reduced by the compensa tion network Rc and Cc This compensation network also reduces the hold time glitch while optimizing the acquisition 100 1k 10k 100k 1M 10M time Using the illustrated op amps and component values the FREGUEBG cR pedestal error has a maximum value of 5 mV over the 10 V input range Both the acquisition and settling times are 850 ns CROSSTALK dB Figure 8 Crosstalk vs Frequency TRENCH ISOLATION In the ADG431A ADG432A and ADG433A an insulating oxide layer trench is placed between the NMOS and PMOS transistors of each CMOS switch Parasitic junctions which occur between the transistors in j
5. Cs ON 35 35 pF typ f 1 MHz POWER REQUIREMENTS Vpp 13 2 V Digital Inputs 0 V or 5 V Ipp 0 0001 0 0001 pA typ 0 03 0 1 0 03 0 1 uA max Ij 0 0001 0 0001 pA typ 0 03 0 1 0 03 0 1 uA max V 5 25 V Power Dissipation 1 9 1 9 uW max NOTES Temperature ranges are as follows B Versions 40 C to 85 C T Versions 55 C to 125 C Guaranteed by design not subject to production test Specifications subject to change without notice Truth Table ADG431 ADG432 ADG431 In ADG432 In Switch Condition 0 1 ON 1 OFF REV B Truth Table ADG433 Logic Switch 1 4 Switch 2 3 0 OFF ON 1 ON OFF ADG431 AD6432 ADG433 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Vpp to Vss Sa RAE wes Oe A eee OEE EAE TT E Tide ue td A 44 V Vpp to GND i peel ek eS es 0 3 V to 25 V Vics tO CrNI utto oie Path oeste 0 3 V to 25 V MNptoGQND re mme es 0 3 V to Vpp 0 3 V peus xd tiM sane Vss 2 V to Vpp 2 V or 30 mA Whichever Occurs First Continuous Current SorD ss 30 mA Peak Current SorD eee 100 mA Pulsed at 1 ms 10 Duty Cycle max Operating Temperature Range Industrial B Version 40 40 C to 85 C Extended T Version 55 C to 125 C Storage Temperature Range 65 C to 150 C Junction Temperature 2 0 0 0 e eee eee 150 C Cerdip Package Power Dissipation
6. inches and mm 16 Lead Cerdip Q 16 0 005 0 13 MIN 0 080 2 03 MAX gt Me gt rt F 0 310 7 87 0 220 5 59 0 320 8 13 0 290 7 37 0 840 21 34 MAX 0 060 1 52 0 200 5 08 3 015 0 38 MA 0 150 0 200 5 08 A J k xi 6 81 ea 0 125 3 18 pie gt 0 015 0 38 SEATING gt B19 10 38 0 023 0 58 01 00 0 070 1 78 BL ANE 45 0 008 0 20 0 014 0 36 2 54 9 030 0 76 ov BSC 16 Lead Plastic DIP Narrow N 16 0 840 21 34 0 745 18 92 a A 5 0 280 7 11 E 8 x 6 10 0 325 8 26 X 0 300 7 62 0 195 4 95 PIN 1 0 060 1 52 0 115 2 93 0 210 5 33 0 015 0 38 e MAX Y HHHHHHH 0 130 0 160 4 06 3 30 0 115 2 93 Se d ou la MIN 0 015 0 381 0 022 0 558 0 100 0 070 1 77 SEATING 0 008 0 204 0 074 0 356 2 54 0 045 1 15 PLANE BSC 16 Lead SOIC R 16A 0 3937 10 00 T 0 3859 9 80 ag 0 1574 4 00 s 0 2440 6 20 0 1497 3 80 1 81 0 2284 5 80 PNI 0 0688 1 75 0 0196 0 50 0 0098 0 25 0 0532 1 35 60099 025 0 25 45 0 0040 0 10 eee y A4 lle 44 8 amp 9 f oso 0 0192 0 49 1 0 lle SEATING 127 0 0138 0 35 0 0099 0 25 0 0500 1 27 PLANE 0 0075 0 19 0 0160 0 41 REV B C1826b 0 11 98 PRINTED IN U S A
7. 28SADG43lfE N i ANALOG DEVICES LC MOS Precision Quad SPST Switches ADG431 ADG432 ADG433 FEATURES 44 V Supply Maximum Ratings 15 V Analog Signal Range Low On Resistance 24 Q Ultralow Power Dissipation 3 9 uW Low Leakage lt 0 25 nA Fast Switching Times ton lt 165 ns torr lt 130 ns Break Before Make Switching Action TTL CMOS Compatible Plug in Replacement for DG411 DG412 DG413 APPLICATIONS Audio and Video Switching Automatic Test Equipment Precision Data Acquisition Battery Powered Systems Sample Hold Systems Communication Systems GENERAL DESCRIPTION The ADG431 ADG432 and ADG433 are monolithic CMOS devices comprising four independently selectable switches They are designed on an enhanced LC MOS process which provides low power dissipation yet gives high switching speed and low on resistance The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals Fast switching speed coupled with high signal bandwidth also make the parts suitable for video signal switching CMOS construction ensures ultralow power dissipa tion making the parts ideally suited for portable and battery powered instruments The ADG431 ADG432 and ADG433 contain four indepen dent SPST switches The ADG431 and ADG422 differ only in that the digital control logic is inverted The ADG431 switches are turned on with a logic low on the appropriate c
8. DG431 ADG432 and ADG433 can be operated from a single rail power supply The parts are fully specified with a single 12 V power supply and will remain functional with single supplies as low as 5 V One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1998 ADG431 ADG432 ADG433 SPECIFICATIONS Dual Supply vo 15 v 10 Vss 15 v 10 V 5 V 10 GND 0 V unless otherwise noted B Versions T Versions 40 C to 55 C to Parameter 25 C 85 C 25 C 125 C Units Test Conditions Comments ANALOG SWITCH Analog Signal Range Vpp to Vss Vpp to Vss V Ron 17 17 Q typ Vp 8 5 V I 10 mA 24 26 24 27 Q max Vpp 13 5 V Vas 13 5 V Ron vs Vp Vs 15 15 typ Ron Drift 0 5 0 5 I C typ Ron Match 5 5 typ Vp 0V I 10 mA LEAKAGE CURRENTS Vpp 16 5 V Vss 16 5 V Source OFF Leakage Is OFF 0 05 0 05 nA typ Vp 15 5 V Vs 15 5 V 0 25 2 0 25 15 nA max Test Circuit 2 Drain OFF Leakage Ip OFF 0 05 0 05 nA typ Vp 15 5 V Vs 15 5 V 0 25 2 0 25 15 nA max Test Circuit 2 Channel ON Leakage Ip I ON 0 1 0 1 nA typ Vp Vs 15 5 V 0 35 3 0 35 17 nA max Test Circuit 3 DIGITAL INPUTS Input High Voltage Ving 2 4 2 4 V min Input Low Voltage Vint 0 8 0 8 V max Input Current Int or INg 0 005 0 005 uA typ Vin VINL or Vinu 0 02 0 02 uA max
9. H Analog Signal Range 0 V to Vpp 0 V to Vpp V Ron 28 28 Q typ 0 lt Vp lt 8 5 V Is 10 mA 42 45 42 45 Q max Vpp 10 8 V Ron vs Vp Vs 20 20 typ Ron Drift 0 5 0 5 C typ Ron Match 5 5 typ Vp 0 V Is 10 mA LEAKAGE CURRENTS Vpp 13 2 V Source OFF Leakage Is OFF 0 04 0 04 nA typ Vp 12 2 1 V Vs 1 12 2 V 0 25 2 0 25 15 nA max Test Circuit 2 Drain OFF Leakage Ip OFF 0 04 0 04 nA typ Vp 12 2 1 V Vs 1 12 2 V 0 25 2 0 25 15 nA max Test Circuit 2 Channel ON Leakage Ip Is ON 0 01 0 01 nA typ Vp Vs 12 2 V 1 V t0 3 t3 t0 3 17 nA max Test Circuit 3 DIGITAL INPUTS Input High Voltage Ving 2 4 2 4 V min Input Low Voltage Vin 0 8 0 8 V max Input Current Int or Imu 0 005 0 005 uA typ Vin VINL or Vinu 0 01 0 01 uA max Cyy Digital Input Capacitance 9 9 pF typ DYNAMIC CHARACTERISTICS Vpp 12 V Vss 0 V ton 165 165 ns typ Ry 300 Q Cy 35 pF 240 240 ns max Vs 8 V Test Circuit 4 torr 60 60 ns typ Ry 300 Q Cj 35 pF 115 115 ns max Vs 8 V Test Circuit 4 Break Before Make Time Delay tp 25 25 ns typ Ry 300 Q Cj 35 pF ADG433 Only Vsi Vs2 10 V Test Circuit 5 Charge Injection 25 25 pC typ Vs 0 V Rs 0 Q Cy 10 nF Test Circuit 6 OFF Isolation 68 68 dB typ R 50 Q Ci 5 pF f 1 MHz Test Circuit 7 Channel to Channel Crosstalk 85 85 dB typ R 50 Q Cy 5 pF f 1 MHz Test Circuit 8 Cs OFF 9 9 pF typ f 1MHz Cp OFF 9 9 pF typ f 1MHz Cp
10. ic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING ESD SENSITIVE DEVICE PIN CONFIGURATION DIP SOIC N1 1 e s IN2 Di hs D2 si 5 ha s2 vss 4 ADG433 fis Voo GND 5 Notto Scale 12 Vi s4 e n 3 D4 1o D3 IN4 a s INS ORDERING GUIDE Model Temperature Range Package Options ADG431BN 40 C to 85 C N 16 ADG431BR 40 C to 85 C R 16A ADG431TQ 55 C to 125 C Q 16 ADG431ABR 40 C to 85 C R 16A ADG432BN 40 C to 85 C N 16 ADG432BR 40 C to 85 C R 16A ADG432TQ 55 C to 125 C Q 16 ADG432ABR 40 C to 85 C R 16A ADG433BN 40 C to 85 C N 16 ADG433BR 40 C to 85 C R 16A ADG433ABR 40 C to 85 C R 16A NOTES 1To order MIL STD 883 Class B processed parts add 883B to T grade part numbers N Plastic DIP R 0 15 Small Outline IC SOIC Q Cerdip 3Trench isolated latch up proof parts See Trench Isolation section TERMINOLOGY Most positive power supply potential Vss Most negative power supply potential in dual supplies In single supply applications it may be connected to GND VL Logic power supply 5 V GND Ground 0 V reference S Source terminal May be an input or output D Drain terminal May be an input or output IN Logic control input Ron Ohmic resistance between D and S Row vs Vp Vs The variation in Roy due to a change in
11. ontrol input while a logic high is required for the ADG432 The ADG433 has two switches with digital control logic similar to that of the ADG431 while the logic is inverted on the other two switches Each switch conducts equally well in both directions when ON and has an input signal range which extends to the supplies In the OFF condition signal levels up to the supplies are blocked All switches exhibit break before make switching action for use in multiplexer applications Inherent in the design is low charge injection for minimum transients when switching the digital inputs REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAMS SWITCHES SHOWN FOR A LOGIC 1 INPUT PRODUCT HIGHLIGHTS 1 Extended Signal Range The ADG431 ADG432 and ADG433 are fabricated on an enhanced LC MOS process giving an increased signal range which extends fully to the supply rails 2 Ultralow Power Dissipation 3 Low Ron 4 Break Before Make Switching This prevents channel shorting when the switches are config ured as a multiplexer 5 Single Supply Operation For applications where the analog signal is unipolar the A
12. the ana log input voltage with a constant load current Ron Drift Change in Roy vs temperature Ron Match Difference between the Ron of any two switches Is OFF Source leakage current with the switch OFF Ip OFF Drain leakage current with the switch OFF Ip Is ON Channel leakage current with the switch ON Vp Vs Analog voltage on terminals D S Cs OFF OFF switch source capacitance Cp OFF OFF switch drain capacitance Cp Cs ON ON switch capacitance Cm Input Capacitance to ground of a digital input ton Delay between applying the digital control input and the output switching on torr Delay between applying the digital control input and the output switching off tp OFF time or ON time measured between the 90 points of both switches when switching from one address state to another Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance Off Isolation A measure of unwanted signal coupling through an OFF switch Charge A measure of the glitch impulse transferred from the Injection digital input to the analog output during switching 4 REV B ADG431 AD6432 ADG433 Typical Performance Graphs 50 Ta 25 C VL 5V Ta 25 C VL 5V 40 30 a a I I z z
13. unction isolated switches are Vin eliminated the result being a completely latch up proof switch In junction isolation the N and P wells of the PMOS and NMOS transistors from a diode that is reverse biased under normal operation However during overvoltage conditions this diode becomes forward biased A silicon controlled rectifier SCR type circuit is formed by the two transistors causing a significant amplification of the current which in turn leads to latch up With trench isolation this diode is removed the result Figure 10 Fast Accurate Sample and Hold being a latch up proof switch ADG431 ADG432 ADG433 6 REV B ADG431 AD6432 ADG433 Test Circuits lg OFF lp OFF Vs uc S l Ron Vi lps Vs ad i Vs J l Vo Test Circuit 1 On Resistance Test Circuit 2 Off Leakage Test Circuit 3 On Leakage 15V 5V 3V Vin ADG431 50 50 3V Ve VIN ApGaa2 50 50 gi 35pF Vour 15V Test Circuit 4 Switching Times 415V 5V Vin 50 50 Cu i 35pF Test Circuit 5 Break Before Make Time Delay 15V 5V O O 3V Vin SP Vout AVour Qing CL x AVour Test Circuit 6 Charge Injection 15V REV B 7 ADG431 AD6432 ADG433 15V 5V 15V Test Circuit 7 Off Isolation 15V 5V CHANNEL TO CHANNEL CROSSTALK 20 x LOG Vs Vour 15V Test Circuit 8 Channel to Channel Crosstalk OUTLINE DIMENSIONS Dimensions shown in

ANALOG DEVICES ADG431/ADG432/ADG433 handbook

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