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ANALOG DEVICES Quad SPDT Switch ADG333A handbook

1. 9119 2 93 0 210 5 33 MAX y WIR E 0 130 0 160 4 06 K 3 30 N MIN 20 Pin SOIC R 20 0 5118 13 00 l 0 4961 12 60 20 11 k 0 2992 7 60 0 2914 7 40 0 4193 10 65 0 3937 10 00 o E 0 115 2 93 gt e gt e I 0 015 0 381 PIN 1 0 1043 2 65 0 0291 0 74 0 022 0 558 0 100 0 070 1 77 SEATING 0 008 0 204 0 0926 2 35 Ios E 45 0 014 0 356 2 54 0 045 1 15 PLANE sui 0 59 BSC R y ry gt e e h ia ge 0 0500 1 27 0 0118 0 30 0 0500 0 0192 0 49 0 0 0157 0 40 SEATING 0 0125 0 32 ee 0 0138 0 35 PLANE 0 33 0 0030 0 10 0 0091 0 23 20 Pin SSOP RS 20 0 295 7 50 0 271 6 90 20 11 s 88 ma a Njo Slo olo 1 10 4 a DN 0 078 1 98 PIN 1 0 07 1 78 0 068 1 73 0 066 1 67 gt Fe 8 0 037 0 94 ad Ia 0 0256 0 0 008 0 203 0 65 SEATING 0 009 0 229 0 022 0 559 0 002 0 050 Bsc N 0 005 0 127 LEADS WILL BE EITHER TIN PLATED OR SOLDIER DIPPED IN ACCORDANCE WITH MIL M 38510 REQUIREMENTS REV 0 C2076 18 10 95 PRINTED IN U S A
2. Mee OON Der a casa abe ted Lal 40 3 V to 30 V Analog Digital Inputs Vss 2V to Vpp 2V or 20 mA Whichever Occurs First Continuous Current S or D Peak Current S or D Pulsed at 1 ms 1096 D uty C ycle M ax O perating T emperature R ange Industrial B Version Storage T emperature R ange 40 C to 85 C 65 C to 125 C Junction Temperature 0 00 eee eee 150 C Plastic Package 64 Thermal Impedance 0008 103 C W Lead T emperature Soldering 10 sec 260 C CAUTION SOIC Package Oja Thermal Impedance 00 eae 74 C W Lead T emperature Soldering Vapor Phase 60 sec 0 0 eee eee 215 C Infrared 15 sec 0 eee eee 220 C SSOP Package Oja Thermal Impedance 00000 130 C W L ead T emperature Soldering Vapor Phase 60sec 0 0 eee eee eee 215 C Infrared 15 sec a e sieran iak a a eee 220 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Only one absolute maximum rating may be applied at any one time Overvoltages at IN S or D will be clamped by internal diodes Current should be l
3. switching the digital inputs REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM SWITCHES SHOWN FOR A LOGIC 1 INPUT PRODUCT HIGHLIGHTS 1 Extended Signal Range T he AD G 333A is fabricated on an enhanced LC M OS process giving an increased signal range which extends to the supply rails 2 Low Power Dissipation 3 Low Ron 4 Single Supply O peration For applications where the analog signal is unipolar the AD G 333A can be operated from a single rail power supply T he part is fully specified with a single 12 V supply Analog Devices Inc 1995 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 ADG333A SPECIFICATIONS DUAL SUPPLY vo 15v Vss 15 V GND 0 V unless otherwise noted 40C to Parameter 25 C 85 C Units Test Conditions C omments ANALOG SWITCH Analog Signal Range Vss to Vpp V Ron 20 Q typ Vp 10 V ls 1 mA 45 45 Q max ARon 5 Q max Vp 5 V Is 2 10 mA Roy M atch 4 Q max Vp 2 10V Is 2 10 mA LEAKAGE CURRENTS Vpp 16 5 V Vss 16 5 V Source OFF Leakage l
4. 5 OFF 0 1 nA typ Vp 2 155 V Vs 4155 V 0 25 3 nA max Test Circuit 2 Channel ON Leakage Ip I5 ON 0 1 nA typ Vs Vp 415 5V 0 4 5 nA max Test Circuit 3 DIGITAL INPUTS Input High Voltage Ving 2 4 V min Input Low Voltage Vin 0 8 V max Input Current line OF linn 0 005 pA typ Vin 20V or Vpp 0 5 uA max DYNAMIC CHARACTERISTICS ton 90 ns typ R 300 Q C 35 pF 175 ns max Vs 2 10V Test Circuit 4 torr 80 ns typ R 2 300 Q C 235 pF 145 ns max Vs 10 V Test Circuit 4 Break Before M ake D elay topen 10 ns min R 300 Q C 35 pF Vs 5 V Test Circuit 5 Charge Injection 2 pC typ Vp 0V Rp 209 C 10 nF 10 pC max Vpp 15 V Vss 15 V Test Circuit 6 OFF Isolation 72 dB typ R 75Q C 5pF f 1MHz Vs 2 3 V rms T est Circuit 7 Channel to C hannel C rosstalk 85 dB typ R 2750 C Z5pF f Z MHz Vs 2 2 3 V rms T est Circuit 8 Cs OFF 5 pF typ Cp Cs ON 20 pF typ POWER REQUIREM ENTS Ipp 0 05 mA typ Digital Inputs 20 V or 5 V 0 25 0 35 mA max lss 0 01 uA typ 1 5 uA max Vpp V ss 3 20 V min V max Vool Vss NOTES 1T emperature range is as follows B Version 40 C to 85 C G uaranteed by design not subject to production test Specifications subject to change without notice REV 0 SINGLE SUPPLY vp 12 v Ves 0 V 10 GND 0 V unless otherwise noted ADG333A 40C to Parameter 25 C 85 C Units Test Conditions C omments ANALOG SWITCH Analog S
5. IAD G333 H vf ANALOG DEVICES Quad SPDT Switch FEATURES 44 V Supply Maximum Ratings Vss to Vpp Analog Signal Range Low On Resistance 45 O max Low ARon 5 O max Low Roy Match 4 max Low Power Dissipation Fast Switching Times ton lt 175 ns torr lt 145 ns Low Leakage Currents 5 nA max Low Charge Injection 10 pC max Break Before Make Switching Action APPLICATIONS Audio and Video Switching Battery Powered Systems Test Equipment Communication Systems GENERAL DESCRIPTION T he ADG 333A is a monolithic CM OS device comprising four independently selectable SPDT switches It is designed on an LCM OS process which provides low power dissipation yet achieves a high switching speed and a low on resistance The on resistance profile is very flat over the full analog input range ensuring good linearity and low distortion when switching audio signals High switching speed also makes the part suitable for video signal switching CM OS construction ensures ultralow power dissipation making the part ideally suited for portable battery powered instruments When they are ON each switch conducts equally well in both directions and has an input signal range which extends to the power supplies In the OFF condition signal levels up to the supplies are blocked All switches exhibit break before make switching action for use in multiplexer applications Inherent in the design is low charge injection for minimum transients when
6. S INFORMATION ADG333A Supply Voltages The AD G 333A can operate off a dual or signal supply Vss should be connected to GN D when operating with a single supply W hen using a dual supply the AD G 333A can also oper ate with unbalanced supplies for example Vpp 20 V and Vss 5 V The only restrictions are that Vpp to GND must not exceed 30 V Vss to GN D must not drop below 30 V and Vpp to Vss must not exceed 44 V It is important to remember that the AD G 333A supply voltage directly affects the input signal range the switch ON resistance and the switching times of the part T he effects of the power supplies on these characteristics can be clearly seen from the characteristic curves in this data sheet Power Supply Sequencing When using CM OS devices care must be taken to ensure correct power supply sequencing Incorrect power supply sequencing can result in the device being subjected to stresses beyond those maximum ratings listed in the data sheet T his is also true for the AD G333A Always sequence Vpp on first followed by Vss and the logic signals An external signal within the maximum specified ratings can then be safely presented to the source or drain of the switch OUTLINE DIMENSIONS Dimensions shown in inches and mm 20 Pin Plastic DIP N 20 1 060 26 90 0 925 23 50 2 1111 0 280 7 11 0 240 6 10 1 10 0 325 8 25 k 0 060 1 52 0 300 7 62 0 195 4 95 PIN 1 0 015 0 38
7. Vs for Different Temperatures Dual Supply 0 3 6 9 12 15 Vp Vs Volts Figure 4 Roy as a Function of Vp Vs for Different Temperatures Single Supply LEAKAGE CURRENT nA 35 10 5 0 5 10 15 Vp Vs Volts Figure 5 Leakage Currents as a Function of Vp Vs Dual Supply 0 001 I OFF 0 c Vpp 16 5V E Vss 16 5V a 0 001 TA 25 C tc 2 o 0 002 Ip ON s ON ls ON 0 003 0 004 0 3 6 9 12 Vp Vs Volts Figure 6 Leakage Currents as a Function of Vp Vs Single Supply Vs Volts Figure 7 Charge Injection as a Function of Vs 160 2 eo SWITCHING TIME ns eo o 60 0 5 10 15 20 Vpp Volts Figure 8 Switching Time as a Function of Vpp 16 5V 16 5V 25 C 0 200 400 600 800 1000 SWITCHING FREQUENCY kHz Figure 9 Ipp as a Function of Switching Frequency REV 0 ls OFF t d Ron Vi lps V Vs V Vv Test Circuit 1 On Resistance Test Circuit 2 Off Leakage Test Circuit 3 On Leakage Vpp 0 1pF 3v Vin 50 50 0v 10V 0v 10V Qing C X AVour AVour CHANNEL TO CHANNEL CROSSTALK 20 x LOG Vs Vourl Test Circuit 7 Off Isolation Test Circuit 8 Channel to Channel Crosstalk REV 0 7 ADG333A APPLICATION
8. e between the Roy of any two Vint M aximum input voltage for logic 0 channels Ving M inimum input voltage for logic 1 Is OFF Source leakage current with the switch Tine liny Input current of the digital input OFF C rosstalk A measure of unwanted signal which is Ip OFF Drain leakage current with the switch coupled through from one channel to another OFF as a result of parasitic capacitance Ip Is ON Channel leakage current with the switch Off Isolation A measure of unwanted signal coupling ON through an OFF switch Vp Vs Analog voltage on terminals D S Charge Injection A measure of the glitch impulse transferred Cs OFF OFF Switch Source Capacitance from the digital input to the analog output Cp OFF OFF Switch D rain Capacitance MORI tenid PIN CONFIGURATION DIP SOIC SSOP N1 1 o 20 Ina SiA 2 19 54A TOP VIEW GND NC Le Not to Scale jsl S2B 14 S3B D2 13 D3 S2A 9 12 S3A iN2 10 11 is NC NO CONNECT REV 0 5 ADG333A Typical Performance Graphs Ron 2 10 15 10 5 0 5 10 15 Vp Vs Volts Figure 1 Roy as a Function of Vp Vs Dual Supply Vp Vs Volts Figure 2 Roy as a Function of Vp Vs Single Power Supply a 85 C o ec 15 40 C 25 C 10 15 10 5 0 5 10 15 Vp Vs Volts Figure 3 Roy as a Function of Vp
9. ignal Range 0 to Vpp V Ron 35 Q typ Vp 1 V 10 V Is 1 mA 75 Q max LEAKAGE CURRENTS Vpp 13 2 V Source OFF Leakage ls OFF 0 1 nA typ Vp 2122 V 1 V Vs 1 V 12 2 V 0 25 3 nA max Test Circuit 2 Channel ON Leakagelp Is ON 0 1 nA typ Vs Vp 12 2 V 1 V 0 4 5 nA max Test Circuit 3 DIGITAL INPUTS Input High Voltage Ving 2 4 V min Input Low Voltage Vint 0 8 V max Input Current line Or linn 0 005 pA typ Vin 0V or Vpp 0 5 uA max DYNAMIC CHARACTERISTICS toN 110 ns typ R 2300 Q C 235 pF 200 ns max Vs 8 V Test Circuit 4 torr 100 ns typ R 2300 0 C 235 pF 180 ns max Vs 8 V Test Circuit 4 Break Before M ake D elay topen 10 ns min R 23000 C 235 pF ns min Vs 5 V Test Circuit 5 Charge Injection 5 pC typ Vp 6V Rp 0Q0 C 10nF Vpp 12 V Vss 0 V Test Circuit 6 OFF Isolation 72 dB typ R 275Q C Z5pF f Z 1MHz Vs 2 1 15 V rms Test Circuit 7 Channel to C hannel C rosstalk 85 dB typ R 2750 C 5pF f Z 1MHz Vs 2 1 15 V rms T est Circuit 8 Cs OFF 5 pF typ Cp Cs ON 20 pF typ POWER REQUIREMENTS Vpp 13 5 V Ipp 0 05 mA typ Digital Inputs 20 V or 5 V 0 25 0 35 mA max Vpp 43 30 V min V max NOTES 1T emperature range is as follows B Version 40 C to 85 C G uaranteed by design not subject to production test Specifications subject to change without notice REV 0 ADG333A ABSOLUTE MAXIMUM RATINGS T4 25 C unless otherwise noted DEA I 44 V E n Ele t ES 0 3 V to 430 V
10. imited to the maximum ratings given ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD G 333A features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING pl ESD SENSITIVE DEVICE ORDERING GUIDE Model Temperature Range Package O ption AD G333ABN 40 C to 85 C N 20 ADG333ABR 40 C to 85 C R 20 ADG333ABRS 40 C to 85 C RS 20 N Plastic DIP R Small Outline IC SOIC RS Shrink Small Outline Package SSOP Tablel Truth Table Logic Switch A Switch B 0 OFF ON 1 ON OFF REV 0 TERMINOLOGY Cp Cs ON ON Switch Capacitance 5 Source Terminal May bean input or output D elay between applying the digital control in D Drain T erminal M ay be an input or output put and the output switching on IN Logic Control Input torr D elay between applying the digital control in Ron Ohmic resistance between D and S put and the output switching off ARon Ron variation due to a change in the analog topen Break Before M ake delay when switches are input voltage with a constant load current configured as a multiplexer Ron Match Differenc

ANALOG DEVICES Quad SPDT Switch ADG333A handbook

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