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ANALOG DEVICES Low Voltage 1.15 V to 5.5 V 4-Channel Bidirectional Logic Level Translator ADG3304 handbook

1. ADG3304 ANALOG Low Voltage 1 15 V to 5 5 V 4 Channel DEVICES Bidirectional Logic Level Translator ADG3304 FEATURES Bidirectional level translation Operates from 1 15 V to 5 5 V Low quiescent current lt 5 pA No direction pin APPLICATIONS SPI MICROWIRE level translation Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communications devices Telecommunications equipment Network switches and routers Storage systems SAN NAS Computing server applications GPS Portable POS systems Low cost serial interfaces GENERAL DESCRIPTION The ADG3304 is a bidirectional logic level translator that con tains four bidirectional channels It can be used in multivoltage digital system applications such as data transfer between a low voltage digital signal processing controller and a higher voltage device using SPI and MICROWIRE interfaces The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction in which the translation takes place The voltage applied to Vcca sets the logic levels on the A side of the device while Vccy sets the levels on the Y side For proper operation Vcca must always be less than Vccy The Vcca com patible logic signals applied to the A side of the device appear as Vccy compatible levels on the Y side Similarly Vccy compatible logic levels applied to the Y sid
2. ADG3304 TABLE OF CONTENTS Specifications P 3 Absolute Maximum Ratings essent 6 6 Pin Configurations and Function Descriptions 7 Typical Performance Characteristics sse 8 Test CITCUIS uite ite ie eH REPRE HER 12 TerminoloBy i etie ee tede eee bee 15 Theory of Operation eet eese ieiunus 16 Level Translator Architecture ses 16 REVISION HISTORY 12 05 Rev A to Rev B Changes to 3 Changes to Table2 IU E 6 Changes to Figure 3 and Table 4 7 Updated Outline Dimensions seen 19 Changes to Ordering Guide sse 21 6 05 Rev 0 to Rev A Added EECSP Pack ge erepta retenta Universal 1 05 Revision 0 Initial Version Input Driving Requirements sse 16 Output Load Requirement sese 16 Enable Operation eite eR 16 Power Supplies ettet te dette 16 Data nene eee 17 REA HERR deeds 18 Layout Guidelines cite 18 O tline Dimensions entente tete t tds 19 Ordering Guide 20 Rev B Page 2 of 20 SPECIFICATIONS ADG3304 Vecy 1 65 V to 5 5 V Vcca 1 15 V to Vecy GND 0 V Ta 25 C All specifications Tum to Tmax unless otherwise noted Table 1 B Version Parameter Symbol Test Conditions Comments M
3. 25 C to 85 C 12 Ball Wafer Level Chip Scale Package WLCSP SDC CB 12 ADG3304BCBZ REEL7 25 C to 85 C 12 Ball Wafer Level Chip Scale Package WLCSP SDC CB 12 Branding on these packages is limited to three characters due to space constraints 2 Z Pb free part 2005 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D04860 0 12 05 B DEVICES www analog com Rev B Page 20 of 20 WWW ZFA CN SRA MPDFH MN PR 1 Pz W C WWW Zfa cm CA WALA PAK XICPIEO41662 gl 3 HR XA ZB XYI 0755 83278916 83278919 ALEC 010 62632888 62636888
4. A ns POWER REQUIREMENTS Power Supply Voltages Vcca lt Vecy 1 15 5 5 V Vccv 1 65 5 5 V Quiescent Power Supply Current Icca Va 0V Veca Vv 0 V Vecy 0 17 5 uA Vcca Vecy 5 5 V EN 1 Iccy Va 0V Veca Vy O V Vecy 0 27 5 uA Vcca Vccy 5 5 V EN 1 Three State Mode Power Supply Current 1 Vcca Vecy 5 5 V EN 0 0 1 5 uA luiz v Vcca Vecy 5 5 V EN 0 0 1 5 uA 1 Temperature range is as follows B version 40 C 85 C for the TSSOP and LFCSP 25 C to 85 C for the WLCSP Guaranteed by design not production tested Rev B Page 5 of 20 ADG3304 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 2 Parameter Rating Vcca to GND 0 3 V to 7 V Vccy to GND Vcca to 7 V Digital Inputs A 0 3 V to Vcca 0 3 V Digital Inputs Y 0 3 V to Vccy 0 3 V EN to GND 0 3 V to 7 V Operating Temperature Range Extended Industrial B Version TSSOP and LFCSP 40 C 85 C Industrial B Version WLCSP 25 C to 85 C Storage Temperature Range 65 C to 150 C Junction Temperature 150 C Oja Thermal Impedance 4 Layer Board 14 Lead TSSOP 89 21 C W 12 Ball WLCSP 120 C W 20 Lead LFCSP 30 4 C W Lead Temperature Soldering 10 sec 300 C IR Reflow Peak Temperature lt 20 sec 260 C ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human b
5. Delay tein vs Capacitive Load at Pin A Y gt A Level Translation Ta 25 C 1 CHANNEL 8 DATA RATE 50kbps PROPAGATION DELAY ns 13 18 23 28 33 CAPACITIVE LOAD pF 38 43 48 53 Figure 22 Propagation Delay ter vs Capacitive Load at Pin A Y gt A Level Translation 04860 028 04860 029 04860 030 ADG3304 TA 25 C DATA RATE 25Mbps C 50pF 1 CHANNEL Ta 25 C DATA RATE 50Mbps 15pF i 1 CHANNEL 400mV DIV 5ns DIV 04860 037 04860 040 Figure 23 Eye Diagram at Y Output Figure 26 Eye Diagram at A Output 1 2 V to 1 8 V Level Translation 25 Mbps 3 3 V to 1 8 V Level Translation 50 Mbps 25 C 50pF DATA RATE 25Mbps 1 CHANNEL Ta 25 C DATA RATE 50Mbps CL 50pF 1 CHANNEL 200 5ns DIV 1V DIV 3ns DIV Figure 24 Eye Diagram at A Output Figure 27 Eye Diagram at Y Output 1 8 V to 1 2 V Level Translation 25 Mbps 3 3 V to 5 V Level Translation 50 Mbps 04860 038 04860 041 25 C 50pF DATA RATE 1 CHANNEL Ta 25 C DATA RATE 50Mbps 15pF 1 CHANNEL Eu IMEEM 3ns DIV 800mV DIV 3ns DIV Figure 25 Eye Diagram at Y Output Figure 28 Eye Diagram at A Output 1 8 V to 3 3 V Level Translation 50 Mbps 5 V to 3 3 V Level Translation 50 Mbps 04860 039 04860 042 Rev B Page 11 of 20 ADG3304 TEST CIRCUITS 0
6. ns Y gt A Level Translation Rs Rr 500 C 15 pF see Figure 38 Propagation Delay 4 Rise Time tR voA ns Fall Time tEY gt A 3 ns Maximum Data Rate Dmax Y gt A 50 Mbps Channel to Channel Skew tskew Y gt A 2 3 5 ns Part to Part Skew tepskew YA 2 ns Rev B Page 3 of 20 ADG3304 B Version Parameter Symbol Test Conditions Comments Min Typ Max Unit 1 8V 0 15 V lt Vcca Vecy Vecy 3 3 V 0 3 V A Y Translation Rs Rr 2 500 C 50 pF see Figure 37 Propagation Delay tP AsY 8 11 ns Rise Time tr Asy 2 5 ns Fall Time tF A Y 2 5 ns Maximum Data Rate Dmax A Y 50 Mbps Channel to Channel Skew tsKew A gt Y 2 4 ns Part to Part Skew A gt Y 4 ns Y gt A Translation Rs Rr 50Q C 15 pF see Figure 38 Propagation Delay 5 8 ns Rise Time tr 5A 2 3 5 ns Fall Time te voA 2 3 5 ns Maximum Data Rate Dmax Y gt A 50 Mbps Channel to Channel Skew tskew Y gt a 2 3 ns Part to Part Skew tepskew Y gt A 3 ns 1 15 V to 1 3 V lt Vcca Vecy Vecy 3 3 V 0 3 V A gt Y Translation Rs Rr 50 O C 50 pF see Figure 37 Propagation Delay teasy 9 18 ns Rise Time tr Asy 3 5 ns Fall Time tE A gt Y 2 5 ns Maximum Data Rate Dmax A gt Y 40 Mbps Channel to Channel Skew tskEw A gt Y 2 5 Part to Part Skew tepskew A gt Y 10 ns Y gt A Translation Rs Rr 500 C 15 pF see Figure 38 Propagation Delay 5 9 Rise Time tR Y gt A 2 4 ns Fall Time
7. te voA 2 4 ns Maximum Data Rate Dmax Y gt A 40 Mbps Channel to Channel Skew tskew 2 4 ns Part to Part Skew tPPSKEW Y gt A 4 ns 1 15 V to 1 3 V lt Vcc Vecy Vecy 1 8 V 0 3 V A Y Translation Rs Rr 50 O CL 50 pF see Figure 37 Propagation Delay tP AY 12 25 ns Rise Time tg A gt Y 7 12 ns Fall Time tr Asy 3 5 ns Maximum Data Rate Dmax A Y 25 Mbps Channel to Channel Skew tskEW A Y 2 5 ns Part to Part Skew A gt Y 15 ns Rev B Page 4 of 20 ADG3304 B Version Parameter Symbol Test Conditions Comments Min Typ Max Unit Y gt A Translation Rs Rr 500 C 15 pF see Figure 38 Propagation Delay 14 35 Rise Time tR voA 5 16 ns Fall Time tE Y gt A 2 5 6 5 ns Maximum Data Rate Dmax Y gt A 25 Mbps Channel to Channel Skew tskew Y2A 3 6 5 ns Part to Part Skew tepskEW Y gt A 23 5 ns 2 5 V 0 2V lt Vcca Vecy Vcv 3 3 V 0 3 V A gt Y Translation Rs Rr 50 O C 50 pF see Figure 37 Propagation Delay teasy 7 10 ns Rise Time R A gt Y 2 5 ns Fall Time tE A gt Y 2 5 ns Maximum Data Rate Dmax A Y 60 Mbps Channel to Channel Skew tskEW A gt Y 1 5 ns Part to Part Skew tPPSKEW A gt Y ns YA Translation Rs Rr 50 Q C 15 pF see Figure 38 Propagation Delay 5 8 Rise Time trysa 1 ns Fall Time tr voA 3 5 ns Maximum Data Rate Dmax Y gt A 60 Mbps Channel to Channel Skew tskew Y gt A 2 ns Part to Part Skew Y gt
8. 0 012 04860 013 Iccy mA IccA mA Iccy mA ADG3304 7 Ta 25 C Ta 25 C 1 CHANNEL 1 CHANNEL Veca 1 8V 6 Vcca 3 3V Vecy 3 3V Vecy 5V 5 T 4 E 8 3 2 1 e 0 z 13 23 33 43 53 CAPACITIVE LOAD pF 3 CAPACITIVE LOAD pF 3 Figure 11 Iccy vs Capacitive Load at Pin Y for A gt Y 1 8 V53 3 V Figure 14 Icca vs Capacitive Load at Pin A for YA 5 V3 3 V Level Translation Level Translation 10 TA 25 C TA 25 C 1 CHANNEL 9 1 CHANNEL Vcca 1 8V DATA RATE 50kbps Voca 1 2V Vccy 1 8V 8 7 5 E ul 2 4 Veca 1 8V Vccy 3 3V 3 2 Veca 3 3V Vecy 5V 1 t 0 8 3 13 23 33 43 53 63 73 CAPACITIVE LOAD pF 8 CAPACITIVE LOAD pF 3 Figure 12 Icca vs Capacitive Load at Pin A for Y gt A 3 3 V gt 1 8 V Figure 15 Rise Time vs Capacitive Load at Pin Y A gt Y Level Translation Level Translation 12 4 0 TA 25 C Ta 25 C 1 CHANNEL 1 CHANNEL xs Veca 3 3V 5 DATA RATE 50kbps Veca 1 2V Vecy 1 8V 10 lvccy 5V CCA ccy 3 0 8 2 5 u A 1 8V Vccy 3 3V 6 2 0 d a 4 amp 15 1 0 2 0 5 0 S 0 13 23 33 43 53 63 73 13 23 33 43 53 63 73 3 CAPACITIVE LOAD pF 3 CAPACITIVE LOAD pF 3 Figure 13 Iccy vs Capacitive Load at Pin Y for AY 3 3 V gt 5 V Figu
9. 04860 057 Figure 4 20 Lead LFCSP_VQ Pin Configuration Pin No TSSOP LFCSP Mnemonic Description 1 19 Veca Power Supply Voltage Input for the A1 to A4 I O Pins 1 15 V lt Vcca lt Vccy 2 20 A1 Input Output A1 Referenced to Vcca 3 2 A2 Input Output A2 Referenced to Vcca 4 3 A3 Input Output A3 Referenced to Vcca 5 4 A4 Input Output A4 Referenced to Vcca 6 9 1 5 6 7 10 11 15 16 NC No Connect 7 8 GND Ground 8 9 EN Active High Enable Input 10 12 4 Input Output Y4 Referenced to Vccv 11 13 Y3 Input Output Y3 Referenced to Vccv 12 14 Y2 Input Output Y2 Referenced to Vccv 13 17 Y1 Input Output Y1 Referenced to Vccv 14 18 Vccv Power Supply Voltage Input for the Y1 to Y4 I O Pins 1 65 V lt 5 5 V Table 4 12 Ball WLCSP Pin Function Descriptions Bump No Mnemonic Description al Y1 Input Output Y1 Referenced to Vccy a2 Y2 Input Output Y2 Referenced to Vccy a3 Y3 Input Output Y3 Referenced to Vccy a4 4 Input Output Y4 Referenced to Vccy b1 Vccv Power Supply Voltage Input for the Y1 to Y4 I O Pins 1 65 V lt Vcc x 5 5 V b2 VccA Power Supply Voltage Input for the A1 to A4 I O Pins 1 15 V x Vcca b3 EN Active High Enable Input b4 GND Ground cl Al Input Output A1 Referenced to Vcca c2 A2 Input Output A2 Referenced to Vcca c3 A3 Input Output A3 Referenced to Vcca c4 A4 Input Output A4 Referenced to Vcca Rev B Page 7 of 20 ADG3
10. 1 to Pin A4 Vona Logic output high voltage at Pin A1 to Pin A4 Vora Logic output low voltage at Pin A1 to Pin A4 Ca Capacitance measured at Pin A1 to Pin A4 EN 0 Ia niz Leakage current at Pin A1 to Pin A4 when EN 0 high impedance state at Pin A1 to Pin A4 Viny Logic input high voltage at Pin Y1 to Pin Y4 Vuy Logic input low voltage at Pin Y1 to Pin Y4 Vony Logic output high voltage at Pin Y1 to Pin Y4 Voix Logic output low voltage at Pin Y1 to Pin Y4 Cy Capacitance measured at Pin Y1 to Pin Y4 EN 0 Ix ni z Leakage current at Pin Y1 to Pin Y4 when EN 0 high impedance state at Pin Y1 to Pin Y4 Vinen Logic input high voltage at the EN pin Vuen Logic input low voltage at the EN pin Cen Capacitance measured at EN pin Iren Enable EN pin leakage current ten Three state enable time for Pin A1 to Pin A4 and Pin Y1 to Pin Y4 te acy Propagation delay when translating logic levels in the A2Y direction tr asy Rise time when translating logic levels in the A gt Y direction ADG3304 TR A Fall time when translating logic levels in the A gt Y direction Dmax asy Guaranteed data rate when translating logic levels in the A gt Y direction under the driving and loading conditions specified in Table 1 Tskew A Y Difference between propagation delays on any two channels when translating logic levels in the A gt Y direction tepskEw A Y Difference in propa
11. 304 TYPICAL PERFORMANCE CHARACTERISTICS Icca mA lccv mA Icca mA 04860 005 10 Ir 225 0 9 1 CHANNEL C 50pF 0 8 Veca 33V Vecy 5V d CCA ccy 0 6 0 5 0 4 Veca 1 8V Vecy 3 3V 03 cC ccy 0 2 0 1 Veca 1 2V Vecy 1 8V 0 0 5 10 15 20 25 30 35 40 45 50 DATA RATE Mbps Figure 5 Icca vs Data Rate A gt Y Level Translation 10 HS 256 9 1 CHANNEL 50pF 8 7 6 5 4 8 2 1 0 0 5 10 15 20 25 30 35 40 45 50 DATA RATE Mbps Figure 6 Iccy vs Data Rate A gt Y Level Translation 25 C 1 CHANNEL C 15pF 0 5 10 15 20 25 30 35 40 45 DATA RATE Mbps Figure 7 Icca vs Data Rate Y gt A Level Translation 50 04860 004 04860 006 Iccy mA Iccy mA Icca mA Rev B Page 8 of 20 Ta 25 C 1 CHANNEL C 15pF 0 5 10 15 20 25 30 35 40 45 50 DATA RATE Mbps Figure 8 Iccy vs Data Rate Y gt A Level Translation 25 C 1 CHANNEL Veca 1 2V Vecy 1 8V CAPACITIVE LOAD pF Figure 9 Iccy vs Capacitive Load at Pin Y for A gt Y 1 2 V gt 1 8 V Level Translation Ta 25 C 1 CHANNEL Veca 1 2V 1 8V CAPACITIVE LOAD pF Figure 10 Icca vs Capacitive Load at Pin A for Y gt A 1 8 V gt 1 2 V Level Translation 04860 007 0486
12. 4860 043 Figure 29 VowVo Voltages at Pin A ADG3304 i 04860 044 Figure 30 Vor Vo Voltages at Pin Y SO ADG3304 l Q lt i C V Figure 31 Three State Leakage Current at Pin A 04860 045 Rev B Page 12 of 20 METER ee d O Figure 32 Three State Leakage Current at Pin Y ADG3304 C Q E Q Q ADG3304 Q C a V Figure 33 EN Pin Leakage Current ADG3304 d HLAH Figure 34 Capacitance at Pin A 04860 046 04860 047 04860 048 ADG3304 d Q O O lt CAPACITANCE METER Q V Figure 35 Capacitance at Pin Y 04860 049 AY DIRECTION VccA ADG3304 O Rs Zo 500 0 AW 502 Rr V SIGNAL SOURCE Y 4A DIRECTION Mec ADG3304 O O VccA Vccv VccA Veca Vecy Vccv VccA NOTES 1 ten IS WHICHEVER IS LARGER BETWEEN ten AND tena IN BOTH AY AND Y gt A DIRECTIONS Figure 36 Enable Time Rev B Page 13 of 20 1MO 04860 050 ADG3304 ADG3304 ADG3304 ADG3304 SIGNAL SOURCE 04860 052 trys tEASY tray 04860 051 Figure 38 Switching Characteristics Y gt A Level Translation Figure 37 Switching Characteristics A gt Y Level Translation Rev B Page 14 of 20 TERMINOLOGY Vina Logic input high voltage at Pin Al to Pin 4 Vua Logic input low voltage at Pin A
13. ch results in faster rise and fall times The inputs of the unused channels A or Y should be tied to their corresponding Vcc rail Vcca or Vccy or to GND INPUT DRIVING REQUIREMENTS To ensure correct operation of the ADG3304 the circuit that drives the input of the ADG3304 channels should have an output impedance of less than or equal to 150 Q and a minimum peak current driving capability of 36 mA OUTPUT LOAD REQUIREMENTS The ADG3304 level translator is designed to drive CMOS compatible loads If current driving capability is required it is recommended to use buffers between the ADG3304 outputs and the load ENABLE OPERATION The ADG3304 provides three state operation at the A and Y I O pins by using the enable pin EN as shown in Table 5 Table 5 Truth Table EN Y I O Pins A I O Pins 0 Hi Z Hi Z 1 Normal operation Normal operation 1 High impedance state In normal operation the ADG3304 performs level translation While EN 0 the ADG3304 enters into three state mode In this mode the current consumption from both the Vcca and Vccy supplies is reduced allowing the user to save power which is critical especially on battery operated systems The EN input pin can be driven with either Vcca compatible or Vccy compatible logic levels POWER SUPPLIES For proper operation of the ADG3304 the voltage applied to the Vcca must be less than or equal to the voltage applied to Vccv To meet this
14. condition the recommended power up sequence is Vccv first and then Vcca The ADG3304 operates properly only after both supply voltages reach their nominal values It is not recommended to use the part in a system where during power up Vcca can be greater than Vccy due to a significant increase in the current taken from the Vcca supply For optimum performance the Vcca pin and Vccy pin should be decoupled to GND as close as possible to the device Rev B Page 16 of 20 DATA RATE The maximum data rate at which the device is guaranteed to operate is a function of the Vcca and Vccy supply voltage combination and the load capacitance It is given by the maximum frequency of a square wave that can be applied to the device which meets the Vou and Vox levels at the output and does not exceed the maximum junction temperature see the Absolute Maximum Ratings section Table 6 shows the guaranteed data rates at which the ADG3304 can operate in both directions A gt Y or Y gt A level translation for various Vcca and Vccy supply combinations Table 6 Guaranteed Data Rate Mbps ADG3304 Vecy 1 8V 2 5V 3 3V 5V Vcca 1 65 V to 1 95 V 2 3 V to 2 7 V 3 0 V to 3 6 V 4 5 V to 5 5 V 1 2V 1 15 V to 1 3 V 25 30 40 40 1 8 V 1 65 V to 1 95 V 45 50 50 2 5 V 2 3 V to 2 7 V 60 50 3 3 V 3 0 V to 3 6 V 50 5V 4 5 V to 5 5 V 1 The load capacitance used is 50 pF when translating in the A gt Y d
15. e of the device appear as Vcca compatible logic levels on the A side Rev B Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM VccA Vccv A1 Y1 A2 Y2 A3 Y3 A4 Y4 EN GND Figure 1 The enable pin EN provides three state operation on both the A side and the Y side pins When the EN pin is pulled low the terminals on both sides of the device are in the high impedance state The EN pin is referred to the Vcca supply voltage and driven high for normal operation The ADG3304 is available in compact 14 lead TSSOP 12 ball WLCSP and 20 lead LFCSP It is guaranteed to operate over the 1 15 V to 5 5 V supply voltage range PRODUCT HIGHLIGHTS 1 Bidirectional level translation 2 Fully guaranteed over the 1 15 V to 5 5 V supply range 3 No direction pin 4 Available in 14 lead TSSOP 12 ball WLCSB and 20 lead LECSP One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved
16. erial Links When the application requires level translation between a micro processor and multiple peripheral devices the ADG3304 I O pins can be three stated by setting EN 0 This feature allows the ADG3304 to share the data buses with other devices without causing contention issues Figure 41 shows an application where a 1 8 V microprocessor is connected to a 3 3 V peripheral device using the three state feature VOL microprocessor O12 MICROCONTROLLER PERIPHERAL DEVICE 1 VOLa PERIPHERAL DEVICE 2 04860 055 Figure 41 1 8 V to 3 3 V Level Translation Circuit Using the Three State Feature LAYOUT GUIDELINES As with any high speed digital IC the printed circuit board layout is important for the overall performance of the circuit Care should be taken to ensure proper power supply bypass and return paths for the high speed signals Each Vcc pin Vcca and Vccy should be bypassed using low effective series resistance ESR and effective series inductance ESI capacitors placed as close as possible to the Vcca pin and the Vccy pin The parasitic inductance of the high speed signal track may cause significant overshoot This effect can be reduced by keeping the length of the tracks as short as possible A solid copper plane for the return path GND is also recommended Rev B Page 18 of 20 OUTLINE DIMENSIONS 0 20 20 0 09 1 0 75 050 T ie 05 g
17. gation delay between any one channel and the same channel on a different part under same driving loading conditions when translating in the A gt Y direction te y gt a Propagation delay when translating logic levels in the Y gt A direction tr Y gt a Rise time when translating logic levels in the Y gt A direction try Fall time when translating logic levels in the Y gt A direction Dmax Y gt A Guaranteed data rate when translating logic levels in the Y gt A direction under the driving and loading conditions specified in Table 1 tskew Y gt A Difference between propagation delays on any two channels when translating logic levels in the Y gt A direction TPPSKEW YA Difference in propagation delay between any one channel and the same channel on a different part under the same driving loading conditions when translating in the Y gt A direction Vcca Vcca supply voltage Vocx Vccy supply voltage Icca Vcca supply current Iccx Vccy supply current Iuiz A Vcca supply current during three state mode EN 0 Iuiz Y Vccy supply current during three state mode EN 0 Rev B Page 15 of 20 ADG3304 THEORY OF OPERATION The ADG3304 level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used The device requires two supplies Vcca and Vccy Vcca These supplies set the logic levels on each side of the device When driving the A
18. gg SEATING 9 0 45 COPLANARITY PLANE 0 10 COMPLIANT TO JEDEC STANDARDS MO 153 AB 1 Figure 42 14 Lead Thin Shrink Small Outline Package TSSOP RU 14 Dimensions shown in millimeters 0 65 0 59 0 53 SEATING a PLANE TO BALL 1 0 32 IDENTIFIER 028 TOP VIEW BALL SIDE DOWN 2 0 50 BSC BALL PITCH 0 2 oat BOTTOM em 0 24 0 15 VIEW 0 20 0 13 BALL SIDE UP 111105 0 Figure 43 12 Ball Wafer Level Chip Scale Package WLCSP CB 12 Dimensions shown in millimeters PIN 1 INDICATOR 12MAx 380 MAX 1 00 0 65 t 0 05 MAX 0 85 0 05 0 80 Euge 0 02 NOM SEATING 020 COPLANARITY PLANE BSC REF 0 08 COMPLIANT TO JEDEC STANDARDS MO 220 VGGD 1 Figure 44 20 Lead Lead Frame Chip Scale Package LFCSP VO 4mm x 4mm Body Very Thin Quad CP 20 1 Dimensions shown in millimeters Rev B Page 19 of 20 ADG3304 ADG3304 ORDERING GUIDE Package Model Temperature Range Package Description Branding Option ADG3304BRUZ 40 C to 85 C 14 Lead Thin Shrink Small Outline Package TSSOP RU 14 ADG3304BRUZ REEL 40 C to 85 C 14 Lead Thin Shrink Small Outline Package TSSOP RU 14 ADG3304BRUZ REEL7 40 C to 85 C 14 Lead Thin Shrink Small Outline Package TSSOP RU 14 ADG3304BCPZ REEL 40 C to 85 C 20 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 20 1 ADG3304BCPZ REEL72 40 C to 85 C 20 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 20 1 ADG3304BCBZ REEL
19. in Typ Max Unit LOGIC INPUTS OUTPUTS A Side Input High Voltage Vina Vcca 1 15 V Vcca 0 3 V Vina Vcca 1 2 V to 5 5 V Vcca 0 4 Input Low Voltage 0 4 V Output High Voltage Vona Vy lou 20 pA see Figure 29 Vcca 0 4 Output Low Voltage Vora Vy OV lo 20 pA see Figure 29 0 4 V Capacitance Ca f 1 MHz EN 0 see Figure 34 9 pF Leakage Current ILA Hi z Va 0V Vcca EN 0 see Figure 31 1 yA Y Side Input High Voltage Viny Vc 0 4 V Input Low Voltage Viy 0 4 V Output High Voltage Va Veca lou 20 pA see Figure30 Vccy 0 4 V Output Low Voltage Voi Va OV lo 20 pA see Figure 30 0 4 V Capacitance Cy f 1 MHz EN 0 see Figure 35 6 pF Leakage Current ly Hi z Vy 0 V Vccy EN 0 see Figure 32 1 uA Enable EN Input High Voltage Vihen Vcca 1 15 V Vcca 0 3 Vihen Vcca 1 2 V to 5 5 V Vcca 0 4 V Input Low Voltage Vien 0 4 V Leakage Current ILEN Ven 0 V Vcca Va OV 1 uA see Figure 33 Capacitance Cen 3 pF Enable Time ten Rs Rr 50 Q Va 0 V Vcca A gt Y 1 1 8 us Vy 0 V Vccy Y gt A see Figure 36 SWITCHING CHARACTERISTICS 3 3 V 0 3V lt Vcca Vecy Vcv 5 V 0 5 V A gt Y Level Translation Rs R 50 O C 50 pF see Figure 37 Propagation Delay tP AY 6 10 ns Rise Time tr A gt Y 2 3 5 ns Fall Time tF Asy 3 5 ns Maximum Data Rate Dmax A Y 50 Mbps Channel to Channel Skew tskew 2 4 ns Part to Part Skew tPPskEW A gt Y 3
20. irection and 15 pF when translating in the Y gt A direction Rev B Page 17 of 20 ADG3304 APPLICATIONS The ADG3304 is designed for digital circuits that operate at different supply voltages therefore logic level translation is required The lower voltage logic signals are connected to the A pins and the higher voltage logic signals are connected to the Y pins The ADG3304 can provide level translation in both directions from A gt Y or Y gt A on all four channels eliminating the need for a level translator IC for each direction The internal architecture allows the ADG3304 to perform bidirectional level translation without an additional signal to set the direction in which the translation is made It also allows simultaneous data flow in both directions on the same part for example when two channels translate in A gt Y direction while the other two translate in Y gt A direction This simplifies the design by eliminating the timing requirements for the direction signal and reducing the number of ICs used for level translation Figure 40 shows an application where two microprocessors operating at 1 8 V and 3 3 V respectively can transfer data simultaneously using two full duplex serial links TX1 RX1 and TX2 RX2 Vecy ADG3304 C Veca ma TX MICROPROCESSOR MICROCONTROLLER MICROPROCESSOR MICROCONTROLLER 04860 056 Figure 40 1 8 V to 3 3 V Level Translation Circuit on Two Full Duplex S
21. ody and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Only one absolute maximum rating can be applied at any one time LS ESD SENSITIVE DEVICE Rev B Page 6 of 20 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADG3304 H TOP VIEW a Not to Scale 04860 002 NC NO CONNECT Figure 2 14 Lead TSSOP Pin Configuration BALL a1 INDICATOR 04860 003 NOTES TOP VIEW BALLS AT THE BOTTOM Not to Scale Figure 3 12 Ball WLCSP Pin Configuration Table 3 14 Lead TSSOP and 20 lead LFCSP Pin Function Descriptions PIN 1 INDICATOR ADG3304 TOP VIEW Not to Scale onoano ooazo LEENE NC NO CONNECT 1 THE EXPOSED PADDLE CAN BE TIED TO GND OR LEFT FLOATING DO NOT TIE IT TO Vcca or Vecy ADG3304 15 NC 14 Y2 13 Y3 12 Y4 11 NC
22. pins the device translates the Vcca compatible logic levels to Vccy compatible logic levels available at the Y pins Similarly because the device is capable of bidirectional translation when driving the Y pins the Vccy compatible logic levels are translated to Vcca compatible logic levels available at the A pins When EN 0 Pin to Pin A4 and Pin Y1 to Pin Y4 are three stated When EN is driven high the ADG3304 goes into normal operation mode and performs level translation LEVEL TRANSLATOR ARCHITECTURE The ADG3304 consists of four bidirectional channels Each channel can translate logic levels in either the A gt Y or the Y gt A direction It uses a one shot accelerator architecture which ensures excellent switching characteristics Figure 39 shows a simplified block diagram of a bidirectional channel VccA Vccv i lt 2 T Figure 39 Simplified Block Diagram of an ADG3304 Channel 860 053 The logic level translation in the A gt Y direction is performed using a level translator U1 and an inverter U2 while the translation in the Y gt A direction is performed using Inverter U3 and Inverter U4 The one shot generator detects a rising or falling edge present on either the A side or the Y side of the channel It sends a short pulse that turns on the PMOS transistors T1 to T2 for a rising edge or the NMOS transistors 13 to T4 for a falling edge This charges discharges the capacitive load faster whi
23. re 16 Fall Time vs Capacitive Load at Pin Y A gt Y Level Translation Level Translation Rev B Page 9 of 20 ADG3304 RISE TIME ns Ta 25 C 1 CHANNEL DATA RATE 50kbps CA 1 8V Vecy 3 3V CAPACITIVE LOAD pF 04860 025 Figure 17 Rise Time vs Capacitive Load at Pin A YA Level Translation 4 0 3 5 DATA RATE 50kbps 1 5 FALL TIME ns Ta 25 C 1 CHANNEL 28 33 38 43 48 53 CAPACITIVE LOAD pF 04860 026 Figure 18 Fall Time vs Capacitive Load at Pin A Y gt A Level Translation 14 eo eo N PROPAGATION DELAY ns o Ta 25 C 1 CHANNEL DATA RATE 50kbps Veca 1 2V Vccy 1 8V 13 23 33 43 53 63 73 CAPACITIVE LOAD pF Figure 19 Propagation Delay vs Capacitive Load at Pin Y A gt Y Level Translation 04860 027 Rev B Page 10 of 20 12 DATA RATE 50kbps TA 25 C 1 CHANNEL E eo Veca 12V Vecy 1 8V Veca 1 8V Vecy 3 3V PROPAGATION DELAY ns 0 13 23 33 43 Veca 3 3V Vecy 5 53 63 73 CAPACITIVE LOAD pF Figure 20 Propagation Delay ter vs Capacitive Load at Pin Y AY Level Translation 25 C 1 CHANNEL DATA RATE 50kbps PROPAGATION DELAY ns 8V Vecy 3 3V 33 38 43 48 53 CAPACITIVE LOAD pF Figure 21 Propagation

ANALOG DEVICES Low Voltage 1.15 V to 5.5 V 4-Channel Bidirectional Logic Level Translator ADG3304 handbook

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