ANALOG DEVICES 2.5 V/3.3 V 2:1 Multiplexer/ Demultiplexer Bus Switch ADG3249 handbook
Contents
1. 100 0 03 0 1 1 0 10 100 1000 FREQUENCY MHz TPC 14 Crosstalk vs Frequency TIME ns 40 20 0 20 40 60 80 TEMPERATURE C TPC 17 Enable Disable Time vs Temperature 0 05 10 15 20 25 30 3 5 Va Ve V TPC 12 Charge Injection vs Source Voltage Ta 25 C Vcc 3 3V 2 5V SEL Ve Vin 0dBm N W ANALYZER RL Rs 500 100 0 03 0 1 1 0 10 100 1000 JITTER ps p p FREQUENCY MHz TPC 15 Off Isolation vs Frequency D o y 05 07 09 11 13 15 17 19 DATA RATE Gbps TPC 18 Jitter vs Data Rate PRBS 31 REV 0 ADG3249 Vec SEL 3 3V H Vin 1 5V p p 20dB ATTENUATION E F E a z ul W 20dB 38 7mV DIV SEL 3 3V ATTENUATION 20mV DIV SEL 2 5V ATTENUATION 133 7ps DIV Viu 22V p p TA 25C 166 3ps DIV Viy 1Vp p TA 25C EYE WIDTH CLOCK PERIOD p WEH UA p NOPR VA JITTER p p CLOCK PERIOD x 100 os o7 03 pi 43 5 i7 19 TPC 20 Eye Pattern 1 244 Gbps TPC 21 Eye Pattern 1 Gbps Vcc 3 3 V PRBS 31 Vcc 2 5 V PRBS 31 DATA RATE Gbps TPC 192. ADG3249 ANALOG DEVICES 2 9 V 3 3 V 2 1 Multiplexer Demultiplexer Bus Switch AD63249 FEATURES 225 ps Propagation Delay through the Switch 4 5 Q Switch Connection between Ports Data Rate 1 244 Gbps 2 5 V 3 3 V Supply Operation Selectable Level Shifting Translation Level Translation 3 3 V to 2 5 V 3 3 V to 1 8 V 2 5 V to 1 8 V Small Signal Bandwidth 610 MHz 8 Lead SOT 23 Package APPLICATIONS 3 3 V to 1 8 V Voltage Translation 3 3 V to 2 5 V Voltage Translation 2 5 V to 1 8 V Voltage Translation Docking Stations Memory Switching Analog Switch Applications GENERAL DESCRIPTION The ADG3249 is a 2 5 V or 3 3 V high performance 2 1 multi plexer demultiplexer bus switch It is designed on a low voltage CMOS process which provides low power dissipation yet gives high switching speed and very low on resistance This allows the input to be connected to the output without additional propaga tion delay or generating additional ground bounce noise Each switch of the ADG3249 conducts equally well in both direc tions when on The ADG3249 exhibits break before make switching action preventing momentary shorting when switch ing channels This device is ideal for applications requiring level translation When operated from a 3 3 V supply level translation from 3 3 V inputs to 2 5 V outputs is allowed Similarly if the device is operated from 2 5 V supply and 2 5 V inputs are applied the device will tra
3. 0 01 1 uA OFF State Leakage Current 162 0 lt A B lt Vcc 0 01 El uA ON State Leakage Current 0 lt A B Vec 0 01 1 uA Maximum Pass Voltage Vp Va Vg Vcc SEL 3 3 V Io 5 uA 2 0 2 5 2 9 V VA Vg Vcc SEL 2 5 V Io 5 uA 1 5 1 8 2 1 V VA Vg Voc 3 3 V SEL 0 V 16 5 uA 1 5 1 8 2 1 V CAPACITANCE A Port Off Capacitance C4 OFF f 1 MHz EN Vec 3 5 pF B Port Off Capacitance Cg OFF f 1 MHz EN Vcc 4 5 pF A B Port On Capacitance Ca Cg ON f 1 MHz 8 5 pF Control Input Capacitance Cw Css f 1 MHz 4 pF Cin f 1 MHz 6 5 pF SWITCHING CHARACTERISTICS Propagation Delay A to B or B to A tpp tp tprH Cr 50 pF Vec SEL 3 V 0 225 ns Propagation Delay Matching 5 ps Bus Enable Time EN to A or B tpzH PZL Voc 3 0 V to 3 6 V SEL Vec 1 3 5 4 8 ns Bus Disable Time EN to A or B tpHz PLZ Voc 3 0 V to 3 6 V SEL Vcc 1 5 5 8 2 ns Bus Enable Time EN to A or B tpzrp PZL Vcc 3 0 V to 3 6 V SEL 0V 1 3 2 4 5 ns Bus Disable Time EN to A or B PHZ PIZ Vcc 3 0 V to 3 6 V SEL 0V 1 4 5 7 7 ns Bus Enable Time EN to A or B TPZH tpzL Vec 2 3 V to 2 7 V SEL Vcc 1 3 5 4 6 ns Bus Disable Time EN to A or B PHZ PIZ Vec 2 3 V to 2 7 V SEL Vec 1 4 5 8 ns Break before Make Time tBBM R 510 Q Cr 50 pF 5 10 ns Transition Time tTRANS Ri 510 Q Ci 50 pF SEL Vec 16 29 ns Ri 510 Q Cy 50 pF SEL 0 V 15 22 ns Maximum Data Rate Voc SEL 3 3 V Va Vp 2 V 1 244 Gbps Channel Jitt
4. 5 Vae V VaVe V TPC 3 On Resistance vs Input Voltage TPC 2 On Resistance vs Input Voltage Ron 2 0 05 10 15 20 25 30 35 VA Vg V TPC 5 On Resistance vs Input Voltage for Different Temperatures TPC 6 Pass Voltage vs Vcc Icc 0 05 10 15 20 25 30 35 ol O 5 10 15 20 25 30 35 40 45 50 VaVe V ENABLE FREQUENCY MHz TPC 8 Pass Voltage vs Vcc TPC 9 lcc vs Enable Frequency ADG3249 3 0 2 5 Vour V i 1 0 0 5 0 0 00 0 04 0 06 008 0 10 lo A TPC 10 Output Low Characteristic Ta 25 C 5H Vec 3 3V 2 5V SEL Vec 6 H Vin odBm N W ANALYZER RL Rs 500 ATTENUATION dB 8 0 03 0 1 1 0 10 100 1000 FREQUENCY MHz TPC 13 Bandwidth vs Frequency TIME ns 40 20 0 20 40 60 80 TEMPERATURE C TPC 16 Enable Disable Time vs Temperature 3 0 TA 25 C 2 5 Va Vec EN 0 2 0 Voc SEL 3 3V 515 o 10 vec SEL 2 5V 0 5 Voc 3 3V SEL 0V 0 0 10 0 08 0 06 004 002 0 lo A TPC 11 Output High Characteristic Ta 25 C Voc 3 3V 2 5V SEL Vcc Vin OdBm N W ANALYZER Ru Rs 500
5. Eye Width vs Data Rate PRBS 31 REV 0 7 ADG3249 TIMING MEASUREMENT INFORMATION For the following load circuit and waveforms the notation that is used is Vy and Voyr where Vin V4 and Voyr Vg or Viy gt Vg and Voyr V4 NOTES PULSE GENERATOR PULSE GENERATOR FOR ALL PULSES tp lt 2 5ns tp lt 2 5ns FREQUENCY lt 10MHz C INCLUDES BOARD STRAY AND LOAD CAPACITANCES Ry ISTHE TERMINATION RESISTOR SHOULD BE EQUAL TO ZouT OFTHE PULSE GENERATOR Figure 1 Load Circuit 2xV swi 3 e 1 GND Test Conditions CONTROL INPUT EN T ov tpLH lt gt Figure 2 Propagation Delay Symbol Vcc 3 3 V 0 3 V SEL Vcc Vcc 2 5 V 0 2 V SEL Vcc Vcc 3 3 Vt 0 3 V SEL 0 V Unit Ry 500 500 500 Q Va 300 150 150 mV CL 50 30 30 pF Vr 1 5 0 9 0 9 V ENABLE DISABLE ViNH CONTROL INPUT EN Vr ar MEA ov Table III Switch Position tpzlL gt p z Test S1 Vour Vcc vn ov eme we NS VA VL VA tprz trzr 2 X Vcc E A VL TPHZ PZH GND tpzHh 4 toyz Vin V Vout V NU CC wi GND Vr HSA ov ov Figure 3 Enable and Disable Times 8 REV 0 BUS SWITCH APPLICATIONS Mixed Voltage Operation Level Translation Bus switches can provide an ideal solution for interfacing between mixed voltage systems The ADG3240 is suitable for applications where voltage translation from 3 3 V technology to a lower voltage tec
6. MEMORY BANK C MEMORY BANK D MEMORY ADDRESS Figure 12 ADG3249 Used to Reduce Both Access Time and Noise REV 0 ADG3249 OUTLINE DIMENSIONS 8 Lead Small Outline Transistor Package SOT 23 RJ 8 Dimensions shown in millimeters la 2 90 NEM RRR 2 80 BSC 0 65 BSC 1 95 1 30 BSC 145 0 90 ma 145MAX 022 i 008 y 0 60 x 015MAX 0 38 022 SEATING PLANE ejas eo 8 COMPLIANT TO JEDEC STANDARDS MO 178BA REV 0 11 0 0 0L 0 07709 12
7. ance and thus improved frequency performance than their analog counterparts The bus switch channel itself consisting solely of an NMOS switch limits the operating voltage see TPC 1 for a typical plot but in many cases this does not present an issue Multiplexing Many systems such as docking stations and memory banks have a large number of common bus signals Common prob lems faced by designers of these systems include e Large delays caused by capacitive loading of the bus e Noise due to simultaneous switching of the address and data bus signals Figure 11 shows an array of memory banks in which each ad dress and data signal is loaded by the sum of the individual loads If a bus switch is used as shown in Figure 12 the output load on the memory address and data bits is halved The speed at which the selected bank s data can flow is much improved because the capacitance loading is halved and the switches introduce negligible propagation delay Bus noise is also reduced High Impedance during Power Up Power Down To ensure the high impedance state during power up or power down EN should be tied to Vcc through a pull up resistor the minimum value of the resistor is determined by the current sinking capability of the driver 10 MEMORY ADDRESS MEMORY DATA BANK A MEMORY BANK B MEMORY BANK C MEMORY BANK D Figure 11 All Memory Banks Are Permanently Connected to the Bus MEMORY BANK A MEMORY BANK B
8. e or any other conditions above those listed in the operational 4 GND Ground Reference sections of this specification is not implied Exposure to absolute maximum rating 5 B Port B Input or Output conditions for extended periods may affect device reliability Only one absolute 6 IN Channel Select maximum rating may be applied at any one time 7 SEL Level Translation Select 8 Voc Positive Power Supply Voltage Table II Truth Table IN SEL FUNCTION X Disconnect L AO B 3 3 V to 1 8 V Level Shifting H AO B 3 3 V to 2 5 V 2 5 V to 1 8 V Level Shifting L A B 3 3 V to 1 8 V Level Shifting H Al B 3 3 V to 2 5 V 2 5 V to 1 8 V Level Shifting SEL 0 V only when Vpp 3 3 V x 10 Er rr i E mmer ORDERING GUIDE Model Temperature Range Package Description Package Branding ADG3249BRJ R2 40 C to 85 C SOT 23 Small Outline Transistor Package RJ 8 SHA ADG3249BRJ REEL 40 C to 85 C SOT 23 Small Outline Transistor Package RJ 8 SHA ADG3249BRJ REEL7 40 C to 85 C SOT 23 Small Outline Transistor Package RJ 8 SHA CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily WARNING accumulate on the human body and test equipment and can discharge without detection Although the E ADG3249 features proprietary ESD protection circuitry permanent damage may occur on devices prt S ESD subjected to high energy electro
9. er Voc SEL 3 3 V Va Vp 2 V 45 ps p p DIGITAL SWITCH On Resistance Ron Voc 3 V SEL Veo Va 0 V Iga 8 mA 4 5 8 Q Vec 3 V SEL Vecs Va 1 7 V Ipaq 8 mA 12 28 Q Vec 2 3 V SEL Vec Va 0 V Ipa 8 mA 5 9 Q Voc 2 3 V SEL Voc Va 1 V Iga 8 mA 9 18 Q Vcc 3 V SEL 0 V V4 0 V Iga 8 mA 5 8 Q Voc 3 V SEL 0 V Va 1 V Ipa 8 mA 12 Q On Resistance Matching ARon Voc 3 V SEL Vec Va 0 V In 8 mA 0 1 0 5 Q Voc 3 V SEL 0 V Va 0 V I 8 mA 0 1 0 5 Q POWER REQUIREMENTS Vec 2 3 3 6 V Quiescent Power Supply Current Icc Digital Inputs 0 V or Vec SEL Vec 0 01 1 uA Digital Inputs 0 V or Vcc SEL 0 V 0 1 0 2 mA Increase in Icc per Input Alcc Vcc 3 6 V EN 3 0 V SEL Vcc IN Vcc 0 15 8 uA NOTES Temperature range is as follows B Version 40 C to 85 C Typical values are at 25 C unless otherwise stated 5Guaranteed by design not subject to production test The digital switch contributes no propagation delay other than the RC delay of the typical Roy of the switch and the load capacitance when driven by an ideal voltage source Since the time constant is much smaller than the rise fall times of typical driving signals it adds very little propagation delay to the system Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side Propagation delay
10. he EN control input when the input is not driven at the supplies Data Propagation Delay through the Switch in the ON State Propagation delay is related to the RC time constant Ron X Cy where Cr is the load capacitance Bus Enable Times These are the times taken to cross the Vr voltage at the switch output when the switch turns on in response to the control signal EN Bus Disable Times These are the time taken to place the switch in the high impedance OFF state in response to the control signal They are measured as the time taken for the output voltage to change by V4 from the original quiescent level with reference to the logic level transition at the control input Refer to Figure 3 for enable and disable times On or Off Time Measured between the 90 points of both switches when switching fom one to another Time taken to switch from one channel to the other measured from 50 of the IN signal to 90 of the OUT signal Maximum Rate at which Data Can Be Passed through the Switch Peak to Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel REV 0 Typical Performance Characteristics ADG3249 Lp HE L LIBELLI V V 0 0 05 10 15 20 25 30 35 VaVe V TPC 1 On Resistance vs Input Voltage TPC 4 On Resistance vs Input Voltage for Different Temperatures TPC 7 Pass Voltage vs Vcc REV 0 Be ES Vi LL E 0 05 10 15 20 25 30 0 05 10 15 20 25 30 3
11. hnology is needed This device can translate from 2 5 V to 1 8 V or bidirectionally from 3 3 V directly to 2 5 V Figure 4 shows a block diagram of a typical application in which a user needs to interface between a 3 3 V ADC and a 2 5 V microprocessor The microprocessor may not have 3 3 V toler ant inputs therefore placing the ADG3249 between the two devices allows the devices to communicate easily The bus switch directly connects the two blocks thus introducing minimal propagation delay timing skew or noise 3 3V 3 3V 2 5V O o O amp 2 5V a e YAD eo MICROPROCESSOR a lt Figure 4 Level Translation between a 3 3 V ADC anda 2 5 V Microprocessor 3 3 V to 2 5 V Translation When Vcc is 3 3 V SEL 3 3 V and the input signal range is 0 V to Vcc the maximum output signal will be clamped to within a voltage threshold below the Vcc supply In this case the output will be limited to 2 5 V as shown in Figure 6 This device can be used for translation from 2 5 V to 3 3 V devices and also between two 3 3 V devices 3 3V 3 3V 2 5V lt Figure 5 3 3 V to 2 5 V Voltage Translation SEL Vcc 2 5V ADG3249 2 5V Vour 3 3V SUPPLY SEL 3 3V 25V gt 55 ra b Vin ov SWITCH 3 3V INPUT Figure 6 3 3 V to 2 5 V Voltage Translation SEL Vcc REV 0 ADG3249 2 5 V to 1 8 V Translation When Vcc is 2 5 V SEL 2 5 V and the input signal range is 0 V to Vcc
12. matching between channels is calculated from the on resistance matching and load capacitance of 50 pF See Timing Measurement Information section This current applies to the control pin EN only The A and B ports contribute no significant ac or dc currents as they transition Specifications subject to change without notice 2 REV 0 ADG3249 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION T4 25 C unless otherwise noted 8 Lead SOT 23 Mt GND teet e at y ERR eee nes 0 5 V to 4 6 V DigitallnputstoGND 0 5 V to 4 6 V EN 1 e 8 Vcc DC Input Voltage sie i epi rerai as 0 5 V to 4 6 V Ao z ADG3249 7 sec DCOutputCurrent 25 mA per Channel A1 s TOPVIEW elin Not to Scale Operating Temperature Range GND 4 B Industrial B Version 409C to 85 C EE e quer 65 Tt x Storage Temperature Range We 120 Table I Pin Function Descriptions Junction Temperature 150 C Oja Thermal Impedance 206 C W Pin No Mnemonic Description Lead Temperature Soldering 10 sec 300 C T IR Reflow Peak Temperature lt 20 sec 235 C 1 EN Enable Active Low 2 AO Port AO Input or Output Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the 3 Al Port Al Input or Output device at thes
13. nslate the outputs to 1 8 V In addition a level translating pin SEL is included When SEL is low Vec is reduced internally allowing for level translating between 3 3 V inputs and 1 8 V outputs The ADG3249 is available in a tiny 8 lead SOT 23 package REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies FUNCTIONAL BLOCK DIAGRAM ADG3249 PRODUCT HIGHLIGHTS 1 3 3 V or 2 5 V supply operation 2 Extremely low propagation delay through switch 3 4 5 switches connect inputs to outputs 4 Tiny SOT 23 package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved ADG3249 SPECIFICATIONS tris ctnense ntea orent Tato Ta B Version Parameter Symbol Conditions Min Typ Max Unit DC ELECTRICAL CHARACTERISTICS Input High Voltage VINH Vec 2 7 V to 3 6 V 2 0 V Vinu Voc 2 3 V to 2 7 V 1 7 V Input Low Voltage Vint Vec 2 7 V to 3 6 V 0 8 V Vint Vcc 2 3 V to 2 7 V 0 7 V Input Leakage Current Ii
14. static discharges Therefore proper ESD precautions arerecommended to avoid performance degradation or loss of functionality SENSITIVE DEVICE REV 0 3 ADG3249 TERMINOLOGY ARoN Cx OFF Cx ON Cy Cs CEN Icc Alcc PLE PHL pZH gt pzL PHZ gt tPLZ BBM TRANS Max Data Rate Channel Jitter Positive Power Supply Voltage Ground 0 V Reference Minimum Input Voltage for Logic 1 Maximum Input Voltage for Logic 0 Input Leakage Current at the Control Inputs OFF State Leakage Current It is the maximum leakage current at the switch pin in the OFF state ON State Leakage Current It is the maximum leakage current at the switch pin in the ON state Maximum Pass Voltage The maximum pass voltage relates to the clamped output voltage of an NMOS device when the switch input voltage is egual to the supply voltage Ohmic Resistance Offered by a Switch in the ON State It is measured at a given voltage by forcing a specified amount of current through the switch ON Resistance Match between Any Two Channels i e Roy max to Roy min OFF Switch Capacitance ON Switch Capacitance Control Input Capacitance This consists of IN SEL and EN Quiescent Power Supply Current This current represents the leakage current between the Vcc and ground pins It is measured when all control inputs are at a logic high or low level and the switches are OFF Extra power supply current component for t
15. the maximum output signal will as before be clamped to within a voltage threshold below the Vcc supply In this case the output will be limited to approximately 1 8 V as shown in Figure 8 2 5V ADG3249 gt 1 8V Figure 7 2 5 V to 1 8 V Voltage Translation SEL 2 5 Vcc Vour 2 5V SUPPLY SEL 2 5V 1 8V 55 ER gt nO ji ov SWITCH 2 5V INPUT Figure 8 2 5 V to 1 8 V Voltage Translation SEL Vcc 3 3 V to 1 8 V Translation The ADG3249 offers the option of interfacing between a 3 3 V device and a 1 8 V device This is possible through use of the SEL pin The SEL pin is an active low control pin SEL acti vates internal circuitry in the ADG3242 that allows voltage translation between 3 3 V devices and 1 8 V devices When Vcc is 3 3 V and the input signal range is 0 V to Vcc the maximum output signal will be clamped to 1 8 V as shown in Figure 9 To do this the SEL pin must be tied to Logic 0 If SEL is unused it should be tied directly to Vcc 3 3V O 3 3V ADG3249 M 1 8V Figure 9 3 3 V to 1 8 V Voltage Translation SEL 0 V Vour 3 3V SUPPLY E lt SWITCH OUTPUT j i Vin ov SWITCH 3V INPUT 3 Figure 10 3 3 V to 1 8 V Voltage Translation SEL 0 V ADG3249 Analog Switching Bus switches can be used in many analog switching applications for example video graphics Bus switches can have lower on resistance smaller ON and OFF channel capacit
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ANALOG DEVICES 2.5 V/3.3 V 2:1 Multiplexer/ Demultiplexer Bus Switch ADG3249 handbook