ANALOG DEVICES 2.5 V/3.3 V 10-Bit 2-Port Level Translating Bus Switch ADG3245 handbook
Contents
1. ADG3243 1 ANALOG DEVICES 2 9 V 3 3 V 8 Bit 2 Port Level Translating Bus Switch Preliminary Technical Data ADG3245 FEATURES 225 ps Propagation Delay through the Switch 4 5 Switch Connection between Ports Data Rate 1 244 Gbps 2 5 V 3 3 V Supply Operation Selectable Level Shifting Translation Level Translation 3 3 V to 2 5 V 3 3 V to 1 8 V 2 5 V to 1 8 V Small Signal Bandwidth 610 MHz 20 Lead TSSOP and LFCSP Packages APPLICATIONS 3 3 V to 1 8 V Voltage Translation 3 3 V to 2 5 V Voltage Translation 2 5 V to 1 8 V Voltage Translation Bus Switching Bus Isolation Hot Swap Hot Plug Analog Switch Applications GENERAL DESCRIPTION The ADG3245 is a 2 5 V or 3 3 V 8 bit 2 port digital switch It is designed on Analog Devices low voltage CMOS process which provides low power dissipation yet gives high switching speed and very low on resistance allowing inputs to be connected to outputs without additional propagation delay or generating additional ground bounce noise The switches are enabled by means of the Bus Enable BE input signal These digital switches allow bidirectional signals to be switched when ON In the OFF condition signal levels up to the supplies are blocked This device is ideal for applications requiring level translation When operated from a 3 3 V supply level translation from 3 3 V inputs to 2 5 V outputs is allowed Similarly if the device is operated from a 2 5 V supply and2. TPC 14 Crosstalk vs Frequency TIME ns 40 20 0 20 40 60 80 100 TEMPERATURE C TPC 17 Enable Disable Time vs Temperature Qu 0 05 10 15 20 25 3 0 V TPC 12 Charge Injection vs Source Voltage Ta 25 Voc 3 3V 2 5V SEL Vcc Viy 0dBm N W ANALYZER Rg 500 ATTENUATION dB 0 03 0 1 1 10 100 1000 FREQUENCY MHz TPC 15 Off Isolation vs Frequency Voc SEL 3 3V Vin 2V 20dB ATTENUATION 0 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 DATA RATE GBPS TPC 18 Jitter vs Data Rate PRBS 31 REV PrE ca 8 E Vcc SEL 3 3V Vin 2V p p 20dB ATTENUATION EYE WIDTH CLOCK PERIOD E JITTER p p CLOCK PERIOD x 100 EYE WIDTH 50 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 DATA RATE GBPS TPC 19 Eye Width vs Data Rate PRBS 31 50 1mV DIV ATTENUATION 50ps DIV Voc 33 25 C ES SEL 3 3V CX TPC 22 Jitter 1 244 GBPS PRBS 31 REV PrE Bees TIN CL E ILL URN ES LA ss EROR ER ES RT Vec 2 5V 20dB GARB eee e 3 7 2098 37mV DIV lt 2 5 ATTENUATION s DIV SEL 3 3V ATTENUATION 200ps DIV 2 Ta 26 C p 22V T4 25 C TPC 21 Eye Pattern 1 GBPS Vcc 2
3. 2 5 V inputs are applied the device will translate the outputs to 1 8 V In addition to this a level translating select pin SEL is included When SEL is low is reduced internally allowing for level translation between 3 3 V inputs and 1 8 V outputs This makes the device suited to applications requiring level translation between different supplies such as converter to DSP microcontroller interfacing REV PrE Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies FUNCTIONAL BLOCK DIAGRAM 0 Lp BO PRODUCT HIGHLIGHTS 1 3 3 V or 2 5 V supply operation Extremely low propagation delay through switch 4 5 Q switches connect inputs to outputs Level voltage translation 20 lead TSSOP and LFCSP 4 mm x 4 mm packages E aba One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved ADG3245 SPECIFICATIONS otherwise noted Vec 2 3 V to 3 6 V GND 0 V all specifications Tm to Tmax unless B
4. clamped to within a voltage threshold below the Vcc supply 2 5V 2 5V E 1 8V Figure 7 2 5 to 1 8 V Voltage Translation SEL 2 5 V In this case the output will be limited to approximately 1 8 V as shown in Figure 7 Vout 2 5V SUPPLY SEL 2 5V 5 i 55 EE gt 28 1 Vin ov SWITCH 2 5V INPUT Figure 8 2 5 V to 1 8 V Voltage Translation SEL 2 5 V 3 3 V to 1 8 V Translation ADG3245 offers the option of interfacing between a 3 3 V device and a 1 8 V device This is possible through use of the SEL pin SEL pin An active low control pin SEL activates internal circuitry in the ADG3245 that allows voltage translation between 3 3 V devices and 1 8 V devices 3 3V 3 3V D 1 8V Figure 9 3 3 V to 1 8 V Voltage Translation SEL 0 V When is 3 3 V and the input signal range is 0 V to the max output signal will be clamped to 1 8 V as shown in Figure 9 To do this the SEL pin must be tied to Logic 0 If SEL is unused it should be tied directly to ADG3245 Vout 3 3V SUPPLY lt SWITCH OUTPUT T ov SWITCH 3 3V INPUT Figure 10 3 3 Vto 1 8 V Voltage Translation SEL 0 V Bus Isolation A common requirement of bus architectures is low capacitance loading of the bus Such systems require bus bridge devices that extend the number of loads on the bus without exceeding the specifications Becaus
5. or B tprZ Vec 2 3 V to 2 7 V SEL 0 5 1 75 2 6 ns Max Data Rate Voc SEL 3 3 V Va Vp 2 V 1 244 Gbps Channel Jitter SEL 3 3 V VJVg 2 V 50 ps p p Operating Frequency Bus Enable fgg 10 MHz DIGITAL SWITCH On Resistance 3 SEL Vcc Va 0 8 mA 4 5 8 Q V SEL Veo Va 1 7 V 8 mA 15 28 Q Voc 2 3 SEL Voc Va 0 V Ip 8 mA 5 9 Q Voc 2 3 SEL Voc Va 1 V Ip 8 mA 11 18 Q 3 SEL 0 V V4 0 V 8 mA 5 8 Q 3 V SEL 0 V Va 1 V 8 mA 14 Q On Resistance Matching ARon Voc 3 V SEL Va 0 V Iga 8 mA 0 45 Q Vec V SEL Va 1 V 8 mA 0 65 Q POWER REQUIREMENTS 2 3 3 6 Quiescent Power Supply Current Icc Digital Inputs 0 V or Vec SEL Vec 0 001 1 uA Digital Inputs 0 V or SEL 0 V 0 65 1 2 mA Increase in Icc per Input Alec Vcc 3 6 V BE 3 0 V SEL Vec 130 NOTES Temperature range is as follows B Version 40 C to 85 Typical values are at 25 C unless otherwise stated 3Guaranteed by design not subject to production test digital switch contributes no propagation delay other than the RC delay of the typical Roy of the switch and the load capacitance when driven by an ideal voltage source Since the time constant is much smaller than the rise fall times of typical driving signals it adds very little propa
6. 5 On Resistance vs Input TPC 6 Pass Voltage vs Voltage for Different Temperatures Voltage for Different Temperatures 0 05 10 15 20 25 30 35 4 6 8 Vee ENABLE FREQUENCY MHz TPC 7 Pass Voltage vs Vcc TPC 8 Pass Voltage vs Vcc TPC 9 vs Enable Frequency REV PrE 5 ADG3245 3 0 Voc SEL 2 5V OL 0 0 01 0 02 0 03 0 04 0 05 0 06 0 07 0 08 0 09 0 10 lg A TPC 10 Output Low Characteristic 0 2 TA 25 C Vec 3 3V 2 5V a SEL V 4 cc 0dBm 5 N W ANALYZER RL Rs 500 L 5 8 10 12 14 0 03 04 1 10 100 1000 FREQUENCY MHz TPC 13 Bandwidth vs Frequency ENABLE _ pnm uc ewe EIE TIME ns 40 20 0 20 40 60 80 100 TEMPERATURE C TPC 16 Enable Disable Time vs Temperature 3 0 Ty 25 C 2 5 Vcc BE 0 2 0 Voc SEL 3 3V gt 515 AL a 2 m gt 1 0 vec SEL 2 5V 0 5 Vcc 3 3V SEL 0V 0 0 10 0 09 0 08 0 07 0 06 0 05 0 04 0 03 0 02 0 01 0 lg A TPC 11 Output High Characteristic Ta 25 C Voc 3 3V 2 5V SEL Vcc ADJACENT CHANNELS Viy 0dBm N W ANALYZER ATTENUATION dB 0 03 0 1 1 10 100 1000 FREQUENCY MHz
7. 5 V PRBS 31 TPC 20 Eye Pattern 1 244 GBPS 3 3 V PRBS 31 7 ADG3245 TIMING MEASUREMENT INFORMATION For the following load circuit and waveforms the notation that is used is Viy and where Vin andVour Vg or Vin andVour PULSE GENERATOR NOTES PULSE GENERATOR FOR ALL PULSES tg lt 2 5ns lt 2 5ns FREQUENCY lt 10MHz C INCLUDES BOARD STRAY AND LOAD CAPACITANCES IS THE TERMINATION RESISTOR SHOULD BE EQUAL TO 207 OF THE PULSE GENERATOR Figure 1 Load Circuit Test Conditions Vin CONTROL INPUT 4 gt lt gt vas Y vr VL Figure 2 Propagation Delay Symbol Vcc 3 3 0 3 V SEL Vcc Vec 2 5 V 0 2 V SEL Vcc 3 3 V 0 3 V SEL 0 V Unit 500 500 500 Q Va 300 150 150 mV CL 50 30 30 pF Vr 1 5 0 9 0 9 V ENABLE DISABLE CONTROL INPUT BE Table III Switch Position gt TEST S1 Vour Vin OV 2 X Vcc ME trzH GND _ Vour GND Figure 3 Enable and Disable Times 8 REV PrE BUS SWITCH APPLICATIONS Mixed Voltage Operation Level Translation Bus switches can be used to provide an ideal solution for inter facing between mixed voltage systems The ADG3245 is suitable for applications where voltage translation from 3 3 V technology to a lower voltage technology is needed T
8. A flowthrough pinout simplifies the PCB layout REV PrE OUTLINE DIMENSIONS 20 Lead Chip Scale Package LFCSP 4 X 4mm Body CP 20 Dimensions shown in millimeters UUU t PIN 1 215 INDICATOR ms 2 25 VIEW 2 10 SQ 1 95 0 75 6 0 55 ANNAN ue 0 70 MAX 0 35 png 12 0 65 050 10 ije iis 023 0 90 i i 0 05 0 18 0 80 0 02 5 002 SEATING 025 000 COPLANARITY BSC REF 0 08 COMPLIANT TO JEDEC STANDARDS MO 220 VGGD 1 20 Lead Thin Shrink Small Outline Package TSSOP RU 20 Dimensions shown in millimeters 6 40 BSC MA 0 20 075 D 0 30 alk he 0 60 COPLANARITY 0 19 SEATING 0 45 0 10 PLANE COMPLIANT TO JEDEC STANDARDS MO 153AC REV PrE 11 34d 0 c 0 110 02 5 NI GALNIYd 12
9. Version Parameter Symbol Conditions Min Typ Max Unit DC ELECTRICAL CHARACTERISTICS Input High Voltage Vec 2 7 V to 3 6 V 2 0 V 2 3 V to 2 7 1 7 V Input Low Voltage Vint Vec 2 7 V to 3 6 V 0 8 V Vint 2 3 V to 2 7 V 0 7 V Input Leakage Current Ii 0 01 1 uA OFF State Leakage Current 0 lt A B lt 0 01 1 uA ON State Leakage Current lt lt 0 01 1 uA Max Pass Voltage Vp Va Vg Vec SEL 3 3 V Io 5 2 0 2 5 2 9 V VA Vg SEL 2 5 V 5 uA 1 5 1 8 23 V VA Vg Voc 3 3 V SEL 0 V 5 1 5 1 8 22 V CAPACITANCE A Port Off Capacitance C4 OFF f 1MHz 5 pF B Port Off Capacitance OFF f 1MHz 5 pF A B Port On Capacitance Ca ON f 1 MHz 10 pF Control Input Capacitance Cm f 1MHz 6 pF SWITCHING CHARACTERISTICS Propagation Delay A to B or B to A tpp 50 pF SEL 0 225 ns Propagation Delay Matching 22 5 ps Bus Enable Time BE to A or B trzr 3 0 V to 3 6 V SEL Vec 1 3 2 4 8 ns Bus Disable Time BE to A or B tprz 3 0 V to 3 6 V SEL Vec 1 3 2 4 8 ns Bus Enable Time BE to A or B 3 0 V to 3 6 V 0 0 5 2 2 3 3 ns Bus Disable Time BE to A or 3 0 V to 3 6 SEL 0V 0 5 1 7 2 9 ns Bus Enable Time BE to A or B Vec 2 3 V to 2 7 V SEL Vec 0 5 2 2 3 ns Bus Disable Time BE to A
10. e the ADG3245 is designed specifically for applications that do not need drive yet require simple logic functions it solves this requirement The device isolates access to the bus thus minimizing capacitance loading BUS BACKPLANE BUS SWITCH LOCATION Figure 11 Location of Bus Switched in a Bus Isolation Application Hot Plug and Hot Swap Isolation The ADG3245 is suitable for hot swap and hot plug applications The output signal of the ADG3245 is limited to a voltage that is below the Vcc supply as shown in Figures 6 8 and 10 Therefore the switch acts like a buffer to take the impact from hot insertion protecting vital and expensive chipsets from damage In hot plug applications the system cannot be shutdown when new hardware is being added To overcome this a bus switch can be positioned on the backplane between the bus devices and the hot plug connectors The bus switch is turned off during hot plug Figure 12 shows a typical example of this type of application 10 PLUG IN CARD 1 CARD I O PLUG IN CARD 2 CARD I O Figure 12 ADG3245 in a Hot Plug Application There are many systems that require the ability to handle hot swapping such as docking stations PCI boards for servers and line cards for telecommunications switches If the bus can be isolated prior to insertion or removal then there is more control over the hot swap event This isolation can be achieved using a bus switch The bus switch
11. e those listed in the operational Junction Temperature 150 C sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Only one absolute maximum rating may be applied at any one time ORDERING GUIDE Model Temperature Range Package Description Package Option ADG3245BCP 40 C to 85 C Leaded Chip Scale Package LFCSP CP 20 ADG3245BRU 409 to 85 C Thin Shrink Small Outline Package TSSOP RU 20 Table I Pin Description Table II Truth Table Pin Mnemonic Description BE SEL Function BE Bus Enable Active Low L L B 3 3 V to 1 8 V Level Shifting SEL Level Translation Select L H A B 3 3 V to 2 5 V 2 5 V to 1 8 V Level Shifting Ax Port A Inputs or Outputs H X Disconnect Bx Port B Inputs or Outputs SEL 0 V only when VDD 3 3 V 10 PIN CONFIGURATION 20 Lead LFCSP and 20 Lead TSSOP SEL 1 e 20 ao 19 BE A1 3 18 Bo PIN 1 INDICATOR A2 ADG3245 VIEW 4 B3 Not to Scale ps A5 B4 8 13 B5 a7 9 12 Be GND fio 1 B7 CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily WARNING accumulate on the human body and test equipment and can discharge without detection Although the ADG3245 features proprietary ESD protection circui
12. ent Component for the BE Control Input when the input is not driven at the supplies Data Propagation Delay Through the Switch in the ON State Propagation delay is related to the RC time constant Ron X where is the load capacitance Bus Enable Times These are the times taken to cross the voltage at the switch output when the switch turns on in response to the control signal BE Bus Disable Times This is the time taken to place the switch in the high impedance OFF state in response to the con trol signal It is measured as the time taken for the output voltage to change by V4 from the original quiescent level with reference to the logic level transition at the control input Refer to Figure 3 for enable and disable times Maximum Rate at which Data Can Be Passed through the Switch Peak to Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel Operating Frequency of Bus Enable This is the maximum frequency at which Bus Enable BE can be toggled 4 REV PrE Typical Performance Characteristics ADG3245 eMe ses II lt Vec 3 3V Vec 3 3V tT NE II II LIII 0 0 05 10 15 20 25 30 35 d 7 1 05 10 15 ue 25 30 35 V VaVe TPC 1 On Resistance vs TPC 2 On Resistance vs TPC 3 On Resistance vs Input Voltage Input Voltage Input Voltage 0 05 10 15 20 25 30 35 TPC 4 On Resistance vs Input TPC
13. es are positioned on the hot swap card between the connector and the devices During hot swap the ground pin of the hot swap card must connect to the ground pin of the back plane before any other signal or power pins Analog Switching Bus switches can be used in many analog switching applications for example video graphics Bus switches can have lower on resistance smaller ON and OFF channel capacitance and thus improved frequency performance than their analog counterparts The bus switch channel itself consisting solely of an NMOS switch limits the operating voltage see TPC 1 for a typical plot but in many cases this does not present an issue High Impedance During Power Up Power Down To ensure the high impedance state during power up or power down BE should be tied to Vcc through a pull up resistor the minimum value of the resistor is determined by the current sinking capability of the driver PACKAGE AND PINOUT The ADG3245 is packaged in both a small 20 lead TSSOP or a tiny 20 lead LFCSP package The area of the TSSOP option is 37 5 mm while the area of the LFCSP option is 16 mm This leads to a 57 savings in board space when using LFCSP pack age compared with the TSSOP package This makes the LFCSP option an excellent choice for space constrained applications The ADG3245 in the TSSOP package offers a flowthrough pinout The term flowthrough signifies that all the inputs are on opposite sides from the outputs
14. gation delay to the system Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF 5See Timing Measurement Information This current applies to the control pin BE only The A and B ports contribute no significant ac or dc currents as they transition Specifications subject to change without notice REV PrE ABSOLUTE MAXIMUM RATINGS LFCSP Package 25 C unless otherwise noted Thermal Impedance 30 4 C W Vocto GND mead 0 5 V to 4 6 V TSSOP Package Digital Inputs to GND 0 5 V to 4 6 V Oja Thermal Impedance 143 C W DC Input Voltage ver mess 0 5 V to 4 6 V Lead Temperature Soldering 10 seconds 300 C DC Output 120mA Reflow Peak Temperature 20 seconds 235 C Operating Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause perma Industrial B Version 409 to 85 C nent damage to the device This is a stress rating only functional operation of the Storage Temperature Range 65 C to 150 C device at these or any other conditions abov
15. his device can translate from 3 3 V to 1 8 V from 2 5 V to 1 8 V or bidirectionally from 3 3 V directly to 2 5 V Figure 4 shows a block diagram of a typical application in which a user needs to interface between a 3 3 V ADC and a 2 5 V microprocessor microprocessor may not have 3 3 V toler ant inputs therefore placing the ADG3245 between the two devices allows the devices to communicate easily The bus switch directly connects the two blocks thus introducing minimal propagation delay timing skew or noise 3 3V 3 3V 2 5V 3 3V 25V MICROPROCESSOR Figure 4 Level Translation between a 3 3 V ADC and a 2 5 V Microprocessor 3 3 V to 2 5 V Translation When Vcc is 3 3 V SEL 3 3 V and the input signal range is 0 V to Vcc the max output signal will be clamped to within a voltage threshold below the Vcc supply 3 3V 2 5V 2 5V Figure 5 3 3 V to 2 5 V Voltage Translation SEL 2 3 3 V In this case the output will be limited to 2 5 V as shown in Figure 6 Vour 3 3V SUPPLY SEL 3 3V BBV pee emm 55 Vin ov SWITCH 3 3V INPUT Figure 6 3 3 V to 2 5 V Voltage Translation SEL 2 3 3 V This device can be used for translation from 2 5 V to 3 3 V devices and also between two 3 3 V devices REV PrE 2 5 V to 1 8 V Translation When is 2 5 V SEL 2 5 V and the input signal range is 0 V to Vcc the max output signal will as before be
16. try permanent damage may occur on devices Sept 4 subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended ESD SENSITIVE DEVICE to avoid performance degradation or loss of functionality REV PrE 3 ADG3245 TERMINOLOGY Alcc teur 2 Max Data Rate Channel Jitter fgg Positive Power Supply Voltage Ground 0 V Reference Minimum Input Voltage for Logic 1 Maximum Input Voltage for Logic 0 Input Leakage Current at the Control Inputs OFF State Leakage Current It is the maximum leakage current at the switch pin in the OFF state ON State Leakage Current It is the maximum leakage current at the switch pin in the ON state Max Pass Voltage The max pass voltage relates to the clamped output voltage of an NMOS device when the switch input voltage is equal to the supply voltage Ohmic Resistance Offered by a Switch in the ON State It is measured at a given voltage by forcing a specified amount of current through the switch On Resistance Match between Any Two Channels i e Rox Max Ron Min OFF Switch Capacitance ON Switch Capacitance Control Input Capacitance This consists of BE and SEL Quiescent Power Supply Current This current represents the leakage current between the Vcc and ground pins It is measured when all control inputs are at a logic HIGH or LOW level and the switches are OFF Extra Power Supply Curr
Download Pdf Manuals
Related Search
ANALOG DEVICES 2.5 V/3.3 V 10 Bit 2 Port Level Translating Bus Switch ADG3245 handbook