ANALOG DEVICES ADG201A/ADG202A LC2MOS quad SPST Switches handbook
Contents
1. Vss Cin Digital input capacitance Ipp Cp Cs ON Input or output capacitance when the switch Iss is on Delay time between the 50 and 90 points of the digital input and switch ON condition Delay time between the 50 and 90 points of the digital input and switch OFF condition OFF time measured between 50 points of both switches which are connected as a multi plexer when switching from one address state to another Maximum Input Voltage for a Logic Low Minimum Input Voltage for a Logic High Tint Ginn Input current of the digital input Most positive voltage supply Most negative voltage supply Positive supply current Negative supply current MECHANICAL INFORMATION OUTLINE DIMENSIONS Dimensions shown in inches and mm 16 Pin Plastic N 16 16 Pin Cerdip Q 16 JIL 0 26 6 53 0 24 6 1 0 30 7 62 0 24 6 1 gt 0 755 1918 0 306 778 0 32 8 128 t 0 745 18 93 7 0 294 7 47 0 785 19 94 029 7 366 014 3 56 0 75 79 08 t on 13 32 032 3 08 7 0 18 4 572 i T 0 155 3 937 MIN 0 14 3 56 1 ot Ey 0 78 4 45 0 20 5 08 9 015 0 381 0 12 3 05 0 125 3 475 I 0 008 0 203 l 0 012 0 305 4 778 0 023 0 584 Th 2 734 15 0 07 11 j 4 0 065 1 66 0 02 0 508 0105 2 67 9 008 0 203 0 03 0 752 0 015 0 381 0 09 2 28 0 0 045 115 0 015 0 38 0 098 2 42 LEAD N2. A LOGIC 1 INPUT PRODUCT HIGHLIGHTS 1 Extended Signal Range These switches are fabricated on an enhanced LC 7MOS process resulting in high breakdown and an increased analog signal range of 15V 2 Single Supply Operation For applications where the analog signal is unipolar OV to 15V the switches can be operated from a single 15V supply 3 Low Leakage Leakage currents in the range of 500pA make these switches suitable for high precision circuits The added feature of Break before Make allows for multiple outputs to be tied together for multiplexer applications while keeping leakage errors to a minimum ADG201A IN ADG202A IN SWITCH CONDITION Table l Truth Table One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 Twx 710 394 6577 Telex 924491 Cable ANALOG NORWOODMASS 40 Cto 40 C to Parameter 85 C 85 C ANALOG SWITCH Analog Signal Range Ron Ron vs Vp Vs Ron Drift Ron Match Is OFF OFF Input Leakage Ip OFF OFF Output Leakage Ip ON ON Channel Leakage DIGITAL CONTROL Vinn Input High Voltage Vin Input Low Voltage Eine or Linn DYNAMICCHARACTERISTICS TOPEN ton torr OFF Isolation Channel to Channel Crosstalk Cs OFF Cp OFF Cp Cs ON Cyn Digital Input Capacitance Qiny Charge Injection POWER SUPPLY Ipp Ipp Iss Iss Power Dissipation NOTES Sample tested at 25 C to ensure compli
3. Chip Carrier PLCC Cerdip ADG202AKR 40Cto 850 risa OP ADG202AKP 40 C to 85 C P 20A ADG202ABQ 40 C to 85 C Q 16 ADG202ATQ 55 Cto 125 C Q 16 ADG202ATE 55 Cto 125 C E 20A PIN CONFIGURATIONS DIP SOIC LCCC 14 s2 ADG201A ADG201A Vss 5 ADG201A ADG202A ADG202A Vop ADG202A TOP VIEW NC TOP VIEW Not ta Scale TOP VIEW NC Not to Scale GND 7 Not to Scale 83 54 8 IN3 9 10 11 12 13 Tr q Oo 7 8 22328 NC NO CONNECT Nc NO CONNECT NC NO CONNECT ADG201A ADG202A FUNCTIONAL DIAGRAM 15V Voo LEVEL SHIFTER TO LEVEL SHIFTER D Vss 15V Figure 1 Typical Digital Input Cell REV A 3 ADG201A ADG202A Typical Performance Characteristics The switches are guaranteed functional with reduced single or dual supplies down to 4 5V Ron Q Von 10 8V Voo 15V Vss 0V Vss 10 8V Ron 2 Vo Vs Volts Vo Vs Volts Ron as a Function of Vp Vs Dual Supply Voltage Ron as a Function of Vp Vs Single Supply Voltage 100 Voo 16 5V Vsg 16 5V ott ls OFF Ip OFF D LEAKAGE CURRENT nA TRIGGER LEVEL Volts 0 1 25 35 45 55 65 75 85 95 105 115 125 SUPPLY VOLTAGE Volts TEMPERATURE C Leakage Current as a Function of Temperature Note Trigger Lev
4. O 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42 SOIC Package 0 2440 6 20 0 2284 5 80 0 1574 4 00 51497 3 80 0 3937 10 00 0 3859 9 80 h x45 9 80 le F 0 0588 1 75 9 0098 0 25 0 0532 1 35 0 0099 0 25 La 0 0040 0 10 F m e SEATING 0 0075 0 19 yo 0 0500 1 27 0 0192 0 49 PLANE H BSC 0 0138 0 35 0 0500 1 27 0 0160 0 47 20 Terminal Leadless Ceramic Chip Carrier E 20A 0 082 0 014 2 085 0 455 0 040 x 45 7 F 2 44 02 x 45 REF 3 PLCS 0 025 0 003 TE 0 685 0 075 0 020 x 45 0 51 x 45 REF 20 Terminal Plastic Leaded Chip Carrier P 20A 0 173 0 008 4 385 0 185 0 390 0 008 go 9 905 0 125 7 0 106 0 015 2 665 0375 0 353 0 003 iaae 0 076 S0 H 220 nae w p 0035 20 01 0 89 0 25 0 045 0 003 Li 1 142 20 076 0 029 0 003 Ln Pa 0 737 0 076 0 017 0 004 F 0 432 0 101 J ry g LE 4 I 0 02 050 Max 51 1127 0 060 un REV
5. O 0 ADG201AQ O O ANALOG DEVICES LC MOS Quad SPST Switches ADG201A ADG202A FEATURES 44V Supply Maximum Rating 15V Analog Signal Range Low Ron 602 Low Leakage 0 5nA Break Before Make Switching Extended Plastic Temperature Range 40 C to 85 C Low Power Dissipation 33mW Available in 16 Lead DIP SOIC and 20 Lead PLCC LCCC Packages Superior Second Source ADG201A Replaces DG201A HI 201 ADG202A Replaces DG202 GENERAL DESCRIPTION The ADG201A and ADG202A are monolithic CMOS devices comprising four independently selectable switches They are designed on an enhanced LC MOS process which gives an in creased signal handling capability of 15V These switches also feature high switching speeds and low Ron The ADG201A and ADG202A consist of four SPST switches They differ only in that the digital control logic is inverted All devices exhibit break before make switching action Inherent in the design is low charge injection for minimum transients when switching the digital inputs REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implica tion or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAMS ADG201A ADG202A SWITCHES SHOWN FOR
6. ance Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise stated Vpn to Vss oe ee 44V Vpp to GND 0 ee ee 25V Vss to GND 25V Analog Inputs Voltage atS D Vss 0 3V to Vpp 0 3V Continuous Current Sor D 30mA Pulsed Current S or D lms Duration 10 Duty Cycle 70mA Digital Inputs Voltage at IN Vss 2V to Vpop 2V or 20mA Whichever Occurs First T Version 55 C to 125 C 25 C Test Conditions 10VSVsx 10V Ips 1 0mA Test Circuit 1 Vs OV Ips ImA Vo 14V Vs 14V Test Circuit 2 Vp 14V V 14V Test Circuit 2 Vp 14V Test Circuit 3 Test Circuit 4 Test Circuit 4 Vs 10V p p f 100kHz Ry 75Q Test Circuit 6 Test Circuit 7 Rs 00 Cy 1000pF Vs 0V Test Circuit 5 Digital Inputs Vint or Vin Power Dissipation Any Package Upto 75 C 470mW Derates above 75 C by 6mW C Operating Temperature 40 C to 85 C 40 C to 85 C 55 C to 125 C 65 C to 150 C 300 C Commercial K Version Industrial B Version Extended T Version Storage Temperature Range Lead Temperature Soldering 10sec NOTE 1Overvoltage at IN S or D will be clamped by diodes Current should be limited to the Maximum Rating above COMMENT Stresses above those listed under Absol
7. el vs Power Supply Voltage Dual or Single Leakage Currents Reduce as the Supply Voltages Reduce Supply Voltage 500 400 zZ 2 300 2 2 200 100 0 5 7 9 11 13 15 SUPPLY VOLTAGE Volts SUPPLY VOLTAGE Volts Switching Time vs Supply Voltage Dual Supply Switching Time vs Supply Voltage Single Supply 4 REV A Test Circuits ADG201A ADG202A Q ls OFF tp OFF F14V 14V O O _ 14V Vs Ron Vl bs Test Circuit 1 Test Circuit 2 Test Circuit 3 15V 3V ADG201A Vin 50 50 3V I Vin 50 50 ADG202A Test Circuit 4 5V Vin Vo f AVo QINJ C x AVo Test Circuit 5 Charge Injection ADG201A Viy 5V OFFISOLATION ADG202A Vin 0V 20 x LOG V3 Vol ADG201A Viy 0V CHANNEL TO CHANNEL CROSSTALK ADG202A Vin 5V 20 x LOG Vs Vol Test Circuit 6 Off Isolation Test Circuit 7 Channel to Channel Crosstalk REV A _5 ADG201A ADG202A TERMINOLOGY ton Ron Ohmic resistance between terminals OUT and S torr Ron Match Difference between the Ron of any two channels Is OFF Source terminal leakage current when the switch tOPEN is off Ip OFF Drain terminal leakage current when the switch is off Ip ON Leakage current that flows from the closed switch Vint into the body Vin Vp Vs Analog voltage on terminal D S Cs OFF Switch input capacitance OFF condition Vpp Cp OFF Switch output capacitance OFF condition
8. ute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Only one Absolute Maximum Rating may be applied at any one time REV A ADG201A ADG202A CAUTION ESD electrostatic discharge sensitive device The digital control inputs are diode protect WARNING ed however permanent damage may occur on unconnected devices subject to high energy lt electrostatic fields Unused devices must be stored in conductive foam or shunts The protective AS foam should be discharged to the destination socket before devices are removed ESD SENSITIVE DEVICE ORDERING GUIDE Temperature Package Range Option ADG201AKN 40 C to 85 C N 16 ADG201AKR 40 C to 85 C R 16A ADG201AKP 40 C to 85 C P 20A eed MIL STD 883 Class B ed dd 883B to T grad _ ane o _ o order 883 Class B processed parts a to T grade part ADGZIIATO sa a on Q H numbers See Analog Devices Military Products Databook 1990 for T military data sheet ADG201ATE 55 C to 125 C E 20A E Leadless Ceramic Chip Carrier LCCC N Plastic DIP R 0 15 ADG202AKN 40 C to 85 C N 16 Small Outline IC SOIC P Plastic Leaded
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ANALOG DEVICES ADG201A/ADG202A LC2MOS quad SPST Switches handbook