ANALOG DEVICES ADG1204 2 pF Off Capacitance 1 pC Charge Injection ±15 V/12 V 4:1 iCMOS Multiplexer handbook
Contents
1. 10 MA 50 Q max LEAKAGE CURRENTS Voo 10 V Vss 10 V Source Off Leakage Is Off 0 01 nA typ Vs 0 V 10 V Vo 10 V O V Figure 22 0 5 1 5 nA max Drain Off Leakage lo Off 0 01 nA typ Vs 0 V 10 V Vo 10 V O V Figure 22 0 5 1 5 nA max Channel On Leakage Ip Is On 0 04 nA typ Vs Vp 0 V or 10 V Figure 23 1 2 5 nA max DIGITAL INPUTS Input High Voltage Vini 2 0 V min Input Low Voltage Vint 0 8 V max Input Current livor Ini 0 005 uA typ Vin Vint Or VinH 0 5 pA max Digital Input Capacitance Civ 5 pF typ DYNAMIC CHARACTERISTICS Transition Time trrans 40 nstyp R 2500 C0 235 pF ns max Vs 10 V Figure 24 ton EN 40 ns typ Ri 500Q C 35 pF 90 ns max Vs 10 V Figure 24 torr EN 20 ns typ Ri 50 O C 35 pF 40 ns max Vs 10 V Figure 24 Break before Make Time Delay to 15 ns typ Ri 50 O C 35 pF 1 ns min Vs1 Vs2 10 V Figure 25 Charge Injection 1 pCtyp Vs OV Rs 00Q C 1 nF Figure 26 Off Isolation 75 dB typ R 2500 C 5 pF f 1 MHz Figure 27 Channel to Channel Crosstalk 85 dB typ Ri 500Q C 5pF f 1MHz Figure 28 Total Harmonic Distortion Noise 0 002 96 typ R 600 O 5 V rms f 20 Hz to 20 kHz 3 dB Bandwidth 700 MHztyp RL 500 C 5 pF Figure 29 Cs Off 2 pF typ Co Off 7 pF typ Cp Cs On 4 pF typ POWER REQUIREMENTS Vpp 16 5 V Vss 16 5 V Ibo 0 001 uA typ Digital Inputs 0 V or Vop 5 0 uA max Ipp 150 pA typ Digital Inputs 2 5 V 300 uA max Iss 0 002. AD61204 TBD TBD Figure 10 Leakage Currents as a Function of Vp Vs Figure 13 Leakage Currents as a Function of Temperature TBD TBD Figure 11 Leakage Currents as a Function of Vp Vs Figure 14 Supply Currents vs Input Switching Frequency TBD TBD Figure 12 Leakage Currents as a Function of Temperature Figure 15 Charge Injection vs Source Voltage Rev PrD Page 11 of 16 ADG1204 TBD TBD Figure 16 ton torr Times vs Temperature Figure 19 On Response vs Frequency TBD TBD Figure 17 Off Isolation vs Frequency Figure 20 THD N vs Frequency TBD Figure 18 Crosstalk vs Frequency Rev PrD Page 12 of 16 TEST CIRCUITS ko ls OFF lp OFF fs ol Ibs NC No Connect 04779 0 020 q 04779 0 021 Figure 21 Test Circuit 1 0On Resistance Figure 22 Test Circuit 2 Off Leakage ADDRESS DRIVE V Min oy Vout trRANSITION l TRANSITION 04779 0 023 Figure 24 Test Circuit 4 Address to Output Switching Times 8096 8096 Vour teem ENABLE DRIVE V Vin oU Vo OUTPUT O Vour ov tonten toFF EN Vs m J Figure 26 Test Circuit 6 Enable to Output Switching Delay Rev PrD Page 13 of 16 3V _ ADDRESS DRIVE Vi VIN oy A 04779 0 024 04779 0 025 ADG1204 04779 0 022 Figure 23 Test Circuit 3 On Leakage ADG1204 Vour Qing CL x AVour Vi SW OFF SW OFF IN 04779 0 026
3. 4 torr EN The delay between applying the digital control input and the output switching off Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching Off Isolation A measure of unwanted signal coupling through an off switch Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance Bandwidth The frequency at which the output is attenuated by 3 dB On Response The frequency response of the on switch Insertion Loss The loss due to the on resistance of the switch THD N The ratio of the harmonic amplitude plus noise of the signal to the fundamental trrans The delay time between the 50 and 90 points of the digital input and switch on condition when switching from one address state to another Rev PrD Page 9 of 16 ADG1204 TYPICAL PERFORMANCE CHARACTERISTICS TBD TBD Figure 4 On Resistance as a Function of Vp Vs for Single Supply Figure 7 On Resistance as a Function of Vp Vs for Different Temperatures Single Supply TBD TBD Figure 5 On Resistance as a Function of Vp Vs for Dual Supply Figure 8 On Resistance as a Function of Vp Vs for Different Temperatures Dual Supply TBD TBD Figure 6 On Resistance as a Function of Vp Vs for Different Temperatures Figure 9 Leakage Currents as a Function of Vp Vs Single Supply Rev PrD Page 10 of 16
4. V Vo 10 V 1 V Figure 22 0 5 1 5 nA max Drain Off Leakage Ip Off 0 01 nA typ Vs 1 V 10 V Vp 10 V 1 V Figure 22 0 5 1 5 nA max Channel On Leakage lo Is On 0 04 nA typ Vs Vp 1 Vor 10 V Figure 23 1 2 5 nA max DIGITAL INPUTS Input High Voltage Vini 2 0 V min Input Low Voltage Vini 0 8 V max Input Current lint Or linn 0 001 uA typ Vin Vini Or Vinh 0 5 uA max Digital Input Capacitance Civ 5 pF typ DYNAMIC CHARACTERISTICS Transition Time trrans 40 nstyp Ri 500Q C 35 pF ns max Vs 10 V Figure 24 ton EN 50 ns typ R 50 O C 35 pF ns max Vs 8 V Figure 24 torr EN 15 ns typ Ri 50 O C 35 pF ns max Vs 8 V Figure 24 Break before Make Time Delay to 15 ns typ Ri 50 O C 35 pF 1 ns min Vs1 Vs2 8 V Figure 25 Charge Injection 5 pC typ Vs O0V Rs 00 C 1 nF Figure 26 Off Isolation 75 dB typ R 500 C 5 pF f 1 MHz Figure 27 Channel to Channel Crosstalk 85 dB typ R 500 CL 5 pF f 1 MHz Figure 28 3 dB Bandwidth 700 MHz typ R 2500 C 5 pF Figure 29 Cs Off 2 pF typ Co Off 2 pF typ Cp Cs On 4 pF typ Rev PrD Page 5 of 16 ADG1204 Parameter POWER REQUIREMENTS lbp loo 25 C 0 001 150 85 C Y Version 5 0 300 Unit pA typ uA max pA typ uA max Test Conditions Comments Vop 13 2V Digital inputs 0 V or Voo Digital inputs 2 5 V 1 Y Version temperature range is 40 C to 12
5. 1 pA typ Digital Inputs 0 V or Vop 5 0 uA max Rev PrD Page 3 of 16 ADG1204 Parameter 25 C 85 C Y Version Unit Test Conditions Comments lanp 0 001 pA typ Digital Inputs 0 V or Vop 5 0 pA max lanp 150 pA typ Digital Inputs 2 5 V 300 uA max 1 Y Version temperature range is 40 C to 125 C Guaranteed by design not subject to production test Vpp 5 V 1096 Vss 5 V 10 GND 0 V unless otherwise noted Table 2 Parameter 25 C 85 C Y Version Unit Test Conditions Comments ANALOG SWITCH Analog Signal Range Vss to Voo V On Resistance Ron 220 Q typ Vs 3 3 V ls 10 mA Figure 21 Q max On Resistance Match between 10 Q typ Channels ARon Q max Vs 3 3 V ls 10 mA On Resistance Flatness Retation 30 Q typ Vs 3 3 V ls 10 mA O max LEAKAGE CURRENTS Voo 5 5 V Vss 5 5 V Source Off Leakage Is Off 0 01 nA typ Vp 44 5 V Vs 4 5 V Figure 22 0 5 1 5 nA max Drain Off Leakage Ip Off 0 01 nA typ Vp 4 5 V Vs 4 5 V Figure 22 0 5 1 5 nA max Channel On Leakage Ip Is On 0 04 nA typ Vp Vs 4 5 V Figure 23 1 2 5 nA max DIGITAL INPUTS Input High Voltage Vinx 2 0 V min Input Low Voltage Vint 0 8 V max Input Current lint Or linn 0 005 uA typ Vin Vint Or VinH 0 5 pA max Digital Input Capacitance Civ 5 pF typ DYNAMIC CHARACTERISTICS ton 160 ns typ Ri 300 Q C 35 pF ns max Vs 3 V Fig
6. 5 C Guaranteed by design not subject to production test Rev PrD Page 6 of 16 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 4 Parameter Rating Voo to Vss 38V Voo to GND 0 3 V to 25 V Vss to GND 0 3 V to 25 V Analog Inputs Vss 0 3 V to Vpp 0 3 V Digital Inputs GND 0 3 V to Voo 0 3 V or Peak Current S or D Continuous Current S or D Operating Temperature Range Industrial B Version Automotive Y Version Storage Temperature Range Junction Temperature 14 Lead TSSOP 8s Thermal Impedance 12 Lead LFCSP 6 Thermal Impedance Lead Temperature Soldering Vapor Phase 60 s Infrared 15 s 30 mA whichever occurs first 100 mA pulsed at 1 ms 1096 duty cycle max 30mA 40 C to 85 C 40 C to 125 C 65 C to 150 C 150 C 150 4 C W 30 4 C W 215 C 220 C ADG1204 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Only one absolute maximum rating may be applied at any one time 1 Overvoltages at IN S or D are clamped by internal diodes Current should be limited to the maximum rating
7. Figure 27 Test Circuit 7 Charge Injection NETWORK NETWORK ANALYZER ANALYZER 3 v OFF ISOLATION 20 LOG 5 CHANNEL TO CHANNEL CROSSTALK 20 LOG mE Figure 28 Test Circuit 8 Off Isolation Figure 30 Test Circuit 10 Channel to Channel Crosstalk NETWORK ANALYZER AUDIO PRECISION Vour WITH SWITCH Vour WITHOUT SWITCH 04779 0 028 INSERTION LOSS 20 LOG Figure 29 Test Circuit 9 Bandwidth Figure 31 Test Circuit 11 THD Noise Rev PrD Page 14 of 16 04779 0 029 04779 0 030 OUTLINE DIMENSIONS Figure 32 14 Lead Thin Shrink Small Outline Package TSSOP PIN 1 INDICATOR 1 20 AD61204 0 20 Max 0 09 Yi 0 75 8 wi l 0 60 30 0 0 45 019 BEANE COPLANARITY 0 10 COMPLIANT TO JEDEC STANDARDS MO 153AB 1 RU 14 Dimension shown in millimeters PIN 1 INDICATOR 1 45 12 MAX 0 80 MAX gt 0 65 TYP 1 00 F 0 85 0 05 MAX 0 80 i 0 02 NOM eb COPLANARITY SEATING ZE PLANE LE 0 20 REF 0 08 COMPLIANT TO JEDEC STANDARDS MO 220 VEED 1 EXCEPT FOR EXPOSED PAD DIMENSION Figure 33 12 Lead Lead Frame Chip Scale Package VO LFCSP 3mm x 3 mm Body Very Thin Quad CP 12 1 Dimensions shown in inches and millimeters 1 30 SQ ii 1 15 oy ORDERING GUIDE Model Temperature Range Package Description Package Option ADG1204YRU 40 C to 125 C Thin Shrink Small Outline Package TSSOP RU 14 ADG1204YCP 40 C to 125 C Lead Frame Chip S
8. cale Package LFCSP CP 12 1 Rev PrD Page 15 of 16 ADG1204 NOTES 2004 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www ana l 0 g com PRO4779 0 11 04 PrD DEVI CES Rev PrD Page 16 of 16
9. e an input or an output 6 4 D Drain Terminal Can be an input or an output 7 9 5 NC No Connection 10 6 S4 Source Terminal Can be an input or an output 11 7 S3 Source Terminal Can be an input or an output 12 8 Vop Most Positive Power Supply Potential 13 9 GND Ground 0 V Reference 14 10 A1 Logic Control Input Rev PrD Page 8 of 16 TERMINOLOGY Ibp The positive supply current Iss The negative supply current Vo Vs The analog voltage on Terminals D and S Ron The ohmic resistance between D and S RELAT ON Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range Is Off The source leakage current with the switch off I Off The drain leakage current with the switch off Ip Is On The channel leakage current with the switch on Vint The maximum input voltage for Logic 0 Visi The minimum input voltage for Logic 1 In Imn The input current of the digital input Cs Off The off switch source capacitance which is measured with reference to ground C Off The off switch drain capacitance which is measured with reference to ground AD61204 C C5 On The on switch capacitance which is measured with reference to ground Cm The digital input capacitance ton EN The delay between applying the digital control input and the output switching on See Figure 24 Test Circuit
10. ng are required Fast switching speed coupled with high signal bandwidth make the parts suitable for video signal switching iCMOS construc tion ensures ultralow power dissipation making the parts ideally suited for portable and battery powered instruments Rev PrD Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 04779 0 001 Figure 1 The ADG1204 switches one of four inputs to a common output D as determined by the 3 bit binary address lines AO Al and EN Logic 0 on the EN pin disables the device Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies In the off condi tion signal levels up to the supplies are blocked All switches exhibit break before make switching action Inherent in the design is low charge injection for minimum transients when switching the digital inputs PRODUCT HIGHLIGHTS 1 2 pF off capacitance 15 V supply 2 1 pC charge injection 3 3V logic compatible digital inputs Vin 2 0 V Vu 0 8 V 4 No Vi l
11. ogic power supply required Ultralow power dissipation 0 03 uW 14 lead TSSOP and 12 lead 3 mm x 3 mm LFCSP package as One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved ADG1204 TABLE OF CONTENTS SPECI CALI OMS orii aba eee noz asa ese asa aaa 3 Pin Configurations and Function Descriptions 8 Dual Supply csset ttt to R metus 3 Terminology zeit te ee ten ttt toten 9 Single Supply nete tttm atate bees 5 Typical Performance Characteristics sees 10 Absolute Maximum Ratings essent 7 Test CAE CUIU Ss eet m pie tegere 13 Trath Table ttt ete repe bit 7 Outline Dimensions tte e RE atem tete teta 15 ESD Caution anie imet pete tt ai ase abode dieto 7 Ordering Guilde eere te nee nC RR 15 REVISION HISTORY 11 04 Revision PrD Preliminary Version Rev PrD Page 2 of 16 SPECIFIGATIONS AD61204 DUAL SUPPLY Vpp 15 V 1096 Vss 15 V GND 0 V unless otherwise noted Table 1 Parameter 25 C 85 C Y Version Unit Test Conditions Comments ANALOG SWITCH Analog Signal Range Vop to Vss V On Resistance Ron 120 160 180 QO typ Vs 10 V ls 10 mA Figure 21 Q max On Resistance Match between 5 Qtyp Vs 410 V Is 10 mA Channels ARon Q max On Resistance Flatness Retation 25 Q typ Vs 5 V O V 5 V Is
12. s given ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality TRUTH TABLE Table 5 EN A1 A0 si S2 S3 sa 0 X X Off Off Off Off 1 0 0 On Off Off Off 1 0 1 Off On Off Off 1 1 0 Off Off On Off 1 1 1 Off Off Off On S ESD SENSITIVE DEVICE Rev PrD Page 7 of 16 ADG1204 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 12 EN 11 A0 10 A1 PIN 1 Vss 1 f oO INDICATOR 9 GND S1 of ADG1204 l H 8 Vpp S2 a TOP VIEW 7 S3 l Not to Scale J NC NO CONNECT w c ADG1204 TOP VIEW 04779 0 002 04779 0 003 NC NO CONNECT Q 2 3 Figure 2 TSSOP Pin Configuration Figure 3 LFCSP Pin Configuration Table 6 Pin Function Descriptions Pin No TSSOP LFCSP Mnemonic Function 1 11 A0 Logic Control Input 2 12 EN Active High Digital Input When low the device is disabled and all switches are off When high Ax logic inputs determine on switches 3 1 Vss Most Negative Power Supply Potential 4 2 S1 Source Terminal Can be an input or an output 5 3 S2 Source Terminal Can b
13. ure 24 torr 60 nstyp Ri 300 Q C 35 pF ns max Vs 3 V Figure 24 Break before Make Time Delay to 50 ns typ Ri 300 0 C 35 pF 1 ns min Vsi Vs2 3 V Figure 25 Charge Injection 20 pC typ Vs 0V Rs 00 C 1 nF Figure 26 pC max Off Isolation 56 dB typ R 2500 C 25 pF f 1 MHz Figure 27 Channel to Channel Crosstalk 60 dB typ R 500 CL 5 pF f 1 MHz Figure 28 3 dB Bandwidth 20 MHztyp RL 500 C 5 pF Figure 29 Cs Off 15 pF typ f 1MHz Cp Off pF typ f 1 MHz Cp Cs On 100 pF typ f 1 MHz Rev PrD Page 4 of 16 AD61204 Parameter 25 C 85 C Y Version Unit Test Conditions Comments POWER REQUIREMENTS Voo 45 5 V Vss 5 5 V Ipp 0 001 pA typ Digital Inputs 2 0 V or 5 5 V 5 0 uA max Iss 0 001 pA typ Digital Inputs 2 0 V or 5 5 V 5 0 pA max 1 Y Version temperature range is 40 C to 125 C Guaranteed by design not subject to production test SINGLE SUPPLY Vpp 12V 1096 Vss 0 V GND 0 V unless otherwise noted Table 3 Parameter 25 C 85 C Y Version Unit Test Conditions Comments ANALOG SWITCH Analog Signal Range O V to Voo V On Resistance Ron 220 Qtyp Vs 10 V Is 10 mA Figure 21 O max On Resistance Match between 1 Qtyp Vs 10 V Is 210 mA Channels ARon Q max On Resistance Flatness Retation 12 Q typ Vs 3 V 6 V 9 V Is 10 mA LEAKAGE CURRENTS Vop 12 V Source Off Leakage ls Off 0 01 nA typ Vs 1 V 10
14. zETgADG12044 p ES ANALOG 2 pF Off Capacitance 1 pC Charge Injection DEVICES 15 V 12 V 4 1 iGMOST Multiplexer AD61204 FUNCTIONAL BLOCK DIAGRAM ADG1204 FEATURES 2 pF off capacitance 1 pC charge injection 33 V supply range 120 Q on resistance Fully specified at 12 V x15 V No V supply required 3 V logic compatible inputs Rail to rail operation 14 lead TSSOP and 12 lead LFCSP Typical power consumption 0 03 pW APPLICATIONS Automatic test equipment Data aquisition systems Battery powered systems Sample and hold systems Audio signal routing Communication systems GENERAL DESCRIPTION The ADG1204 is a CMOS analog multiplexer comprising four single channels designed on an iCMOS process iCMOS industrial CMOS is a modular manufacturing process that combines high voltage CMOS complementary metal oxide semiconductor and bipolar technologies It enables the development of a wide range of high performance analog ICs capable of 30 V operation in a footprint that no other genera tion of high voltage parts has been able to achieve Unlike analog ICs using conventional CMOS processes iCMOS components can tolerate high supply voltages while providing increased performance dramatically lower power consumption and reduced package size The ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample and hold applications where low glitch and fast settli
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ANALOG DEVICES ADG1204 2 pF Off Capacitance 1 pC Charge Injection